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GET /api/patches/57844/?format=api
{ "id": 57844, "url": "http://patches.dpdk.org/api/patches/57844/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-2-git-send-email-xavier.huwei@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1566568031-45991-2-git-send-email-xavier.huwei@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1566568031-45991-2-git-send-email-xavier.huwei@huawei.com", "date": "2019-08-23T13:46:50", "name": "[01/22] net/hns3: add hardware registers definition", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9719ab1e6c816b5d673a66058bd9b174d93b5b11", "submitter": { "id": 1405, "url": "http://patches.dpdk.org/api/people/1405/?format=api", "name": "Wei Hu (Xavier)", "email": "xavier.huwei@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-2-git-send-email-xavier.huwei@huawei.com/mbox/", "series": [ { "id": 6114, "url": "http://patches.dpdk.org/api/series/6114/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6114", "date": "2019-08-23T13:46:49", "name": "add hns3 ethernet PMD driver", "version": 1, "mbox": "http://patches.dpdk.org/series/6114/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57844/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/57844/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D107B1BFD1;\n\tFri, 23 Aug 2019 15:49:40 +0200 (CEST)", "from huawei.com (szxga07-in.huawei.com [45.249.212.35])\n\tby dpdk.org (Postfix) with ESMTP id 3BD8E1BFC0\n\tfor <dev@dpdk.org>; Fri, 23 Aug 2019 15:49:33 +0200 (CEST)", "from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58])\n\tby Forcepoint Email with ESMTP id 9684FDA074A28E8A0F84;\n\tFri, 23 Aug 2019 21:49:31 +0800 (CST)", "from localhost.localdomain (10.67.212.132) by\n\tDGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP\n\tServer id 14.3.439.0; Fri, 23 Aug 2019 21:49:24 +0800" ], "From": "\"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<linuxarm@huawei.com>, <xavier_huwei@163.com>, <liudongdong3@huawei.com>,\n\t<forest.zhouchang@huawei.com>", "Date": "Fri, 23 Aug 2019 21:46:50 +0800", "Message-ID": "<1566568031-45991-2-git-send-email-xavier.huwei@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "References": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.212.132]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH 01/22] net/hns3: add hardware registers definition", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The Hisilicon Network Subsytem is a long term evolution IP which is\nsupposed to be used in Hisilicon ICT SoCs such as Kunpeng 920.\n\nThis patch adds hardware definition header file for hns3(Hisilicon\nNetwork Subsystem 3) PMD driver.\n\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\nSigned-off-by: Chunsong Feng <fengchunsong@huawei.com>\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\nSigned-off-by: Hao Chen <chenhao164@huawei.com>\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\n---\n drivers/net/hns3/hns3_regs.h | 98 ++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 98 insertions(+)\n create mode 100644 drivers/net/hns3/hns3_regs.h", "diff": "diff --git a/drivers/net/hns3/hns3_regs.h b/drivers/net/hns3/hns3_regs.h\nnew file mode 100644\nindex 0000000..5a4f315\n--- /dev/null\n+++ b/drivers/net/hns3/hns3_regs.h\n@@ -0,0 +1,98 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2019 Hisilicon Limited.\n+ */\n+\n+#ifndef _HNS3_REGS_H_\n+#define _HNS3_REGS_H_\n+\n+/* bar registers for cmdq */\n+#define HNS3_CMDQ_TX_ADDR_L_REG\t\t0x27000\n+#define HNS3_CMDQ_TX_ADDR_H_REG\t\t0x27004\n+#define HNS3_CMDQ_TX_DEPTH_REG\t\t0x27008\n+#define HNS3_CMDQ_TX_TAIL_REG\t\t0x27010\n+#define HNS3_CMDQ_TX_HEAD_REG\t\t0x27014\n+#define HNS3_CMDQ_RX_ADDR_L_REG\t\t0x27018\n+#define HNS3_CMDQ_RX_ADDR_H_REG\t\t0x2701c\n+#define HNS3_CMDQ_RX_DEPTH_REG\t\t0x27020\n+#define HNS3_CMDQ_RX_TAIL_REG\t\t0x27024\n+#define HNS3_CMDQ_RX_HEAD_REG\t\t0x27028\n+#define HNS3_CMDQ_INTR_STS_REG\t\t0x27104\n+#define HNS3_CMDQ_INTR_EN_REG\t\t0x27108\n+#define HNS3_CMDQ_INTR_GEN_REG\t\t0x2710C\n+\n+/* Vector0 interrupt CMDQ event source register(RW) */\n+#define HNS3_VECTOR0_CMDQ_SRC_REG\t0x27100\n+/* Vector0 interrupt CMDQ event status register(RO) */\n+#define HNS3_VECTOR0_CMDQ_STAT_REG\t0x27104\n+\n+#define HNS3_VECTOR0_OTHER_INT_STS_REG\t0x20800\n+\n+#define HNS3_MISC_VECTOR_REG_BASE\t0x20400\n+#define HNS3_VECTOR0_OTER_EN_REG\t0x20600\n+#define HNS3_MISC_RESET_STS_REG\t\t0x20700\n+#define HNS3_GLOBAL_RESET_REG\t\t0x20A00\n+#define HNS3_FUN_RST_ING\t\t0x20C00\n+#define HNS3_GRO_EN_REG\t\t\t0x28000\n+\n+/* Vector0 register bits for reset */\n+#define HNS3_VECTOR0_FUNCRESET_INT_B\t0\n+#define HNS3_VECTOR0_GLOBALRESET_INT_B\t5\n+#define HNS3_VECTOR0_CORERESET_INT_B\t6\n+#define HNS3_VECTOR0_IMPRESET_INT_B\t7\n+\n+/* CMDQ register bits for RX event(=MBX event) */\n+#define HNS3_VECTOR0_RX_CMDQ_INT_B\t1\n+#define HNS3_VECTOR0_REG_MSIX_MASK\t0x1FF00\n+/* RST register bits for RESET event */\n+#define HNS3_VECTOR0_RST_INT_B\t2\n+\n+#define HNS3_VF_RST_ING\t\t\t0x07008\n+#define HNS3_VF_RST_ING_BIT\t\tBIT(16)\n+\n+/* bar registers for rcb */\n+#define HNS3_RING_RX_BASEADDR_L_REG\t\t0x00000\n+#define HNS3_RING_RX_BASEADDR_H_REG\t\t0x00004\n+#define HNS3_RING_RX_BD_NUM_REG\t\t\t0x00008\n+#define HNS3_RING_RX_BD_LEN_REG\t\t\t0x0000C\n+#define HNS3_RING_RX_MERGE_EN_REG\t\t0x00014\n+#define HNS3_RING_RX_TAIL_REG\t\t\t0x00018\n+#define HNS3_RING_RX_HEAD_REG\t\t\t0x0001C\n+#define HNS3_RING_RX_FBDNUM_REG\t\t\t0x00020\n+#define HNS3_RING_RX_OFFSET_REG\t\t\t0x00024\n+#define HNS3_RING_RX_FBD_OFFSET_REG\t\t0x00028\n+#define HNS3_RING_RX_PKTNUM_RECORD_REG\t\t0x0002C\n+#define HNS3_RING_RX_STASH_REG\t\t\t0x00030\n+#define HNS3_RING_RX_BD_ERR_REG\t\t\t0x00034\n+\n+#define HNS3_RING_TX_BASEADDR_L_REG\t\t0x00040\n+#define HNS3_RING_TX_BASEADDR_H_REG\t\t0x00044\n+#define HNS3_RING_TX_BD_NUM_REG\t\t\t0x00048\n+#define HNS3_RING_TX_PRIORITY_REG\t\t0x0004C\n+#define HNS3_RING_TX_TC_REG\t\t\t0x00050\n+#define HNS3_RING_TX_MERGE_EN_REG\t\t0x00054\n+#define HNS3_RING_TX_TAIL_REG\t\t\t0x00058\n+#define HNS3_RING_TX_HEAD_REG\t\t\t0x0005C\n+#define HNS3_RING_TX_FBDNUM_REG\t\t\t0x00060\n+#define HNS3_RING_TX_OFFSET_REG\t\t\t0x00064\n+#define HNS3_RING_TX_EBD_NUM_REG\t\t0x00068\n+#define HNS3_RING_TX_PKTNUM_RECORD_REG\t\t0x0006C\n+#define HNS3_RING_TX_EBD_OFFSET_REG\t\t0x00070\n+#define HNS3_RING_TX_BD_ERR_REG\t\t\t0x00074\n+\n+#define HNS3_RING_EN_REG\t\t\t0x00090\n+\n+#define HNS3_RING_EN_B\t\t\t\t0\n+\n+#define HNS3_TQP_REG_OFFSET\t\t\t0x80000\n+#define HNS3_TQP_REG_SIZE\t\t\t0x200\n+\n+/* bar registers for tqp interrupt */\n+#define HNS3_TQP_INTR_CTRL_REG\t\t\t0x20000\n+#define HNS3_TQP_INTR_GL0_REG\t\t\t0x20100\n+#define HNS3_TQP_INTR_GL1_REG\t\t\t0x20200\n+#define HNS3_TQP_INTR_GL2_REG\t\t\t0x20300\n+#define HNS3_TQP_INTR_RL_REG\t\t\t0x20900\n+\n+#define HNS3_TQP_INTR_REG_SIZE\t\t\t4\n+\n+#endif /* _HNS3_REGS_H_ */\n", "prefixes": [ "01/22" ] }