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GET /api/patches/57843/?format=api
{ "id": 57843, "url": "http://patches.dpdk.org/api/patches/57843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-3-git-send-email-xavier.huwei@huawei.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1566568031-45991-3-git-send-email-xavier.huwei@huawei.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1566568031-45991-3-git-send-email-xavier.huwei@huawei.com", "date": "2019-08-23T13:46:51", "name": "[02/22] net/hns3: add some definitions for data structure and macro", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "c41c51e374f8e0f23ed54b17b7b5b38e206d1e38", "submitter": { "id": 1405, "url": "http://patches.dpdk.org/api/people/1405/?format=api", "name": "Wei Hu (Xavier)", "email": "xavier.huwei@huawei.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1566568031-45991-3-git-send-email-xavier.huwei@huawei.com/mbox/", "series": [ { "id": 6114, "url": "http://patches.dpdk.org/api/series/6114/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=6114", "date": "2019-08-23T13:46:49", "name": "add hns3 ethernet PMD driver", "version": 1, "mbox": "http://patches.dpdk.org/series/6114/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57843/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/57843/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 057A11BFC4;\n\tFri, 23 Aug 2019 15:49:37 +0200 (CEST)", "from huawei.com (szxga07-in.huawei.com [45.249.212.35])\n\tby dpdk.org (Postfix) with ESMTP id 14B941BFB4\n\tfor <dev@dpdk.org>; Fri, 23 Aug 2019 15:49:33 +0200 (CEST)", "from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58])\n\tby Forcepoint Email with ESMTP id 9A9CD3F019876348F136;\n\tFri, 23 Aug 2019 21:49:31 +0800 (CST)", "from localhost.localdomain (10.67.212.132) by\n\tDGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP\n\tServer id 14.3.439.0; Fri, 23 Aug 2019 21:49:25 +0800" ], "From": "\"Wei Hu (Xavier)\" <xavier.huwei@huawei.com>", "To": "<dev@dpdk.org>", "CC": "<linuxarm@huawei.com>, <xavier_huwei@163.com>, <liudongdong3@huawei.com>,\n\t<forest.zhouchang@huawei.com>", "Date": "Fri, 23 Aug 2019 21:46:51 +0800", "Message-ID": "<1566568031-45991-3-git-send-email-xavier.huwei@huawei.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "References": "<1566568031-45991-1-git-send-email-xavier.huwei@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.212.132]", "X-CFilter-Loop": "Reflected", "Subject": "[dpdk-dev] [PATCH 02/22] net/hns3: add some definitions for data\n\tstructure and macro", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds some data structure definitions, macro definitions and\ninline functions for hns3 PMD drivers.\n\nSigned-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>\nSigned-off-by: Chunsong Feng <fengchunsong@huawei.com>\nSigned-off-by: Min Hu (Connor) <humin29@huawei.com>\nSigned-off-by: Hao Chen <chenhao164@huawei.com>\nSigned-off-by: Huisong Li <lihuisong@huawei.com>\n---\n drivers/net/hns3/hns3_ethdev.h | 609 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 609 insertions(+)\n create mode 100644 drivers/net/hns3/hns3_ethdev.h", "diff": "diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h\nnew file mode 100644\nindex 0000000..bfb54f2\n--- /dev/null\n+++ b/drivers/net/hns3/hns3_ethdev.h\n@@ -0,0 +1,609 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2019 Hisilicon Limited.\n+ */\n+\n+#ifndef _HNS3_ETHDEV_H_\n+#define _HNS3_ETHDEV_H_\n+\n+#include <sys/time.h>\n+#include <rte_alarm.h>\n+\n+/* Vendor ID */\n+#define PCI_VENDOR_ID_HUAWEI\t\t\t0x19e5\n+\n+/* Device IDs */\n+#define HNS3_DEV_ID_GE\t\t\t\t0xA220\n+#define HNS3_DEV_ID_25GE\t\t\t0xA221\n+#define HNS3_DEV_ID_25GE_RDMA\t\t\t0xA222\n+#define HNS3_DEV_ID_50GE_RDMA\t\t\t0xA224\n+#define HNS3_DEV_ID_100G_RDMA_MACSEC\t\t0xA226\n+#define HNS3_DEV_ID_100G_VF\t\t\t0xA22E\n+#define HNS3_DEV_ID_100G_RDMA_PFC_VF\t\t0xA22F\n+\n+#define HNS3_UC_MACADDR_NUM\t\t96\n+#define HNS3_MC_MACADDR_NUM\t\t128\n+\n+#define HNS3_MAX_BD_SIZE\t\t65535\n+#define HNS3_MAX_TX_BD_PER_PKT\t\t8\n+#define HNS3_MAX_FRAME_LEN\t\t9728\n+#define HNS3_MIN_FRAME_LEN\t\t64\n+#define HNS3_VLAN_TAG_SIZE\t\t4\n+#define HNS3_DEFAULT_RX_BUF_LEN\t\t2048\n+\n+#define HNS3_ETH_OVERHEAD \\\n+\t(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)\n+#define HNS3_PKTLEN_TO_MTU(pktlen)\t((pktlen) - HNS3_ETH_OVERHEAD)\n+#define HNS3_MAX_MTU\t(HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)\n+#define HNS3_DEFAULT_MTU\t\t1500UL\n+#define HNS3_DEFAULT_FRAME_LEN\t\t(HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)\n+\n+#define HNS3_4_TCS\t\t\t4\n+#define HNS3_8_TCS\t\t\t8\n+#define HNS3_MAX_TC_NUM\t\t\t8\n+\n+#define HNS3_MAX_PF_NUM\t\t\t8\n+#define HNS3_UMV_TBL_SIZE\t\t3072\n+#define HNS3_DEFAULT_UMV_SPACE_PER_PF \\\n+\t(HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)\n+\n+#define HNS3_PF_CFG_BLOCK_SIZE\t\t32\n+#define HNS3_PF_CFG_DESC_NUM \\\n+\t(HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)\n+\n+#define HNS3_DEFAULT_ENABLE_PFC_NUM\t0\n+\n+#define HNS3_INTR_UNREG_FAIL_RETRY_CNT\t5\n+#define HNS3_INTR_UNREG_FAIL_DELAY_MS\t500\n+\n+#define HNS3_QUIT_RESET_CNT\t\t10\n+#define HNS3_QUIT_RESET_DELAY_MS\t100\n+\n+#define HNS3_POLL_RESPONE_MS\t\t1\n+\n+#define HNS3_MAX_USER_PRIO\t\t8\n+#define HNS3_PG_NUM\t\t\t4\n+enum hns3_fc_mode {\n+\tHNS3_FC_NONE,\n+\tHNS3_FC_RX_PAUSE,\n+\tHNS3_FC_TX_PAUSE,\n+\tHNS3_FC_FULL,\n+\tHNS3_FC_DEFAULT\n+};\n+\n+#define HNS3_SCH_MODE_SP\t0\n+#define HNS3_SCH_MODE_DWRR\t1\n+struct hns3_pg_info {\n+\tuint8_t pg_id;\n+\tuint8_t pg_sch_mode; /* 0: sp; 1: dwrr */\n+\tuint8_t tc_bit_map;\n+\tuint32_t bw_limit;\n+\tuint8_t tc_dwrr[HNS3_MAX_TC_NUM];\n+};\n+\n+struct hns3_tc_info {\n+\tuint8_t tc_id;\n+\tuint8_t tc_sch_mode; /* 0: sp; 1: dwrr */\n+\tuint8_t pgid;\n+\tuint32_t bw_limit;\n+\tuint8_t up_to_tc_map; /* user priority maping on the TC */\n+};\n+\n+struct hns3_dcb_info {\n+\tuint8_t num_tc;\n+\tuint8_t num_pg; /* It must be 1 if vNET-Base schd */\n+\tuint8_t pg_dwrr[HNS3_PG_NUM];\n+\tuint8_t prio_tc[HNS3_MAX_USER_PRIO];\n+\tstruct hns3_pg_info pg_info[HNS3_PG_NUM];\n+\tstruct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];\n+\tuint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */\n+\tuint8_t pfc_en; /* Pfc enabled or not for user priority */\n+};\n+\n+enum hns3_fc_status {\n+\tHNS3_FC_STATUS_NONE,\n+\tHNS3_FC_STATUS_MAC_PAUSE,\n+\tHNS3_FC_STATUS_PFC,\n+};\n+\n+struct hns3_tc_queue_info {\n+\tuint8_t\ttqp_offset; /* TQP offset from base TQP */\n+\tuint8_t\ttqp_count; /* Total TQPs */\n+\tuint8_t\ttc; /* TC index */\n+\tbool enable; /* If this TC is enable or not */\n+};\n+\n+struct hns3_cfg {\n+\tuint8_t vmdq_vport_num;\n+\tuint8_t tc_num;\n+\tuint16_t tqp_desc_num;\n+\tuint16_t rx_buf_len;\n+\tuint16_t rss_size_max;\n+\tuint8_t phy_addr;\n+\tuint8_t media_type;\n+\tuint8_t mac_addr[RTE_ETHER_ADDR_LEN];\n+\tuint8_t default_speed;\n+\tuint32_t numa_node_map;\n+\tuint8_t speed_ability;\n+\tuint16_t umv_space;\n+};\n+\n+/* mac media type */\n+enum hns3_media_type {\n+\tHNS3_MEDIA_TYPE_UNKNOWN,\n+\tHNS3_MEDIA_TYPE_FIBER,\n+\tHNS3_MEDIA_TYPE_COPPER,\n+\tHNS3_MEDIA_TYPE_BACKPLANE,\n+\tHNS3_MEDIA_TYPE_NONE,\n+};\n+\n+struct hns3_mac {\n+\tuint8_t mac_addr[RTE_ETHER_ADDR_LEN];\n+\tbool default_addr_setted; /* whether default addr(mac_addr) is setted */\n+\tuint8_t media_type;\n+\tuint8_t phy_addr;\n+\tuint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */\n+\tuint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */\n+\tuint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */\n+\tuint32_t link_speed; /* ETH_SPEED_NUM_ */\n+};\n+\n+\n+/* Primary process maintains driver state in main thread.\n+ *\n+ * +---------------+\n+ * | UNINITIALIZED |<-----------+\n+ * +---------------+\t\t|\n+ *\t|.eth_dev_init\t\t|.eth_dev_uninit\n+ *\tV\t\t\t|\n+ * +---------------+------------+\n+ * | INITIALIZED |\n+ * +---------------+<-----------<---------------+\n+ *\t|.dev_configure\t\t|\t\t|\n+ *\tV\t\t\t|failed\t\t|\n+ * +---------------+------------+\t\t|\n+ * | CONFIGURING |\t\t\t\t|\n+ * +---------------+----+\t\t\t|\n+ *\t|success\t|\t\t\t|\n+ *\t|\t\t|\t\t+---------------+\n+ *\t|\t\t|\t\t| CLOSING |\n+ *\t|\t\t|\t\t+---------------+\n+ *\t|\t\t|\t\t\t^\n+ *\tV\t\t|.dev_configure\t\t|\n+ * +---------------+----+\t\t\t|.dev_close\n+ * | CONFIGURED |----------------------------+\n+ * +---------------+<-----------+\n+ *\t|.dev_start\t\t|\n+ *\tV\t\t\t|\n+ * +---------------+\t\t|\n+ * | STARTING |------------^\n+ * +---------------+ failed\t|\n+ *\t|success\t\t|\n+ *\t|\t\t+---------------+\n+ *\t|\t\t| STOPPING |\n+ *\t|\t\t+---------------+\n+ *\t|\t\t\t^\n+ *\tV\t\t\t|.dev_stop\n+ * +---------------+------------+\n+ * | STARTED |\n+ * +---------------+\n+ */\n+enum hns3_adapter_state {\n+\tHNS3_NIC_UNINITIALIZED = 0,\n+\tHNS3_NIC_INITIALIZED,\n+\tHNS3_NIC_CONFIGURING,\n+\tHNS3_NIC_CONFIGURED,\n+\tHNS3_NIC_STARTING,\n+\tHNS3_NIC_STARTED,\n+\tHNS3_NIC_STOPPING,\n+\tHNS3_NIC_CLOSING,\n+\tHNS3_NIC_CLOSED,\n+\tHNS3_NIC_REMOVED,\n+\tHNS3_NIC_NSTATES\n+};\n+\n+/* Reset various stages, execute in order */\n+enum hns3_reset_stage {\n+\t/* Stop query services, stop transceiver, disable MAC */\n+\tRESET_STAGE_DOWN,\n+\t/* Clear reset completion flags, disable send command */\n+\tRESET_STAGE_PREWAIT,\n+\t/* Inform IMP to start resetting */\n+\tRESET_STAGE_REQ_HW_RESET,\n+\t/* Waiting for hardware reset to complete */\n+\tRESET_STAGE_WAIT,\n+\t/* Reinitialize hardware */\n+\tRESET_STAGE_DEV_INIT,\n+\t/* Restore user settings and enable MAC */\n+\tRESET_STAGE_RESTORE,\n+\t/* Restart query services, start transceiver */\n+\tRESET_STAGE_DONE,\n+\t/* Not in reset state */\n+\tRESET_STAGE_NONE,\n+};\n+\n+enum hns3_reset_level {\n+\tHNS3_NONE_RESET,\n+\tHNS3_VF_FUNC_RESET, /* A VF function reset */\n+\t/*\n+\t * All VFs under a PF perform function reset.\n+\t * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value\n+\t * of the reset level and the one defined in kernel driver should be\n+\t * same.\n+\t */\n+\tHNS3_VF_PF_FUNC_RESET = 2,\n+\t/*\n+\t * All VFs under a PF perform FLR reset.\n+\t * Kernel PF driver use mailbox to inform DPDK VF to do reset, the value\n+\t * of the reset level and the one defined in kernel driver should be\n+\t * same.\n+\t */\n+\tHNS3_VF_FULL_RESET = 3,\n+\tHNS3_FLR_RESET, /* A VF perform FLR reset */\n+\t/* All VFs under the rootport perform a global or IMP reset */\n+\tHNS3_VF_RESET,\n+\tHNS3_FUNC_RESET, /* A PF function reset */\n+\t/* All PFs under the rootport perform a global reset */\n+\tHNS3_GLOBAL_RESET,\n+\tHNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */\n+\tHNS3_MAX_RESET\n+};\n+\n+enum hns3_wait_result {\n+\tHNS3_WAIT_UNKNOWN,\n+\tHNS3_WAIT_REQUEST,\n+\tHNS3_WAIT_SUCCESS,\n+\tHNS3_WAIT_TIMEOUT\n+};\n+\n+#define HNS3_RESET_SYNC_US 100000\n+\n+struct hns3_reset_stats {\n+\tuint64_t request_cnt; /* Total request reset times */\n+\tuint64_t global_cnt; /* Total GLOBAL reset times */\n+\tuint64_t imp_cnt; /* Total IMP reset times */\n+\tuint64_t exec_cnt; /* Total reset executive times */\n+\tuint64_t success_cnt; /* Total reset successful times */\n+\tuint64_t fail_cnt; /* Total reset failed times */\n+\tuint64_t merge_cnt; /* Total merged in high reset times */\n+};\n+\n+typedef bool (*check_completion_func)(struct hns3_hw *hw);\n+\n+struct hns3_wait_data {\n+\tvoid *hns;\n+\tuint64_t end_ms;\n+\tuint64_t interval;\n+\tint16_t count;\n+\tenum hns3_wait_result result;\n+\tcheck_completion_func check_completion;\n+};\n+\n+struct hns3_reset_ops {\n+\tvoid (*reset_service)(void *arg);\n+\tint (*stop_service)(struct hns3_adapter *hns);\n+\tint (*prepare_reset)(struct hns3_adapter *hns);\n+\tint (*wait_hardware_ready)(struct hns3_adapter *hns);\n+\tint (*reinit_dev)(struct hns3_adapter *hns);\n+\tint (*restore_conf)(struct hns3_adapter *hns);\n+\tint (*start_service)(struct hns3_adapter *hns);\n+};\n+\n+enum hns3_schedule {\n+\tSCHEDULE_NONE,\n+\tSCHEDULE_PENDING,\n+\tSCHEDULE_REQUESTED,\n+\tSCHEDULE_DEFERRED,\n+};\n+\n+struct hns3_reset_data {\n+\tenum hns3_reset_stage stage;\n+\trte_atomic16_t schedule;\n+\t/* Reset flag, covering the entire reset process */\n+\trte_atomic16_t resetting;\n+\t/* Used to disable sending cmds during reset */\n+\trte_atomic16_t disable_cmd;\n+\t/* The reset level being processed */\n+\tenum hns3_reset_level level;\n+\t/* Reset level set, each bit represents a reset level */\n+\tuint64_t pending;\n+\t/* Request reset level set, from interrupt or mailbox */\n+\tuint64_t request;\n+\tint attempts; /* Reset failure retry */\n+\tint retries; /* Timeout failure retry in reset_post */\n+\t/*\n+\t * At the time of global or IMP reset, the command cannot be sent to\n+\t * stop the tx/rx queues. Tx/Rx queues may be access mbuf during the\n+\t * reset process, so the mbuf is required to be released after the reset\n+\t * is completed.The mbuf_deferred_free is used to mark whether mbuf\n+\t * needs to be released.\n+\t */\n+\tbool mbuf_deferred_free;\n+\tstruct timeval start_time;\n+\tstruct hns3_reset_stats stats;\n+\tconst struct hns3_reset_ops *ops;\n+\tstruct hns3_wait_data *wait_data;\n+};\n+\n+struct hns3_hw {\n+\tstruct rte_eth_dev_data *data;\n+\tvoid *io_base;\n+\tstruct hns3_mac mac;\n+\tunsigned int secondary_cnt; /* Number of secondary processes init'd. */\n+\tuint32_t fw_version;\n+\n+\tuint16_t num_msi;\n+\tuint16_t total_tqps_num; /* total task queue pairs of this PF */\n+\tuint16_t tqps_num; /* num task queue pairs of this function */\n+\tuint16_t rss_size_max; /* HW defined max RSS task queue */\n+\tuint16_t rx_buf_len;\n+\tuint16_t num_tx_desc; /* desc num of per tx queue */\n+\tuint16_t num_rx_desc; /* desc num of per rx queue */\n+\n+\tstruct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];\n+\tint mc_addrs_num; /* Multicast mac addresses number */\n+\n+\tuint8_t num_tc; /* Total number of enabled TCs */\n+\tuint8_t hw_tc_map;\n+\tenum hns3_fc_mode current_mode;\n+\tenum hns3_fc_mode requested_mode;\n+\tstruct hns3_dcb_info dcb_info;\n+\tenum hns3_fc_status current_fc_status; /* current flow control status */\n+\tstruct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];\n+\tuint16_t alloc_tqps;\n+\tuint16_t alloc_rss_size; /* Queue number per TC */\n+\n+\tuint32_t flag;\n+\t/*\n+\t * PMD setup and configuration is not thread safe. Since it is not\n+\t * performance sensitive, it is better to guarantee thread-safety\n+\t * and add device level lock. Adapter control operations which\n+\t * change its state should acquire the lock.\n+\t */\n+\trte_spinlock_t lock;\n+\tenum hns3_adapter_state adapter_state;\n+\tstruct hns3_reset_data reset;\n+};\n+\n+#define HNS3_FLAG_TC_BASE_SCH_MODE\t\t1\n+#define HNS3_FLAG_VNET_BASE_SCH_MODE\t\t2\n+\n+struct hns3_err_msix_intr_stats {\n+\tuint64_t mac_afifo_tnl_intr_cnt;\n+\tuint64_t ppu_mpf_abnormal_intr_st2_cnt;\n+\tuint64_t ssu_port_based_pf_intr_cnt;\n+\tuint64_t ppp_pf_abnormal_intr_cnt;\n+\tuint64_t ppu_pf_abnormal_intr_cnt;\n+};\n+\n+/* vlan entry information. */\n+struct hns3_user_vlan_table {\n+\tLIST_ENTRY(hns3_user_vlan_table) next;\n+\tbool hd_tbl_status;\n+\tuint16_t vlan_id;\n+};\n+\n+struct hns3_port_base_vlan_config {\n+\tuint16_t state;\n+\tuint16_t pvid;\n+};\n+\n+/* Vlan tag configuration for RX direction */\n+struct hns3_rx_vtag_cfg {\n+\tuint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */\n+\tuint8_t strip_tag1_en; /* Whether strip inner vlan tag */\n+\tuint8_t strip_tag2_en; /* Whether strip outer vlan tag */\n+\tuint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */\n+\tuint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */\n+};\n+\n+/* Vlan tag configuration for TX direction */\n+struct hns3_tx_vtag_cfg {\n+\tbool accept_tag1; /* Whether accept tag1 packet from host */\n+\tbool accept_untag1; /* Whether accept untag1 packet from host */\n+\tbool accept_tag2;\n+\tbool accept_untag2;\n+\tbool insert_tag1_en; /* Whether insert inner vlan tag */\n+\tbool insert_tag2_en; /* Whether insert outer vlan tag */\n+\tuint16_t default_tag1; /* The default inner vlan tag to insert */\n+\tuint16_t default_tag2; /* The default outer vlan tag to insert */\n+};\n+\n+struct hns3_vtag_cfg {\n+\tstruct hns3_rx_vtag_cfg rx_vcfg;\n+\tstruct hns3_tx_vtag_cfg tx_vcfg;\n+};\n+\n+/* Request types for IPC. */\n+enum hns3_mp_req_type {\n+\tHNS3_MP_REQ_START_RXTX = 1,\n+\tHNS3_MP_REQ_STOP_RXTX,\n+\tHNS3_MP_REQ_MAX\n+};\n+\n+/* Pameters for IPC. */\n+struct hns3_mp_param {\n+\tenum hns3_mp_req_type type;\n+\tint port_id;\n+\tint result;\n+};\n+\n+/* Request timeout for IPC. */\n+#define HNS3_MP_REQ_TIMEOUT_SEC 5\n+\n+/* Key string for IPC. */\n+#define HNS3_MP_NAME \"net_hns3_mp\"\n+\n+struct hns3_pf {\n+\tstruct hns3_adapter *adapter;\n+\tbool is_main_pf;\n+\n+\tuint32_t pkt_buf_size; /* Total pf buf size for tx/rx */\n+\tuint32_t tx_buf_size; /* Tx buffer size for each TC */\n+\tuint32_t dv_buf_size; /* Dv buffer size for each TC */\n+\n+\tuint16_t mps; /* Max packet size */\n+\n+\tuint8_t tx_sch_mode;\n+\tuint8_t tc_max; /* max number of tc driver supported */\n+\tuint8_t local_max_tc; /* max number of local tc */\n+\tuint8_t pfc_max;\n+\tuint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */\n+\tuint16_t pause_time;\n+\tbool support_fc_autoneg; /* support FC autonegotiate */\n+\n+\tuint16_t wanted_umv_size;\n+\tuint16_t max_umv_size;\n+\tuint16_t used_umv_size;\n+\n+\t/* Statistics information for abnormal interrupt */\n+\tstruct hns3_err_msix_intr_stats abn_int_stats;\n+\n+\tbool support_sfp_query;\n+\n+\tstruct hns3_vtag_cfg vtag_config;\n+\tstruct hns3_port_base_vlan_config port_base_vlan_cfg;\n+\tLIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;\n+};\n+\n+struct hns3_vf {\n+\tstruct hns3_adapter *adapter;\n+};\n+\n+struct hns3_adapter {\n+\tstruct hns3_hw hw;\n+\n+\t/* Specific for PF or VF */\n+\tbool is_vf; /* false - PF, true - VF */\n+\tunion {\n+\t\tstruct hns3_pf pf;\n+\t\tstruct hns3_vf vf;\n+\t};\n+};\n+\n+#define HNS3_DEV_SUPPORT_DCB_B\t\t\t0x0\n+\n+#define hns3_dev_dcb_supported(hw) \\\n+\thns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B)\n+\n+#define HNS3_DEV_PRIVATE_TO_HW(adapter) \\\n+\t(&((struct hns3_adapter *)adapter)->hw)\n+#define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \\\n+\t((struct hns3_adapter *)adapter)\n+#define HNS3_DEV_PRIVATE_TO_PF(adapter) \\\n+\t(&((struct hns3_adapter *)adapter)->pf)\n+#define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \\\n+\t(&((struct hns3_adapter *)adapter)->vf)\n+#define HNS3_DEV_HW_TO_ADAPTER(hw) \\\n+\tcontainer_of(hw, struct hns3_adapter, hw)\n+\n+#define hns3_set_field(origin, mask, shift, val) \\\n+\tdo { \\\n+\t\t(origin) &= (~(mask)); \\\n+\t\t(origin) |= ((val) << (shift)) & (mask); \\\n+\t} while (0)\n+#define hns3_get_field(origin, mask, shift) \\\n+\t(((origin) & (mask)) >> (shift))\n+#define hns3_set_bit(origin, shift, val) \\\n+\thns3_set_field((origin), (0x1UL << (shift)), (shift), (val))\n+#define hns3_get_bit(origin, shift) \\\n+\thns3_get_field((origin), (0x1UL << (shift)), (shift))\n+\n+/*\n+ * upper_32_bits - return bits 32-63 of a number\n+ * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress\n+ * the \"right shift count >= width of type\" warning when that quantity is\n+ * 32-bits.\n+ */\n+#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))\n+\n+/* lower_32_bits - return bits 0-31 of a number */\n+#define lower_32_bits(n) ((uint32_t)(n))\n+\n+#define BIT(nr) (1UL << (nr))\n+\n+#define BITS_PER_LONG\t(__SIZEOF_LONG__ * 8)\n+#define GENMASK(h, l) \\\n+\t(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))\n+\n+#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))\n+#define rounddown(x, y) ((x) - ((x) % (y)))\n+\n+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n+\n+#define max_t(type, x, y) ({ \\\n+\ttype __max1 = (x); \\\n+\ttype __max2 = (y); \\\n+\t__max1 > __max2 ? __max1 : __max2; })\n+\n+static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)\n+{\n+\trte_write32(value, (volatile void *)((char *)base + reg));\n+}\n+\n+static inline uint32_t hns3_read_reg(void *base, uint32_t reg)\n+{\n+\treturn rte_read32((volatile void *)((char *)base + reg));\n+}\n+\n+#define hns3_write_dev(a, reg, value) \\\n+\thns3_write_reg((a)->io_base, (reg), (value))\n+\n+#define hns3_read_dev(a, reg) \\\n+\thns3_read_reg((a)->io_base, (reg))\n+\n+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\n+\n+#define NEXT_ITEM_OF_ACTION(act, actions, index) \\\n+\tdo {\t\t\t\t\t\t\t\t\\\n+\t\tact = (actions) + (index);\t\t\t\t\\\n+\t\twhile (act->type == RTE_FLOW_ACTION_TYPE_VOID) {\t\\\n+\t\t\t(index)++;\t\t\t\t\t\\\n+\t\t\tact = actions + index;\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t} while (0)\n+\n+#define MSEC_PER_SEC 1000L\n+#define USEC_PER_MSEC 1000L\n+\n+static inline uint64_t\n+get_timeofday_ms(void)\n+{\n+\tstruct timeval tv;\n+\n+\t(void)gettimeofday(&tv, NULL);\n+\n+\treturn (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;\n+}\n+\n+static inline uint64_t\n+hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)\n+{\n+\tuint64_t res;\n+\n+\trte_mb();\n+\tres = ((*addr) & (1UL << nr)) != 0;\n+\trte_mb();\n+\treturn res;\n+}\n+\n+static inline void\n+hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)\n+{\n+\t__sync_fetch_and_or(addr, (1UL << nr));\n+}\n+\n+static inline void\n+hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)\n+{\n+\t__sync_fetch_and_and(addr, ~(1UL << nr));\n+}\n+\n+static inline int64_t\n+hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)\n+{\n+\tuint64_t mask = (1UL << nr);\n+\n+\treturn __sync_fetch_and_and(addr, ~mask) & mask;\n+}\n+\n+#endif /* _HNS3_ETHDEV_H_ */\n", "prefixes": [ "02/22" ] }