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GET /api/patches/57380/?format=api
{ "id": 57380, "url": "http://patches.dpdk.org/api/patches/57380/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190802042006.14507-1-vattunuru@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190802042006.14507-1-vattunuru@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190802042006.14507-1-vattunuru@marvell.com", "date": "2019-08-02T04:20:06", "name": "[dpdk-devPATCH,v2,1/1] common/octeontx2: fix unaligned mbox memory accesses", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "553e4c3fed9e76dfb88991bfd08fd0d3f42748ae", "submitter": { "id": 1277, "url": "http://patches.dpdk.org/api/people/1277/?format=api", "name": "Vamsi Krishna Attunuru", "email": "vattunuru@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190802042006.14507-1-vattunuru@marvell.com/mbox/", "series": [ { "id": 5882, "url": "http://patches.dpdk.org/api/series/5882/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5882", "date": "2019-08-02T04:20:06", "name": "[dpdk-devPATCH,v2,1/1] common/octeontx2: fix unaligned mbox memory accesses", "version": 2, "mbox": "http://patches.dpdk.org/series/5882/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57380/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57380/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 51C651C219;\n\tFri, 2 Aug 2019 06:20:17 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id A9F771C212\n\tfor <dev@dpdk.org>; Fri, 2 Aug 2019 06:20:15 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx724IQuW023310; Thu, 1 Aug 2019 21:20:14 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2u42fsjs91-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 01 Aug 2019 21:20:14 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 1 Aug 2019 21:20:12 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 1 Aug 2019 21:20:12 -0700", "from hyd1vattunuru-dt.caveonetworks.com (unknown [10.29.52.72])\n\tby maili.marvell.com (Postfix) with ESMTP id 504CB3F703F;\n\tThu, 1 Aug 2019 21:20:10 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-type; s=pfpt0818;\n\tbh=spYmSOWCPZyDzgnHQ6egympE0qI93fupfA9iSZjdT5U=; \n\tb=O+7EYvx/UGWR93cHcIsgQyIc6bU/nTCOsuImsurgAr0EEI10yu0DNaVPk3XwZ6qHFQkN\n\tZj3CJWswoqMgK3woBBdNOiwQg0RC3/SKP78xW5S0x6YY4yEt+baj7dFQwJLoRuPVV6rp\n\tDjpPs9Sg3l3NFe1l/e78JWt6u4O90D08HYwRdGczEqL/dopqwh2U9Ha6b8fufOQHew89\n\tLq3MMFViOGh6iD/pFLVGDcpSZ1odKtz4kAhuPWPx0Bcw7k/VStuqDho3g5Z28LYF9Be2\n\t9zLOZQoQ/8JmnAAx1EkMvV2Jf84uGNc6aHn7glNcZ8vKBkDWOElwJkpF2tYWyMe8XxdG\n\tgw== ", "From": "<vattunuru@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <jerinj@marvell.com>, Vamsi Attunuru\n\t<vattunuru@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>", "Date": "Fri, 2 Aug 2019 09:50:06 +0530", "Message-ID": "<20190802042006.14507-1-vattunuru@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20190801182928.26216-1-vattunuru@marvell.com>", "References": "<20190801182928.26216-1-vattunuru@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:5.22.84,1.0.8\n\tdefinitions=2019-08-02_03:2019-07-31,2019-08-02 signatures=0", "Subject": "[dpdk-dev] [dpdk-devPATCH v2 1/1] common/octeontx2: fix unaligned\n\tmbox memory accesses", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Vamsi Attunuru <vattunuru@marvell.com>\n\nOcteontx2 PMD's mailbox client uses device memory to send messages\nto mailbox server in the admin function Linux kernel driver.\nThe device memory used for the mailbox communication needs to\nbe qualified as volatile memory type to avoid unaligned device\nmemory accesses because of compiler's memory access coalescing.\n\nThis patch modifies the mailbox request and responses as volatile\ntype which were non-volatile earlier and accessed from unaligned\nmemory addresses.\n\nFixes: 2b71657c8660 (\"common/octeontx2: add mbox request and response \")\n\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\nV2 Changes:\n* Moved __otx2_io to individual members to align with other mbox elements.\n* Updated commit message.\n\n drivers/common/octeontx2/otx2_mbox.h | 42 +++++++++++++-------------\n drivers/mempool/octeontx2/otx2_mempool_debug.c | 4 +--\n drivers/mempool/octeontx2/otx2_mempool_ops.c | 6 ++--\n drivers/net/octeontx2/otx2_ethdev_debug.c | 6 ++--\n 4 files changed, 29 insertions(+), 29 deletions(-)", "diff": "diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h\nindex b2c59c8..1bdaa91 100644\n--- a/drivers/common/octeontx2/otx2_mbox.h\n+++ b/drivers/common/octeontx2/otx2_mbox.h\n@@ -552,16 +552,16 @@ struct npa_aq_enq_req {\n \t\t * LF fills the pool_id in aura.pool_addr. AF will translate\n \t\t * the pool_id to pool context pointer.\n \t\t */\n-\t\tstruct npa_aura_s aura;\n+\t\t__otx2_io struct npa_aura_s aura;\n \t\t/* Valid when op == WRITE/INIT and ctype == POOL */\n-\t\tstruct npa_pool_s pool;\n+\t\t__otx2_io struct npa_pool_s pool;\n \t};\n \t/* Mask data when op == WRITE (1=write, 0=don't write) */\n \tunion {\n \t\t/* Valid when op == WRITE and ctype == AURA */\n-\t\tstruct npa_aura_s aura_mask;\n+\t\t__otx2_io struct npa_aura_s aura_mask;\n \t\t/* Valid when op == WRITE and ctype == POOL */\n-\t\tstruct npa_pool_s pool_mask;\n+\t\t__otx2_io struct npa_pool_s pool_mask;\n \t};\n };\n \n@@ -569,9 +569,9 @@ struct npa_aq_enq_rsp {\n \tstruct mbox_msghdr hdr;\n \tunion {\n \t\t/* Valid when op == READ and ctype == AURA */\n-\t\tstruct npa_aura_s aura;\n+\t\t__otx2_io struct npa_aura_s aura;\n \t\t/* Valid when op == READ and ctype == POOL */\n-\t\tstruct npa_pool_s pool;\n+\t\t__otx2_io struct npa_pool_s pool;\n \t};\n };\n \n@@ -655,39 +655,39 @@ struct nix_aq_enq_req {\n \tuint8_t __otx2_io op;\n \tunion {\n \t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */\n-\t\tstruct nix_rq_ctx_s rq;\n+\t\t__otx2_io struct nix_rq_ctx_s rq;\n \t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */\n-\t\tstruct nix_sq_ctx_s sq;\n+\t\t__otx2_io struct nix_sq_ctx_s sq;\n \t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */\n-\t\tstruct nix_cq_ctx_s cq;\n+\t\t__otx2_io struct nix_cq_ctx_s cq;\n \t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */\n-\t\tstruct nix_rsse_s rss;\n+\t\t__otx2_io struct nix_rsse_s rss;\n \t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */\n-\t\tstruct nix_rx_mce_s mce;\n+\t\t__otx2_io struct nix_rx_mce_s mce;\n \t};\n \t/* Mask data when op == WRITE (1=write, 0=don't write) */\n \tunion {\n \t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */\n-\t\tstruct nix_rq_ctx_s rq_mask;\n+\t\t__otx2_io struct nix_rq_ctx_s rq_mask;\n \t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */\n-\t\tstruct nix_sq_ctx_s sq_mask;\n+\t\t__otx2_io struct nix_sq_ctx_s sq_mask;\n \t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */\n-\t\tstruct nix_cq_ctx_s cq_mask;\n+\t\t__otx2_io struct nix_cq_ctx_s cq_mask;\n \t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */\n-\t\tstruct nix_rsse_s rss_mask;\n+\t\t__otx2_io struct nix_rsse_s rss_mask;\n \t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */\n-\t\tstruct nix_rx_mce_s mce_mask;\n+\t\t__otx2_io struct nix_rx_mce_s mce_mask;\n \t};\n };\n \n struct nix_aq_enq_rsp {\n \tstruct mbox_msghdr hdr;\n \tunion {\n-\t\tstruct nix_rq_ctx_s rq;\n-\t\tstruct nix_sq_ctx_s sq;\n-\t\tstruct nix_cq_ctx_s cq;\n-\t\tstruct nix_rsse_s rss;\n-\t\tstruct nix_rx_mce_s mce;\n+\t\t__otx2_io struct nix_rq_ctx_s rq;\n+\t\t__otx2_io struct nix_sq_ctx_s sq;\n+\t\t__otx2_io struct nix_cq_ctx_s cq;\n+\t\t__otx2_io struct nix_rsse_s rss;\n+\t\t__otx2_io struct nix_rx_mce_s mce;\n \t};\n };\n \ndiff --git a/drivers/mempool/octeontx2/otx2_mempool_debug.c b/drivers/mempool/octeontx2/otx2_mempool_debug.c\nindex eef61ef..4d40fde 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool_debug.c\n+++ b/drivers/mempool/octeontx2/otx2_mempool_debug.c\n@@ -7,7 +7,7 @@\n #define npa_dump(fmt, ...) fprintf(stderr, fmt \"\\n\", ##__VA_ARGS__)\n \n static inline void\n-npa_lf_pool_dump(struct npa_pool_s *pool)\n+npa_lf_pool_dump(__otx2_io struct npa_pool_s *pool)\n {\n \tnpa_dump(\"W0: Stack base\\t\\t0x%\"PRIx64\"\", pool->stack_base);\n \tnpa_dump(\"W1: ena \\t\\t%d\\nW1: nat_align \\t\\t%d\\nW1: stack_caching \\t%d\",\n@@ -45,7 +45,7 @@ npa_lf_pool_dump(struct npa_pool_s *pool)\n }\n \n static inline void\n-npa_lf_aura_dump(struct npa_aura_s *aura)\n+npa_lf_aura_dump(__otx2_io struct npa_aura_s *aura)\n {\n \tnpa_dump(\"W0: Pool addr\\t\\t0x%\"PRIx64\"\\n\", aura->pool_addr);\n \ndiff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c b/drivers/mempool/octeontx2/otx2_mempool_ops.c\nindex ff63be5..f5a4fe3 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool_ops.c\n+++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c\n@@ -355,14 +355,14 @@ npa_lf_aura_pool_init(struct otx2_mbox *mbox, uint32_t aura_id,\n \taura_init_req->aura_id = aura_id;\n \taura_init_req->ctype = NPA_AQ_CTYPE_AURA;\n \taura_init_req->op = NPA_AQ_INSTOP_INIT;\n-\tmemcpy(&aura_init_req->aura, aura, sizeof(*aura));\n+\totx2_mbox_memcpy(&aura_init_req->aura, aura, sizeof(*aura));\n \n \tpool_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n \n \tpool_init_req->aura_id = aura_id;\n \tpool_init_req->ctype = NPA_AQ_CTYPE_POOL;\n \tpool_init_req->op = NPA_AQ_INSTOP_INIT;\n-\tmemcpy(&pool_init_req->pool, pool, sizeof(*pool));\n+\totx2_mbox_memcpy(&pool_init_req->pool, pool, sizeof(*pool));\n \n \totx2_mbox_msg_send(mbox, 0);\n \trc = otx2_mbox_wait_for_rsp(mbox, 0);\n@@ -605,9 +605,9 @@ npa_lf_aura_range_update_check(uint64_t aura_handle)\n \tuint64_t aura_id = npa_lf_aura_handle_to_aura(aura_handle);\n \tstruct otx2_npa_lf *lf = otx2_npa_lf_obj_get();\n \tstruct npa_aura_lim *lim = lf->aura_lim;\n+\t__otx2_io struct npa_pool_s *pool;\n \tstruct npa_aq_enq_req *req;\n \tstruct npa_aq_enq_rsp *rsp;\n-\tstruct npa_pool_s *pool;\n \tint rc;\n \n \treq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_debug.c b/drivers/net/octeontx2/otx2_ethdev_debug.c\nindex 9f06e55..c8b4cd5 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_debug.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_debug.c\n@@ -235,7 +235,7 @@ otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n }\n \n static inline void\n-nix_lf_sq_dump(struct nix_sq_ctx_s *ctx)\n+nix_lf_sq_dump(__otx2_io struct nix_sq_ctx_s *ctx)\n {\n \tnix_dump(\"W0: sqe_way_mask \\t\\t%d\\nW0: cq \\t\\t\\t\\t%d\",\n \t\t ctx->sqe_way_mask, ctx->cq);\n@@ -295,7 +295,7 @@ nix_lf_sq_dump(struct nix_sq_ctx_s *ctx)\n }\n \n static inline void\n-nix_lf_rq_dump(struct nix_rq_ctx_s *ctx)\n+nix_lf_rq_dump(__otx2_io struct nix_rq_ctx_s *ctx)\n {\n \tnix_dump(\"W0: wqe_aura \\t\\t\\t%d\\nW0: substream \\t\\t\\t0x%03x\",\n \t\t ctx->wqe_aura, ctx->substream);\n@@ -355,7 +355,7 @@ nix_lf_rq_dump(struct nix_rq_ctx_s *ctx)\n }\n \n static inline void\n-nix_lf_cq_dump(struct nix_cq_ctx_s *ctx)\n+nix_lf_cq_dump(__otx2_io struct nix_cq_ctx_s *ctx)\n {\n \tnix_dump(\"W0: base \\t\\t\\t0x%\" PRIx64 \"\\n\", ctx->base);\n \n", "prefixes": [ "dpdk-devPATCH", "v2", "1/1" ] }