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GET /api/patches/57245/?format=api
{ "id": 57245, "url": "http://patches.dpdk.org/api/patches/57245/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1564404065-4823-4-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1564404065-4823-4-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1564404065-4823-4-git-send-email-viacheslavo@mellanox.com", "date": "2019-07-29T12:41:05", "name": "[3/3] net/mlx5: fix the Tx completion request generation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8cae0ce8542c6927821c2dfdbe342f39fa42e2c5", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1564404065-4823-4-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 5812, "url": "http://patches.dpdk.org/api/series/5812/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5812", "date": "2019-07-29T12:41:02", "name": "net/mlx5: transmit datapath cumulative fix pack", "version": 1, "mbox": "http://patches.dpdk.org/series/5812/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/57245/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/57245/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6A1081BF9F;\n\tMon, 29 Jul 2019 14:41:25 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 13AC31BF9D\n\tfor <dev@dpdk.org>; Mon, 29 Jul 2019 14:41:24 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tviacheslavo@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 29 Jul 2019 15:41:20 +0300", "from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx\n\t[10.210.17.40])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6TCfK5m010910;\n\tMon, 29 Jul 2019 15:41:20 +0300", "from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1])\n\tby pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id\n\tx6TCfKlf005053; Mon, 29 Jul 2019 12:41:20 GMT", "(from viacheslavo@localhost)\n\tby pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id x6TCfKTn005052; \n\tMon, 29 Jul 2019 12:41:20 GMT" ], "X-Authentication-Warning": "pegasus12.mtr.labs.mlnx: viacheslavo set sender to\n\tviacheslavo@mellanox.com using -f", "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "yskoh@mellanox.com, shahafs@mellanox.com", "Date": "Mon, 29 Jul 2019 12:41:05 +0000", "Message-Id": "<1564404065-4823-4-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1564404065-4823-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1564404065-4823-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 3/3] net/mlx5: fix the Tx completion request\n\tgeneration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The packets transmitting in mlx5 is performed by building\nTx descriptors (WQEs) and sending last ones to the NIC.\nThe descriptor can contain the special flags, telling the NIC\nto generate Tx completion notification (CQEs). At the beginning\nof tx_burst() routine PMD checks whether there are some Tx\ncompletions and frees the transmitted packet buffers.\n\nThe flags to request completion generation must be set once\nper specified amount of packets to provide uniform stream\nof completions and freeing the Tx queue in unifirm fashion.\nThe previous implementation sets the completion request\ngeneration once per burst, if burst size if big enough it may\nlatency in CQE generation and freeing large amount of buffers\nin tx_burst routine on multiple completions which also\naffects the latency and even causes the Tx queue overflow\nand Tx drops.\n\nThis patches enforces the completion request will be set\nin the exact Tx descriptor if specified amount of packets\nis already sent.\n\nFixes: 18a1c20044c0 (\"net/mlx5: implement Tx burst template\")\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/net/mlx5/mlx5_defs.h | 2 +-\n drivers/net/mlx5/mlx5_prm.h | 17 +++++++-----\n drivers/net/mlx5/mlx5_rxtx.c | 64 +++++++++++++++++++++++++++++---------------\n 3 files changed, 55 insertions(+), 28 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 461e916..d7440fd 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -28,7 +28,7 @@\n * Request TX completion every time descriptors reach this threshold since\n * the previous request. Must be a power of two for performance reasons.\n */\n-#define MLX5_TX_COMP_THRESH 32\n+#define MLX5_TX_COMP_THRESH 32u\n \n /*\n * Request TX completion every time the total number of WQEBBs used for inlining\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 32bc7a6..89548d4 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -72,7 +72,7 @@\n * boundary with accounting the title Control and Ethernet\n * segments.\n */\n-#define MLX5_EMPW_DEF_INLINE_LEN (3U * MLX5_WQE_SIZE + \\\n+#define MLX5_EMPW_DEF_INLINE_LEN (3u * MLX5_WQE_SIZE + \\\n \t\t\t\t MLX5_DSEG_MIN_INLINE_SIZE - \\\n \t\t\t\t MLX5_WQE_DSEG_SIZE)\n /*\n@@ -90,11 +90,16 @@\n * If there are no enough resources to built minimal\n * EMPW the sending loop exits.\n */\n-#define MLX5_EMPW_MIN_PACKETS (2 + 3 * 4)\n-#define MLX5_EMPW_MAX_PACKETS ((MLX5_WQE_SIZE_MAX - \\\n-\t\t\t\tMLX5_WQE_CSEG_SIZE - \\\n-\t\t\t\tMLX5_WQE_ESEG_SIZE) / \\\n-\t\t\t\tMLX5_WSEG_SIZE)\n+#define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)\n+/*\n+ * Maximal amount of packets to be sent with EMPW.\n+ * This value is not recommended to exceed MLX5_TX_COMP_THRESH,\n+ * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs\n+ * without CQE generation request, being multiplied by\n+ * MLX5_TX_COMP_MAX_CQE it may cause significant latency\n+ * in tx burst routine at the moment of freeing multiple mbufs.\n+ */\n+#define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH\n /*\n * Default packet length threshold to be inlined with\n * ordinary SEND. Inlining saves the MR key search\ndiff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c\nindex c2b93c6..5984c50 100644\n--- a/drivers/net/mlx5/mlx5_rxtx.c\n+++ b/drivers/net/mlx5/mlx5_rxtx.c\n@@ -2063,8 +2063,6 @@ enum mlx5_txcmp_code {\n *\n * @param txq\n * Pointer to TX queue structure.\n- * @param n_mbuf\n- * Number of mbuf not stored yet in elts array.\n * @param loc\n * Pointer to burst routine local context.\n * @param olx\n@@ -2073,18 +2071,23 @@ enum mlx5_txcmp_code {\n */\n static __rte_always_inline void\n mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,\n-\t\t\t unsigned int n_mbuf,\n \t\t\t struct mlx5_txq_local *restrict loc,\n-\t\t\t unsigned int olx __rte_unused)\n+\t\t\t unsigned int olx)\n {\n-\tuint16_t head = txq->elts_head + n_mbuf;\n+\tuint16_t head = txq->elts_head;\n+\tunsigned int part;\n \n+\tpart = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc->pkts_sent -\n+\t\t(MLX5_TXOFF_CONFIG(MULTI) ? loc->pkts_copy : 0);\n+\thead += part;\n \tif ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||\n-\t (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres) {\n+\t (MLX5_TXOFF_CONFIG(INLINE) &&\n+\t (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {\n \t\tvolatile struct mlx5_wqe *last = loc->wqe_last;\n \n \t\ttxq->elts_comp = head;\n-\t\ttxq->wqe_comp = txq->wqe_ci;\n+\t\tif (MLX5_TXOFF_CONFIG(INLINE))\n+\t\t\ttxq->wqe_comp = txq->wqe_ci;\n \t\t/* Request unconditional completion on last WQE. */\n \t\tlast->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n \t\t\t\t\t MLX5_COMP_MODE_OFFSET);\n@@ -3023,6 +3026,8 @@ enum mlx5_txcmp_code {\n \twqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);\n \ttxq->wqe_ci += (ds + 3) / 4;\n \tloc->wqe_free -= (ds + 3) / 4;\n+\t/* Request CQE generation if limits are reached. */\n+\tmlx5_tx_request_completion(txq, loc, olx);\n \treturn MLX5_TXCMP_CODE_MULTI;\n }\n \n@@ -3131,6 +3136,8 @@ enum mlx5_txcmp_code {\n \t} while (true);\n \ttxq->wqe_ci += (ds + 3) / 4;\n \tloc->wqe_free -= (ds + 3) / 4;\n+\t/* Request CQE generation if limits are reached. */\n+\tmlx5_tx_request_completion(txq, loc, olx);\n \treturn MLX5_TXCMP_CODE_MULTI;\n }\n \n@@ -3287,6 +3294,8 @@ enum mlx5_txcmp_code {\n \twqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);\n \ttxq->wqe_ci += (ds + 3) / 4;\n \tloc->wqe_free -= (ds + 3) / 4;\n+\t/* Request CQE generation if limits are reached. */\n+\tmlx5_tx_request_completion(txq, loc, olx);\n \treturn MLX5_TXCMP_CODE_MULTI;\n }\n \n@@ -3496,6 +3505,8 @@ enum mlx5_txcmp_code {\n \t\t--loc->elts_free;\n \t\t++loc->pkts_sent;\n \t\t--pkts_n;\n+\t\t/* Request CQE generation if limits are reached. */\n+\t\tmlx5_tx_request_completion(txq, loc, olx);\n \t\tif (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))\n \t\t\treturn MLX5_TXCMP_CODE_EXIT;\n \t\tloc->mbuf = *pkts++;\n@@ -3637,7 +3648,7 @@ enum mlx5_txcmp_code {\n \t\t struct mlx5_txq_local *restrict loc,\n \t\t unsigned int ds,\n \t\t unsigned int slen,\n-\t\t unsigned int olx __rte_unused)\n+\t\t unsigned int olx)\n {\n \tassert(!MLX5_TXOFF_CONFIG(INLINE));\n #ifdef MLX5_PMD_SOFT_COUNTERS\n@@ -3652,6 +3663,8 @@ enum mlx5_txcmp_code {\n \tloc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);\n \ttxq->wqe_ci += (ds + 3) / 4;\n \tloc->wqe_free -= (ds + 3) / 4;\n+\t/* Request CQE generation if limits are reached. */\n+\tmlx5_tx_request_completion(txq, loc, olx);\n }\n \n /*\n@@ -3694,6 +3707,8 @@ enum mlx5_txcmp_code {\n \tloc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);\n \ttxq->wqe_ci += (len + 3) / 4;\n \tloc->wqe_free -= (len + 3) / 4;\n+\t/* Request CQE generation if limits are reached. */\n+\tmlx5_tx_request_completion(txq, loc, olx);\n }\n \n /**\n@@ -3865,6 +3880,7 @@ enum mlx5_txcmp_code {\n \t\t\t\tif (unlikely(!loc->elts_free ||\n \t\t\t\t\t !loc->wqe_free))\n \t\t\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n+\t\t\t\tpkts_n -= part;\n \t\t\t\tgoto next_empw;\n \t\t\t}\n \t\t\t/* Packet attributes match, continue the same eMPW. */\n@@ -3884,6 +3900,8 @@ enum mlx5_txcmp_code {\n \t\ttxq->wqe_ci += (2 + part + 3) / 4;\n \t\tloc->wqe_free -= (2 + part + 3) / 4;\n \t\tpkts_n -= part;\n+\t\t/* Request CQE generation if limits are reached. */\n+\t\tmlx5_tx_request_completion(txq, loc, olx);\n \t\tif (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))\n \t\t\treturn MLX5_TXCMP_CODE_EXIT;\n \t\tloc->mbuf = *pkts++;\n@@ -3922,10 +3940,14 @@ enum mlx5_txcmp_code {\n \t\tstruct mlx5_wqe_dseg *restrict dseg;\n \t\tstruct mlx5_wqe_eseg *restrict eseg;\n \t\tenum mlx5_txcmp_code ret;\n-\t\tunsigned int room, part;\n+\t\tunsigned int room, part, nlim;\n \t\tunsigned int slen = 0;\n \n-next_empw:\n+\t\t/*\n+\t\t * Limits the amount of packets in one WQE\n+\t\t * to improve CQE latency generation.\n+\t\t */\n+\t\tnlim = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);\n \t\t/* Check whether we have minimal amount WQEs */\n \t\tif (unlikely(loc->wqe_free <\n \t\t\t ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))\n@@ -4044,12 +4066,6 @@ enum mlx5_txcmp_code {\n \t\t\t\tmlx5_tx_idone_empw(txq, loc, part, slen, olx);\n \t\t\t\treturn MLX5_TXCMP_CODE_EXIT;\n \t\t\t}\n-\t\t\t/* Check if we have minimal room left. */\n-\t\t\tif (room < MLX5_WQE_DSEG_SIZE) {\n-\t\t\t\tpart -= room;\n-\t\t\t\tmlx5_tx_idone_empw(txq, loc, part, slen, olx);\n-\t\t\t\tgoto next_empw;\n-\t\t\t}\n \t\t\tloc->mbuf = *pkts++;\n \t\t\tif (likely(pkts_n > 1))\n \t\t\t\trte_prefetch0(*pkts);\n@@ -4089,6 +4105,10 @@ enum mlx5_txcmp_code {\n \t\t\t\tmlx5_tx_idone_empw(txq, loc, part, slen, olx);\n \t\t\t\treturn MLX5_TXCMP_CODE_ERROR;\n \t\t\t}\n+\t\t\t/* Check if we have minimal room left. */\n+\t\t\tnlim--;\n+\t\t\tif (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))\n+\t\t\t\tbreak;\n \t\t\t/*\n \t\t\t * Check whether packet parameters coincide\n \t\t\t * within assumed eMPW batch:\n@@ -4114,7 +4134,7 @@ enum mlx5_txcmp_code {\n \t\tif (unlikely(!loc->elts_free ||\n \t\t\t !loc->wqe_free))\n \t\t\treturn MLX5_TXCMP_CODE_EXIT;\n-\t\tgoto next_empw;\n+\t\t/* Continue the loop with new eMPW session. */\n \t}\n \tassert(false);\n }\n@@ -4355,6 +4375,8 @@ enum mlx5_txcmp_code {\n \t\t}\n \t\t++loc->pkts_sent;\n \t\t--pkts_n;\n+\t\t/* Request CQE generation if limits are reached. */\n+\t\tmlx5_tx_request_completion(txq, loc, olx);\n \t\tif (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))\n \t\t\treturn MLX5_TXCMP_CODE_EXIT;\n \t\tloc->mbuf = *pkts++;\n@@ -4630,9 +4652,6 @@ enum mlx5_txcmp_code {\n \t/* Take a shortcut if nothing is sent. */\n \tif (unlikely(loc.pkts_sent == 0))\n \t\treturn 0;\n-\t/* Not all of the mbufs may be stored into elts yet. */\n-\tpart = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;\n-\tmlx5_tx_request_completion(txq, part, &loc, olx);\n \t/*\n \t * Ring QP doorbell immediately after WQE building completion\n \t * to improve latencies. The pure software related data treatment\n@@ -4640,10 +4659,13 @@ enum mlx5_txcmp_code {\n \t * processed in this thread only by the polling.\n \t */\n \tmlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, 0);\n+\t/* Not all of the mbufs may be stored into elts yet. */\n+\tpart = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent -\n+\t\t(MLX5_TXOFF_CONFIG(MULTI) ? loc.pkts_copy : 0);\n \tif (!MLX5_TXOFF_CONFIG(INLINE) && part) {\n \t\t/*\n \t\t * There are some single-segment mbufs not stored in elts.\n-\t\t * It can be only if last packet was single-segment.\n+\t\t * It can be only if the last packet was single-segment.\n \t\t * The copying is gathered into one place due to it is\n \t\t * a good opportunity to optimize that with SIMD.\n \t\t * Unfortunately if inlining is enabled the gaps in\n", "prefixes": [ "3/3" ] }