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GET /api/patches/5687/?format=api
{ "id": 5687, "url": "http://patches.dpdk.org/api/patches/5687/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1434999524-26528-11-git-send-email-cchemparathy@ezchip.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1434999524-26528-11-git-send-email-cchemparathy@ezchip.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1434999524-26528-11-git-send-email-cchemparathy@ezchip.com", "date": "2015-06-22T18:58:42", "name": "[dpdk-dev,v2,10/12] tile: initial TILE-Gx support.", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "193b06305d186f5a535918c3cf5ebead211a2b76", "submitter": { "id": 132, "url": "http://patches.dpdk.org/api/people/132/?format=api", "name": "Cyril Chemparathy", "email": "cchemparathy@ezchip.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1434999524-26528-11-git-send-email-cchemparathy@ezchip.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/5687/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/5687/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id CED6DC9EE;\n\tMon, 22 Jun 2015 20:59:16 +0200 (CEST)", "from sclab-apps-2.localdomain (sc-fw1.tilera.com [12.218.212.162])\n\tby dpdk.org (Postfix) with ESMTP id 1EC4AC904\n\tfor <dev@dpdk.org>; Mon, 22 Jun 2015 20:58:57 +0200 (CEST)", "by sclab-apps-2.localdomain (Postfix, from userid 1318)\n\tid D6F9B220504; Mon, 22 Jun 2015 11:58:45 -0700 (PDT)" ], "X-CheckPoint": "{55885AF0-10-A3D4DA0C-C0000002}", "From": "Cyril Chemparathy <cchemparathy@ezchip.com>", "To": "dev@dpdk.org", "Date": "Mon, 22 Jun 2015 11:58:42 -0700", "Message-Id": "<1434999524-26528-11-git-send-email-cchemparathy@ezchip.com>", "X-Mailer": "git-send-email 2.1.2", "In-Reply-To": "<1434999524-26528-1-git-send-email-cchemparathy@ezchip.com>", "References": "<1434999524-26528-1-git-send-email-cchemparathy@ezchip.com>", "Subject": "[dpdk-dev] [PATCH v2 10/12] tile: initial TILE-Gx support.", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit adds support for the TILE-Gx platform, as well as the TILE\nCPU architecture. This architecture port is fairly simple due to its\nreliance on generics for most arch stuff.\n\nChange-Id: I809fcf740e25ba5976a6b7736c1673515338cf80\nSigned-off-by: Cyril Chemparathy <cchemparathy@ezchip.com>\n---\n config/defconfig_tile-tilegx-linuxapp-gcc | 69 ++++++++++++++++\n .../common/include/arch/tile/rte_atomic.h | 86 ++++++++++++++++++++\n .../common/include/arch/tile/rte_byteorder.h | 91 +++++++++++++++++++++\n .../common/include/arch/tile/rte_cpuflags.h | 85 ++++++++++++++++++++\n .../common/include/arch/tile/rte_cycles.h | 70 ++++++++++++++++\n .../common/include/arch/tile/rte_memcpy.h | 93 ++++++++++++++++++++++\n .../common/include/arch/tile/rte_prefetch.h | 61 ++++++++++++++\n .../common/include/arch/tile/rte_rwlock.h | 70 ++++++++++++++++\n .../common/include/arch/tile/rte_spinlock.h | 92 +++++++++++++++++++++\n mk/arch/tile/rte.vars.mk | 39 +++++++++\n mk/machine/tilegx/rte.vars.mk | 57 +++++++++++++\n 11 files changed, 813 insertions(+)\n create mode 100644 config/defconfig_tile-tilegx-linuxapp-gcc\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_atomic.h\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_byteorder.h\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_cpuflags.h\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_cycles.h\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_memcpy.h\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_prefetch.h\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_rwlock.h\n create mode 100644 lib/librte_eal/common/include/arch/tile/rte_spinlock.h\n create mode 100644 mk/arch/tile/rte.vars.mk\n create mode 100644 mk/machine/tilegx/rte.vars.mk", "diff": "diff --git a/config/defconfig_tile-tilegx-linuxapp-gcc b/config/defconfig_tile-tilegx-linuxapp-gcc\nnew file mode 100644\nindex 0000000..4023878\n--- /dev/null\n+++ b/config/defconfig_tile-tilegx-linuxapp-gcc\n@@ -0,0 +1,69 @@\n+# BSD LICENSE\n+#\n+# Copyright (C) EZchip Semiconductor 2015.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of EZchip Semiconductor nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+#include \"common_linuxapp\"\n+\n+CONFIG_RTE_MACHINE=\"tilegx\"\n+\n+CONFIG_RTE_ARCH=\"tile\"\n+CONFIG_RTE_ARCH_TILE=y\n+CONFIG_RTE_ARCH_64=y\n+CONFIG_RTE_ARCH_STRICT_ALIGN=y\n+CONFIG_RTE_FORCE_INTRINSICS=y\n+\n+CONFIG_RTE_TOOLCHAIN=\"gcc\"\n+CONFIG_RTE_TOOLCHAIN_GCC=y\n+\n+# Disable things that we don't support or need\n+CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n\n+CONFIG_RTE_EAL_IGB_UIO=n\n+CONFIG_RTE_EAL_VFIO=n\n+CONFIG_RTE_LIBRTE_KNI=n\n+CONFIG_RTE_LIBRTE_XEN_DOM0=n\n+CONFIG_RTE_LIBRTE_IGB_PMD=n\n+CONFIG_RTE_LIBRTE_EM_PMD=n\n+CONFIG_RTE_LIBRTE_IXGBE_PMD=n\n+CONFIG_RTE_LIBRTE_I40E_PMD=n\n+CONFIG_RTE_LIBRTE_FM10K_PMD=n\n+CONFIG_RTE_LIBRTE_VIRTIO_PMD=n\n+CONFIG_RTE_LIBRTE_VMXNET3_PMD=n\n+CONFIG_RTE_LIBRTE_ENIC_PMD=n\n+\n+# This following libraries are not available on the tile architecture. So\n+# they're turned off.\n+CONFIG_RTE_LIBRTE_LPM=n\n+CONFIG_RTE_LIBRTE_ACL=n\n+CONFIG_RTE_LIBRTE_SCHED=n\n+CONFIG_RTE_LIBRTE_PORT=n\n+CONFIG_RTE_LIBRTE_TABLE=n\n+CONFIG_RTE_LIBRTE_PIPELINE=n\n+\n+# Enable and override things that we need\n+CONFIG_RTE_MEMPOOL_ALIGN=128\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_atomic.h b/lib/librte_eal/common/include/arch/tile/rte_atomic.h\nnew file mode 100644\nindex 0000000..3dc8eb8\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_atomic.h\n@@ -0,0 +1,86 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) EZchip Semiconductor Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of EZchip Semiconductor nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_ATOMIC_TILE_H_\n+#define _RTE_ATOMIC_TILE_H_\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_atomic.h\"\n+\n+/**\n+ * General memory barrier.\n+ *\n+ * Guarantees that the LOAD and STORE operations generated before the\n+ * barrier occur before the LOAD and STORE operations generated after.\n+ * This function is architecture dependent.\n+ */\n+static inline void rte_mb(void)\n+{\n+\t__sync_synchronize();\n+}\n+\n+/**\n+ * Write memory barrier.\n+ *\n+ * Guarantees that the STORE operations generated before the barrier\n+ * occur before the STORE operations generated after.\n+ * This function is architecture dependent.\n+ */\n+static inline void rte_wmb(void)\n+{\n+\t__sync_synchronize();\n+}\n+\n+/**\n+ * Read memory barrier.\n+ *\n+ * Guarantees that the LOAD operations generated before the barrier\n+ * occur before the LOAD operations generated after.\n+ * This function is architecture dependent.\n+ */\n+static inline void rte_rmb(void)\n+{\n+\t__sync_synchronize();\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ATOMIC_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_byteorder.h b/lib/librte_eal/common/include/arch/tile/rte_byteorder.h\nnew file mode 100644\nindex 0000000..7239e43\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_byteorder.h\n@@ -0,0 +1,91 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) EZchip Semiconductor Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of EZchip Semiconductor nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_BYTEORDER_TILE_H_\n+#define _RTE_BYTEORDER_TILE_H_\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_byteorder.h\"\n+\n+#if !(__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8))\n+#define rte_bswap16(x) rte_constant_bswap16(x)\n+#endif\n+\n+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+\n+#define rte_cpu_to_le_16(x) (x)\n+#define rte_cpu_to_le_32(x) (x)\n+#define rte_cpu_to_le_64(x) (x)\n+\n+#define rte_cpu_to_be_16(x) rte_bswap16(x)\n+#define rte_cpu_to_be_32(x) rte_bswap32(x)\n+#define rte_cpu_to_be_64(x) rte_bswap64(x)\n+\n+#define rte_le_to_cpu_16(x) (x)\n+#define rte_le_to_cpu_32(x) (x)\n+#define rte_le_to_cpu_64(x) (x)\n+\n+#define rte_be_to_cpu_16(x) rte_bswap16(x)\n+#define rte_be_to_cpu_32(x) rte_bswap32(x)\n+#define rte_be_to_cpu_64(x) rte_bswap64(x)\n+\n+#else /* RTE_BIG_ENDIAN */\n+\n+#define rte_cpu_to_le_16(x) rte_bswap16(x)\n+#define rte_cpu_to_le_32(x) rte_bswap32(x)\n+#define rte_cpu_to_le_64(x) rte_bswap64(x)\n+\n+#define rte_cpu_to_be_16(x) (x)\n+#define rte_cpu_to_be_32(x) (x)\n+#define rte_cpu_to_be_64(x) (x)\n+\n+#define rte_le_to_cpu_16(x) rte_bswap16(x)\n+#define rte_le_to_cpu_32(x) rte_bswap32(x)\n+#define rte_le_to_cpu_64(x) rte_bswap64(x)\n+\n+#define rte_be_to_cpu_16(x) (x)\n+#define rte_be_to_cpu_32(x) (x)\n+#define rte_be_to_cpu_64(x) (x)\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_BYTEORDER_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h b/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h\nnew file mode 100644\nindex 0000000..08aa957\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_cpuflags.h\n@@ -0,0 +1,85 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) EZchip Semiconductor Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of EZchip Semiconductor nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_CPUFLAGS_TILE_H_\n+#define _RTE_CPUFLAGS_TILE_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <elf.h>\n+#include <fcntl.h>\n+#include <assert.h>\n+#include <unistd.h>\n+\n+#include \"generic/rte_cpuflags.h\"\n+\n+/* software based registers */\n+enum cpu_register_t {\n+\tREG_DUMMY = 0\n+};\n+\n+/**\n+ * Enumeration of all CPU features supported\n+ */\n+enum rte_cpu_flag_t {\n+\tRTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */\n+};\n+\n+static const struct feature_entry cpu_feature_table[] = {\n+};\n+\n+/*\n+ * Read AUXV software register and get cpu features for Power\n+ */\n+static inline void\n+rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,\n+\t\t __attribute__((unused)) uint32_t subleaf,\n+\t\t __attribute__((unused)) cpuid_registers_t out)\n+{\n+}\n+\n+/*\n+ * Checks if a particular flag is available on current machine.\n+ */\n+static inline int\n+rte_cpu_get_flag_enabled(__attribute__((unused)) enum rte_cpu_flag_t feature)\n+{\n+\treturn -ENOENT;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CPUFLAGS_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_cycles.h b/lib/librte_eal/common/include/arch/tile/rte_cycles.h\nnew file mode 100644\nindex 0000000..0b2200a\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_cycles.h\n@@ -0,0 +1,70 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) EZchip Semiconductor Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of EZchip Semiconductor nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_CYCLES_TILE_H_\n+#define _RTE_CYCLES_TILE_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <arch/cycle.h>\n+\n+#include \"generic/rte_cycles.h\"\n+\n+/**\n+ * Read the time base register.\n+ *\n+ * @return\n+ * The time base for this lcore.\n+ */\n+static inline uint64_t\n+rte_rdtsc(void)\n+{\n+\treturn get_cycle_count();\n+}\n+\n+static inline uint64_t\n+rte_rdtsc_precise(void)\n+{\n+\trte_mb();\n+\treturn rte_rdtsc();\n+}\n+\n+static inline uint64_t\n+rte_get_tsc_cycles(void) { return rte_rdtsc(); }\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_CYCLES_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_memcpy.h b/lib/librte_eal/common/include/arch/tile/rte_memcpy.h\nnew file mode 100644\nindex 0000000..9b5b37e\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_memcpy.h\n@@ -0,0 +1,93 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) EZchip Semiconductor Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of EZchip Semiconductor nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_MEMCPY_TILE_H_\n+#define _RTE_MEMCPY_TILE_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <stdint.h>\n+#include <string.h>\n+\n+#include \"generic/rte_memcpy.h\"\n+\n+static inline void\n+rte_mov16(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 16);\n+}\n+\n+static inline void\n+rte_mov32(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 32);\n+}\n+\n+static inline void\n+rte_mov48(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 48);\n+}\n+\n+static inline void\n+rte_mov64(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 64);\n+}\n+\n+static inline void\n+rte_mov128(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 128);\n+}\n+\n+static inline void\n+rte_mov256(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 256);\n+}\n+\n+#define rte_memcpy(d, s, n)\tmemcpy((d), (s), (n))\n+\n+static inline void *\n+rte_memcpy_func(void *dst, const void *src, size_t n)\n+{\n+\treturn memcpy(dst, src, n);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_MEMCPY_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_prefetch.h b/lib/librte_eal/common/include/arch/tile/rte_prefetch.h\nnew file mode 100644\nindex 0000000..f02d9fa\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_prefetch.h\n@@ -0,0 +1,61 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) EZchip Semiconductor Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of EZchip Semiconductor nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_PREFETCH_TILE_H_\n+#define _RTE_PREFETCH_TILE_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_prefetch.h\"\n+\n+static inline void rte_prefetch0(volatile void *p)\n+{\n+\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 3);\n+}\n+\n+static inline void rte_prefetch1(volatile void *p)\n+{\n+\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 2);\n+}\n+\n+static inline void rte_prefetch2(volatile void *p)\n+{\n+\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 1);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_PREFETCH_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_rwlock.h b/lib/librte_eal/common/include/arch/tile/rte_rwlock.h\nnew file mode 100644\nindex 0000000..8f67a19\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_rwlock.h\n@@ -0,0 +1,70 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) EZchip Semiconductor Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of EZchip Semiconductor nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_RWLOCK_TILE_H_\n+#define _RTE_RWLOCK_TILE_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_rwlock.h\"\n+\n+static inline void\n+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_read_lock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_read_unlock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_write_lock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_write_unlock(rwl);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_RWLOCK_TILE_H_ */\ndiff --git a/lib/librte_eal/common/include/arch/tile/rte_spinlock.h b/lib/librte_eal/common/include/arch/tile/rte_spinlock.h\nnew file mode 100644\nindex 0000000..e91f99e\n--- /dev/null\n+++ b/lib/librte_eal/common/include/arch/tile/rte_spinlock.h\n@@ -0,0 +1,92 @@\n+/*\n+ * BSD LICENSE\n+ *\n+ * Copyright (C) EZchip Semiconductor Ltd. 2015.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of EZchip Semiconductor nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+*/\n+\n+#ifndef _RTE_SPINLOCK_TILE_H_\n+#define _RTE_SPINLOCK_TILE_H_\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_common.h>\n+#include \"generic/rte_spinlock.h\"\n+\n+static inline int rte_tm_supported(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline void\n+rte_spinlock_lock_tm(rte_spinlock_t *sl)\n+{\n+\trte_spinlock_lock(sl); /* fall-back */\n+}\n+\n+static inline int\n+rte_spinlock_trylock_tm(rte_spinlock_t *sl)\n+{\n+\treturn rte_spinlock_trylock(sl);\n+}\n+\n+static inline void\n+rte_spinlock_unlock_tm(rte_spinlock_t *sl)\n+{\n+\trte_spinlock_unlock(sl);\n+}\n+\n+static inline void\n+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\trte_spinlock_recursive_lock(slr); /* fall-back */\n+}\n+\n+static inline void\n+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\trte_spinlock_recursive_unlock(slr);\n+}\n+\n+static inline int\n+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\treturn rte_spinlock_recursive_trylock(slr);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_SPINLOCK_TILE_H_ */\ndiff --git a/mk/arch/tile/rte.vars.mk b/mk/arch/tile/rte.vars.mk\nnew file mode 100644\nindex 0000000..b518986\n--- /dev/null\n+++ b/mk/arch/tile/rte.vars.mk\n@@ -0,0 +1,39 @@\n+# BSD LICENSE\n+#\n+# Copyright (C) EZchip Semiconductor Ltd. 2015.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of EZchip Semiconductor nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+\n+ARCH ?= tile\n+CROSS ?= tile-\n+\n+CPU_CFLAGS ?=\n+CPU_LDFLAGS ?=\n+CPU_ASFLAGS ?=\n+\n+export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS\ndiff --git a/mk/machine/tilegx/rte.vars.mk b/mk/machine/tilegx/rte.vars.mk\nnew file mode 100644\nindex 0000000..c8256f1\n--- /dev/null\n+++ b/mk/machine/tilegx/rte.vars.mk\n@@ -0,0 +1,57 @@\n+# BSD LICENSE\n+#\n+# Copyright (C) EZchip Semiconductor Ltd. 2015.\n+#\n+# Redistribution and use in source and binary forms, with or without\n+# modification, are permitted provided that the following conditions\n+# are met:\n+#\n+# * Redistributions of source code must retain the above copyright\n+# notice, this list of conditions and the following disclaimer.\n+# * Redistributions in binary form must reproduce the above copyright\n+# notice, this list of conditions and the following disclaimer in\n+# the documentation and/or other materials provided with the\n+# distribution.\n+# * Neither the name of EZchip Semiconductor nor the names of its\n+# contributors may be used to endorse or promote products derived\n+# from this software without specific prior written permission.\n+#\n+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+\n+#\n+# machine:\n+#\n+# - can define ARCH variable (overridden by cmdline value)\n+# - can define CROSS variable (overridden by cmdline value)\n+# - define MACHINE_CFLAGS variable (overridden by cmdline value)\n+# - define MACHINE_LDFLAGS variable (overridden by cmdline value)\n+# - define MACHINE_ASFLAGS variable (overridden by cmdline value)\n+# - can define CPU_CFLAGS variable (overridden by cmdline value) that\n+# overrides the one defined in arch.\n+# - can define CPU_LDFLAGS variable (overridden by cmdline value) that\n+# overrides the one defined in arch.\n+# - can define CPU_ASFLAGS variable (overridden by cmdline value) that\n+# overrides the one defined in arch.\n+# - may override any previously defined variable\n+#\n+\n+# ARCH =\n+# CROSS =\n+# MACHINE_CFLAGS =\n+# MACHINE_LDFLAGS =\n+# MACHINE_ASFLAGS =\n+# CPU_CFLAGS =\n+# CPU_LDFLAGS =\n+# CPU_ASFLAGS =\n+\n+MACHINE_CFLAGS =\n", "prefixes": [ "dpdk-dev", "v2", "10/12" ] }