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GET /api/patches/56836/?format=api
{ "id": 56836, "url": "http://patches.dpdk.org/api/patches/56836/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1563786795-14027-12-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1563786795-14027-12-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1563786795-14027-12-git-send-email-matan@mellanox.com", "date": "2019-07-22T09:12:58", "name": "[11/28] net/mlx5: create advanced Rx object using new API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b7dfe89602c3a7a0e58eb84433302d5fb5930d1f", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1563786795-14027-12-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 5639, "url": "http://patches.dpdk.org/api/series/5639/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5639", "date": "2019-07-22T09:12:48", "name": "net/mlx5: support LRO", "version": 1, "mbox": "http://patches.dpdk.org/series/5639/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56836/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/56836/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3E3AC1BE38;\n\tMon, 22 Jul 2019 11:13:53 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id C93B01BDF6\n\tfor <dev@dpdk.org>; Mon, 22 Jul 2019 11:13:29 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tmatan@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 22 Jul 2019 12:13:23 +0300", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n\t[10.210.16.112])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6M9DMja010084;\n\tMon, 22 Jul 2019 12:13:23 +0300" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "Shahaf Shuler <shahafs@mellanox.com>, Yongseok Koh <yskoh@mellanox.com>, \n\tViacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "dev@dpdk.org, Dekel Peled <dekelp@mellanox.com>", "Date": "Mon, 22 Jul 2019 09:12:58 +0000", "Message-Id": "<1563786795-14027-12-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1563786795-14027-1-git-send-email-matan@mellanox.com>", "References": "<1563786795-14027-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 11/28] net/mlx5: create advanced Rx object using\n\tnew API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@mellanox.com>\n\nImplement function mlx5_devx_cmd_create_tir() to create TIR\nobject using DevX API..\nAdd related structs in mlx5.h and mlx5_prm.h.\n\nSigned-off-by: Dekel Peled <dekelp@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5.h | 26 +++++++++++++\n drivers/net/mlx5/mlx5_devx_cmds.c | 72 ++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_prm.h | 81 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 179 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex fbd1311..183acfb 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -320,6 +320,30 @@ struct mlx5_devx_modify_rq_attr {\n \tuint32_t lwm:16; /* Contained WQ lwm. */\n };\n \n+struct mlx5_rx_hash_field_select {\n+\tuint32_t l3_prot_type:1;\n+\tuint32_t l4_prot_type:1;\n+\tuint32_t selected_fields:30;\n+};\n+\n+/* TIR attributes structure, used by TIR operations. */\n+struct mlx5_devx_tir_attr {\n+\tuint32_t disp_type:4;\n+\tuint32_t lro_timeout_period_usecs:16;\n+\tuint32_t lro_enable_mask:4;\n+\tuint32_t lro_max_msg_sz:8;\n+\tuint32_t inline_rqn:24;\n+\tuint32_t rx_hash_symmetric:1;\n+\tuint32_t tunneled_offload_en:1;\n+\tuint32_t indirect_table:24;\n+\tuint32_t rx_hash_fn:4;\n+\tuint32_t self_lb_block:2;\n+\tuint32_t transport_domain:24;\n+\tuint32_t rx_hash_toeplitz_key[10];\n+\tstruct mlx5_rx_hash_field_select rx_hash_field_selector_outer;\n+\tstruct mlx5_rx_hash_field_select rx_hash_field_selector_inner;\n+};\n+\n /**\n * Type of object being allocated.\n */\n@@ -810,5 +834,7 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,\n \t\t\t\tint socket);\n int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,\n \t\t\t struct mlx5_devx_modify_rq_attr *rq_attr);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,\n+\t\t\t\t\tstruct mlx5_devx_tir_attr *tir_attr);\n \n #endif /* RTE_PMD_MLX5_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c\nindex e8953bb..5faa2a0 100644\n--- a/drivers/net/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.c\n@@ -576,3 +576,75 @@ struct mlx5_devx_obj *\n \t}\n \treturn ret;\n }\n+\n+/**\n+ * Create TIR using DevX API.\n+ *\n+ * @param[in] ctx\n+ * ibv_context returned from mlx5dv_open_device.\n+ * @param [in] tir_attr\n+ * Pointer to TIR attributes structure.\n+ *\n+ * @return\n+ * The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_tir(struct ibv_context *ctx,\n+\t\t\t struct mlx5_devx_tir_attr *tir_attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};\n+\tvoid *tir_ctx, *outer, *inner;\n+\tstruct mlx5_devx_obj *tir = NULL;\n+\tint i;\n+\n+\ttir = rte_calloc(__func__, 1, sizeof(*tir), 0);\n+\tif (!tir) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate TIR data\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);\n+\ttir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);\n+\tMLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);\n+\tMLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,\n+\t\t tir_attr->lro_timeout_period_usecs);\n+\tMLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);\n+\tMLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);\n+\tMLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);\n+\tMLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);\n+\tMLX5_SET(tirc, tir_ctx, tunneled_offload_en,\n+\t\t tir_attr->tunneled_offload_en);\n+\tMLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);\n+\tMLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);\n+\tMLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);\n+\tMLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);\n+\tfor (i = 0; i < 10; i++) {\n+\t\tMLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],\n+\t\t\t tir_attr->rx_hash_toeplitz_key[i]);\n+\t}\n+\touter = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);\n+\tMLX5_SET(rx_hash_field_select, outer, l3_prot_type,\n+\t\t tir_attr->rx_hash_field_selector_outer.l3_prot_type);\n+\tMLX5_SET(rx_hash_field_select, outer, l4_prot_type,\n+\t\t tir_attr->rx_hash_field_selector_outer.l4_prot_type);\n+\tMLX5_SET(rx_hash_field_select, outer, selected_fields,\n+\t\t tir_attr->rx_hash_field_selector_outer.selected_fields);\n+\tinner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);\n+\tMLX5_SET(rx_hash_field_select, inner, l3_prot_type,\n+\t\t tir_attr->rx_hash_field_selector_inner.l3_prot_type);\n+\tMLX5_SET(rx_hash_field_select, inner, l4_prot_type,\n+\t\t tir_attr->rx_hash_field_selector_inner.l4_prot_type);\n+\tMLX5_SET(rx_hash_field_select, inner, selected_fields,\n+\t\t tir_attr->rx_hash_field_selector_inner.selected_fields);\n+\ttir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),\n+\t\t\t\t\t\t out, sizeof(out));\n+\tif (!tir->obj) {\n+\t\tDRV_LOG(ERR, \"Failed to create TIR using DevX\");\n+\t\trte_errno = errno;\n+\t\trte_free(tir);\n+\t\treturn NULL;\n+\t}\n+\ttir->id = MLX5_GET(create_tir_out, out, tirn);\n+\treturn tir;\n+}\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 7ec709b..970dee0 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -627,6 +627,7 @@ enum {\n \tMLX5_CMD_OP_QUERY_HCA_CAP = 0x100,\n \tMLX5_CMD_OP_CREATE_MKEY = 0x200,\n \tMLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,\n+\tMLX5_CMD_OP_CREATE_TIR = 0x900,\n \tMLX5_CMD_OP_CREATE_RQ = 0x908,\n \tMLX5_CMD_OP_MODIFY_RQ = 0x909,\n \tMLX5_CMD_OP_QUERY_TIS = 0x915,\n@@ -1407,6 +1408,86 @@ struct mlx5_ifc_modify_rq_in_bits {\n \tstruct mlx5_ifc_rqc_bits ctx;\n };\n \n+enum {\n+\tMLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,\n+\tMLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,\n+\tMLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,\n+\tMLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,\n+\tMLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,\n+};\n+\n+struct mlx5_ifc_rx_hash_field_select_bits {\n+\tu8 l3_prot_type[0x1];\n+\tu8 l4_prot_type[0x1];\n+\tu8 selected_fields[0x1e];\n+};\n+\n+enum {\n+\tMLX5_TIRC_DISP_TYPE_DIRECT = 0x0,\n+\tMLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,\n+};\n+\n+enum {\n+\tMLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,\n+\tMLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,\n+};\n+\n+enum {\n+\tMLX5_RX_HASH_FN_NONE = 0x0,\n+\tMLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,\n+\tMLX5_RX_HASH_FN_TOEPLITZ = 0x2,\n+};\n+\n+enum {\n+\tMLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,\n+\tMLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,\n+};\n+\n+struct mlx5_ifc_tirc_bits {\n+\tu8 reserved_at_0[0x20];\n+\tu8 disp_type[0x4];\n+\tu8 reserved_at_24[0x1c];\n+\tu8 reserved_at_40[0x40];\n+\tu8 reserved_at_80[0x4];\n+\tu8 lro_timeout_period_usecs[0x10];\n+\tu8 lro_enable_mask[0x4];\n+\tu8 lro_max_msg_sz[0x8];\n+\tu8 reserved_at_a0[0x40];\n+\tu8 reserved_at_e0[0x8];\n+\tu8 inline_rqn[0x18];\n+\tu8 rx_hash_symmetric[0x1];\n+\tu8 reserved_at_101[0x1];\n+\tu8 tunneled_offload_en[0x1];\n+\tu8 reserved_at_103[0x5];\n+\tu8 indirect_table[0x18];\n+\tu8 rx_hash_fn[0x4];\n+\tu8 reserved_at_124[0x2];\n+\tu8 self_lb_block[0x2];\n+\tu8 transport_domain[0x18];\n+\tu8 rx_hash_toeplitz_key[10][0x20];\n+\tstruct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;\n+\tstruct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;\n+\tu8 reserved_at_2c0[0x4c0];\n+};\n+\n+struct mlx5_ifc_create_tir_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 tirn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_create_tir_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0xc0];\n+\tstruct mlx5_ifc_tirc_bits ctx;\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \n", "prefixes": [ "11/28" ] }