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GET /api/patches/56827/?format=api
{ "id": 56827, "url": "http://patches.dpdk.org/api/patches/56827/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1563786795-14027-4-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1563786795-14027-4-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1563786795-14027-4-git-send-email-matan@mellanox.com", "date": "2019-07-22T09:12:50", "name": "[03/28] net/mlx5: support LRO caps query using devx API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "92810f196f45364e661240385290e6ddf5def3d4", "submitter": { "id": 796, "url": "http://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1563786795-14027-4-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 5639, "url": "http://patches.dpdk.org/api/series/5639/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5639", "date": "2019-07-22T09:12:48", "name": "net/mlx5: support LRO", "version": 1, "mbox": "http://patches.dpdk.org/series/5639/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56827/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/56827/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 727151BDEC;\n\tMon, 22 Jul 2019 11:13:28 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 6B6131BD66\n\tfor <dev@dpdk.org>; Mon, 22 Jul 2019 11:13:24 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tmatan@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 22 Jul 2019 12:13:22 +0300", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n\t[10.210.16.112])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6M9DMjS010084;\n\tMon, 22 Jul 2019 12:13:22 +0300" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "Shahaf Shuler <shahafs@mellanox.com>, Yongseok Koh <yskoh@mellanox.com>, \n\tViacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "dev@dpdk.org, Dekel Peled <dekelp@mellanox.com>", "Date": "Mon, 22 Jul 2019 09:12:50 +0000", "Message-Id": "<1563786795-14027-4-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1563786795-14027-1-git-send-email-matan@mellanox.com>", "References": "<1563786795-14027-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 03/28] net/mlx5: support LRO caps query using\n\tdevx API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@mellanox.com>\n\nUpdate function mlx5_devx_cmd_query_hca_attr() to query HCA\ncapabilities related to LRO.\n\nAdd relevant structs in drivers/net/mlx5/mlx5_prm.h.\n\nSigned-off-by: Dekel Peled <dekelp@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5.h | 8 ++++++\n drivers/net/mlx5/mlx5_devx_cmds.c | 14 ++++++++++\n drivers/net/mlx5/mlx5_prm.h | 58 ++++++++++++++++++++-------------------\n 3 files changed, 52 insertions(+), 28 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 4074a7e..ff407f6 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -165,6 +165,9 @@ struct mlx5_devx_mkey_attr {\n \tuint32_t pd;\n };\n \n+/* HCA supports this number of time periods for LRO. */\n+#define MLX5_LRO_NUM_SUPP_PERIODS 4\n+\n /* HCA attributes. */\n struct mlx5_hca_attr {\n \tuint32_t eswitch_manager:1;\n@@ -175,6 +178,11 @@ struct mlx5_hca_attr {\n \tuint32_t wqe_vlan_insert:1;\n \tuint32_t wqe_inline_mode:2;\n \tuint32_t vport_inline_mode:3;\n+\tuint32_t lro_cap:1;\n+\tuint32_t tunnel_lro_gre:1;\n+\tuint32_t tunnel_lro_vxlan:1;\n+\tuint32_t lro_max_msg_sz_mode:2;\n+\tuint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];\n };\n \n /* Flow list . */\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c\nindex 18f8ab6..1cba00f 100644\n--- a/drivers/net/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.c\n@@ -360,6 +360,20 @@ struct mlx5_devx_obj *\n \thcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n \tattr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, wqe_vlan_insert);\n+\tattr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,\n+\t\t\t\t lro_cap);\n+\tattr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,\n+\t\t\t\t\thcattr, tunnel_lro_gre);\n+\tattr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,\n+\t\t\t\t\t hcattr, tunnel_lro_vxlan);\n+\tattr->lro_max_msg_sz_mode = MLX5_GET\n+\t\t\t\t\t(per_protocol_networking_offload_caps,\n+\t\t\t\t\t hcattr, lro_max_msg_sz_mode);\n+\tfor (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {\n+\t\tattr->lro_timer_supported_periods[i] =\n+\t\t\tMLX5_GET(per_protocol_networking_offload_caps, hcattr,\n+\t\t\t\t lro_timer_supported_periods[i]);\n+\t}\n \tattr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,\n \t\t\t\t\t hcattr, wqe_inline_mode);\n \tif (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex 3c2b3d8..4f20dea 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -1084,16 +1084,42 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 reserved_at_61f[0x1e1];\n };\n \n+struct mlx5_ifc_qos_cap_bits {\n+\tu8 packet_pacing[0x1];\n+\tu8 esw_scheduling[0x1];\n+\tu8 esw_bw_share[0x1];\n+\tu8 esw_rate_limit[0x1];\n+\tu8 reserved_at_4[0x1];\n+\tu8 packet_pacing_burst_bound[0x1];\n+\tu8 packet_pacing_typical_size[0x1];\n+\tu8 flow_meter_srtcm[0x1];\n+\tu8 reserved_at_8[0x8];\n+\tu8 log_max_flow_meter[0x8];\n+\tu8 flow_meter_reg_id[0x8];\n+\tu8 reserved_at_25[0x20];\n+\tu8 packet_pacing_max_rate[0x20];\n+\tu8 packet_pacing_min_rate[0x20];\n+\tu8 reserved_at_80[0x10];\n+\tu8 packet_pacing_rate_table_size[0x10];\n+\tu8 esw_element_type[0x10];\n+\tu8 esw_tsar_type[0x10];\n+\tu8 reserved_at_c0[0x10];\n+\tu8 max_qos_para_vport[0x10];\n+\tu8 max_tsar_bw_share[0x20];\n+\tu8 reserved_at_100[0x6e8];\n+};\n+\n struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n \tu8 csum_cap[0x1];\n \tu8 vlan_cap[0x1];\n \tu8 lro_cap[0x1];\n \tu8 lro_psh_flag[0x1];\n \tu8 lro_time_stamp[0x1];\n-\tu8 reserved_at_5[0x2];\n+\tu8 lro_max_msg_sz_mode[0x2];\n \tu8 wqe_vlan_insert[0x1];\n \tu8 self_lb_en_modifiable[0x1];\n-\tu8 reserved_at_9[0x2];\n+\tu8 self_lb_mc[0x1];\n+\tu8 self_lb_uc[0x1];\n \tu8 max_lso_cap[0x5];\n \tu8 multi_pkt_send_wqe[0x2];\n \tu8 wqe_inline_mode[0x2];\n@@ -1102,7 +1128,8 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n \tu8 scatter_fcs[0x1];\n \tu8 enhanced_multi_pkt_send_wqe[0x1];\n \tu8 tunnel_lso_const_out_ip_id[0x1];\n-\tu8 reserved_at_1c[0x2];\n+\tu8 tunnel_lro_gre[0x1];\n+\tu8 tunnel_lro_vxlan[0x1];\n \tu8 tunnel_stateless_gre[0x1];\n \tu8 tunnel_stateless_vxlan[0x1];\n \tu8 swp[0x1];\n@@ -1120,31 +1147,6 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {\n \tu8 reserved_at_200[0x600];\n };\n \n-struct mlx5_ifc_qos_cap_bits {\n-\tu8 packet_pacing[0x1];\n-\tu8 esw_scheduling[0x1];\n-\tu8 esw_bw_share[0x1];\n-\tu8 esw_rate_limit[0x1];\n-\tu8 reserved_at_4[0x1];\n-\tu8 packet_pacing_burst_bound[0x1];\n-\tu8 packet_pacing_typical_size[0x1];\n-\tu8 flow_meter_srtcm[0x1];\n-\tu8 reserved_at_8[0x8];\n-\tu8 log_max_flow_meter[0x8];\n-\tu8 flow_meter_reg_id[0x8];\n-\tu8 reserved_at_25[0x20];\n-\tu8 packet_pacing_max_rate[0x20];\n-\tu8 packet_pacing_min_rate[0x20];\n-\tu8 reserved_at_80[0x10];\n-\tu8 packet_pacing_rate_table_size[0x10];\n-\tu8 esw_element_type[0x10];\n-\tu8 esw_tsar_type[0x10];\n-\tu8 reserved_at_c0[0x10];\n-\tu8 max_qos_para_vport[0x10];\n-\tu8 max_tsar_bw_share[0x20];\n-\tu8 reserved_at_100[0x6e8];\n-};\n-\n union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;\n \tstruct mlx5_ifc_per_protocol_networking_offload_caps_bits\n", "prefixes": [ "03/28" ] }