Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/56816/?format=api
{ "id": 56816, "url": "http://patches.dpdk.org/api/patches/56816/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1563797960-58560-1-git-send-email-xiao.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1563797960-58560-1-git-send-email-xiao.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1563797960-58560-1-git-send-email-xiao.zhang@intel.com", "date": "2019-07-22T12:19:20", "name": "[v7] net/e1000: fix i219 hang on reset/close", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8964458d8cf82301fc7e56f855b5cfa23d620291", "submitter": { "id": 1352, "url": "http://patches.dpdk.org/api/people/1352/?format=api", "name": "Xiao Zhang", "email": "xiao.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1563797960-58560-1-git-send-email-xiao.zhang@intel.com/mbox/", "series": [ { "id": 5634, "url": "http://patches.dpdk.org/api/series/5634/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5634", "date": "2019-07-22T12:19:20", "name": "[v7] net/e1000: fix i219 hang on reset/close", "version": 7, "mbox": "http://patches.dpdk.org/series/5634/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56816/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/56816/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 222192F42;\n\tMon, 22 Jul 2019 05:24:15 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby dpdk.org (Postfix) with ESMTP id E93B02BA8;\n\tMon, 22 Jul 2019 05:24:12 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t21 Jul 2019 20:24:12 -0700", "from npg-dpdk-zhangxiao.sh.intel.com ([10.67.110.190])\n\tby orsmga007.jf.intel.com with ESMTP; 21 Jul 2019 20:24:10 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,293,1559545200\"; d=\"scan'208\";a=\"159752596\"", "From": "Xiao Zhang <xiao.zhang@intel.com>", "To": "dev@dpdk.org", "Cc": "wenzhuo.lu@intel.com, wei.zhao1@intel.com,\n\tXiao Zhang <xiao.zhang@intel.com>, stable@dpdk.org", "Date": "Mon, 22 Jul 2019 20:19:20 +0800", "Message-Id": "<1563797960-58560-1-git-send-email-xiao.zhang@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1563794359-24011-1-git-send-email-xiao.zhang@intel.com>", "References": "<1563794359-24011-1-git-send-email-xiao.zhang@intel.com>", "Subject": "[dpdk-dev] [v7] net/e1000: fix i219 hang on reset/close", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Unit hang may occur if multiple descriptors are available in the rings\nduring reset or close. This state can be detected by configure status\nby bit 8 in register. If the bit is set and there are pending\ndescriptors in one of the rings, we must flush them before reset or\nclose.\n\nFixes: 80580344(\"e1000: support EM devices (also known as e1000/e1000e)\")\nCc: stable@dpdk.org\n\nSigned-off-by: Xiao Zhang <xiao.zhang@intel.com>\n---\nv7 Add fix line.\nv6 Change the fix on em driver instead of igb driver and update the \nregister address according to C-Spec.\nv5 Change the subject.\nv4 Correct the tail descriptor of tx ring.\nv3 Add loop to handle all tx and rx queues.\nv2 Use configuration register instead of NVM7 to get the hang state.\n---\n drivers/net/e1000/e1000_ethdev.h | 4 ++\n drivers/net/e1000/em_ethdev.c | 5 ++\n drivers/net/e1000/em_rxtx.c | 108 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 117 insertions(+)", "diff": "diff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h\nindex 67acb73..01ff943 100644\n--- a/drivers/net/e1000/e1000_ethdev.h\n+++ b/drivers/net/e1000/e1000_ethdev.h\n@@ -35,6 +35,9 @@\n #define IGB_MAX_RX_QUEUE_NUM 8\n #define IGB_MAX_RX_QUEUE_NUM_82576 16\n \n+#define E1000_I219_MAX_RX_QUEUE_NUM\t\t2\n+#define E1000_I219_MAX_TX_QUEUE_NUM\t\t2\n+\n #define E1000_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */\n #define E1000_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */\n #define E1000_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */\n@@ -522,5 +525,6 @@ int igb_action_rss_same(const struct rte_flow_action_rss *comp,\n int igb_config_rss_filter(struct rte_eth_dev *dev,\n \t\t\tstruct igb_rte_flow_rss_conf *conf,\n \t\t\tbool add);\n+void em_flush_desc_rings(struct rte_eth_dev *dev);\n \n #endif /* _E1000_ETHDEV_H_ */\ndiff --git a/drivers/net/e1000/em_ethdev.c b/drivers/net/e1000/em_ethdev.c\nindex dc88661..62d3a95 100644\n--- a/drivers/net/e1000/em_ethdev.c\n+++ b/drivers/net/e1000/em_ethdev.c\n@@ -738,6 +738,11 @@ eth_em_stop(struct rte_eth_dev *dev)\n \tem_lsc_intr_disable(hw);\n \n \te1000_reset_hw(hw);\n+\n+\t/* Flush desc rings for i219 */\n+\tif (hw->mac.type >= e1000_pch_spt)\n+\t\tem_flush_desc_rings(dev);\n+\n \tif (hw->mac.type >= e1000_82544)\n \t\tE1000_WRITE_REG(hw, E1000_WUC, 0);\n \ndiff --git a/drivers/net/e1000/em_rxtx.c b/drivers/net/e1000/em_rxtx.c\nindex 708f832..96c10cd 100644\n--- a/drivers/net/e1000/em_rxtx.c\n+++ b/drivers/net/e1000/em_rxtx.c\n@@ -18,6 +18,7 @@\n #include <rte_log.h>\n #include <rte_debug.h>\n #include <rte_pci.h>\n+#include <rte_bus_pci.h>\n #include <rte_memory.h>\n #include <rte_memcpy.h>\n #include <rte_memzone.h>\n@@ -59,6 +60,11 @@\n #define E1000_TX_OFFLOAD_NOTSUP_MASK \\\n \t\t(PKT_TX_OFFLOAD_MASK ^ E1000_TX_OFFLOAD_MASK)\n \n+/* PCI offset for querying configuration status register */\n+#define PCI_CFG_STATUS_REG 0x06\n+#define FLUSH_DESC_REQUIRED 0x100\n+\n+\n /**\n * Structure associated with each descriptor of the RX ring of a RX queue.\n */\n@@ -2000,3 +2006,105 @@ em_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \tqinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;\n \tqinfo->conf.offloads = txq->offloads;\n }\n+\n+static void e1000_flush_tx_ring(struct rte_eth_dev *dev)\n+{\n+\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tvolatile struct e1000_data_desc *tx_desc;\n+\tvolatile uint32_t *tdt_reg_addr;\n+\tuint32_t tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;\n+\tuint16_t size = 512;\n+\tstruct em_tx_queue *txq;\n+\tint i;\n+\n+\tif (dev->data->tx_queues == NULL)\n+\t\treturn;\n+\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n+\tE1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);\n+\tfor (i = 0; i < dev->data->nb_tx_queues &&\n+\t\ti < E1000_I219_MAX_TX_QUEUE_NUM; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\t\ttdt = E1000_READ_REG(hw, E1000_TDT(i));\n+\t\tif (tdt != txq->tx_tail)\n+\t\t\treturn;\n+\t\ttx_desc = &txq->tx_ring[txq->tx_tail];\n+\t\ttx_desc->buffer_addr = rte_cpu_to_le_64(txq->tx_ring_phys_addr);\n+\t\ttx_desc->lower.data = rte_cpu_to_le_32(txd_lower | size);\n+\t\ttx_desc->upper.data = 0;\n+\n+\t\trte_wmb();\n+\t\ttxq->tx_tail++;\n+\t\tif (txq->tx_tail == txq->nb_tx_desc)\n+\t\t\ttxq->tx_tail = 0;\n+\t\trte_io_wmb();\n+\t\ttdt_reg_addr = E1000_PCI_REG_ADDR(hw, E1000_TDT(i));\n+\t\tE1000_PCI_REG_WRITE_RELAXED(tdt_reg_addr, txq->tx_tail);\n+\t\tusec_delay(250);\n+\t}\n+}\n+\n+static void e1000_flush_rx_ring(struct rte_eth_dev *dev)\n+{\n+\tuint32_t rctl, rxdctl;\n+\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tint i;\n+\n+\trctl = E1000_READ_REG(hw, E1000_RCTL);\n+\tE1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);\n+\tE1000_WRITE_FLUSH(hw);\n+\tusec_delay(150);\n+\n+\tfor (i = 0; i < dev->data->nb_rx_queues &&\n+\t\ti < E1000_I219_MAX_RX_QUEUE_NUM; i++) {\n+\t\trxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));\n+\t\t/* zero the lower 14 bits (prefetch and host thresholds) */\n+\t\trxdctl &= 0xffffc000;\n+\n+\t\t/* update thresholds: prefetch threshold to 31,\n+\t\t * host threshold to 1 and make sure the granularity\n+\t\t * is \"descriptors\" and not \"cache lines\"\n+\t\t */\n+\t\trxdctl |= (0x1F | (1UL << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);\n+\n+\t\tE1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);\n+\t}\n+\t/* momentarily enable the RX ring for the changes to take effect */\n+\tE1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);\n+\tE1000_WRITE_FLUSH(hw);\n+\tusec_delay(150);\n+\tE1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);\n+}\n+\n+/**\n+ * em_flush_desc_rings - remove all descriptors from the descriptor rings\n+ *\n+ * In i219, the descriptor rings must be emptied before resetting/closing the\n+ * HW. Failure to do this will cause the HW to enter a unit hang state which\n+ * can only be released by PCI reset on the device\n+ *\n+ */\n+\n+void em_flush_desc_rings(struct rte_eth_dev *dev)\n+{\n+\tuint32_t fextnvm11, tdlen;\n+\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tuint16_t pci_cfg_status = 0;\n+\n+\tfextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);\n+\tE1000_WRITE_REG(hw, E1000_FEXTNVM11,\n+\t\t\tfextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);\n+\ttdlen = E1000_READ_REG(hw, E1000_TDLEN(0));\n+\trte_pci_read_config(pci_dev, &pci_cfg_status, sizeof(pci_cfg_status),\n+\t\t\t\tPCI_CFG_STATUS_REG);\n+\n+\t/* do nothing if we're not in faulty state, or if the queue is empty */\n+\tif ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {\n+\t\t/* flush desc ring */\n+\t\te1000_flush_tx_ring(dev);\n+\t\trte_pci_read_config(pci_dev, &pci_cfg_status,\n+\t\t\t\tsizeof(pci_cfg_status), PCI_CFG_STATUS_REG);\n+\t\tif (pci_cfg_status & FLUSH_DESC_REQUIRED)\n+\t\t\te1000_flush_rx_ring(dev);\n+\t}\n+}\n", "prefixes": [ "v7" ] }