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{ "id": 56563, "url": "http://patches.dpdk.org/api/patches/56563/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190717052837.647-7-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190717052837.647-7-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190717052837.647-7-rnagadheeraj@marvell.com", "date": "2019-07-17T05:29:09", "name": "[06/10] crypto/nitrox: add hardware queue management functionality", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ae3d8b3dd303e0d9e85e5f11cafd1a5cb422e60a", "submitter": { "id": 1365, "url": "http://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190717052837.647-7-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 5550, "url": "http://patches.dpdk.org/api/series/5550/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5550", "date": "2019-07-17T05:29:01", "name": "add Nitrox crypto device support", "version": 1, "mbox": "http://patches.dpdk.org/series/5550/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56563/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/56563/checks/", "tags": {}, "related": [], "headers": { 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"uEgezmRUQP/IHBgBv77A9jWIRxRn9gfCAQ617DpVuU1ZAmDEH9cGmHSoKmQWCgHg78OmxhrQHd5l2uyTz8vjC2bcpM0yVi8MCT/tJrMANobcIx+BmuzYLIRPvca2+badD8NlWdr/NSAwczm3dgFmiFwXWp1FV78EaJvx7osYMraB4s4dGVsZF4mJMz2t8AHMxNSePFOxt8oe++R+ILPhG68TM7/tc6C0VXwZVi/+qE5b6vGggIAlrDDmJA2/bKGSdWCB3jR4dBAFADXD0ywp+HNumB1F2w+gye78hXG7PDucA9dgMqmwuzrGp1fXT+4IP7PKagrIOAWuT6F0n92P0aVgVkgyfeEyQBkmJukBaUUsDkKK2Dw1yISNWDuqxGqcH+M1jpPBxVk6Im0DqlWEi/gjG1n0nmQGGdEQstAOoFs=", "Content-Type": "text/plain; charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-MS-Exchange-CrossTenant-Network-Message-Id": "0d6a9ab3-6562-44e5-d5f7-08d70a77b184", "X-MS-Exchange-CrossTenant-originalarrivaltime": "17 Jul 2019 05:29:09.4231\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "70e1fb47-1155-421d-87fc-2e58f638b6e0", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "rnagadheeraj@marvell.com", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR18MB2767", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:5.22.84,1.0.8\n\tdefinitions=2019-07-17_02:2019-07-16,2019-07-17 signatures=0", "Subject": "[dpdk-dev] [PATCH 06/10] crypto/nitrox: add hardware queue\n\tmanagement functionality", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add hardware queue management code corresponding to queue pair setup\nand release functions.\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n drivers/crypto/nitrox/nitrox_csr.h | 13 ++++\n drivers/crypto/nitrox/nitrox_hal.c | 151 +++++++++++++++++++++++++++++++++++++\n drivers/crypto/nitrox/nitrox_hal.h | 128 +++++++++++++++++++++++++++++++\n drivers/crypto/nitrox/nitrox_qp.c | 51 ++++++++++++-\n drivers/crypto/nitrox/nitrox_qp.h | 8 ++\n 5 files changed, 347 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h\nindex 879104515..fb9a34817 100644\n--- a/drivers/crypto/nitrox/nitrox_csr.h\n+++ b/drivers/crypto/nitrox/nitrox_csr.h\n@@ -9,6 +9,19 @@\n #include <rte_io.h>\n \n #define CSR_DELAY\t30\n+#define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset))\n+\n+/* NPS packet registers */\n+#define NPS_PKT_IN_INSTR_CTLX(_i)\t(0x10060 + ((_i) * 0x40000))\n+#define NPS_PKT_IN_INSTR_BADDRX(_i)\t(0x10068 + ((_i) * 0x40000))\n+#define NPS_PKT_IN_INSTR_RSIZEX(_i)\t(0x10070 + ((_i) * 0x40000))\n+#define NPS_PKT_IN_DONE_CNTSX(_i)\t(0x10080 + ((_i) * 0x40000))\n+#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)\t(0x10078 + ((_i) * 0x40000))\n+#define NPS_PKT_IN_INT_LEVELSX(_i)\t\t(0x10088 + ((_i) * 0x40000))\n+\n+#define NPS_PKT_SLC_CTLX(_i)\t\t(0x10000 + ((_i) * 0x40000))\n+#define NPS_PKT_SLC_CNTSX(_i)\t\t(0x10008 + ((_i) * 0x40000))\n+#define NPS_PKT_SLC_INT_LEVELSX(_i)\t(0x10010 + ((_i) * 0x40000))\n \n /* AQM Virtual Function Registers */\n #define AQMQ_QSZX(_i)\t\t\t(0x20008 + ((_i)*0x40000))\ndiff --git a/drivers/crypto/nitrox/nitrox_hal.c b/drivers/crypto/nitrox/nitrox_hal.c\nindex 3dee59215..3c2c24c23 100644\n--- a/drivers/crypto/nitrox/nitrox_hal.c\n+++ b/drivers/crypto/nitrox/nitrox_hal.c\n@@ -12,6 +12,157 @@\n \n #define MAX_VF_QUEUES\t8\n #define MAX_PF_QUEUES\t64\n+#define NITROX_TIMER_THOLD\t0x3FFFFF\n+#define NITROX_COUNT_THOLD 0xFFFFFFFF\n+\n+void\n+nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring)\n+{\n+\tunion nps_pkt_in_instr_ctl pkt_in_instr_ctl;\n+\tuint64_t reg_addr;\n+\tint max_retries = 5;\n+\n+\treg_addr = NPS_PKT_IN_INSTR_CTLX(ring);\n+\tpkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\tpkt_in_instr_ctl.s.enb = 0;\n+\tnitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_ctl.u64);\n+\trte_delay_us_block(100);\n+\n+\t/* wait for enable bit to be cleared */\n+\tpkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\twhile (pkt_in_instr_ctl.s.enb && max_retries--) {\n+\t\trte_delay_ms(10);\n+\t\tpkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\t}\n+}\n+\n+void\n+nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port)\n+{\n+\tunion nps_pkt_slc_ctl pkt_slc_ctl;\n+\tuint64_t reg_addr;\n+\tint max_retries = 5;\n+\n+\t/* clear enable bit */\n+\treg_addr = NPS_PKT_SLC_CTLX(port);\n+\tpkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\tpkt_slc_ctl.s.enb = 0;\n+\tnitrox_write_csr(bar_addr, reg_addr, pkt_slc_ctl.u64);\n+\trte_delay_us_block(100);\n+\n+\tpkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\twhile (pkt_slc_ctl.s.enb && max_retries--) {\n+\t\trte_delay_ms(10);\n+\t\tpkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\t}\n+}\n+\n+void\n+setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize,\n+\t\t\t phys_addr_t raddr)\n+{\n+\tunion nps_pkt_in_instr_ctl pkt_in_instr_ctl;\n+\tunion nps_pkt_in_instr_rsize pkt_in_instr_rsize;\n+\tunion nps_pkt_in_instr_baoff_dbell pkt_in_instr_baoff_dbell;\n+\tunion nps_pkt_in_done_cnts pkt_in_done_cnts;\n+\tuint64_t base_addr, reg_addr;\n+\tint max_retries = 5;\n+\n+\tnps_pkt_input_ring_disable(bar_addr, ring);\n+\n+\t/* write base address */\n+\treg_addr = NPS_PKT_IN_INSTR_BADDRX(ring);\n+\tbase_addr = raddr;\n+\tnitrox_write_csr(bar_addr, reg_addr, base_addr);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* write ring size */\n+\treg_addr = NPS_PKT_IN_INSTR_RSIZEX(ring);\n+\tpkt_in_instr_rsize.u64 = 0;\n+\tpkt_in_instr_rsize.s.rsize = rsize;\n+\tnitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_rsize.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* clear door bell */\n+\treg_addr = NPS_PKT_IN_INSTR_BAOFF_DBELLX(ring);\n+\tpkt_in_instr_baoff_dbell.u64 = 0;\n+\tpkt_in_instr_baoff_dbell.s.dbell = 0xFFFFFFFF;\n+\tnitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_baoff_dbell.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* clear done count */\n+\treg_addr = NPS_PKT_IN_DONE_CNTSX(ring);\n+\tpkt_in_done_cnts.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\tnitrox_write_csr(bar_addr, reg_addr, pkt_in_done_cnts.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* Setup PKT IN RING Interrupt Threshold */\n+\treg_addr = NPS_PKT_IN_INT_LEVELSX(ring);\n+\tnitrox_write_csr(bar_addr, reg_addr, 0xFFFFFFFF);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* enable ring */\n+\treg_addr = NPS_PKT_IN_INSTR_CTLX(ring);\n+\tpkt_in_instr_ctl.u64 = 0;\n+\tpkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\tpkt_in_instr_ctl.s.is64b = 1;\n+\tpkt_in_instr_ctl.s.enb = 1;\n+\tnitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_ctl.u64);\n+\trte_delay_us_block(100);\n+\n+\tpkt_in_instr_ctl.u64 = 0;\n+\tpkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\t/* wait for ring to be enabled */\n+\twhile (!pkt_in_instr_ctl.s.enb && max_retries--) {\n+\t\trte_delay_ms(10);\n+\t\tpkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\t}\n+}\n+\n+void\n+setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port)\n+{\n+\tunion nps_pkt_slc_ctl pkt_slc_ctl;\n+\tunion nps_pkt_slc_cnts pkt_slc_cnts;\n+\tunion nps_pkt_slc_int_levels pkt_slc_int_levels;\n+\tuint64_t reg_addr;\n+\tint max_retries = 5;\n+\n+\tnps_pkt_solicited_port_disable(bar_addr, port);\n+\n+\t/* clear pkt counts */\n+\treg_addr = NPS_PKT_SLC_CNTSX(port);\n+\tpkt_slc_cnts.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\tnitrox_write_csr(bar_addr, reg_addr, pkt_slc_cnts.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* slc interrupt levels */\n+\treg_addr = NPS_PKT_SLC_INT_LEVELSX(port);\n+\tpkt_slc_int_levels.u64 = 0;\n+\tpkt_slc_int_levels.s.bmode = 0;\n+\tpkt_slc_int_levels.s.timet = NITROX_TIMER_THOLD;\n+\n+\tif (NITROX_COUNT_THOLD > 0)\n+\t\tpkt_slc_int_levels.s.cnt = NITROX_COUNT_THOLD - 1;\n+\n+\tnitrox_write_csr(bar_addr, reg_addr, pkt_slc_int_levels.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\t/* enable ring */\n+\treg_addr = NPS_PKT_SLC_CTLX(port);\n+\tpkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\tpkt_slc_ctl.s.rh = 1;\n+\tpkt_slc_ctl.s.z = 1;\n+\tpkt_slc_ctl.s.enb = 1;\n+\tnitrox_write_csr(bar_addr, reg_addr, pkt_slc_ctl.u64);\n+\trte_delay_us_block(100);\n+\n+\tpkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\twhile (!pkt_slc_ctl.s.enb && max_retries--) {\n+\t\trte_delay_ms(10);\n+\t\tpkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\t}\n+}\n \n int\n vf_get_vf_config_mode(uint8_t *bar_addr)\ndiff --git a/drivers/crypto/nitrox/nitrox_hal.h b/drivers/crypto/nitrox/nitrox_hal.h\nindex 6184211a5..dcfbd11d8 100644\n--- a/drivers/crypto/nitrox/nitrox_hal.h\n+++ b/drivers/crypto/nitrox/nitrox_hal.h\n@@ -10,6 +10,129 @@\n \n #include \"nitrox_csr.h\"\n \n+union nps_pkt_slc_cnts {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t slc_int : 1;\n+\t\tuint64_t uns_int : 1;\n+\t\tuint64_t in_int : 1;\n+\t\tuint64_t mbox_int : 1;\n+\t\tuint64_t resend : 1;\n+\t\tuint64_t raz : 5;\n+\t\tuint64_t timer : 22;\n+\t\tuint64_t cnt : 32;\n+#else\n+\t\tuint64_t cnt : 32;\n+\t\tuint64_t timer : 22;\n+\t\tuint64_t raz : 5;\n+\t\tuint64_t resend : 1;\n+\t\tuint64_t mbox_int : 1;\n+\t\tuint64_t in_int : 1;\n+\t\tuint64_t uns_int : 1;\n+\t\tuint64_t slc_int : 1;\n+#endif\n+\t} s;\n+};\n+\n+union nps_pkt_slc_int_levels {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t bmode : 1;\n+\t\tuint64_t raz : 9;\n+\t\tuint64_t timet : 22;\n+\t\tuint64_t cnt : 32;\n+#else\n+\t\tuint64_t cnt : 32;\n+\t\tuint64_t timet : 22;\n+\t\tuint64_t raz : 9;\n+\t\tuint64_t bmode : 1;\n+#endif\n+\t} s;\n+};\n+\n+union nps_pkt_slc_ctl {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz : 61;\n+\t\tuint64_t rh : 1;\n+\t\tuint64_t z : 1;\n+\t\tuint64_t enb : 1;\n+#else\n+\t\tuint64_t enb : 1;\n+\t\tuint64_t z : 1;\n+\t\tuint64_t rh : 1;\n+\t\tuint64_t raz : 61;\n+#endif\n+\t} s;\n+};\n+\n+union nps_pkt_in_instr_ctl {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz : 62;\n+\t\tuint64_t is64b : 1;\n+\t\tuint64_t enb : 1;\n+#else\n+\t\tuint64_t enb : 1;\n+\t\tuint64_t is64b : 1;\n+\t\tuint64_t raz : 62;\n+#endif\n+\t} s;\n+};\n+\n+union nps_pkt_in_instr_rsize {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz : 32;\n+\t\tuint64_t rsize : 32;\n+#else\n+\t\tuint64_t rsize : 32;\n+\t\tuint64_t raz : 32;\n+#endif\n+\t} s;\n+};\n+\n+union nps_pkt_in_instr_baoff_dbell {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t aoff : 32;\n+\t\tuint64_t dbell : 32;\n+#else\n+\t\tuint64_t dbell : 32;\n+\t\tuint64_t aoff : 32;\n+#endif\n+\t} s;\n+};\n+\n+union nps_pkt_in_done_cnts {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t slc_int : 1;\n+\t\tuint64_t uns_int : 1;\n+\t\tuint64_t in_int : 1;\n+\t\tuint64_t mbox_int : 1;\n+\t\tuint64_t resend : 1;\n+\t\tuint64_t raz : 27;\n+\t\tuint64_t cnt : 32;\n+#else\n+\t\tuint64_t cnt : 32;\n+\t\tuint64_t raz : 27;\n+\t\tuint64_t resend : 1;\n+\t\tuint64_t mbox_int : 1;\n+\t\tuint64_t in_int : 1;\n+\t\tuint64_t uns_int : 1;\n+\t\tuint64_t slc_int : 1;\n+#endif\n+\t} s;\n+};\n+\n union aqmq_qsz {\n \tuint64_t u64;\n \tstruct {\n@@ -33,5 +156,10 @@ enum nitrox_vf_mode {\n \n int vf_get_vf_config_mode(uint8_t *bar_addr);\n int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode);\n+void setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize,\n+\t\t\t phys_addr_t raddr);\n+void setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port);\n+void nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring);\n+void nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port);\n \n #endif /* _NITROX_HAL_H_ */\ndiff --git a/drivers/crypto/nitrox/nitrox_qp.c b/drivers/crypto/nitrox/nitrox_qp.c\nindex 9673bb4f3..a56617247 100644\n--- a/drivers/crypto/nitrox/nitrox_qp.c\n+++ b/drivers/crypto/nitrox/nitrox_qp.c\n@@ -10,6 +10,38 @@\n #include \"nitrox_logs.h\"\n \n #define MAX_CMD_QLEN 16384\n+#define CMDQ_PKT_IN_ALIGN 16\n+\n+static int\n+nitrox_setup_cmdq(struct nitrox_qp *qp, uint8_t *bar_addr,\n+\t\t const char *dev_name, uint8_t instr_size, int socket_id)\n+{\n+\tchar mz_name[RTE_MEMZONE_NAMESIZE];\n+\tconst struct rte_memzone *mz;\n+\tsize_t cmdq_size = qp->count * instr_size;\n+\tuint64_t offset;\n+\n+\tsnprintf(mz_name, sizeof(mz_name), \"%s_cmdq_%d\", dev_name, qp->qno);\n+\tmz = rte_memzone_reserve_aligned(mz_name, cmdq_size, socket_id,\n+\t\t\t\t\t RTE_MEMZONE_SIZE_HINT_ONLY |\n+\t\t\t\t\t RTE_MEMZONE_256MB,\n+\t\t\t\t\t CMDQ_PKT_IN_ALIGN);\n+\tif (!mz) {\n+\t\tNITROX_LOG(ERR, \"cmdq memzone reserve failed for %s queue\\n\",\n+\t\t\t mz_name);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tqp->cmdq.mz = mz;\n+\toffset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(qp->qno);\n+\tqp->cmdq.dbell_csr_addr = NITROX_CSR_ADDR(bar_addr, offset);\n+\tqp->cmdq.ring = mz->addr;\n+\tqp->cmdq.instr_size = instr_size;\n+\tsetup_nps_pkt_input_ring(bar_addr, qp->qno, qp->count, mz->iova);\n+\tsetup_nps_pkt_solicit_output_port(bar_addr, qp->qno);\n+\n+\treturn 0;\n+}\n \n static int\n nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id)\n@@ -27,6 +59,15 @@ nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id)\n \treturn 0;\n }\n \n+static int\n+nitrox_release_cmdq(struct nitrox_qp *qp, uint8_t *bar_addr)\n+{\n+\tnps_pkt_solicited_port_disable(bar_addr, qp->qno);\n+\tnps_pkt_input_ring_disable(bar_addr, qp->qno);\n+\n+\treturn rte_memzone_free(qp->cmdq.mz);\n+}\n+\n int\n nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name,\n \t\tuint32_t nb_descriptors, uint8_t instr_size, int socket_id)\n@@ -34,8 +75,6 @@ nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name,\n \tint err;\n \tuint32_t count;\n \n-\tRTE_SET_USED(bar_addr);\n-\tRTE_SET_USED(instr_size);\n \tcount = rte_align32pow2(nb_descriptors);\n \tif (count > MAX_CMD_QLEN) {\n \t\tNITROX_LOG(ERR, \"%s: Number of descriptors too big %d,\"\n@@ -48,6 +87,10 @@ nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name,\n \tqp->count = count;\n \tqp->head = qp->tail = 0;\n \trte_atomic16_init(&qp->pending_count);\n+\terr = nitrox_setup_cmdq(qp, bar_addr, dev_name, instr_size, socket_id);\n+\tif (err)\n+\t\treturn err;\n+\n \terr = nitrox_setup_ridq(qp, socket_id);\n \tif (err)\n \t\tgoto ridq_err;\n@@ -55,6 +98,7 @@ nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name,\n \treturn 0;\n \n ridq_err:\n+\tnitrox_release_cmdq(qp, bar_addr);\n \treturn err;\n \n }\n@@ -68,7 +112,6 @@ nitrox_release_ridq(struct nitrox_qp *qp)\n int\n nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr)\n {\n-\tRTE_SET_USED(bar_addr);\n \tnitrox_release_ridq(qp);\n-\treturn 0;\n+\treturn nitrox_release_cmdq(qp, bar_addr);\n }\ndiff --git a/drivers/crypto/nitrox/nitrox_qp.h b/drivers/crypto/nitrox/nitrox_qp.h\nindex cf0102ff9..0244c4dbf 100644\n--- a/drivers/crypto/nitrox/nitrox_qp.h\n+++ b/drivers/crypto/nitrox/nitrox_qp.h\n@@ -11,11 +11,19 @@\n \n struct nitrox_softreq;\n \n+struct command_queue {\n+\tconst struct rte_memzone *mz;\n+\tuint8_t *dbell_csr_addr;\n+\tuint8_t *ring;\n+\tuint8_t instr_size;\n+};\n+\n struct rid {\n \tstruct nitrox_softreq *sr;\n };\n \n struct nitrox_qp {\n+\tstruct command_queue cmdq;\n \tstruct rid *ridq;\n \tuint32_t count;\n \tuint32_t head;\n", "prefixes": [ "06/10" ] }