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GET /api/patches/56458/?format=api
{ "id": 56458, "url": "http://patches.dpdk.org/api/patches/56458/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1563199161-29745-8-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1563199161-29745-8-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1563199161-29745-8-git-send-email-viacheslavo@mellanox.com", "date": "2019-07-15T13:59:21", "name": "[v2,7/7] net/mlx5: add minimal required Tx data inline", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "efa9cceeb449de1130a33cdda04eb7293dec2936", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1563199161-29745-8-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 5500, "url": "http://patches.dpdk.org/api/series/5500/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5500", "date": "2019-07-15T13:59:14", "name": "net/mlx5: consolidate Tx datapath", "version": 2, "mbox": "http://patches.dpdk.org/series/5500/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56458/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/56458/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 15F4A1BDE4;\n\tMon, 15 Jul 2019 16:00:09 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id DCBF11BDE2\n\tfor <dev@dpdk.org>; Mon, 15 Jul 2019 16:00:07 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tviacheslavo@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 15 Jul 2019 17:00:06 +0300", "from pegasus12.mtr.labs.mlnx. (pegasus12.mtr.labs.mlnx\n\t[10.210.17.40])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6FDxOEQ013758;\n\tMon, 15 Jul 2019 17:00:02 +0300" ], "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "yskoh@mellanox.com", "Date": "Mon, 15 Jul 2019 13:59:21 +0000", "Message-Id": "<1563199161-29745-8-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1563199161-29745-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1562257767-19035-2-git-send-email-viacheslavo@mellanox.com>\n\t<1563199161-29745-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 7/7] net/mlx5: add minimal required Tx data\n\tinline", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Tx data packet data may be inlined into transmit descriptor.\nAt some circumstances ConnectX NICs may require data to be\ninlined for correct operation. The exact data amount may\ndepend on NIC operation mode, requested Tx offloads,\nE-Switch configuration, etc.\n\nThe number of data bytes to inline may be specified with\ndevargs key \"txq_inline_min\". If this key is present the\nspecified value (may be aligned by the driver in order\nnot to exceed the limits and provide better descriptor\nspace utilization) will be used by the driver and it\nis guaranteed the requested data bytes are inlined into\nthe descriptor beside other inline settings.\n\nIf \"txq_inline_min\" key is not present the value may\nbe queried by the driver from the NIC via DevX if this\nfeature is available. This patch provides the implementation\nof this query.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/net/mlx5/mlx5.c | 93 +++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 4 ++\n drivers/net/mlx5/mlx5_defs.h | 18 ++++++\n drivers/net/mlx5/mlx5_devx_cmds.c | 100 ++++++++++++++++++++++++++++++-\n drivers/net/mlx5/mlx5_prm.h | 121 +++++++++++++++++++++++++++++++++++++-\n 5 files changed, 334 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex e803f08..ce3a62b 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1045,6 +1045,97 @@ struct mlx5_dev_spawn_data {\n }\n \n /**\n+ * Configures the minimal amount of data to inline into WQE\n+ * while sending packets.\n+ *\n+ * - the txq_inline_min has the maximal priority, if this\n+ * key is specified in devargs\n+ * - if DevX is enabled the inline mode is queried from the\n+ * device (HCA attributes and NIC vport context if needed).\n+ * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4LX\n+ * and none (0 bytes) for other NICs\n+ *\n+ * @param spawn\n+ * Verbs device parameters (name, port, switch_info) to spawn.\n+ * @param config\n+ * Device configuration parameters.\n+ */\n+static void\n+mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,\n+\t\t struct mlx5_dev_config *config)\n+{\n+\tif (config->txq_inline_min != MLX5_ARG_UNSET) {\n+\t\t/* Application defines size of inlined data explicitly. */\n+\t\tgoto exit;\n+\t}\n+\tif (config->hca_attr.eth_net_offloads) {\n+\t\t/* We have DevX enabled, inline mode queried successfully. */\n+\t\tswitch (config->hca_attr.wqe_inline_mode) {\n+\t\tcase MLX5_CAP_INLINE_MODE_L2:\n+\t\t\t/* outer L2 header must be inlined. */\n+\t\t\tconfig->txq_inline_min = MLX5_INLINE_HSIZE_L2;\n+\t\t\tgoto exit;\n+\t\tcase MLX5_CAP_INLINE_MODE_NOT_REQUIRED:\n+\t\t\t/* No inline data are required by NIC. */\n+\t\t\tconfig->txq_inline_min = MLX5_INLINE_HSIZE_NONE;\n+\t\t\tgoto exit;\n+\t\tcase MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:\n+\t\t\t/* inline mode is defined by NIC vport context. */\n+\t\t\tif (!config->hca_attr.eth_virt)\n+\t\t\t\tbreak;\n+\t\t\tswitch (config->hca_attr.vport_inline_mode) {\n+\t\t\tcase MLX5_INLINE_MODE_NONE:\n+\t\t\t\tconfig->txq_inline_min =\n+\t\t\t\t\tMLX5_INLINE_HSIZE_NONE;\n+\t\t\t\tgoto exit;\n+\t\t\tcase MLX5_INLINE_MODE_L2:\n+\t\t\t\tconfig->txq_inline_min =\n+\t\t\t\t\tMLX5_INLINE_HSIZE_L2;\n+\t\t\t\tgoto exit;\n+\t\t\tcase MLX5_INLINE_MODE_IP:\n+\t\t\t\tconfig->txq_inline_min =\n+\t\t\t\t\tMLX5_INLINE_HSIZE_L3;\n+\t\t\t\tgoto exit;\n+\t\t\tcase MLX5_INLINE_MODE_TCP_UDP:\n+\t\t\t\tconfig->txq_inline_min =\n+\t\t\t\t\tMLX5_INLINE_HSIZE_L4;\n+\t\t\t\tgoto exit;\n+\t\t\tcase MLX5_INLINE_MODE_INNER_L2:\n+\t\t\t\tconfig->txq_inline_min =\n+\t\t\t\t\tMLX5_INLINE_HSIZE_INNER_L2;\n+\t\t\t\tgoto exit;\n+\t\t\tcase MLX5_INLINE_MODE_INNER_IP:\n+\t\t\t\tconfig->txq_inline_min =\n+\t\t\t\t\tMLX5_INLINE_HSIZE_INNER_L3;\n+\t\t\t\tgoto exit;\n+\t\t\tcase MLX5_INLINE_MODE_INNER_TCP_UDP:\n+\t\t\t\tconfig->txq_inline_min =\n+\t\t\t\t\tMLX5_INLINE_HSIZE_INNER_L4;\n+\t\t\t\tgoto exit;\n+\t\t\t}\n+\t\t}\n+\t}\n+\t/*\n+\t * We get here if we are unable to deduce\n+\t * inline data size with DevX. Try PCI ID\n+\t * to determine old NICs.\n+\t */\n+\tswitch (spawn->pci_dev->id.device_id) {\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4:\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:\n+\tcase PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:\n+\t\tconfig->txq_inline_min = MLX5_INLINE_HSIZE_L2;\n+\t\tbreak;\n+\tdefault:\n+\t\tconfig->txq_inline_min = MLX5_INLINE_HSIZE_NONE;\n+\t\tbreak;\n+\t}\n+exit:\n+\tDRV_LOG(DEBUG, \"min tx inline configured: %d\", config->txq_inline_min);\n+}\n+\n+/**\n * Spawn an Ethernet device from Verbs information.\n *\n * @param dpdk_dev\n@@ -1529,6 +1620,8 @@ struct mlx5_dev_spawn_data {\n #else\n \tconfig.dv_esw_en = 0;\n #endif\n+\t/* Detect minimal data bytes to inline. */\n+\tmlx5_set_min_inline(spawn, &config);\n \t/* Store device configuration on private structure. */\n \tpriv->config = config;\n \tif (config.dv_flow_en) {\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 8e2eab3..30be381 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -161,6 +161,10 @@ struct mlx5_devx_counter_set {\n /* HCA attributes. */\n struct mlx5_hca_attr {\n \tuint32_t eswitch_manager:1;\n+\tuint32_t eth_net_offloads:1;\n+\tuint32_t eth_virt:1;\n+\tuint32_t wqe_inline_mode:2;\n+\tuint32_t vport_inline_mode:3;\n };\n \n /* Flow list . */\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 873a595..8c118d5 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -60,6 +60,24 @@\n /* Maximum Packet headers size (L2+L3+L4) for TSO. */\n #define MLX5_MAX_TSO_HEADER (128u + 34u)\n \n+/* Inline data size required by NICs. */\n+#define MLX5_INLINE_HSIZE_NONE 0\n+#define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \\\n+\t\t\t sizeof(struct rte_vlan_hdr))\n+#define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \\\n+\t\t\t sizeof(struct rte_ipv6_hdr))\n+#define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \\\n+\t\t\t sizeof(struct rte_tcp_hdr))\n+#define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \\\n+\t\t\t\t sizeof(struct rte_udp_hdr) + \\\n+\t\t\t\t sizeof(struct rte_vxlan_hdr) + \\\n+\t\t\t\t sizeof(struct rte_ether_hdr) + \\\n+\t\t\t\t sizeof(struct rte_vlan_hdr))\n+#define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \\\n+\t\t\t\t sizeof(struct rte_ipv6_hdr))\n+#define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \\\n+\t\t\t\t sizeof(struct rte_tcp_hdr))\n+\n /* Threshold of buffer replenishment for vectorized Rx. */\n #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \\\n \t(RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2))\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c\nindex e5776c4..de470a6 100644\n--- a/drivers/net/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.c\n@@ -107,6 +107,59 @@ int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj)\n }\n \n /**\n+ * Query NIC vport context.\n+ * Currently fiils minimal inline attribute.\n+ *\n+ * @param[in] ctx\n+ * ibv contexts returned from mlx5dv_open_device.\n+ * @param[in] vport\n+ * vport index\n+ * @param[out] attr\n+ * Attributes device values.\n+ *\n+ * @return\n+ * 0 on success, a negative value otherwise.\n+ */\n+static int\n+mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,\n+\t\t\t\t unsigned int vport,\n+\t\t\t\t struct mlx5_hca_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};\n+\tvoid *vctx;\n+\tint status, syndrome, rc;\n+\n+\t/* Query NIC vport context to determine inline mode. */\n+\tMLX5_SET(query_nic_vport_context_in, in, opcode,\n+\t\t MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);\n+\tMLX5_SET(query_nic_vport_context_in, in, vport_number, vport);\n+\tif (vport)\n+\t\tMLX5_SET(query_nic_vport_context_in, in, other_vport, 1);\n+\trc = mlx5_glue->devx_general_cmd(ctx,\n+\t\t\t\t\t in, sizeof(in),\n+\t\t\t\t\t out, sizeof(out));\n+\tif (rc)\n+\t\tgoto error;\n+\tstatus = MLX5_GET(query_nic_vport_context_out, out, status);\n+\tsyndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);\n+\tif (status) {\n+\t\tDRV_LOG(DEBUG, \"Failed to query NIC vport context, \"\n+\t\t\t\"status %x, syndrome = %x\",\n+\t\t\tstatus, syndrome);\n+\t\treturn -1;\n+\t}\n+\tvctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,\n+\t\t\t nic_vport_context);\n+\tattr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,\n+\t\t\t\t\t min_wqe_inline_mode);\n+\treturn 0;\n+error:\n+\trc = (rc > 0) ? -rc : rc;\n+\treturn rc;\n+}\n+\n+/**\n * Query HCA attributes.\n * Using those attributes we can check on run time if the device\n * is having the required capabilities.\n@@ -136,7 +189,7 @@ int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj)\n \trc = mlx5_glue->devx_general_cmd(ctx,\n \t\t\t\t\t in, sizeof(in), out, sizeof(out));\n \tif (rc)\n-\t\treturn rc;\n+\t\tgoto error;\n \tstatus = MLX5_GET(query_hca_cap_out, out, status);\n \tsyndrome = MLX5_GET(query_hca_cap_out, out, syndrome);\n \tif (status) {\n@@ -147,5 +200,50 @@ int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj)\n \t}\n \thcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n \tattr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);\n+\tattr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,\n+\t\t\t\t\t eth_net_offloads);\n+\tattr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);\n+\tif (!attr->eth_net_offloads)\n+\t\treturn 0;\n+\n+\t/* Query HCA offloads for Ethernet protocol. */\n+\tmemset(in, 0, sizeof(in));\n+\tmemset(out, 0, sizeof(out));\n+\tMLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);\n+\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t MLX5_GET_HCA_CAP_OP_MOD_ETHERNET |\n+\t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\n+\trc = mlx5_glue->devx_general_cmd(ctx,\n+\t\t\t\t\t in, sizeof(in),\n+\t\t\t\t\t out, sizeof(out));\n+\tif (rc) {\n+\t\tattr->eth_net_offloads = 0;\n+\t\tgoto error;\n+\t}\n+\tstatus = MLX5_GET(query_hca_cap_out, out, status);\n+\tsyndrome = MLX5_GET(query_hca_cap_out, out, syndrome);\n+\tif (status) {\n+\t\tDRV_LOG(DEBUG, \"Failed to query devx HCA capabilities, \"\n+\t\t\t\"status %x, syndrome = %x\",\n+\t\t\tstatus, syndrome);\n+\t\tattr->eth_net_offloads = 0;\n+\t\treturn -1;\n+\t}\n+\thcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n+\tattr->wqe_inline_mode = MLX5_GET(eth_offload_cap, hcattr,\n+\t\t\t\t\t wqe_inline_mode);\n+\tif (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)\n+\t\treturn 0;\n+\tif (attr->eth_virt) {\n+\t\trc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);\n+\t\tif (rc) {\n+\t\t\tattr->eth_virt = 0;\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n \treturn 0;\n+error:\n+\trc = (rc > 0) ? -rc : rc;\n+\treturn rc;\n }\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex a251369..617dce4 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -616,6 +616,7 @@ enum {\n \n enum {\n \tMLX5_CMD_OP_QUERY_HCA_CAP = 0x100,\n+\tMLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,\n \tMLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,\n \tMLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,\n };\n@@ -680,7 +681,8 @@ struct mlx5_ifc_query_flow_counter_in_bits {\n \n enum {\n \tMLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,\n-\tMLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,\n+\tMLX5_GET_HCA_CAP_OP_MOD_ETHERNET = 0x1 << 1,\n+\tMLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,\n };\n \n enum {\n@@ -688,6 +690,23 @@ enum {\n \tMLX5_HCA_CAP_OPMOD_GET_CUR = 1,\n };\n \n+enum {\n+\tMLX5_CAP_INLINE_MODE_L2,\n+\tMLX5_CAP_INLINE_MODE_VPORT_CONTEXT,\n+\tMLX5_CAP_INLINE_MODE_NOT_REQUIRED,\n+};\n+\n+enum {\n+\tMLX5_INLINE_MODE_NONE,\n+\tMLX5_INLINE_MODE_L2,\n+\tMLX5_INLINE_MODE_IP,\n+\tMLX5_INLINE_MODE_TCP_UDP,\n+\tMLX5_INLINE_MODE_RESERVED4,\n+\tMLX5_INLINE_MODE_INNER_L2,\n+\tMLX5_INLINE_MODE_INNER_IP,\n+\tMLX5_INLINE_MODE_INNER_TCP_UDP,\n+};\n+\n struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 reserved_at_0[0x30];\n \tu8 vhca_id[0x10];\n@@ -958,6 +977,42 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 reserved_at_61f[0x1e1];\n };\n \n+struct mlx5_ifc_eth_offload_cap_bits {\n+\tu8 csum_cap[0x1];\n+\tu8 vlan_cap[0x1];\n+\tu8 lro_cap[0x1];\n+\tu8 lro_psh_flag[0x1];\n+\tu8 lro_time_stamp[0x1];\n+\tu8 reserved_at_5[0x2];\n+\tu8 wqe_vlan_insert[0x1];\n+\tu8 self_lb_en_modifiable[0x1];\n+\tu8 reserved_at_9[0x2];\n+\tu8 max_lso_cap[0x5];\n+\tu8 multi_pkt_send_wqe[0x2];\n+\tu8 wqe_inline_mode[0x2];\n+\tu8 rss_ind_tbl_cap[0x4];\n+\tu8 reg_umr_sq[0x1];\n+\tu8 scatter_fcs[0x1];\n+\tu8 enhanced_multi_pkt_send_wqe[0x1];\n+\tu8 tunnel_lso_const_out_ip_id[0x1];\n+\tu8 reserved_at_1c[0x2];\n+\tu8 tunnel_stateless_gre[0x1];\n+\tu8 tunnel_stateless_vxlan[0x1];\n+\tu8 swp[0x1];\n+\tu8 swp_csum[0x1];\n+\tu8 swp_lso[0x1];\n+\tu8 reserved_at_23[0xd];\n+\tu8 max_vxlan_udp_ports[0x8];\n+\tu8 reserved_at_38[0x6];\n+\tu8 max_geneve_opt_len[0x1];\n+\tu8 tunnel_stateless_geneve_rx[0x1];\n+\tu8 reserved_at_40[0x10];\n+\tu8 lro_min_mss_size[0x10];\n+\tu8 reserved_at_60[0x120];\n+\tu8 lro_timer_supported_periods[4][0x20];\n+\tu8 reserved_at_200[0x600];\n+};\n+\n struct mlx5_ifc_qos_cap_bits {\n \tu8 packet_pacing[0x1];\n \tu8 esw_scheduling[0x1];\n@@ -985,6 +1040,7 @@ struct mlx5_ifc_qos_cap_bits {\n \n union mlx5_ifc_hca_cap_union_bits {\n \tstruct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;\n+\tstruct mlx5_ifc_eth_offload_cap_bits eth_offload_cap;\n \tstruct mlx5_ifc_qos_cap_bits qos_cap;\n \tu8 reserved_at_0[0x8000];\n };\n@@ -1005,6 +1061,69 @@ struct mlx5_ifc_query_hca_cap_in_bits {\n \tu8 reserved_at_40[0x40];\n };\n \n+struct mlx5_ifc_mac_address_layout_bits {\n+\tu8 reserved_at_0[0x10];\n+\tu8 mac_addr_47_32[0x10];\n+\tu8 mac_addr_31_0[0x20];\n+};\n+\n+struct mlx5_ifc_nic_vport_context_bits {\n+\tu8 reserved_at_0[0x5];\n+\tu8 min_wqe_inline_mode[0x3];\n+\tu8 reserved_at_8[0x15];\n+\tu8 disable_mc_local_lb[0x1];\n+\tu8 disable_uc_local_lb[0x1];\n+\tu8 roce_en[0x1];\n+\tu8 arm_change_event[0x1];\n+\tu8 reserved_at_21[0x1a];\n+\tu8 event_on_mtu[0x1];\n+\tu8 event_on_promisc_change[0x1];\n+\tu8 event_on_vlan_change[0x1];\n+\tu8 event_on_mc_address_change[0x1];\n+\tu8 event_on_uc_address_change[0x1];\n+\tu8 reserved_at_40[0xc];\n+\tu8 affiliation_criteria[0x4];\n+\tu8 affiliated_vhca_id[0x10];\n+\tu8 reserved_at_60[0xd0];\n+\tu8 mtu[0x10];\n+\tu8 system_image_guid[0x40];\n+\tu8 port_guid[0x40];\n+\tu8 node_guid[0x40];\n+\tu8 reserved_at_200[0x140];\n+\tu8 qkey_violation_counter[0x10];\n+\tu8 reserved_at_350[0x430];\n+\tu8 promisc_uc[0x1];\n+\tu8 promisc_mc[0x1];\n+\tu8 promisc_all[0x1];\n+\tu8 reserved_at_783[0x2];\n+\tu8 allowed_list_type[0x3];\n+\tu8 reserved_at_788[0xc];\n+\tu8 allowed_list_size[0xc];\n+\tstruct mlx5_ifc_mac_address_layout_bits permanent_address;\n+\tu8 reserved_at_7e0[0x20];\n+};\n+\n+struct mlx5_ifc_query_nic_vport_context_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+\tstruct mlx5_ifc_nic_vport_context_bits nic_vport_context;\n+};\n+\n+struct mlx5_ifc_query_nic_vport_context_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 other_vport[0x1];\n+\tu8 reserved_at_41[0xf];\n+\tu8 vport_number[0x10];\n+\tu8 reserved_at_60[0x5];\n+\tu8 allowed_list_type[0x3];\n+\tu8 reserved_at_68[0x18];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \n", "prefixes": [ "v2", "7/7" ] }