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GET /api/patches/56454/?format=api
{ "id": 56454, "url": "http://patches.dpdk.org/api/patches/56454/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1563199161-29745-4-git-send-email-viacheslavo@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1563199161-29745-4-git-send-email-viacheslavo@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1563199161-29745-4-git-send-email-viacheslavo@mellanox.com", "date": "2019-07-15T13:59:17", "name": "[v2,3/7] net/mlx5: update Tx datapath definitions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "70668c778321739cc07ea41b5c04bbf537ce9b43", "submitter": { "id": 1102, "url": "http://patches.dpdk.org/api/people/1102/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1563199161-29745-4-git-send-email-viacheslavo@mellanox.com/mbox/", "series": [ { "id": 5500, "url": "http://patches.dpdk.org/api/series/5500/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5500", "date": "2019-07-15T13:59:14", "name": "net/mlx5: consolidate Tx datapath", "version": 2, "mbox": "http://patches.dpdk.org/series/5500/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56454/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/56454/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BCDE82E83;\n\tMon, 15 Jul 2019 15:59:49 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id BF0BD1B9D6\n\tfor <dev@dpdk.org>; Mon, 15 Jul 2019 15:59:47 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tviacheslavo@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 15 Jul 2019 16:59:45 +0300", "from pegasus12.mtr.labs.mlnx. (pegasus12.mtr.labs.mlnx\n\t[10.210.17.40])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6FDxOEM013758;\n\tMon, 15 Jul 2019 16:59:45 +0300" ], "From": "Viacheslav Ovsiienko <viacheslavo@mellanox.com>", "To": "dev@dpdk.org", "Cc": "yskoh@mellanox.com", "Date": "Mon, 15 Jul 2019 13:59:17 +0000", "Message-Id": "<1563199161-29745-4-git-send-email-viacheslavo@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1563199161-29745-1-git-send-email-viacheslavo@mellanox.com>", "References": "<1562257767-19035-2-git-send-email-viacheslavo@mellanox.com>\n\t<1563199161-29745-1-git-send-email-viacheslavo@mellanox.com>", "Subject": "[dpdk-dev] [PATCH v2 3/7] net/mlx5: update Tx datapath definitions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch updates Tx datapath definitions, mostly hardware related.\nThe Tx descriptor structures are redefined with required fields,\nsize definitions are renamed to reflect the meanings in more\nappropriate way. This is a preparation step before introducing\nthe new Tx datapath implementation.\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>\n---\n drivers/net/mlx5/mlx5_defs.h | 2 +-\n drivers/net/mlx5/mlx5_prm.h | 163 +++++++++++++++++++++++++++++++++++++++----\n 2 files changed, 151 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 6861304..873a595 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -58,7 +58,7 @@\n #define MLX5_MAX_XSTATS 32\n \n /* Maximum Packet headers size (L2+L3+L4) for TSO. */\n-#define MLX5_MAX_TSO_HEADER 192\n+#define MLX5_MAX_TSO_HEADER (128u + 34u)\n \n /* Threshold of buffer replenishment for vectorized Rx. */\n #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \\\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex ff5dfbb..a251369 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -39,14 +39,84 @@\n /* Invalidate a CQE. */\n #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)\n \n-/* WQE DWORD size */\n-#define MLX5_WQE_DWORD_SIZE 16\n-\n-/* WQE size */\n-#define MLX5_WQE_SIZE (4 * MLX5_WQE_DWORD_SIZE)\n+/* WQE Segment sizes in bytes. */\n+#define MLX5_WSEG_SIZE 16u\n+#define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)\n+#define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)\n+#define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)\n+\n+/* WQE/WQEBB size in bytes. */\n+#define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)\n+\n+/*\n+ * Max size of a WQE session.\n+ * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,\n+ * the WQE size field in Control Segment is 6 bits wide.\n+ */\n+#define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)\n+\n+/*\n+ * Default minimum number of Tx queues for inlining packets.\n+ * If there are less queues as specified we assume we have\n+ * no enough CPU resources (cycles) to perform inlining,\n+ * the PCIe throughput is not supposed as bottleneck and\n+ * inlining is disabled.\n+ */\n+#define MLX5_EMPW_MIN_TXQS 8u\n+\n+/*\n+ * Default packet length threshold to be inlined with\n+ * enhanced MPW. If packet length exceeds the threshold\n+ * the data are not inlined. Should be aligned in WQEBB\n+ * boundary with accounting the title Control and Ethernet\n+ * segments.\n+ */\n+#define MLX5_EMPW_DEF_INLINE_LEN (3U * MLX5_WQE_SIZE + \\\n+\t\t\t\t MLX5_DSEG_MIN_INLINE_SIZE - \\\n+\t\t\t\t MLX5_WQE_DSEG_SIZE)\n+/*\n+ * Maximal inline data length sent with enhanced MPW.\n+ * Is based on maximal WQE size.\n+ */\n+#define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \\\n+\t\t\t\t MLX5_WQE_CSEG_SIZE - \\\n+\t\t\t\t MLX5_WQE_ESEG_SIZE - \\\n+\t\t\t\t MLX5_WQE_DSEG_SIZE + \\\n+\t\t\t\t MLX5_DSEG_MIN_INLINE_SIZE)\n+/*\n+ * Minimal amount of packets to be sent with EMPW.\n+ * This limits the minimal required size of sent EMPW.\n+ * If there are no enough resources to built minimal\n+ * EMPW the sending loop exits.\n+ */\n+#define MLX5_EMPW_MIN_PACKETS (2 + 3 * 4)\n+#define MLX5_EMPW_MAX_PACKETS ((MLX5_WQE_SIZE_MAX - \\\n+\t\t\t\tMLX5_WQE_CSEG_SIZE - \\\n+\t\t\t\tMLX5_WQE_ESEG_SIZE) / \\\n+\t\t\t\tMLX5_WSEG_SIZE)\n+/*\n+ * Default packet length threshold to be inlined with\n+ * ordinary SEND. Inlining saves the MR key search\n+ * and extra PCIe data fetch transaction, but eats the\n+ * CPU cycles.\n+ */\n+#define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \\\n+\t\t\t\t MLX5_ESEG_MIN_INLINE_SIZE - \\\n+\t\t\t\t MLX5_WQE_CSEG_SIZE - \\\n+\t\t\t\t MLX5_WQE_ESEG_SIZE - \\\n+\t\t\t\t MLX5_WQE_DSEG_SIZE)\n+/*\n+ * Maximal inline data length sent with ordinary SEND.\n+ * Is based on maximal WQE size.\n+ */\n+#define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \\\n+\t\t\t\t MLX5_WQE_CSEG_SIZE - \\\n+\t\t\t\t MLX5_WQE_ESEG_SIZE - \\\n+\t\t\t\t MLX5_WQE_DSEG_SIZE + \\\n+\t\t\t\t MLX5_ESEG_MIN_INLINE_SIZE)\n \n-#define MLX5_OPC_MOD_ENHANCED_MPSW 0\n-#define MLX5_OPCODE_ENHANCED_MPSW 0x29\n+/* Missed in mlv5dv.h, should define here. */\n+#define MLX5_OPCODE_ENHANCED_MPSW 0x29u\n \n /* CQE value to inform that VLAN is stripped. */\n #define MLX5_CQE_VLAN_STRIPPED (1u << 0)\n@@ -114,6 +184,12 @@\n /* Inner L3 type is IPV6. */\n #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)\n \n+/* VLAN insertion flag. */\n+#define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)\n+\n+/* Data inline segment flag. */\n+#define MLX5_ETH_WQE_DATA_INLINE (1u << 31)\n+\n /* Is flow mark valid. */\n #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)\n@@ -130,12 +206,21 @@\n /* Default mark value used when none is provided. */\n #define MLX5_FLOW_MARK_DEFAULT 0xffffff\n \n-/* Maximum number of DS in WQE. */\n+/* Maximum number of DS in WQE. Limited by 6-bit field. */\n #define MLX5_DSEG_MAX 63\n \n /* The completion mode offset in the WQE control segment line 2. */\n #define MLX5_COMP_MODE_OFFSET 2\n \n+/* Amount of data bytes in minimal inline data segment. */\n+#define MLX5_DSEG_MIN_INLINE_SIZE 12\n+\n+/* Amount of data bytes in minimal inline eth segment. */\n+#define MLX5_ESEG_MIN_INLINE_SIZE 18\n+\n+/* Amount of data bytes after eth data segment. */\n+#define MLX5_ESEG_EXTRA_DATA_SIZE 32\n+\n /* Completion mode. */\n enum mlx5_completion_mode {\n \tMLX5_COMP_ONLY_ERR = 0x0,\n@@ -144,11 +229,6 @@ enum mlx5_completion_mode {\n \tMLX5_COMP_CQE_AND_EQE = 0x3,\n };\n \n-/* Small common part of the WQE. */\n-struct mlx5_wqe {\n-\tuint32_t ctrl[4];\n-};\n-\n /* MPW mode. */\n enum mlx5_mpw_mode {\n \tMLX5_MPW_DISABLED,\n@@ -156,6 +236,63 @@ enum mlx5_mpw_mode {\n \tMLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */\n };\n \n+/* WQE Control segment. */\n+struct mlx5_wqe_cseg {\n+\tuint32_t opcode;\n+\tuint32_t sq_ds;\n+\tuint32_t flags;\n+\tuint32_t misc;\n+} __rte_packed __rte_aligned(MLX5_WSEG_SIZE);\n+\n+/* Header of data segment. Minimal size Data Segment */\n+struct mlx5_wqe_dseg {\n+\tuint32_t bcount;\n+\tunion {\n+\t\tuint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];\n+\t\tstruct {\n+\t\t\tuint32_t lkey;\n+\t\t\tuint64_t pbuf;\n+\t\t} __rte_packed;\n+\t};\n+} __rte_packed;\n+\n+/* Subset of struct WQE Ethernet Segment. */\n+struct mlx5_wqe_eseg {\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint32_t swp_offs;\n+\t\t\tuint8_t\tcs_flags;\n+\t\t\tuint8_t\tswp_flags;\n+\t\t\tuint16_t mss;\n+\t\t\tuint32_t metadata;\n+\t\t\tuint16_t inline_hdr_sz;\n+\t\t\tunion {\n+\t\t\t\tuint16_t inline_data;\n+\t\t\t\tuint16_t vlan_tag;\n+\t\t\t};\n+\t\t} __rte_packed;\n+\t\tstruct {\n+\t\t\tuint32_t offsets;\n+\t\t\tuint32_t flags;\n+\t\t\tuint32_t flow_metadata;\n+\t\t\tuint32_t inline_hdr;\n+\t\t} __rte_packed;\n+\t};\n+} __rte_packed;\n+\n+/* The title WQEBB, header of WQE. */\n+struct mlx5_wqe {\n+\tunion {\n+\t\tstruct mlx5_wqe_cseg cseg;\n+\t\tuint32_t ctrl[4];\n+\t};\n+\tstruct mlx5_wqe_eseg eseg;\n+\tunion {\n+\t\tstruct mlx5_wqe_dseg dseg[2];\n+\t\tuint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];\n+\t};\n+} __rte_packed;\n+\n /* WQE for Multi-Packet RQ. */\n struct mlx5_wqe_mprq {\n \tstruct mlx5_wqe_srq_next_seg next_seg;\n", "prefixes": [ "v2", "3/7" ] }