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{
    "id": 56433,
    "url": "http://patches.dpdk.org/api/patches/56433/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190715084442.14686-5-hemant.agrawal@nxp.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190715084442.14686-5-hemant.agrawal@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190715084442.14686-5-hemant.agrawal@nxp.com",
    "date": "2019-07-15T08:44:41",
    "name": "[v3,4/5] bus/fslmc: use cinh read for eqcr ci on ls1088 platform",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "c4009fc4a720adf65b10379f01b36b7e42a3556e",
    "submitter": {
        "id": 477,
        "url": "http://patches.dpdk.org/api/people/477/?format=api",
        "name": "Hemant Agrawal",
        "email": "hemant.agrawal@nxp.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190715084442.14686-5-hemant.agrawal@nxp.com/mbox/",
    "series": [
        {
            "id": 5489,
            "url": "http://patches.dpdk.org/api/series/5489/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5489",
            "date": "2019-07-15T08:44:37",
            "name": "FSLMC bus enchancements",
            "version": 3,
            "mbox": "http://patches.dpdk.org/series/5489/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/56433/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/56433/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CF7D51B9C9;\n\tMon, 15 Jul 2019 10:46:11 +0200 (CEST)",
            "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n\tby dpdk.org (Postfix) with ESMTP id 5A2873772\n\tfor <dev@dpdk.org>; Mon, 15 Jul 2019 10:46:05 +0200 (CEST)",
            "from inva020.nxp.com (localhost [127.0.0.1])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1C3EB1A0169;\n\tMon, 15 Jul 2019 10:46:05 +0200 (CEST)",
            "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 87E2F1A0192;\n\tMon, 15 Jul 2019 10:46:02 +0200 (CEST)",
            "from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net\n\t[10.232.133.63])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 182D4402E3;\n\tMon, 15 Jul 2019 16:45:58 +0800 (SGT)"
        ],
        "From": "Hemant Agrawal <hemant.agrawal@nxp.com>",
        "To": "dev@dpdk.org",
        "Cc": "thomas@monjalon.net,\n\tNipun Gupta <nipun.gupta@nxp.com>",
        "Date": "Mon, 15 Jul 2019 14:14:41 +0530",
        "Message-Id": "<20190715084442.14686-5-hemant.agrawal@nxp.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20190715084442.14686-1-hemant.agrawal@nxp.com>",
        "References": "<20190627093343.5171-2-hemant.agrawal@nxp.com>\n\t<20190715084442.14686-1-hemant.agrawal@nxp.com>",
        "X-Virus-Scanned": "ClamAV using ClamSMTP",
        "Subject": "[dpdk-dev] [PATCH v3 4/5] bus/fslmc: use cinh read for eqcr ci on\n\tls1088 platform",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Nipun Gupta <nipun.gupta@nxp.com>\n\nLS1088 platform CENA operation are causing issues\nat high load. CINH (cache inhibited) mode is working\nfine with minor performance impact.\n\nThis patch enables CINH mode selectively on LS1088 platform\n\nSigned-off-by: Nipun Gupta <nipun.gupta@nxp.com>\n---\n drivers/bus/fslmc/portal/dpaa2_hw_dpio.h      |   2 -\n drivers/bus/fslmc/portal/dpaa2_hw_pvt.h       |   5 -\n .../fslmc/qbman/include/fsl_qbman_portal.h    |   9 +\n drivers/bus/fslmc/qbman/qbman_portal.c        | 278 +++++++++++++++++-\n drivers/bus/fslmc/qbman/qbman_sys.h           |  22 +-\n 5 files changed, 303 insertions(+), 13 deletions(-)",
    "diff": "diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\nindex 17e7e4fad..c68495eaf 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h\n@@ -28,8 +28,6 @@ RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);\n #define DPAA2_PER_LCORE_ETHRX_DPIO RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev\n #define DPAA2_PER_LCORE_ETHRX_PORTAL DPAA2_PER_LCORE_ETHRX_DPIO->sw_portal\n \n-/* Variable to store DPAA2 platform type */\n-extern uint32_t dpaa2_svr_family;\n /* Variable to store DPAA2 DQRR size */\n extern uint8_t dpaa2_dqrr_size;\n /* Variable to store DPAA2 EQCR size */\ndiff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\nindex 0cbde8a9b..92fc76211 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n@@ -23,11 +23,6 @@\n #define lower_32_bits(x) ((uint32_t)(x))\n #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))\n \n-#define SVR_LS1080A             0x87030000\n-#define SVR_LS2080A             0x87010000\n-#define SVR_LS2088A             0x87090000\n-#define SVR_LX2160A             0x87360000\n-\n #ifndef VLAN_TAG_SIZE\n #define VLAN_TAG_SIZE   4 /** < Vlan Header Length */\n #endif\ndiff --git a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\nindex c35dafedb..88f0a9968 100644\n--- a/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\n+++ b/drivers/bus/fslmc/qbman/include/fsl_qbman_portal.h\n@@ -1,6 +1,7 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n  *\n  * Copyright (C) 2014 Freescale Semiconductor, Inc.\n+ * Copyright 2015-2019 NXP\n  *\n  */\n #ifndef _FSL_QBMAN_PORTAL_H\n@@ -8,6 +9,14 @@\n \n #include <fsl_qbman_base.h>\n \n+#define SVR_LS1080A\t0x87030000\n+#define SVR_LS2080A\t0x87010000\n+#define SVR_LS2088A\t0x87090000\n+#define SVR_LX2160A\t0x87360000\n+\n+/* Variable to store DPAA2 platform type */\n+extern uint32_t dpaa2_svr_family;\n+\n /**\n  * DOC - QBMan portal APIs to implement the following functions:\n  * - Initialize and destroy Software portal object.\ndiff --git a/drivers/bus/fslmc/qbman/qbman_portal.c b/drivers/bus/fslmc/qbman/qbman_portal.c\nindex 20da8b921..e6066ce35 100644\n--- a/drivers/bus/fslmc/qbman/qbman_portal.c\n+++ b/drivers/bus/fslmc/qbman/qbman_portal.c\n@@ -76,6 +76,10 @@ qbman_swp_enqueue_ring_mode_direct(struct qbman_swp *s,\n \t\tconst struct qbman_eq_desc *d,\n \t\tconst struct qbman_fd *fd);\n static int\n+qbman_swp_enqueue_ring_mode_cinh_direct(struct qbman_swp *s,\n+\t\tconst struct qbman_eq_desc *d,\n+\t\tconst struct qbman_fd *fd);\n+static int\n qbman_swp_enqueue_ring_mode_mem_back(struct qbman_swp *s,\n \t\tconst struct qbman_eq_desc *d,\n \t\tconst struct qbman_fd *fd);\n@@ -87,6 +91,12 @@ qbman_swp_enqueue_multiple_direct(struct qbman_swp *s,\n \t\tuint32_t *flags,\n \t\tint num_frames);\n static int\n+qbman_swp_enqueue_multiple_cinh_direct(struct qbman_swp *s,\n+\t\tconst struct qbman_eq_desc *d,\n+\t\tconst struct qbman_fd *fd,\n+\t\tuint32_t *flags,\n+\t\tint num_frames);\n+static int\n qbman_swp_enqueue_multiple_mem_back(struct qbman_swp *s,\n \t\tconst struct qbman_eq_desc *d,\n \t\tconst struct qbman_fd *fd,\n@@ -99,7 +109,12 @@ qbman_swp_enqueue_multiple_fd_direct(struct qbman_swp *s,\n \t\tstruct qbman_fd **fd,\n \t\tuint32_t *flags,\n \t\tint num_frames);\n-\n+static int\n+qbman_swp_enqueue_multiple_fd_cinh_direct(struct qbman_swp *s,\n+\t\tconst struct qbman_eq_desc *d,\n+\t\tstruct qbman_fd **fd,\n+\t\tuint32_t *flags,\n+\t\tint num_frames);\n static int\n qbman_swp_enqueue_multiple_fd_mem_back(struct qbman_swp *s,\n \t\tconst struct qbman_eq_desc *d,\n@@ -113,6 +128,11 @@ qbman_swp_enqueue_multiple_desc_direct(struct qbman_swp *s,\n \t\tconst struct qbman_fd *fd,\n \t\tint num_frames);\n static int\n+qbman_swp_enqueue_multiple_desc_cinh_direct(struct qbman_swp *s,\n+\t\tconst struct qbman_eq_desc *d,\n+\t\tconst struct qbman_fd *fd,\n+\t\tint num_frames);\n+static int\n qbman_swp_enqueue_multiple_desc_mem_back(struct qbman_swp *s,\n \t\tconst struct qbman_eq_desc *d,\n \t\tconst struct qbman_fd *fd,\n@@ -273,6 +293,17 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)\n \t\tqbman_swp_release_ptr = qbman_swp_release_mem_back;\n \t}\n \n+\tif (dpaa2_svr_family == SVR_LS1080A) {\n+\t\tqbman_swp_enqueue_ring_mode_ptr =\n+\t\t\t\tqbman_swp_enqueue_ring_mode_cinh_direct;\n+\t\tqbman_swp_enqueue_multiple_ptr =\n+\t\t\t\tqbman_swp_enqueue_multiple_cinh_direct;\n+\t\tqbman_swp_enqueue_multiple_fd_ptr =\n+\t\t\t\tqbman_swp_enqueue_multiple_fd_cinh_direct;\n+\t\tqbman_swp_enqueue_multiple_desc_ptr =\n+\t\t\t\tqbman_swp_enqueue_multiple_desc_cinh_direct;\n+\t}\n+\n \tfor (mask_size = p->eqcr.pi_ring_size; mask_size > 0; mask_size >>= 1)\n \t\tp->eqcr.pi_ci_mask = (p->eqcr.pi_ci_mask<<1) + 1;\n \teqcr_pi = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_PI);\n@@ -700,6 +731,46 @@ static int qbman_swp_enqueue_ring_mode_direct(struct qbman_swp *s,\n \treturn 0;\n }\n \n+static int qbman_swp_enqueue_ring_mode_cinh_direct(\n+\t\tstruct qbman_swp *s,\n+\t\tconst struct qbman_eq_desc *d,\n+\t\tconst struct qbman_fd *fd)\n+{\n+\tuint32_t *p;\n+\tconst uint32_t *cl = qb_cl(d);\n+\tuint32_t eqcr_ci, full_mask, half_mask;\n+\n+\thalf_mask = (s->eqcr.pi_ci_mask>>1);\n+\tfull_mask = s->eqcr.pi_ci_mask;\n+\tif (!s->eqcr.available) {\n+\t\teqcr_ci = s->eqcr.ci;\n+\t\ts->eqcr.ci = qbman_cinh_read(&s->sys,\n+\t\t\t\tQBMAN_CINH_SWP_EQCR_CI) & full_mask;\n+\t\ts->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size,\n+\t\t\t\teqcr_ci, s->eqcr.ci);\n+\t\tif (!s->eqcr.available)\n+\t\t\treturn -EBUSY;\n+\t}\n+\n+\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\tQBMAN_CENA_SWP_EQCR(s->eqcr.pi & half_mask));\n+\tmemcpy(&p[1], &cl[1], 28);\n+\tmemcpy(&p[8], fd, sizeof(*fd));\n+\tlwsync();\n+\n+\t/* Set the verb byte, have to substitute in the valid-bit */\n+\tp[0] = cl[0] | s->eqcr.pi_vb;\n+\tqbman_cena_write_complete_wo_shadow(&s->sys,\n+\t\t\tQBMAN_CENA_SWP_EQCR(s->eqcr.pi & half_mask));\n+\ts->eqcr.pi++;\n+\ts->eqcr.pi &= full_mask;\n+\ts->eqcr.available--;\n+\tif (!(s->eqcr.pi & half_mask))\n+\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n+\n+\treturn 0;\n+}\n+\n static int qbman_swp_enqueue_ring_mode_mem_back(struct qbman_swp *s,\n \t\t\t\t\t\tconst struct qbman_eq_desc *d,\n \t\t\t\t\t\tconst struct qbman_fd *fd)\n@@ -823,6 +894,76 @@ static int qbman_swp_enqueue_multiple_direct(struct qbman_swp *s,\n \treturn num_enqueued;\n }\n \n+static int qbman_swp_enqueue_multiple_cinh_direct(\n+\t\tstruct qbman_swp *s,\n+\t\tconst struct qbman_eq_desc *d,\n+\t\tconst struct qbman_fd *fd,\n+\t\tuint32_t *flags,\n+\t\tint num_frames)\n+{\n+\tuint32_t *p = NULL;\n+\tconst uint32_t *cl = qb_cl(d);\n+\tuint32_t eqcr_ci, eqcr_pi, half_mask, full_mask;\n+\tint i, num_enqueued = 0;\n+\tuint64_t addr_cena;\n+\n+\thalf_mask = (s->eqcr.pi_ci_mask>>1);\n+\tfull_mask = s->eqcr.pi_ci_mask;\n+\tif (!s->eqcr.available) {\n+\t\teqcr_ci = s->eqcr.ci;\n+\t\ts->eqcr.ci = qbman_cinh_read(&s->sys,\n+\t\t\t\tQBMAN_CINH_SWP_EQCR_CI) & full_mask;\n+\t\ts->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size,\n+\t\t\t\teqcr_ci, s->eqcr.ci);\n+\t\tif (!s->eqcr.available)\n+\t\t\treturn 0;\n+\t}\n+\n+\teqcr_pi = s->eqcr.pi;\n+\tnum_enqueued = (s->eqcr.available < num_frames) ?\n+\t\t\ts->eqcr.available : num_frames;\n+\ts->eqcr.available -= num_enqueued;\n+\t/* Fill in the EQCR ring */\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));\n+\t\tmemcpy(&p[1], &cl[1], 28);\n+\t\tmemcpy(&p[8], &fd[i], sizeof(*fd));\n+\t\teqcr_pi++;\n+\t}\n+\n+\tlwsync();\n+\n+\t/* Set the verb byte, have to substitute in the valid-bit */\n+\teqcr_pi = s->eqcr.pi;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));\n+\t\tp[0] = cl[0] | s->eqcr.pi_vb;\n+\t\tif (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) {\n+\t\t\tstruct qbman_eq_desc *d = (struct qbman_eq_desc *)p;\n+\n+\t\t\td->eq.dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) |\n+\t\t\t\t((flags[i]) & QBMAN_EQCR_DCA_IDXMASK);\n+\t\t}\n+\t\teqcr_pi++;\n+\t\tif (!(eqcr_pi & half_mask))\n+\t\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n+\t}\n+\n+\t/* Flush all the cacheline without load/store in between */\n+\teqcr_pi = s->eqcr.pi;\n+\taddr_cena = (size_t)s->sys.addr_cena;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tdcbf(addr_cena +\n+\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));\n+\t\teqcr_pi++;\n+\t}\n+\ts->eqcr.pi = eqcr_pi & full_mask;\n+\n+\treturn num_enqueued;\n+}\n+\n static int qbman_swp_enqueue_multiple_mem_back(struct qbman_swp *s,\n \t\t\t\t\t       const struct qbman_eq_desc *d,\n \t\t\t\t\t       const struct qbman_fd *fd,\n@@ -954,6 +1095,76 @@ static int qbman_swp_enqueue_multiple_fd_direct(struct qbman_swp *s,\n \treturn num_enqueued;\n }\n \n+static int qbman_swp_enqueue_multiple_fd_cinh_direct(\n+\t\tstruct qbman_swp *s,\n+\t\tconst struct qbman_eq_desc *d,\n+\t\tstruct qbman_fd **fd,\n+\t\tuint32_t *flags,\n+\t\tint num_frames)\n+{\n+\tuint32_t *p = NULL;\n+\tconst uint32_t *cl = qb_cl(d);\n+\tuint32_t eqcr_ci, eqcr_pi, half_mask, full_mask;\n+\tint i, num_enqueued = 0;\n+\tuint64_t addr_cena;\n+\n+\thalf_mask = (s->eqcr.pi_ci_mask>>1);\n+\tfull_mask = s->eqcr.pi_ci_mask;\n+\tif (!s->eqcr.available) {\n+\t\teqcr_ci = s->eqcr.ci;\n+\t\ts->eqcr.ci = qbman_cinh_read(&s->sys,\n+\t\t\t\tQBMAN_CINH_SWP_EQCR_CI) & full_mask;\n+\t\ts->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size,\n+\t\t\t\teqcr_ci, s->eqcr.ci);\n+\t\tif (!s->eqcr.available)\n+\t\t\treturn 0;\n+\t}\n+\n+\teqcr_pi = s->eqcr.pi;\n+\tnum_enqueued = (s->eqcr.available < num_frames) ?\n+\t\t\ts->eqcr.available : num_frames;\n+\ts->eqcr.available -= num_enqueued;\n+\t/* Fill in the EQCR ring */\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));\n+\t\tmemcpy(&p[1], &cl[1], 28);\n+\t\tmemcpy(&p[8], fd[i], sizeof(struct qbman_fd));\n+\t\teqcr_pi++;\n+\t}\n+\n+\tlwsync();\n+\n+\t/* Set the verb byte, have to substitute in the valid-bit */\n+\teqcr_pi = s->eqcr.pi;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));\n+\t\tp[0] = cl[0] | s->eqcr.pi_vb;\n+\t\tif (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) {\n+\t\t\tstruct qbman_eq_desc *d = (struct qbman_eq_desc *)p;\n+\n+\t\t\td->eq.dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) |\n+\t\t\t\t((flags[i]) & QBMAN_EQCR_DCA_IDXMASK);\n+\t\t}\n+\t\teqcr_pi++;\n+\t\tif (!(eqcr_pi & half_mask))\n+\t\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n+\t}\n+\n+\t/* Flush all the cacheline without load/store in between */\n+\teqcr_pi = s->eqcr.pi;\n+\taddr_cena = (size_t)s->sys.addr_cena;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tdcbf(addr_cena +\n+\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));\n+\t\teqcr_pi++;\n+\t}\n+\ts->eqcr.pi = eqcr_pi & full_mask;\n+\n+\treturn num_enqueued;\n+}\n+\n static int qbman_swp_enqueue_multiple_fd_mem_back(struct qbman_swp *s,\n \t\t\t\t\t\t  const struct qbman_eq_desc *d,\n \t\t\t\t\t\t  struct qbman_fd **fd,\n@@ -1087,6 +1298,71 @@ static int qbman_swp_enqueue_multiple_desc_direct(struct qbman_swp *s,\n \treturn num_enqueued;\n }\n \n+static int qbman_swp_enqueue_multiple_desc_cinh_direct(\n+\t\tstruct qbman_swp *s,\n+\t\tconst struct qbman_eq_desc *d,\n+\t\tconst struct qbman_fd *fd,\n+\t\tint num_frames)\n+{\n+\tuint32_t *p;\n+\tconst uint32_t *cl;\n+\tuint32_t eqcr_ci, eqcr_pi, half_mask, full_mask;\n+\tint i, num_enqueued = 0;\n+\tuint64_t addr_cena;\n+\n+\thalf_mask = (s->eqcr.pi_ci_mask>>1);\n+\tfull_mask = s->eqcr.pi_ci_mask;\n+\tif (!s->eqcr.available) {\n+\t\teqcr_ci = s->eqcr.ci;\n+\t\ts->eqcr.ci = qbman_cinh_read(&s->sys,\n+\t\t\t\tQBMAN_CINH_SWP_EQCR_CI) & full_mask;\n+\t\ts->eqcr.available = qm_cyc_diff(s->eqcr.pi_ring_size,\n+\t\t\t\t\teqcr_ci, s->eqcr.ci);\n+\t\tif (!s->eqcr.available)\n+\t\t\treturn 0;\n+\t}\n+\n+\teqcr_pi = s->eqcr.pi;\n+\tnum_enqueued = (s->eqcr.available < num_frames) ?\n+\t\t\ts->eqcr.available : num_frames;\n+\ts->eqcr.available -= num_enqueued;\n+\t/* Fill in the EQCR ring */\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));\n+\t\tcl = qb_cl(&d[i]);\n+\t\tmemcpy(&p[1], &cl[1], 28);\n+\t\tmemcpy(&p[8], &fd[i], sizeof(*fd));\n+\t\teqcr_pi++;\n+\t}\n+\n+\tlwsync();\n+\n+\t/* Set the verb byte, have to substitute in the valid-bit */\n+\teqcr_pi = s->eqcr.pi;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tp = qbman_cena_write_start_wo_shadow(&s->sys,\n+\t\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));\n+\t\tcl = qb_cl(&d[i]);\n+\t\tp[0] = cl[0] | s->eqcr.pi_vb;\n+\t\teqcr_pi++;\n+\t\tif (!(eqcr_pi & half_mask))\n+\t\t\ts->eqcr.pi_vb ^= QB_VALID_BIT;\n+\t}\n+\n+\t/* Flush all the cacheline without load/store in between */\n+\teqcr_pi = s->eqcr.pi;\n+\taddr_cena = (size_t)s->sys.addr_cena;\n+\tfor (i = 0; i < num_enqueued; i++) {\n+\t\tdcbf(addr_cena +\n+\t\t\tQBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask));\n+\t\teqcr_pi++;\n+\t}\n+\ts->eqcr.pi = eqcr_pi & full_mask;\n+\n+\treturn num_enqueued;\n+}\n+\n static int qbman_swp_enqueue_multiple_desc_mem_back(struct qbman_swp *s,\n \t\t\t\t\tconst struct qbman_eq_desc *d,\n \t\t\t\t\tconst struct qbman_fd *fd,\ndiff --git a/drivers/bus/fslmc/qbman/qbman_sys.h b/drivers/bus/fslmc/qbman/qbman_sys.h\nindex 71f7a6782..e59fcfd54 100644\n--- a/drivers/bus/fslmc/qbman/qbman_sys.h\n+++ b/drivers/bus/fslmc/qbman/qbman_sys.h\n@@ -381,6 +381,14 @@ static inline uint32_t qbman_set_swp_cfg(uint8_t max_fill, uint8_t wn,\n #define QMAN_REV_5000\t0x05000000\n #define QMAN_REV_MASK\t0xffff0000\n \n+#define SVR_LS1080A\t0x87030000\n+#define SVR_LS2080A\t0x87010000\n+#define SVR_LS2088A\t0x87090000\n+#define SVR_LX2160A\t0x87360000\n+\n+/* Variable to store DPAA2 platform type */\n+extern uint32_t dpaa2_svr_family;\n+\n static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,\n \t\t\t\t     const struct qbman_swp_desc *d,\n \t\t\t\t     uint8_t dqrr_size)\n@@ -388,16 +396,17 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,\n \tuint32_t reg;\n \tint i;\n \tint cena_region_size = 4*1024;\n-\n-\tif ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000\n-\t\t\t&& (d->cena_access_mode == qman_cena_fastest_access))\n-\t\tcena_region_size = 64*1024;\n+\tuint8_t est = 1;\n #ifdef RTE_ARCH_64\n \tuint8_t wn = CENA_WRITE_ENABLE;\n #else\n \tuint8_t wn = CINH_WRITE_ENABLE;\n #endif\n \n+\n+\tif ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000\n+\t\t\t&& (d->cena_access_mode == qman_cena_fastest_access))\n+\t\tcena_region_size = 64*1024;\n \ts->addr_cena = d->cena_bar;\n \ts->addr_cinh = d->cinh_bar;\n \ts->idx = (uint32_t)d->idx;\n@@ -428,6 +437,9 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,\n \t\t\tdccivac(s->addr_cena + i);\n \t}\n \n+\tif (dpaa2_svr_family == SVR_LS1080A)\n+\t\test = 0;\n+\n \tif (s->eqcr_mode == qman_eqcr_vb_array) {\n \t\treg = qbman_set_swp_cfg(dqrr_size, wn,\n \t\t\t\t\t0, 3, 2, 3, 1, 1, 1, 1, 1, 1);\n@@ -438,7 +450,7 @@ static inline int qbman_swp_sys_init(struct qbman_swp_sys *s,\n \t\t\t\t\t\t1, 3, 2, 0, 1, 1, 1, 1, 1, 1);\n \t\telse\n \t\t\treg = qbman_set_swp_cfg(dqrr_size, wn,\n-\t\t\t\t\t\t1, 3, 2, 2, 1, 1, 1, 1, 1, 1);\n+\t\t\t\t\t\test, 3, 2, 2, 1, 1, 1, 1, 1, 1);\n \t}\n \n \tif ((d->qman_version & QMAN_REV_MASK) >= QMAN_REV_5000\n",
    "prefixes": [
        "v3",
        "4/5"
    ]
}