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GET /api/patches/56393/?format=api
{ "id": 56393, "url": "http://patches.dpdk.org/api/patches/56393/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190712095729.159767-2-jasvinder.singh@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190712095729.159767-2-jasvinder.singh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190712095729.159767-2-jasvinder.singh@intel.com", "date": "2019-07-12T09:57:19", "name": "[v4,01/11] sched: remove wrr from strict priority tc queues", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5d09cafc6ced48c80bacfb128a605194c4e6eb4a", "submitter": { "id": 285, "url": "http://patches.dpdk.org/api/people/285/?format=api", "name": "Jasvinder Singh", "email": "jasvinder.singh@intel.com" }, "delegate": { "id": 10018, "url": "http://patches.dpdk.org/api/users/10018/?format=api", "username": "cristian_dumitrescu", "first_name": "Cristian", "last_name": "Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190712095729.159767-2-jasvinder.singh@intel.com/mbox/", "series": [ { "id": 5473, "url": "http://patches.dpdk.org/api/series/5473/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5473", "date": "2019-07-12T09:57:18", "name": "sched: feature enhancements", "version": 4, "mbox": "http://patches.dpdk.org/series/5473/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56393/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/56393/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1180F1B9C7;\n\tFri, 12 Jul 2019 11:57:25 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 4F3652C6A\n\tfor <dev@dpdk.org>; Fri, 12 Jul 2019 11:57:21 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t12 Jul 2019 02:57:20 -0700", "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.223.4])\n\tby orsmga005.jf.intel.com with ESMTP; 12 Jul 2019 02:57:19 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.63,482,1557212400\"; d=\"scan'208\";a=\"341656789\"", "From": "Jasvinder Singh <jasvinder.singh@intel.com>", "To": "dev@dpdk.org", "Cc": "cristian.dumitrescu@intel.com, Abraham Tovar <abrahamx.tovar@intel.com>, \n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>", "Date": "Fri, 12 Jul 2019 10:57:19 +0100", "Message-Id": "<20190712095729.159767-2-jasvinder.singh@intel.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190712095729.159767-1-jasvinder.singh@intel.com>", "References": "<20190711102659.59001-2-jasvinder.singh@intel.com>\n\t<20190712095729.159767-1-jasvinder.singh@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v4 01/11] sched: remove wrr from strict priority\n\ttc queues", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "All higher priority traffic classes contain only one queue, thus\nremove wrr function for them. The lowest priority best-effort\ntraffic class conitnue to have multiple queues and packet are\nscheduled from its queues using wrr function.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Abraham Tovar <abrahamx.tovar@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n app/test/test_sched.c | 2 +-\n examples/qos_sched/init.c | 2 +-\n lib/librte_sched/Makefile | 2 +-\n lib/librte_sched/meson.build | 2 +-\n lib/librte_sched/rte_sched.c | 182 ++++++++++++++++++++---------------\n lib/librte_sched/rte_sched.h | 23 +++--\n 6 files changed, 124 insertions(+), 89 deletions(-)", "diff": "diff --git a/app/test/test_sched.c b/app/test/test_sched.c\nindex 49bb9ea6f..36fa2d425 100644\n--- a/app/test/test_sched.c\n+++ b/app/test/test_sched.c\n@@ -40,7 +40,7 @@ static struct rte_sched_pipe_params pipe_profile[] = {\n \t\t.tc_rate = {305175, 305175, 305175, 305175},\n \t\t.tc_period = 40,\n \n-\t\t.wrr_weights = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},\n+\t\t.wrr_weights = {1, 1, 1, 1},\n \t},\n };\n \ndiff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c\nindex 1209bd7ce..6b63d4e0e 100644\n--- a/examples/qos_sched/init.c\n+++ b/examples/qos_sched/init.c\n@@ -186,7 +186,7 @@ static struct rte_sched_pipe_params pipe_profiles[RTE_SCHED_PIPE_PROFILES_PER_PO\n \t\t.tc_ov_weight = 1,\n #endif\n \n-\t\t.wrr_weights = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},\n+\t\t.wrr_weights = {1, 1, 1, 1},\n \t},\n };\n \ndiff --git a/lib/librte_sched/Makefile b/lib/librte_sched/Makefile\nindex 644fd9d15..3d7f410e1 100644\n--- a/lib/librte_sched/Makefile\n+++ b/lib/librte_sched/Makefile\n@@ -18,7 +18,7 @@ LDLIBS += -lrte_timer\n \n EXPORT_MAP := rte_sched_version.map\n \n-LIBABIVER := 2\n+LIBABIVER := 3\n \n #\n # all source are stored in SRCS-y\ndiff --git a/lib/librte_sched/meson.build b/lib/librte_sched/meson.build\nindex 8e989e5f6..59d43c6d8 100644\n--- a/lib/librte_sched/meson.build\n+++ b/lib/librte_sched/meson.build\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n-version = 2\n+version = 3\n sources = files('rte_sched.c', 'rte_red.c', 'rte_approx.c')\n headers = files('rte_sched.h', 'rte_sched_common.h',\n \t\t'rte_red.h', 'rte_approx.h')\ndiff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex bc06bc3f4..b1f521794 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -37,6 +37,8 @@\n \n #define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)\n #define RTE_SCHED_WRR_SHIFT 3\n+#define RTE_SCHED_TRAFFIC_CLASS_BE (RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE - 1)\n+#define RTE_SCHED_MAX_QUEUES_PER_TC RTE_SCHED_BE_QUEUES_PER_PIPE\n #define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)\n #define RTE_SCHED_PIPE_INVALID UINT32_MAX\n #define RTE_SCHED_BMP_POS_INVALID UINT32_MAX\n@@ -84,8 +86,9 @@ struct rte_sched_pipe_profile {\n \tuint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \tuint8_t tc_ov_weight;\n \n-\t/* Pipe queues */\n-\tuint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];\n+\t/* Pipe best-effort traffic class queues */\n+\tuint8_t n_be_queues;\n+\tuint8_t wrr_cost[RTE_SCHED_BE_QUEUES_PER_PIPE];\n };\n \n struct rte_sched_pipe {\n@@ -100,8 +103,10 @@ struct rte_sched_pipe {\n \tuint64_t tc_time; /* time of next update */\n \tuint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \n+\tuint8_t n_be_queues; /* Best effort traffic class queues */\n+\n \t/* Weighted Round Robin (WRR) */\n-\tuint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];\n+\tuint8_t wrr_tokens[RTE_SCHED_BE_QUEUES_PER_PIPE];\n \n \t/* TC oversubscription */\n \tuint32_t tc_ov_credits;\n@@ -153,16 +158,16 @@ struct rte_sched_grinder {\n \tuint32_t tc_index;\n \tstruct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \tstruct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tuint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tuint16_t qsize;\n+\tuint32_t qindex[RTE_SCHED_MAX_QUEUES_PER_TC];\n+\tuint16_t qsize[RTE_SCHED_MAX_QUEUES_PER_TC];\n \tuint32_t qmask;\n \tuint32_t qpos;\n \tstruct rte_mbuf *pkt;\n \n \t/* WRR */\n-\tuint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-\tuint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-\tuint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n+\tuint16_t wrr_tokens[RTE_SCHED_BE_QUEUES_PER_PIPE];\n+\tuint16_t wrr_mask[RTE_SCHED_BE_QUEUES_PER_PIPE];\n+\tuint8_t wrr_cost[RTE_SCHED_BE_QUEUES_PER_PIPE];\n };\n \n struct rte_sched_port {\n@@ -301,7 +306,6 @@ pipe_profile_check(struct rte_sched_pipe_params *params,\n \t\tif (params->wrr_weights[i] == 0)\n \t\t\treturn -16;\n \t}\n-\n \treturn 0;\n }\n \n@@ -483,7 +487,7 @@ rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n \t\t\" Token bucket: period = %u, credits per period = %u, size = %u\\n\"\n \t\t\" Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\\n\"\n \t\t\" Traffic class 3 oversubscription: weight = %hhu\\n\"\n-\t\t\" WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\\n\",\n+\t\t\" WRR cost: [%hhu, %hhu, %hhu, %hhu]\\n\",\n \t\ti,\n \n \t\t/* Token bucket */\n@@ -502,10 +506,7 @@ rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n \t\tp->tc_ov_weight,\n \n \t\t/* WRR */\n-\t\tp->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],\n-\t\tp->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],\n-\t\tp->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],\n-\t\tp->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);\n+\t\tp->wrr_cost[0], p->wrr_cost[1], p->wrr_cost[2], p->wrr_cost[3]);\n }\n \n static inline uint64_t\n@@ -519,10 +520,12 @@ rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)\n }\n \n static void\n-rte_sched_pipe_profile_convert(struct rte_sched_pipe_params *src,\n+rte_sched_pipe_profile_convert(struct rte_sched_port *port,\n+\tstruct rte_sched_pipe_params *src,\n \tstruct rte_sched_pipe_profile *dst,\n \tuint32_t rate)\n {\n+\tuint32_t wrr_cost[RTE_SCHED_BE_QUEUES_PER_PIPE];\n \tuint32_t i;\n \n \t/* Token Bucket */\n@@ -553,18 +556,36 @@ rte_sched_pipe_profile_convert(struct rte_sched_pipe_params *src,\n \tdst->tc_ov_weight = src->tc_ov_weight;\n #endif\n \n-\t/* WRR */\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tuint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-\t\tuint32_t lcd, lcd1, lcd2;\n-\t\tuint32_t qindex;\n+\t/* WRR queues */\n+\tfor (i = 0; i < RTE_SCHED_BE_QUEUES_PER_PIPE; i++)\n+\t\tif (port->qsize[i])\n+\t\t\tdst->n_be_queues++;\n+\n+\tif (dst->n_be_queues == 1)\n+\t\tdst->wrr_cost[0] = src->wrr_weights[0];\n+\n+\tif (dst->n_be_queues == 2) {\n+\t\tuint32_t lcd;\n+\n+\t\twrr_cost[0] = src->wrr_weights[0];\n+\t\twrr_cost[1] = src->wrr_weights[1];\n+\n+\t\tlcd = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n+\n+\t\twrr_cost[0] = lcd / wrr_cost[0];\n+\t\twrr_cost[1] = lcd / wrr_cost[1];\n \n-\t\tqindex = i * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;\n+\t\tdst->wrr_cost[0] = (uint8_t) wrr_cost[0];\n+\t\tdst->wrr_cost[1] = (uint8_t) wrr_cost[1];\n+\t}\n \n-\t\twrr_cost[0] = src->wrr_weights[qindex];\n-\t\twrr_cost[1] = src->wrr_weights[qindex + 1];\n-\t\twrr_cost[2] = src->wrr_weights[qindex + 2];\n-\t\twrr_cost[3] = src->wrr_weights[qindex + 3];\n+\tif (dst->n_be_queues == 4) {\n+\t\tuint32_t lcd1, lcd2, lcd;\n+\n+\t\twrr_cost[0] = src->wrr_weights[0];\n+\t\twrr_cost[1] = src->wrr_weights[1];\n+\t\twrr_cost[2] = src->wrr_weights[2];\n+\t\twrr_cost[3] = src->wrr_weights[3];\n \n \t\tlcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n \t\tlcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);\n@@ -575,10 +596,10 @@ rte_sched_pipe_profile_convert(struct rte_sched_pipe_params *src,\n \t\twrr_cost[2] = lcd / wrr_cost[2];\n \t\twrr_cost[3] = lcd / wrr_cost[3];\n \n-\t\tdst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];\n-\t\tdst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];\n-\t\tdst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];\n-\t\tdst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];\n+\t\tdst->wrr_cost[0] = (uint8_t) wrr_cost[0];\n+\t\tdst->wrr_cost[1] = (uint8_t) wrr_cost[1];\n+\t\tdst->wrr_cost[2] = (uint8_t) wrr_cost[2];\n+\t\tdst->wrr_cost[3] = (uint8_t) wrr_cost[3];\n \t}\n }\n \n@@ -592,7 +613,7 @@ rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port,\n \t\tstruct rte_sched_pipe_params *src = params->pipe_profiles + i;\n \t\tstruct rte_sched_pipe_profile *dst = port->pipe_profiles + i;\n \n-\t\trte_sched_pipe_profile_convert(src, dst, params->rate);\n+\t\trte_sched_pipe_profile_convert(port, src, dst, params->rate);\n \t\trte_sched_port_log_pipe_profile(port, i);\n \t}\n \n@@ -976,7 +997,7 @@ rte_sched_port_pipe_profile_add(struct rte_sched_port *port,\n \t\treturn status;\n \n \tpp = &port->pipe_profiles[port->n_pipe_profiles];\n-\trte_sched_pipe_profile_convert(params, pp, port->rate);\n+\trte_sched_pipe_profile_convert(port, params, pp, port->rate);\n \n \t/* Pipe profile not exists */\n \tfor (i = 0; i < port->n_pipe_profiles; i++)\n@@ -1715,6 +1736,7 @@ grinder_schedule(struct rte_sched_port *port, uint32_t pos)\n \tstruct rte_sched_queue *queue = grinder->queue[grinder->qpos];\n \tstruct rte_mbuf *pkt = grinder->pkt;\n \tuint32_t pkt_len = pkt->pkt_len + port->frame_overhead;\n+\tint be_tc_active;\n \n \tif (!grinder_credits_check(port, pos))\n \t\treturn 0;\n@@ -1725,13 +1747,18 @@ grinder_schedule(struct rte_sched_port *port, uint32_t pos)\n \t/* Send packet */\n \tport->pkts_out[port->n_pkts_out++] = pkt;\n \tqueue->qr++;\n-\tgrinder->wrr_tokens[grinder->qpos] += pkt_len * grinder->wrr_cost[grinder->qpos];\n+\n+\tbe_tc_active = (grinder->tc_index == RTE_SCHED_TRAFFIC_CLASS_BE);\n+\tgrinder->wrr_tokens[grinder->qpos] +=\n+\t\tpkt_len * grinder->wrr_cost[grinder->qpos] * be_tc_active;\n+\n \tif (queue->qr == queue->qw) {\n \t\tuint32_t qindex = grinder->qindex[grinder->qpos];\n \n \t\trte_bitmap_clear(port->bmp, qindex);\n \t\tgrinder->qmask &= ~(1 << grinder->qpos);\n-\t\tgrinder->wrr_mask[grinder->qpos] = 0;\n+\t\tif (be_tc_active)\n+\t\t\tgrinder->wrr_mask[grinder->qpos] = 0;\n \t\trte_sched_port_set_queue_empty_timestamp(port, qindex);\n \t}\n \n@@ -1877,7 +1904,7 @@ grinder_next_tc(struct rte_sched_port *port, uint32_t pos)\n \n \tgrinder->tc_index = (qindex >> 2) & 0x3;\n \tgrinder->qmask = grinder->tccache_qmask[grinder->tccache_r];\n-\tgrinder->qsize = qsize;\n+\tgrinder->qsize[grinder->tc_index] = qsize;\n \n \tgrinder->qindex[0] = qindex;\n \tgrinder->qindex[1] = qindex + 1;\n@@ -1962,26 +1989,15 @@ grinder_wrr_load(struct rte_sched_port *port, uint32_t pos)\n \tstruct rte_sched_grinder *grinder = port->grinder + pos;\n \tstruct rte_sched_pipe *pipe = grinder->pipe;\n \tstruct rte_sched_pipe_profile *pipe_params = grinder->pipe_params;\n-\tuint32_t tc_index = grinder->tc_index;\n \tuint32_t qmask = grinder->qmask;\n-\tuint32_t qindex;\n-\n-\tqindex = tc_index * 4;\n-\n-\tgrinder->wrr_tokens[0] = ((uint16_t) pipe->wrr_tokens[qindex]) << RTE_SCHED_WRR_SHIFT;\n-\tgrinder->wrr_tokens[1] = ((uint16_t) pipe->wrr_tokens[qindex + 1]) << RTE_SCHED_WRR_SHIFT;\n-\tgrinder->wrr_tokens[2] = ((uint16_t) pipe->wrr_tokens[qindex + 2]) << RTE_SCHED_WRR_SHIFT;\n-\tgrinder->wrr_tokens[3] = ((uint16_t) pipe->wrr_tokens[qindex + 3]) << RTE_SCHED_WRR_SHIFT;\n-\n-\tgrinder->wrr_mask[0] = (qmask & 0x1) * 0xFFFF;\n-\tgrinder->wrr_mask[1] = ((qmask >> 1) & 0x1) * 0xFFFF;\n-\tgrinder->wrr_mask[2] = ((qmask >> 2) & 0x1) * 0xFFFF;\n-\tgrinder->wrr_mask[3] = ((qmask >> 3) & 0x1) * 0xFFFF;\n+\tuint32_t i;\n \n-\tgrinder->wrr_cost[0] = pipe_params->wrr_cost[qindex];\n-\tgrinder->wrr_cost[1] = pipe_params->wrr_cost[qindex + 1];\n-\tgrinder->wrr_cost[2] = pipe_params->wrr_cost[qindex + 2];\n-\tgrinder->wrr_cost[3] = pipe_params->wrr_cost[qindex + 3];\n+\tfor (i = 0; i < pipe->n_be_queues; i++) {\n+\t\tgrinder->wrr_tokens[i] =\n+\t\t\t((uint16_t) pipe->wrr_tokens[i]) << RTE_SCHED_WRR_SHIFT;\n+\t\tgrinder->wrr_mask[i] = ((qmask >> i) & 0x1) * 0xFFFF;\n+\t\tgrinder->wrr_cost[i] = pipe_params->wrr_cost[i];\n+\t}\n }\n \n static inline void\n@@ -1989,19 +2005,12 @@ grinder_wrr_store(struct rte_sched_port *port, uint32_t pos)\n {\n \tstruct rte_sched_grinder *grinder = port->grinder + pos;\n \tstruct rte_sched_pipe *pipe = grinder->pipe;\n-\tuint32_t tc_index = grinder->tc_index;\n-\tuint32_t qindex;\n-\n-\tqindex = tc_index * 4;\n+\tuint32_t i;\n \n-\tpipe->wrr_tokens[qindex] = (grinder->wrr_tokens[0] & grinder->wrr_mask[0])\n-\t\t>> RTE_SCHED_WRR_SHIFT;\n-\tpipe->wrr_tokens[qindex + 1] = (grinder->wrr_tokens[1] & grinder->wrr_mask[1])\n-\t\t>> RTE_SCHED_WRR_SHIFT;\n-\tpipe->wrr_tokens[qindex + 2] = (grinder->wrr_tokens[2] & grinder->wrr_mask[2])\n-\t\t>> RTE_SCHED_WRR_SHIFT;\n-\tpipe->wrr_tokens[qindex + 3] = (grinder->wrr_tokens[3] & grinder->wrr_mask[3])\n-\t\t>> RTE_SCHED_WRR_SHIFT;\n+\tfor (i = 0; i < pipe->n_be_queues; i++)\n+\t\tpipe->wrr_tokens[i] =\n+\t\t\t(grinder->wrr_tokens[i] & grinder->wrr_mask[i]) >>\n+\t\t\t\tRTE_SCHED_WRR_SHIFT;\n }\n \n static inline void\n@@ -2040,22 +2049,31 @@ static inline void\n grinder_prefetch_tc_queue_arrays(struct rte_sched_port *port, uint32_t pos)\n {\n \tstruct rte_sched_grinder *grinder = port->grinder + pos;\n-\tuint16_t qsize, qr[4];\n+\tstruct rte_sched_pipe *pipe = grinder->pipe;\n+\tstruct rte_sched_queue *queue;\n+\tuint32_t i;\n+\tuint16_t qsize, qr[RTE_SCHED_MAX_QUEUES_PER_TC];\n \n-\tqsize = grinder->qsize;\n-\tqr[0] = grinder->queue[0]->qr & (qsize - 1);\n-\tqr[1] = grinder->queue[1]->qr & (qsize - 1);\n-\tqr[2] = grinder->queue[2]->qr & (qsize - 1);\n-\tqr[3] = grinder->queue[3]->qr & (qsize - 1);\n+\tgrinder->qpos = 0;\n+\tif (grinder->tc_index < RTE_SCHED_TRAFFIC_CLASS_BE) {\n+\t\tqueue = grinder->queue[0];\n+\t\tqsize = grinder->qsize[0];\n+\t\tqr[0] = queue->qr & (qsize - 1);\n \n-\trte_prefetch0(grinder->qbase[0] + qr[0]);\n-\trte_prefetch0(grinder->qbase[1] + qr[1]);\n+\t\trte_prefetch0(grinder->qbase[0] + qr[0]);\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < pipe->n_be_queues; i++) {\n+\t\tqueue = grinder->queue[i];\n+\t\tqsize = grinder->qsize[i];\n+\t\tqr[i] = queue->qr & (qsize - 1);\n+\n+\t\trte_prefetch0(grinder->qbase[i] + qr[i]);\n+\t}\n \n \tgrinder_wrr_load(port, pos);\n \tgrinder_wrr(port, pos);\n-\n-\trte_prefetch0(grinder->qbase[2] + qr[2]);\n-\trte_prefetch0(grinder->qbase[3] + qr[3]);\n }\n \n static inline void\n@@ -2064,7 +2082,7 @@ grinder_prefetch_mbuf(struct rte_sched_port *port, uint32_t pos)\n \tstruct rte_sched_grinder *grinder = port->grinder + pos;\n \tuint32_t qpos = grinder->qpos;\n \tstruct rte_mbuf **qbase = grinder->qbase[qpos];\n-\tuint16_t qsize = grinder->qsize;\n+\tuint16_t qsize = grinder->qsize[qpos];\n \tuint16_t qr = grinder->queue[qpos]->qr & (qsize - 1);\n \n \tgrinder->pkt = qbase[qr];\n@@ -2118,18 +2136,24 @@ grinder_handle(struct rte_sched_port *port, uint32_t pos)\n \n \tcase e_GRINDER_READ_MBUF:\n \t{\n-\t\tuint32_t result = 0;\n+\t\tuint32_t wrr_active, result = 0;\n \n \t\tresult = grinder_schedule(port, pos);\n \n+\t\twrr_active = (grinder->tc_index == RTE_SCHED_TRAFFIC_CLASS_BE);\n+\n \t\t/* Look for next packet within the same TC */\n \t\tif (result && grinder->qmask) {\n-\t\t\tgrinder_wrr(port, pos);\n+\t\t\tif (wrr_active)\n+\t\t\t\tgrinder_wrr(port, pos);\n+\n \t\t\tgrinder_prefetch_mbuf(port, pos);\n \n \t\t\treturn 1;\n \t\t}\n-\t\tgrinder_wrr_store(port, pos);\n+\n+\t\tif (wrr_active)\n+\t\t\tgrinder_wrr_store(port, pos);\n \n \t\t/* Look for another active TC within same pipe */\n \t\tif (grinder_next_tc(port, pos)) {\ndiff --git a/lib/librte_sched/rte_sched.h b/lib/librte_sched/rte_sched.h\nindex d61dda9f5..2a935998a 100644\n--- a/lib/librte_sched/rte_sched.h\n+++ b/lib/librte_sched/rte_sched.h\n@@ -66,6 +66,22 @@ extern \"C\" {\n #include \"rte_red.h\"\n #endif\n \n+/** Maximum number of queues per pipe.\n+ * Note that the multiple queues (power of 2) can only be assigned to\n+ * lowest priority (best-effort) traffic class. Other higher priority traffic\n+ * classes can only have one queue.\n+ * Can not change.\n+ *\n+ * @see struct rte_sched_port_params\n+ */\n+#define RTE_SCHED_QUEUES_PER_PIPE 16\n+\n+/** Number of WRR queues for best-effort traffic class per pipe.\n+ *\n+ * @see struct rte_sched_pipe_params\n+ */\n+#define RTE_SCHED_BE_QUEUES_PER_PIPE 4\n+\n /** Number of traffic classes per pipe (as well as subport).\n * Cannot be changed.\n */\n@@ -74,11 +90,6 @@ extern \"C\" {\n /** Number of queues per pipe traffic class. Cannot be changed. */\n #define RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS 4\n \n-/** Number of queues per pipe. */\n-#define RTE_SCHED_QUEUES_PER_PIPE \\\n-\t(RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE * \\\n-\tRTE_SCHED_QUEUES_PER_TRAFFIC_CLASS)\n-\n /** Maximum number of pipe profiles that can be defined per port.\n * Compile-time configurable.\n */\n@@ -165,7 +176,7 @@ struct rte_sched_pipe_params {\n #endif\n \n \t/* Pipe queues */\n-\tuint8_t wrr_weights[RTE_SCHED_QUEUES_PER_PIPE]; /**< WRR weights */\n+\tuint8_t wrr_weights[RTE_SCHED_BE_QUEUES_PER_PIPE]; /**< WRR weights */\n };\n \n /** Queue statistics */\n", "prefixes": [ "v4", "01/11" ] }