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GET /api/patches/56198/?format=api
{ "id": 56198, "url": "http://patches.dpdk.org/api/patches/56198/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1562586229-28201-1-git-send-email-xiao.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1562586229-28201-1-git-send-email-xiao.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1562586229-28201-1-git-send-email-xiao.zhang@intel.com", "date": "2019-07-08T11:43:49", "name": "[v2] net/e1000: i219 unit hang issue fix on reset/close", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4ef7fc41df7c3c08783a1225266211482b405e62", "submitter": { "id": 1352, "url": "http://patches.dpdk.org/api/people/1352/?format=api", "name": "Xiao Zhang", "email": "xiao.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1562586229-28201-1-git-send-email-xiao.zhang@intel.com/mbox/", "series": [ { "id": 5381, "url": "http://patches.dpdk.org/api/series/5381/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5381", "date": "2019-07-08T11:43:49", "name": "[v2] net/e1000: i219 unit hang issue fix on reset/close", "version": 2, "mbox": "http://patches.dpdk.org/series/5381/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56198/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/56198/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 11E4731FC;\n\tMon, 8 Jul 2019 04:48:26 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 888ED1C01\n\tfor <dev@dpdk.org>; Mon, 8 Jul 2019 04:48:23 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t07 Jul 2019 19:48:22 -0700", "from npg-dpdk-zhangxiao.sh.intel.com ([10.67.110.190])\n\tby orsmga003.jf.intel.com with ESMTP; 07 Jul 2019 19:48:21 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.63,465,1557212400\"; d=\"scan'208\";a=\"167545032\"", "From": "Xiao Zhang <xiao.zhang@intel.com>", "To": "dev@dpdk.org", "Cc": "Xiao Zhang <xiao.zhang@intel.com>", "Date": "Mon, 8 Jul 2019 19:43:49 +0800", "Message-Id": "<1562586229-28201-1-git-send-email-xiao.zhang@intel.com>", "X-Mailer": "git-send-email 2.7.4", "Subject": "[dpdk-dev] [v2] net/e1000: i219 unit hang issue fix on reset/close", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Unit hang may occur if multiple descriptors are available in the rings\nduring reset or close. This state can be detected by configure status\nby bit 8 in register. If the bit is set and there are pending descriptors\nin one of the rings, we must flush them before reset or close.\n\nSigned-off-by: Xiao Zhang <xiao.zhang@intel.com>\n---\n drivers/net/e1000/base/e1000_ich8lan.h | 1 +\n drivers/net/e1000/e1000_ethdev.h | 1 +\n drivers/net/e1000/igb_ethdev.c | 4 ++\n drivers/net/e1000/igb_rxtx.c | 96 ++++++++++++++++++++++++++++++++++\n 4 files changed, 102 insertions(+)", "diff": "diff --git a/drivers/net/e1000/base/e1000_ich8lan.h b/drivers/net/e1000/base/e1000_ich8lan.h\nindex bc4ed1d..1f2a3f8 100644\n--- a/drivers/net/e1000/base/e1000_ich8lan.h\n+++ b/drivers/net/e1000/base/e1000_ich8lan.h\n@@ -120,6 +120,7 @@ POSSIBILITY OF SUCH DAMAGE.\n #define E1000_FEXTNVM7_SIDE_CLK_UNGATE\t0x00000004\n #if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT)\n #define E1000_FEXTNVM7_DISABLE_SMB_PERST\t0x00000020\n+#define E1000_FEXTNVM7_NEED_DESCRING_FLUSH\t0x00000100\n #endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */\n #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS\t0x00000800\n #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS\t0x00001000\ndiff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h\nindex 67acb73..3451979 100644\n--- a/drivers/net/e1000/e1000_ethdev.h\n+++ b/drivers/net/e1000/e1000_ethdev.h\n@@ -522,5 +522,6 @@ int igb_action_rss_same(const struct rte_flow_action_rss *comp,\n int igb_config_rss_filter(struct rte_eth_dev *dev,\n \t\t\tstruct igb_rte_flow_rss_conf *conf,\n \t\t\tbool add);\n+void igb_flush_desc_rings(struct rte_eth_dev *dev);\n \n #endif /* _E1000_ETHDEV_H_ */\ndiff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c\nindex 3ee28cf..845101b 100644\n--- a/drivers/net/e1000/igb_ethdev.c\n+++ b/drivers/net/e1000/igb_ethdev.c\n@@ -1589,6 +1589,10 @@ eth_igb_close(struct rte_eth_dev *dev)\n \teth_igb_stop(dev);\n \tadapter->stopped = 1;\n \n+\t/* Flush desc rings for i219 */\n+\tif (hw->mac.type >= e1000_pch_spt)\n+\t\tigb_flush_desc_rings(dev);\n+\n \te1000_phy_hw_reset(hw);\n \tigb_release_manageability(hw);\n \tigb_hw_control_release(hw);\ndiff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c\nindex c5606de..33eeb4e 100644\n--- a/drivers/net/e1000/igb_rxtx.c\n+++ b/drivers/net/e1000/igb_rxtx.c\n@@ -18,6 +18,7 @@\n #include <rte_log.h>\n #include <rte_debug.h>\n #include <rte_pci.h>\n+#include <rte_bus_pci.h>\n #include <rte_memory.h>\n #include <rte_memcpy.h>\n #include <rte_memzone.h>\n@@ -63,6 +64,9 @@\n #define IGB_TX_OFFLOAD_NOTSUP_MASK \\\n \t\t(PKT_TX_OFFLOAD_MASK ^ IGB_TX_OFFLOAD_MASK)\n \n+/* PCI offset for querying descriptor ring status*/\n+#define PCICFG_DESC_RING_STATUS 0xE4\n+\n /**\n * Structure associated with each descriptor of the RX ring of a RX queue.\n */\n@@ -2962,3 +2966,95 @@ igb_config_rss_filter(struct rte_eth_dev *dev,\n \n \treturn 0;\n }\n+\n+static void e1000_flush_tx_ring(struct rte_eth_dev *dev)\n+{\n+\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tvolatile union e1000_adv_tx_desc *tx_desc;\n+\tuint32_t tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;\n+\tuint16_t size = 512;\n+\tstruct igb_tx_queue *txq;\n+\n+\tif (dev->data->tx_queues == NULL)\n+\t\treturn;\n+\ttxq = dev->data->tx_queues[0];\n+\n+\ttctl = E1000_READ_REG(hw, E1000_TCTL);\n+\tE1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);\n+\ttdt = E1000_READ_REG(hw, E1000_TDT(0));\n+\tif (tdt != txq->tx_tail)\n+\t\treturn;\n+\ttx_desc = txq->tx_ring;\n+\ttx_desc->read.buffer_addr = txq->tx_ring_phys_addr;\n+\ttx_desc->read.cmd_type_len = rte_cpu_to_le_32(txd_lower | size);\n+\ttx_desc->read.olinfo_status = 0;\n+\n+\trte_wmb();\n+\ttxq->tx_tail++;\n+\tif (txq->tx_tail == txq->nb_tx_desc)\n+\t\ttxq->tx_tail = 0;\n+\trte_io_wmb();\n+\tE1000_WRITE_REG(hw, E1000_TDT(0), txq->tx_tail);\n+\tusec_delay(250);\n+}\n+\n+static void e1000_flush_rx_ring(struct rte_eth_dev *dev)\n+{\n+\tuint32_t rctl, rxdctl;\n+\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\trctl = E1000_READ_REG(hw, E1000_RCTL);\n+\tE1000_WRITE_REG(hw, E1000_TCTL, rctl & ~E1000_RCTL_EN);\n+\tE1000_WRITE_FLUSH(hw);\n+\tusec_delay(150);\n+\n+\trxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));\n+\t/* zero the lower 14 bits (prefetch and host thresholds) */\n+\trxdctl &= 0xffffc000;\n+\n+\t/* update thresholds: prefetch threshold to 31, host threshold to 1\n+\t * and make sure the granularity is \"descriptors\" and not \"cache lines\"\n+\t */\n+\trxdctl |= (0x1F | (1UL << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);\n+\n+\tE1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl);\n+\t/* momentarily enable the RX ring for the changes to take effect */\n+\tE1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);\n+\tE1000_WRITE_FLUSH(hw);\n+\tusec_delay(150);\n+\tE1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);\n+}\n+\n+/**\n+ * igb_flush_desc_rings - remove all descriptors from the descriptor rings\n+ *\n+ * In i219, the descriptor rings must be emptied before resetting/closing the\n+ * HW. Failure to do this will cause the HW to enter a unit hang state which\n+ * can only be released by PCI reset on the device\n+ *\n+ */\n+\n+void igb_flush_desc_rings(struct rte_eth_dev *dev)\n+{\n+\tuint32_t fextnvm11, tdlen;\n+\tstruct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n+\tuint32_t hang_state = 0;\n+\n+\tfextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);\n+\tE1000_WRITE_REG(hw, E1000_FEXTNVM11,\n+\t\t\tfextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);\n+\ttdlen = E1000_READ_REG(hw, E1000_TDLEN(0));\n+\trte_pci_read_config(pci_dev, &hang_state, sizeof(hang_state),\n+\t\t\t\tPCICFG_DESC_RING_STATUS);\n+\n+\t/* do nothing if we're not in faulty state, or if the queue is empty */\n+\tif ((hang_state & E1000_FEXTNVM7_NEED_DESCRING_FLUSH) && tdlen) {\n+\t\t/* flush desc ring */\n+\t\te1000_flush_tx_ring(dev);\n+\t\trte_pci_read_config(pci_dev, &hang_state, sizeof(hang_state),\n+\t\t\t\t\tPCICFG_DESC_RING_STATUS);\n+\t\tif (hang_state & E1000_FEXTNVM7_NEED_DESCRING_FLUSH)\n+\t\t\te1000_flush_rx_ring(dev);\n+\t}\n+}\n", "prefixes": [ "v2" ] }