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GET /api/patches/56197/?format=api
{ "id": 56197, "url": "http://patches.dpdk.org/api/patches/56197/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1562419420-30278-1-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1562419420-30278-1-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1562419420-30278-1-git-send-email-anoobj@marvell.com", "date": "2019-07-06T13:23:39", "name": "[1/2] common/cpt: remove redundant bit swaps", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "aea841542f989e5979d70fbfc501f03d829a055b", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1562419420-30278-1-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 5380, "url": "http://patches.dpdk.org/api/series/5380/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5380", "date": "2019-07-06T13:23:40", "name": "[1/2] common/cpt: remove redundant bit swaps", "version": 1, "mbox": "http://patches.dpdk.org/series/5380/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/56197/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/56197/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6A44A5424;\n\tSat, 6 Jul 2019 15:51:27 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 6897F37AF\n\tfor <dev@dpdk.org>; Sat, 6 Jul 2019 15:51:23 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx66DoFt2001765; Sat, 6 Jul 2019 06:51:22 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tjs0nrn5h-2\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSat, 06 Jul 2019 06:51:22 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 6 Jul 2019 06:51:19 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 6 Jul 2019 06:51:19 -0700", "from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56])\n\tby maili.marvell.com (Postfix) with ESMTP id 25ACD3F739E;\n\tSat, 6 Jul 2019 06:23:45 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : mime-version :\n\tcontent-transfer-encoding : content-type; s=pfpt0818;\n\tbh=ptMzZ3kAnTr1+5KCzBx93TR0u5F/0Lf9TbntOUpPtk4=; \n\tb=HtgCRPnix0CzM0ArIYNNy8Bze7kdNVxshsB+IzOqjyagM1sL8Qj6aq01U7+sZBbNz9AZ\n\tucg58XDYFBYKO4Gg2TWXG7Vdb149hK8t7GszFyWrkfvfT4AD57lwt/CTXPZ3AgRPfs8o\n\tuIjsyLU8xZGOD9+HCR5uq3MR8gbMicBd3Sn48zGaCVfUHqU0n4Mp3iXyptGlxiLn++dj\n\tbcm7bDkkTpU4v7asR/ustPnL+TGqXyAF9sr1C1n1hnsVhMy5INNlkS5hSuKxdt2RRv14\n\tFGrYZwXpERCqtAeOSHCfbmKP2F9SnMdyMoPnAb+kJFahaOva3/OTgnkzM2h6fh+ooPgw\n\t2w== ", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara\n\t<pablo.de.lara.guarch@intel.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n\tNarayana Prasad <pathreya@marvell.com>, <dev@dpdk.org>", "Date": "Sat, 6 Jul 2019 18:53:39 +0530", "Message-ID": "<1562419420-30278-1-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-07-06_04:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 1/2] common/cpt: remove redundant bit swaps", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The bit swaps can be removed by re-arranging the structure.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\n---\n drivers/common/cpt/cpt_hw_types.h | 7 +++\n drivers/common/cpt/cpt_ucode.h | 116 ++++++++++++--------------------------\n 2 files changed, 44 insertions(+), 79 deletions(-)", "diff": "diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h\nindex 7be1d12..e2b127d 100644\n--- a/drivers/common/cpt/cpt_hw_types.h\n+++ b/drivers/common/cpt/cpt_hw_types.h\n@@ -30,10 +30,17 @@\n typedef union {\n \tuint64_t u64;\n \tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n \t\tuint16_t opcode;\n \t\tuint16_t param1;\n \t\tuint16_t param2;\n \t\tuint16_t dlen;\n+#else\n+\t\tuint16_t dlen;\n+\t\tuint16_t param2;\n+\t\tuint16_t param1;\n+\t\tuint16_t opcode;\n+#endif\n \t} s;\n } vq_cmd_word0_t;\n \ndiff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h\nindex e02b34a..c589b58 100644\n--- a/drivers/common/cpt/cpt_ucode.h\n+++ b/drivers/common/cpt/cpt_ucode.h\n@@ -520,16 +520,15 @@ cpt_digest_gen_prep(uint32_t flags,\n \n \t/*GP op header */\n \tvq_cmd_w0.u64 = 0;\n-\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(((uint16_t)hash_type << 8));\n+\tvq_cmd_w0.s.param2 = ((uint16_t)hash_type << 8);\n \tif (ctx->hmac) {\n \t\topcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;\n-\t\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(key_len);\n-\t\tvq_cmd_w0.s.dlen =\n-\t\t\trte_cpu_to_be_16((data_len + ROUNDUP8(key_len)));\n+\t\tvq_cmd_w0.s.param1 = key_len;\n+\t\tvq_cmd_w0.s.dlen = data_len + ROUNDUP8(key_len);\n \t} else {\n \t\topcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;\n \t\tvq_cmd_w0.s.param1 = 0;\n-\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(data_len);\n+\t\tvq_cmd_w0.s.dlen = data_len;\n \t}\n \n \topcode.s.minor = 0;\n@@ -540,10 +539,10 @@ cpt_digest_gen_prep(uint32_t flags,\n \t\t/* Minor op is passthrough */\n \t\topcode.s.minor = 0x03;\n \t\t/* Send out completion code only */\n-\t\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(0x1);\n+\t\tvq_cmd_w0.s.param2 = 0x1;\n \t}\n \n-\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t/* DPTR has SG list */\n \tin_buffer = m_vaddr;\n@@ -622,7 +621,7 @@ cpt_digest_gen_prep(uint32_t flags,\n \tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n \n \t/* This is DPTR len incase of SG mode */\n-\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\tvq_cmd_w0.s.dlen = size;\n \n \tm_vaddr = (uint8_t *)m_vaddr + size;\n \tm_dma += size;\n@@ -635,11 +634,6 @@ cpt_digest_gen_prep(uint32_t flags,\n \n \treq->ist.ei1 = dptr_dma;\n \treq->ist.ei2 = rptr_dma;\n-\t/* First 16-bit swap then 64-bit swap */\n-\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n-\t * to eliminate all the swapping\n-\t */\n-\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n \n \t/* vq command w3 */\n \tvq_cmd_w3.u64 = 0;\n@@ -798,8 +792,8 @@ cpt_enc_hmac_prep(uint32_t flags,\n \n \t/* GP op header */\n \tvq_cmd_w0.u64 = 0;\n-\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n-\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);\n+\tvq_cmd_w0.s.param1 = encr_data_len;\n+\tvq_cmd_w0.s.param2 = auth_data_len;\n \t/*\n \t * In 83XX since we have a limitation of\n \t * IV & Offset control word not part of instruction\n@@ -826,9 +820,9 @@ cpt_enc_hmac_prep(uint32_t flags,\n \t\treq->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr\n \t\t\t\t\t\t + outputlen - iv_len);\n \n-\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);\n+\t\tvq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;\n \n-\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\t\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t\tif (likely(iv_len)) {\n \t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr\n@@ -861,7 +855,7 @@ cpt_enc_hmac_prep(uint32_t flags,\n \n \t\topcode.s.major |= CPT_DMA_MODE;\n \n-\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\t\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t\tif (likely(iv_len)) {\n \t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr\n@@ -1005,7 +999,7 @@ cpt_enc_hmac_prep(uint32_t flags,\n \t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n \n \t\t/* This is DPTR len incase of SG mode */\n-\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\t\tvq_cmd_w0.s.dlen = size;\n \n \t\tm_vaddr = (uint8_t *)m_vaddr + size;\n \t\tm_dma += size;\n@@ -1020,12 +1014,6 @@ cpt_enc_hmac_prep(uint32_t flags,\n \t\treq->ist.ei2 = rptr_dma;\n \t}\n \n-\t/* First 16-bit swap then 64-bit swap */\n-\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n-\t * to eliminate all the swapping\n-\t */\n-\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n-\n \tctx_dma = fc_params->ctx_buf.dma_addr +\n \t\toffsetof(struct cpt_ctx, fctx);\n \t/* vq command w3 */\n@@ -1175,8 +1163,8 @@ cpt_dec_hmac_prep(uint32_t flags,\n \t\tencr_offset = inputlen;\n \n \tvq_cmd_w0.u64 = 0;\n-\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n-\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);\n+\tvq_cmd_w0.s.param1 = encr_data_len;\n+\tvq_cmd_w0.s.param2 = auth_data_len;\n \n \t/*\n \t * In 83XX since we have a limitation of\n@@ -1209,9 +1197,9 @@ cpt_dec_hmac_prep(uint32_t flags,\n \t\t * hmac.\n \t\t */\n \n-\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);\n+\t\tvq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;\n \n-\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\t\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t\tif (likely(iv_len)) {\n \t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n@@ -1245,7 +1233,7 @@ cpt_dec_hmac_prep(uint32_t flags,\n \n \t\topcode.s.major |= CPT_DMA_MODE;\n \n-\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\t\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t\tif (likely(iv_len)) {\n \t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n@@ -1401,7 +1389,7 @@ cpt_dec_hmac_prep(uint32_t flags,\n \t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n \n \t\t/* This is DPTR len incase of SG mode */\n-\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\t\tvq_cmd_w0.s.dlen = size;\n \n \t\tm_vaddr = (uint8_t *)m_vaddr + size;\n \t\tm_dma += size;\n@@ -1417,12 +1405,6 @@ cpt_dec_hmac_prep(uint32_t flags,\n \t\treq->ist.ei2 = rptr_dma;\n \t}\n \n-\t/* First 16-bit swap then 64-bit swap */\n-\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n-\t * to eliminate all the swapping\n-\t */\n-\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n-\n \tctx_dma = fc_params->ctx_buf.dma_addr +\n \t\toffsetof(struct cpt_ctx, fctx);\n \t/* vq command w3 */\n@@ -1579,8 +1561,8 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags,\n \t * GP op header, lengths are expected in bits.\n \t */\n \tvq_cmd_w0.u64 = 0;\n-\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n-\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);\n+\tvq_cmd_w0.s.param1 = encr_data_len;\n+\tvq_cmd_w0.s.param2 = auth_data_len;\n \n \t/*\n \t * In 83XX since we have a limitation of\n@@ -1609,9 +1591,9 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags,\n \t\treq->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr\n \t\t\t\t\t\t + outputlen - iv_len);\n \n-\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);\n+\t\tvq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;\n \n-\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\t\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t\tif (likely(iv_len)) {\n \t\t\tuint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr\n@@ -1638,7 +1620,7 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags,\n \n \t\topcode.s.major |= CPT_DMA_MODE;\n \n-\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\t\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t\t/* DPTR has SG list */\n \t\tin_buffer = m_vaddr;\n@@ -1740,7 +1722,7 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags,\n \t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n \n \t\t/* This is DPTR len incase of SG mode */\n-\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\t\tvq_cmd_w0.s.dlen = size;\n \n \t\tm_vaddr = (uint8_t *)m_vaddr + size;\n \t\tm_dma += size;\n@@ -1755,12 +1737,6 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags,\n \t\treq->ist.ei2 = rptr_dma;\n \t}\n \n-\t/* First 16-bit swap then 64-bit swap */\n-\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n-\t * to eliminate all the swapping\n-\t */\n-\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n-\n \t/* vq command w3 */\n \tvq_cmd_w3.u64 = 0;\n \tvq_cmd_w3.s.grp = 0;\n@@ -1886,7 +1862,7 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,\n \t * GP op header, lengths are expected in bits.\n \t */\n \tvq_cmd_w0.u64 = 0;\n-\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n+\tvq_cmd_w0.s.param1 = encr_data_len;\n \n \t/*\n \t * In 83XX since we have a limitation of\n@@ -1915,9 +1891,9 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,\n \t\treq->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr\n \t\t\t\t\t\t + outputlen - iv_len);\n \n-\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);\n+\t\tvq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;\n \n-\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\t\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t\tif (likely(iv_len)) {\n \t\t\tuint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr\n@@ -1945,7 +1921,7 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,\n \n \t\topcode.s.major |= CPT_DMA_MODE;\n \n-\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\t\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t\t/* DPTR has SG list */\n \t\tin_buffer = m_vaddr;\n@@ -2020,7 +1996,7 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,\n \t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n \n \t\t/* This is DPTR len incase of SG mode */\n-\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\t\tvq_cmd_w0.s.dlen = size;\n \n \t\tm_vaddr = (uint8_t *)m_vaddr + size;\n \t\tm_dma += size;\n@@ -2035,12 +2011,6 @@ cpt_zuc_snow3g_dec_prep(uint32_t req_flags,\n \t\treq->ist.ei2 = rptr_dma;\n \t}\n \n-\t/* First 16-bit swap then 64-bit swap */\n-\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n-\t * to eliminate all the swapping\n-\t */\n-\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n-\n \t/* vq command w3 */\n \tvq_cmd_w3.u64 = 0;\n \tvq_cmd_w3.s.grp = 0;\n@@ -2150,9 +2120,9 @@ cpt_kasumi_enc_prep(uint32_t req_flags,\n \t * GP op header, lengths are expected in bits.\n \t */\n \tvq_cmd_w0.u64 = 0;\n-\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n-\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);\n-\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\tvq_cmd_w0.s.param1 = encr_data_len;\n+\tvq_cmd_w0.s.param2 = auth_data_len;\n+\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t/* consider iv len */\n \tif (flags == 0x0) {\n@@ -2279,7 +2249,7 @@ cpt_kasumi_enc_prep(uint32_t req_flags,\n \tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n \n \t/* This is DPTR len incase of SG mode */\n-\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\tvq_cmd_w0.s.dlen = size;\n \n \tm_vaddr = (uint8_t *)m_vaddr + size;\n \tm_dma += size;\n@@ -2293,12 +2263,6 @@ cpt_kasumi_enc_prep(uint32_t req_flags,\n \treq->ist.ei1 = dptr_dma;\n \treq->ist.ei2 = rptr_dma;\n \n-\t/* First 16-bit swap then 64-bit swap */\n-\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n-\t * to eliminate all the swapping\n-\t */\n-\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n-\n \t/* vq command w3 */\n \tvq_cmd_w3.u64 = 0;\n \tvq_cmd_w3.s.grp = 0;\n@@ -2394,8 +2358,8 @@ cpt_kasumi_dec_prep(uint64_t d_offs,\n \t * GP op header, lengths are expected in bits.\n \t */\n \tvq_cmd_w0.u64 = 0;\n-\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n-\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\tvq_cmd_w0.s.param1 = encr_data_len;\n+\tvq_cmd_w0.s.opcode = opcode.flags;\n \n \t/* consider iv len */\n \tencr_offset += iv_len;\n@@ -2480,7 +2444,7 @@ cpt_kasumi_dec_prep(uint64_t d_offs,\n \tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n \n \t/* This is DPTR len incase of SG mode */\n-\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\tvq_cmd_w0.s.dlen = size;\n \n \tm_vaddr = (uint8_t *)m_vaddr + size;\n \tm_dma += size;\n@@ -2494,12 +2458,6 @@ cpt_kasumi_dec_prep(uint64_t d_offs,\n \treq->ist.ei1 = dptr_dma;\n \treq->ist.ei2 = rptr_dma;\n \n-\t/* First 16-bit swap then 64-bit swap */\n-\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n-\t * to eliminate all the swapping\n-\t */\n-\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n-\n \t/* vq command w3 */\n \tvq_cmd_w3.u64 = 0;\n \tvq_cmd_w3.s.grp = 0;\n", "prefixes": [ "1/2" ] }