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GET /api/patches/55727/?format=api
{ "id": 55727, "url": "http://patches.dpdk.org/api/patches/55727/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-58-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190630180609.36705-58-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190630180609.36705-58-jerinj@marvell.com", "date": "2019-06-30T18:06:09", "name": "[v2,57/57] net/octeontx2: add Rx interrupts support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7afdeb5dfea2bbdedce8beadce75ed11ca2f2034", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-58-jerinj@marvell.com/mbox/", "series": [ { "id": 5236, "url": "http://patches.dpdk.org/api/series/5236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5236", "date": "2019-06-30T18:05:12", "name": "OCTEON TX2 Ethdev driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55727/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/55727/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AC8771BC76;\n\tSun, 30 Jun 2019 20:12:34 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 560A71B9B5\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 20:09:30 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5UI54DB015680; Sun, 30 Jun 2019 11:09:29 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2te7gm3yg7-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 30 Jun 2019 11:09:29 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 30 Jun 2019 11:09:27 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 30 Jun 2019 11:09:27 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id C6CCE3F703F;\n\tSun, 30 Jun 2019 11:09:25 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=lVAljzD9O8pWtaEa4PCLPyX9g7IDnNFAI8JghDAo6+A=;\n\tb=RGxnpRY8hgVtTEnGqMBbK0lX3CGy1FV9Re1pyG2x0cWnt2BSUqqvD+zOia2ZVUAXmhvA\n\tXGak4shxID2KuaIfSTcBUmgoU2lcZjkvnlR5oBY3nKhbKCUxmqdMzMIH3RQkJYaEyyC1\n\tCWgXGBfPxe5IA7pQM/1abK9mXHxQ0A2LydHfrocfreJnLuRMCaeQqBEh8PH4vlMvi29X\n\tiLZvWI4wke8f3MaoPgYO+CEuT3co5pWrU8VXQlvfib0u4DEDuIG6H1FljItcLrT72FFP\n\tNsF/MhTxpE5SHfCy0/gqT1+S4ghsQ9GjRKWOwtKVbqtiDS+XdeODtBj0M1kPW0kKgrbI\n\tKw== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, John McNamara <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>, Jerin Jacob <jerinj@marvell.com>, \"Nithin\n\tDabilpuram\" <ndabilpuram@marvell.com>, Kiran Kumar K\n\t<kirankumark@marvell.com>", "CC": "Harman Kalra <hkalra@marvell.com>", "Date": "Sun, 30 Jun 2019 23:36:09 +0530", "Message-ID": "<20190630180609.36705-58-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190630180609.36705-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>\n\t<20190630180609.36705-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-30_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 57/57] net/octeontx2: add Rx interrupts support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Harman Kalra <hkalra@marvell.com>\n\nThis patch implements rx interrupts feature required for power\nsaving. These interrupts can be enabled/disabled on demand.\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n doc/guides/nics/features/octeontx2.ini | 1 +\n doc/guides/nics/features/octeontx2_vf.ini | 1 +\n doc/guides/nics/octeontx2.rst | 1 +\n drivers/net/octeontx2/otx2_ethdev.c | 31 ++++++\n drivers/net/octeontx2/otx2_ethdev.h | 16 +++\n drivers/net/octeontx2/otx2_ethdev_irq.c | 125 ++++++++++++++++++++++\n 6 files changed, 175 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\nindex be10dc0c8..66952328b 100644\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ b/doc/guides/nics/features/octeontx2.ini\n@@ -5,6 +5,7 @@\n ;\n [Features]\n Speed capabilities = Y\n+Rx interrupt = Y\n Lock-free Tx queue = Y\n SR-IOV = Y\n Multiprocess aware = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vf.ini b/doc/guides/nics/features/octeontx2_vf.ini\nindex bef451d01..16799309b 100644\n--- a/doc/guides/nics/features/octeontx2_vf.ini\n+++ b/doc/guides/nics/features/octeontx2_vf.ini\n@@ -7,6 +7,7 @@\n Speed capabilities = Y\n Lock-free Tx queue = Y\n Multiprocess aware = Y\n+Rx interrupt = Y\n Link status = Y\n Link status event = Y\n Runtime Rx queue setup = Y\ndiff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst\nindex 517e9e641..dbd376665 100644\n--- a/doc/guides/nics/octeontx2.rst\n+++ b/doc/guides/nics/octeontx2.rst\n@@ -36,6 +36,7 @@ Features of the OCTEON TX2 Ethdev PMD are:\n - Debug utilities - Context dump and error interrupt support\n - IEEE1588 timestamping\n - HW offloaded `ethdev Rx queue` to `eventdev event queue` packet injection\n+- Support Rx interrupt\n \n Prerequisites\n -------------\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 170593e95..7f50a4c0e 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -277,6 +277,8 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,\n \n \t/* Many to one reduction */\n \taq->cq.qint_idx = qid % dev->qints;\n+\t/* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */\n+\taq->cq.cint_idx = qid;\n \n \tif (otx2_ethdev_fixup_is_limit_cq_full(dev)) {\n \t\tuint16_t min_rx_drop;\n@@ -1204,6 +1206,8 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t\totx2_nix_vlan_fini(eth_dev);\n \t\totx2_flow_free_all_resources(dev);\n \t\toxt2_nix_unregister_queue_irqs(eth_dev);\n+\t\tif (eth_dev->data->dev_conf.intr_conf.rxq)\n+\t\t\toxt2_nix_unregister_cq_irqs(eth_dev);\n \t\tnix_set_nop_rxtx_function(eth_dev);\n \t\trc = nix_store_queue_cfg_and_then_release(eth_dev);\n \t\tif (rc)\n@@ -1264,6 +1268,27 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto free_nix_lf;\n \t}\n \n+\t/* Register cq IRQs */\n+\tif (eth_dev->data->dev_conf.intr_conf.rxq) {\n+\t\tif (eth_dev->data->nb_rx_queues > dev->cints) {\n+\t\t\totx2_err(\"Rx interrupt cannot be enabled, rxq > %d\",\n+\t\t\t\t dev->cints);\n+\t\t\tgoto free_nix_lf;\n+\t\t}\n+\t\t/* Rx interrupt feature cannot work with vector mode because,\n+\t\t * vector mode doesn't process packets unless min 4 pkts are\n+\t\t * received, while cq interrupts are generated even for 1 pkt\n+\t\t * in the CQ.\n+\t\t */\n+\t\tdev->scalar_ena = true;\n+\n+\t\trc = oxt2_nix_register_cq_irqs(eth_dev);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to register CQ interrupts rc=%d\", rc);\n+\t\t\tgoto free_nix_lf;\n+\t\t}\n+\t}\n+\n \t/* Configure loop back mode */\n \trc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);\n \tif (rc) {\n@@ -1576,6 +1601,8 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.vlan_strip_queue_set\t = otx2_nix_vlan_strip_queue_set,\n \t.vlan_tpid_set\t\t = otx2_nix_vlan_tpid_set,\n \t.vlan_pvid_set\t\t = otx2_nix_vlan_pvid_set,\n+\t.rx_queue_intr_enable\t = otx2_nix_rx_queue_intr_enable,\n+\t.rx_queue_intr_disable\t = otx2_nix_rx_queue_intr_disable,\n };\n \n static inline int\n@@ -1824,6 +1851,10 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n \t/* Unregister queue irqs */\n \toxt2_nix_unregister_queue_irqs(eth_dev);\n \n+\t/* Unregister cq irqs */\n+\tif (eth_dev->data->dev_conf.intr_conf.rxq)\n+\t\toxt2_nix_unregister_cq_irqs(eth_dev);\n+\n \trc = nix_lf_free(dev);\n \tif (rc)\n \t\totx2_err(\"Failed to free nix lf, rc=%d\", rc);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 3703acc69..f6905db83 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -102,6 +102,13 @@\n #define OP_ERR\t\t\tBIT_ULL(CQ_OP_STAT_OP_ERR)\n #define CQ_ERR\t\t\tBIT_ULL(CQ_OP_STAT_CQ_ERR)\n \n+#define CQ_CQE_THRESH_DEFAULT\t0x1ULL /* IRQ triggered when\n+\t\t\t\t\t* NIX_LF_CINTX_CNT[QCOUNT]\n+\t\t\t\t\t* crosses this value\n+\t\t\t\t\t*/\n+#define CQ_TIMER_THRESH_DEFAULT\t0xAULL /* ~1usec i.e (0xA * 100nsec) */\n+#define CQ_TIMER_THRESH_MAX 255\n+\n #define NIX_RSS_OFFLOAD\t\t(ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\\\n \t\t\t\t ETH_RSS_TCP | ETH_RSS_SCTP | \\\n \t\t\t\t ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)\n@@ -248,6 +255,7 @@ struct otx2_eth_dev {\n \tuint16_t qints;\n \tuint8_t configured;\n \tuint8_t configured_qints;\n+\tuint8_t configured_cints;\n \tuint8_t configured_nb_rx_qs;\n \tuint8_t configured_nb_tx_qs;\n \tuint16_t nix_msixoff;\n@@ -262,6 +270,7 @@ struct otx2_eth_dev {\n \tuint64_t rx_offload_capa;\n \tuint64_t tx_offload_capa;\n \tstruct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];\n+\tstruct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];\n \tuint16_t txschq[NIX_TXSCH_LVL_CNT];\n \tuint16_t txschq_contig[NIX_TXSCH_LVL_CNT];\n \tuint16_t txschq_index[NIX_TXSCH_LVL_CNT];\n@@ -384,8 +393,15 @@ void otx2_eth_dev_link_status_update(struct otx2_dev *dev,\n /* IRQ */\n int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);\n int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);\n+int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);\n void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);\n void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);\n+void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);\n+\n+int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,\n+\t\t\t\t uint16_t rx_queue_id);\n+int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,\n+\t\t\t\t uint16_t rx_queue_id);\n \n /* Debug */\n int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c\nindex 066aca7a5..9006e5c8b 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_irq.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_irq.c\n@@ -5,6 +5,7 @@\n #include <inttypes.h>\n \n #include <rte_bus_pci.h>\n+#include <rte_malloc.h>\n \n #include \"otx2_ethdev.h\"\n \n@@ -171,6 +172,18 @@ nix_lf_sq_debug_reg(struct otx2_eth_dev *dev, uint32_t off)\n \t\t\t (int)((reg >> 8) & 0xfffff), (uint8_t)(reg & 0xff));\n }\n \n+static void\n+nix_lf_cq_irq(void *param)\n+{\n+\tstruct otx2_qint *cint = (struct otx2_qint *)param;\n+\tstruct rte_eth_dev *eth_dev = cint->eth_dev;\n+\tstruct otx2_eth_dev *dev;\n+\n+\tdev = otx2_eth_pmd_priv(eth_dev);\n+\t/* Clear interrupt */\n+\totx2_write64(BIT_ULL(0), dev->base + NIX_LF_CINTX_INT(cint->qintx));\n+}\n+\n static void\n nix_lf_q_irq(void *param)\n {\n@@ -315,6 +328,92 @@ oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev)\n \t}\n }\n \n+int\n+oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint8_t rc = 0, vec, q;\n+\n+\tdev->configured_cints = RTE_MIN(dev->cints,\n+\t\t\t\t\teth_dev->data->nb_rx_queues);\n+\n+\tfor (q = 0; q < dev->configured_cints; q++) {\n+\t\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_CINT_START + q;\n+\n+\t\t/* Clear CINT CNT */\n+\t\totx2_write64(0, dev->base + NIX_LF_CINTX_CNT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\totx2_write64(BIT_ULL(0), dev->base + NIX_LF_CINTX_ENA_W1C(q));\n+\n+\t\tdev->cints_mem[q].eth_dev = eth_dev;\n+\t\tdev->cints_mem[q].qintx = q;\n+\n+\t\t/* Sync cints_mem update */\n+\t\trte_smp_wmb();\n+\n+\t\t/* Register queue irq vector */\n+\t\trc = otx2_register_irq(handle, nix_lf_cq_irq,\n+\t\t\t\t &dev->cints_mem[q], vec);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Fail to register CQ irq, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tif (!handle->intr_vec) {\n+\t\t\thandle->intr_vec = rte_zmalloc(\"intr_vec\",\n+\t\t\t\t\t dev->configured_cints *\n+\t\t\t\t\t sizeof(int), 0);\n+\t\t\tif (!handle->intr_vec) {\n+\t\t\t\totx2_err(\"Failed to allocate %d rx intr_vec\",\n+\t\t\t\t\t dev->configured_cints);\n+\t\t\t\treturn -ENOMEM;\n+\t\t\t}\n+\t\t}\n+\t\t/* VFIO vector zero is resereved for misc interrupt so\n+\t\t * doing required adjustment. (b13bfab4cd)\n+\t\t */\n+\t\thandle->intr_vec[q] = RTE_INTR_VEC_RXTX_OFFSET + vec;\n+\n+\t\t/* Configure CQE interrupt coalescing parameters */\n+\t\totx2_write64(((CQ_CQE_THRESH_DEFAULT) |\n+\t\t\t (CQ_CQE_THRESH_DEFAULT << 32) |\n+\t\t\t (CQ_TIMER_THRESH_DEFAULT << 48)),\n+\t\t\t dev->base + NIX_LF_CINTX_WAIT((q)));\n+\n+\t\t/* Keeping the CQ interrupt disabled as the rx interrupt\n+\t\t * feature needs to be enabled/disabled on demand.\n+\t\t */\n+\t}\n+\n+\treturn rc;\n+}\n+\n+void\n+oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint vec, q;\n+\n+\tfor (q = 0; q < dev->configured_cints; q++) {\n+\t\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_CINT_START + q;\n+\n+\t\t/* Clear CINT CNT */\n+\t\totx2_write64(0, dev->base + NIX_LF_CINTX_CNT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\totx2_write64(BIT_ULL(0), dev->base + NIX_LF_CINTX_ENA_W1C(q));\n+\n+\t\t/* Unregister queue irq vector */\n+\t\totx2_unregister_irq(handle, nix_lf_cq_irq,\n+\t\t\t\t &dev->cints_mem[q], vec);\n+\t}\n+}\n+\n int\n otx2_nix_register_irqs(struct rte_eth_dev *eth_dev)\n {\n@@ -341,3 +440,29 @@ otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev)\n \tnix_lf_unregister_err_irq(eth_dev);\n \tnix_lf_unregister_ras_irq(eth_dev);\n }\n+\n+int\n+otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,\n+\t\t\t uint16_t rx_queue_id)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\t/* Enable CINT interrupt */\n+\totx2_write64(BIT_ULL(0), dev->base +\n+\t\t NIX_LF_CINTX_ENA_W1S(rx_queue_id));\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,\n+\t\t\t uint16_t rx_queue_id)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\t/* Clear and disable CINT interrupt */\n+\totx2_write64(BIT_ULL(0), dev->base +\n+\t\t NIX_LF_CINTX_ENA_W1C(rx_queue_id));\n+\n+\treturn 0;\n+}\n", "prefixes": [ "v2", "57/57" ] }