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GET /api/patches/55680/?format=api
{ "id": 55680, "url": "http://patches.dpdk.org/api/patches/55680/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-5-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190630180609.36705-5-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190630180609.36705-5-jerinj@marvell.com", "date": "2019-06-30T18:05:16", "name": "[v2,04/57] net/octeontx2: add devargs parsing functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "50924f6a3dd375e5d53af6c4355313e0f9686e53", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190630180609.36705-5-jerinj@marvell.com/mbox/", "series": [ { "id": 5236, "url": "http://patches.dpdk.org/api/series/5236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5236", "date": "2019-06-30T18:05:12", "name": "OCTEON TX2 Ethdev driver", "version": 2, "mbox": "http://patches.dpdk.org/series/5236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55680/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/55680/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6FE551B9B2;\n\tSun, 30 Jun 2019 20:06:58 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id A4D871B965\n\tfor <dev@dpdk.org>; Sun, 30 Jun 2019 20:06:48 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5UI50uC015649; Sun, 30 Jun 2019 11:06:48 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2te7gm3y7g-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 30 Jun 2019 11:06:48 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 30 Jun 2019 11:06:46 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 30 Jun 2019 11:06:46 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id A90B13F703F;\n\tSun, 30 Jun 2019 11:06:43 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=mQJlPAX4YGCuWH6wLTEco+MxDQqDE9wQBLSoWZhpfEw=;\n\tb=N2Gfuf6DWU8XLhceI98WUslFwd91eHF3QhHmCtQsx5It2ItuZ/FgXT6cQr9sGJw0UHM3\n\tf+vOdP0br63r3sUdqqwP3Ey9kWKZtsGzUHFH9P9MG+WUNS14AHULmG945W6/naK2CC2G\n\t1i/lNmiDTmSfYOmQnSCE79GBKiOmyFREgkpQONN8AH1Ct60rYrIxHMWB0Iy+cpbBFtep\n\tjlb6eQNccFdUN7gH1+QZe7pmQtBlxAkkXB3xcH9tUKDxvvYjxykVkxtHq9nX+yxjc3Su\n\tReGt+/HByuucWA+EzcVMkFfSeTyL3G/KgIeW1s0AZ4PoRuaT4JoThmSMabPw6Tq0MVVI\n\tbA== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>, \"John\n\tMcNamara\" <john.mcnamara@intel.com>, Marko Kovacevic\n\t<marko.kovacevic@intel.com>", "CC": "Pavan Nikhilesh <pbhagavatula@marvell.com>, Vamsi Attunuru\n\t<vattunuru@marvell.com>", "Date": "Sun, 30 Jun 2019 23:35:16 +0530", "Message-ID": "<20190630180609.36705-5-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190630180609.36705-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>\n\t<20190630180609.36705-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-30_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 04/57] net/octeontx2: add devargs parsing\n\tfunctions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nadd various devargs command line options supported by\nthis driver.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Kiran Kumar K <kirankumark@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n doc/guides/nics/octeontx2.rst | 67 ++++++++\n drivers/net/octeontx2/Makefile | 5 +-\n drivers/net/octeontx2/meson.build | 1 +\n drivers/net/octeontx2/otx2_ethdev.c | 7 +\n drivers/net/octeontx2/otx2_ethdev.h | 23 +++\n drivers/net/octeontx2/otx2_ethdev_devargs.c | 165 ++++++++++++++++++++\n drivers/net/octeontx2/otx2_rx.h | 10 ++\n 7 files changed, 276 insertions(+), 2 deletions(-)\n create mode 100644 drivers/net/octeontx2/otx2_ethdev_devargs.c\n create mode 100644 drivers/net/octeontx2/otx2_rx.h", "diff": "diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst\nindex f0bd36be3..92a7ebc42 100644\n--- a/doc/guides/nics/octeontx2.rst\n+++ b/doc/guides/nics/octeontx2.rst\n@@ -30,3 +30,70 @@ The following options may be modified in the ``config`` file.\n - ``CONFIG_RTE_LIBRTE_OCTEONTX2_PMD`` (default ``y``)\n \n Toggle compilation of the ``librte_pmd_octeontx2`` driver.\n+\n+Runtime Config Options\n+----------------------\n+\n+- ``HW offload ptype parsing disable`` (default ``0``)\n+\n+ Packet type parsing is HW offloaded by default and this feature may be toggled\n+ using ``ptype_disable`` ``devargs`` parameter.\n+\n+- ``Rx&Tx scalar mode enable`` (default ``0``)\n+\n+ Ethdev supports both scalar and vector mode, it may be selected at runtime\n+ using ``scalar_enable`` ``devargs`` parameter.\n+\n+- ``RSS reta size`` (default ``64``)\n+\n+ RSS redirection table size may be configured during runtime using ``reta_size``\n+ ``devargs`` parameter.\n+\n+ For example::\n+\n+ -w 0002:02:00.0,reta_size=256\n+\n+ With the above configuration, reta table of size 256 is populated.\n+\n+- ``Flow priority levels`` (default ``3``)\n+\n+ RTE Flow priority levels can be configured during runtime using\n+ ``flow_max_priority`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -w 0002:02:00.0,flow_max_priority=10\n+\n+ With the above configuration, priority level was set to 10 (0-9). Max\n+ priority level supported is 32.\n+\n+- ``Reserve Flow entries`` (default ``8``)\n+\n+ RTE flow entries can be pre allocated and the size of pre allocation can be\n+ selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -w 0002:02:00.0,flow_prealloc_size=4\n+\n+ With the above configuration, pre alloc size was set to 4. Max pre alloc\n+ size supported is 32.\n+\n+- ``Max SQB buffer count`` (default ``512``)\n+\n+ Send queue descriptor buffer count may be limited during runtime using\n+ ``max_sqb_count`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -w 0002:02:00.0,max_sqb_count=64\n+\n+ With the above configuration, each send queue's decscriptor buffer count is\n+ limited to a maximum of 64 buffers.\n+\n+\n+.. note::\n+\n+ Above devarg parameters are configurable per device, user needs to pass the\n+ parameters to all the PCIe devices if application requires to configure on\n+ all the ethdev ports.\ndiff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex 4ff3609d2..d1c8871d8 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -29,9 +29,10 @@ LIBABIVER := 1\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_mac.c\t\\\n-\totx2_ethdev.c\n+\totx2_ethdev.c\t\\\n+\totx2_ethdev_devargs.c\n \n LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2 -lrte_eal\n-LDLIBS += -lrte_ethdev -lrte_bus_pci\n+LDLIBS += -lrte_ethdev -lrte_bus_pci -lrte_kvargs\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex b153f166d..b5c6fb978 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -5,6 +5,7 @@\n sources = files(\n \t\t'otx2_mac.c',\n \t\t'otx2_ethdev.c',\n+\t\t'otx2_ethdev_devargs.c'\n \t\t)\n \n deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2']\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 08f03b4c3..eeba0c2c6 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -137,6 +137,13 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)\n \tmemset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -\n \t\toffsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));\n \n+\t/* Parse devargs string */\n+\trc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to parse devargs rc=%d\", rc);\n+\t\tgoto error;\n+\t}\n+\n \tif (!dev->mbox_active) {\n \t\t/* Initialize the base otx2_dev object\n \t\t * only if already present\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex d9f72686a..a83688392 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -9,11 +9,13 @@\n \n #include <rte_common.h>\n #include <rte_ethdev.h>\n+#include <rte_kvargs.h>\n \n #include \"otx2_common.h\"\n #include \"otx2_dev.h\"\n #include \"otx2_irq.h\"\n #include \"otx2_mempool.h\"\n+#include \"otx2_rx.h\"\n \n #define OTX2_ETH_DEV_PMD_VERSION\t\"1.0\"\n \n@@ -31,6 +33,10 @@\n /* Used for struct otx2_eth_dev::flags */\n #define OTX2_LINK_CFG_IN_PROGRESS_F\tBIT_ULL(0)\n \n+#define NIX_MAX_SQB\t\t\t512\n+#define NIX_MIN_SQB\t\t\t32\n+#define NIX_RSS_RETA_SIZE\t\t64\n+\n #define NIX_TX_OFFLOAD_CAPA ( \\\n \tDEV_TX_OFFLOAD_MBUF_FAST_FREE\t| \\\n \tDEV_TX_OFFLOAD_MT_LOCKFREE\t| \\\n@@ -56,6 +62,15 @@\n \tDEV_RX_OFFLOAD_QINQ_STRIP | \\\n \tDEV_RX_OFFLOAD_TIMESTAMP)\n \n+struct otx2_rss_info {\n+\tuint16_t rss_size;\n+};\n+\n+struct otx2_npc_flow_info {\n+\tuint16_t flow_prealloc_size;\n+\tuint16_t flow_max_priority;\n+};\n+\n struct otx2_eth_dev {\n \tOTX2_DEV; /* Base class */\n \tMARKER otx2_eth_dev_data_start;\n@@ -72,12 +87,16 @@ struct otx2_eth_dev {\n \tuint16_t nix_msixoff;\n \tuintptr_t base;\n \tuintptr_t lmt_addr;\n+\tuint16_t scalar_ena;\n+\tuint16_t max_sqb_count;\n \tuint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */\n \tuint64_t rx_offloads;\n \tuint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */\n \tuint64_t tx_offloads;\n \tuint64_t rx_offload_capa;\n \tuint64_t tx_offload_capa;\n+\tstruct otx2_rss_info rss_info;\n+\tstruct otx2_npc_flow_info npc_flow;\n } __rte_cache_aligned;\n \n static inline struct otx2_eth_dev *\n@@ -96,4 +115,8 @@ int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,\n int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);\n int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);\n \n+/* Devargs */\n+int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,\n+\t\t\t struct otx2_eth_dev *dev);\n+\n #endif /* __OTX2_ETHDEV_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c\nnew file mode 100644\nindex 000000000..85e7e312a\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_ethdev_devargs.c\n@@ -0,0 +1,165 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <inttypes.h>\n+#include <math.h>\n+\n+#include \"otx2_ethdev.h\"\n+\n+static int\n+parse_flow_max_priority(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint16_t val;\n+\n+\tval = atoi(value);\n+\n+\t/* Limit the max priority to 32 */\n+\tif (val < 1 || val > 32)\n+\t\treturn -EINVAL;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint16_t val;\n+\n+\tval = atoi(value);\n+\n+\t/* Limit the prealloc size to 32 */\n+\tif (val < 1 || val > 32)\n+\t\treturn -EINVAL;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_reta_size(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint32_t val;\n+\n+\tval = atoi(value);\n+\n+\tif (val <= ETH_RSS_RETA_SIZE_64)\n+\t\tval = ETH_RSS_RETA_SIZE_64;\n+\telse if (val > ETH_RSS_RETA_SIZE_64 && val <= ETH_RSS_RETA_SIZE_128)\n+\t\tval = ETH_RSS_RETA_SIZE_128;\n+\telse if (val > ETH_RSS_RETA_SIZE_128 && val <= ETH_RSS_RETA_SIZE_256)\n+\t\tval = ETH_RSS_RETA_SIZE_256;\n+\telse\n+\t\tval = NIX_RSS_RETA_SIZE;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_ptype_flag(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint32_t val;\n+\n+\tval = atoi(value);\n+\tif (val)\n+\t\tval = 0; /* Disable NIX_RX_OFFLOAD_PTYPE_F */\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_flag(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\n+\t*(uint16_t *)extra_args = atoi(value);\n+\n+\treturn 0;\n+}\n+\n+static int\n+parse_sqb_count(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint32_t val;\n+\n+\tval = atoi(value);\n+\n+\tif (val < NIX_MIN_SQB || val > NIX_MAX_SQB)\n+\t\treturn -EINVAL;\n+\n+\t*(uint16_t *)extra_args = val;\n+\n+\treturn 0;\n+}\n+\n+#define OTX2_RSS_RETA_SIZE \"reta_size\"\n+#define OTX2_PTYPE_DISABLE \"ptype_disable\"\n+#define OTX2_SCL_ENABLE \"scalar_enable\"\n+#define OTX2_MAX_SQB_COUNT \"max_sqb_count\"\n+#define OTX2_FLOW_PREALLOC_SIZE \"flow_prealloc_size\"\n+#define OTX2_FLOW_MAX_PRIORITY \"flow_max_priority\"\n+\n+int\n+otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)\n+{\n+\tuint16_t offload_flag = NIX_RX_OFFLOAD_PTYPE_F;\n+\tuint16_t rss_size = NIX_RSS_RETA_SIZE;\n+\tuint16_t sqb_count = NIX_MAX_SQB;\n+\tuint16_t flow_prealloc_size = 8;\n+\tuint16_t flow_max_priority = 3;\n+\tuint16_t scalar_enable = 0;\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\tgoto null_devargs;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\tgoto exit;\n+\n+\trte_kvargs_process(kvlist, OTX2_PTYPE_DISABLE,\n+\t\t\t &parse_ptype_flag, &offload_flag);\n+\trte_kvargs_process(kvlist, OTX2_RSS_RETA_SIZE,\n+\t\t\t &parse_reta_size, &rss_size);\n+\trte_kvargs_process(kvlist, OTX2_SCL_ENABLE,\n+\t\t\t &parse_flag, &scalar_enable);\n+\trte_kvargs_process(kvlist, OTX2_MAX_SQB_COUNT,\n+\t\t\t &parse_sqb_count, &sqb_count);\n+\trte_kvargs_process(kvlist, OTX2_FLOW_PREALLOC_SIZE,\n+\t\t\t &parse_flow_prealloc_size, &flow_prealloc_size);\n+\trte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,\n+\t\t\t &parse_flow_max_priority, &flow_max_priority);\n+\trte_kvargs_free(kvlist);\n+\n+null_devargs:\n+\tdev->rx_offload_flags = offload_flag;\n+\tdev->scalar_ena = scalar_enable;\n+\tdev->max_sqb_count = sqb_count;\n+\tdev->rss_info.rss_size = rss_size;\n+\tdev->npc_flow.flow_prealloc_size = flow_prealloc_size;\n+\tdev->npc_flow.flow_max_priority = flow_max_priority;\n+\treturn 0;\n+\n+exit:\n+\treturn -EINVAL;\n+}\n+\n+RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,\n+\t\t\t OTX2_RSS_RETA_SIZE \"=<64|128|256>\"\n+\t\t\t OTX2_PTYPE_DISABLE \"=1\"\n+\t\t\t OTX2_SCL_ENABLE \"=1\"\n+\t\t\t OTX2_MAX_SQB_COUNT \"=<32-512>\"\n+\t\t\t OTX2_FLOW_PREALLOC_SIZE \"=<1-32>\"\n+\t\t\t OTX2_FLOW_MAX_PRIORITY \"=<1-32>\");\ndiff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h\nnew file mode 100644\nindex 000000000..1749c43ff\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_rx.h\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_RX_H__\n+#define __OTX2_RX_H__\n+\n+#define NIX_RX_OFFLOAD_PTYPE_F BIT(1)\n+\n+#endif /* __OTX2_RX_H__ */\n", "prefixes": [ "v2", "04/57" ] }