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GET /api/patches/55613/?format=api
{ "id": 55613, "url": "http://patches.dpdk.org/api/patches/55613/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-9-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628182354.228-9-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-9-pbhagavatula@marvell.com", "date": "2019-06-28T18:23:19", "name": "[v3,08/42] event/octeontx2: add event port config functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "33db4cc2bdef9ce249d05174e7ffb9c01bb3ea6b", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190628182354.228-9-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5227, "url": "http://patches.dpdk.org/api/series/5227/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5227", "date": "2019-06-28T18:23:11", "name": "OCTEONTX2 event device driver", "version": 3, "mbox": "http://patches.dpdk.org/series/5227/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55613/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55613/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DEE801B9A1;\n\tFri, 28 Jun 2019 20:24:25 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id DFC581B970\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:24:18 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIKCIe010202 for <dev@dpdk.org>; Fri, 28 Jun 2019 11:24:18 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2tdkg191gg-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 11:24:18 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:24:16 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:24:16 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id E4D7F3F7040;\n\tFri, 28 Jun 2019 11:24:14 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=I9e7hw0FhXFSY9VKV6d7L054HuzAIz0qZZCTPkjU6wE=;\n\tb=djjUMhQxcjirC56COjY1EWecUEiGqsAQZcqcVNENLOkE2H0sX518kFN8LnnxVM8HL8pj\n\t3q0hLXw7nnMYGT2zmW7RMQdiBZ+nfAqzDsfIkBJcshQPOoBy7QQCIRRr9J8Uf87PJtDZ\n\toaAXMngpppPfC3F36huVJEHCxYBaZOTqGQiEvzgepMrulBO2mCKEvPshbGdrU5v6Bbqj\n\tS9i7uzdRvoRJFzJJthsisLOdKRqAdjkxTpYz8phAv6qOUm9qkj2JajENJiPl4N+pXppq\n\t5MV0Ii/spjKxPFICeQnHOId5XanFFBbW8Vv3szaPpS0x5e+1sduGuibD9WoXXgcvAgQo\n\trQ== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 28 Jun 2019 23:53:19 +0530", "Message-ID": "<20190628182354.228-9-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>", "References": "<20190628182354.228-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v3 08/42] event/octeontx2: add event port config\n\tfunctions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd default config, setup and release functions for event ports\ni.e. SSO GWS.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev.c | 110 ++++++++++++++++++++++++++-\n drivers/event/octeontx2/otx2_evdev.h | 59 ++++++++++++++\n 2 files changed, 168 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 94c97fc9e..a6bf861fb 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -144,6 +144,12 @@ sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,\n \treturn 0;\n }\n \n+static void\n+otx2_sso_port_release(void *port)\n+{\n+\trte_free(port);\n+}\n+\n static void\n otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)\n {\n@@ -151,13 +157,24 @@ otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)\n \tRTE_SET_USED(queue_id);\n }\n \n+static void\n+sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)\n+{\n+\tws->tag_op\t\t= base + SSOW_LF_GWS_TAG;\n+\tws->wqp_op\t\t= base + SSOW_LF_GWS_WQP;\n+\tws->getwrk_op\t\t= base + SSOW_LF_GWS_OP_GET_WORK;\n+\tws->swtp_op\t\t= base + SSOW_LF_GWS_SWTP;\n+\tws->swtag_norm_op\t= base + SSOW_LF_GWS_OP_SWTAG_NORM;\n+\tws->swtag_desched_op\t= base + SSOW_LF_GWS_OP_SWTAG_DESCHED;\n+}\n+\n static int\n sso_configure_ports(const struct rte_eventdev *event_dev)\n {\n \tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n \tstruct otx2_mbox *mbox = dev->mbox;\n \tuint8_t nb_lf;\n-\tint rc;\n+\tint i, rc;\n \n \totx2_sso_dbg(\"Configuring event ports %d\", dev->nb_event_ports);\n \n@@ -175,6 +192,40 @@ sso_configure_ports(const struct rte_eventdev *event_dev)\n \t\treturn -ENODEV;\n \t}\n \n+\tfor (i = 0; i < nb_lf; i++) {\n+\t\tstruct otx2_ssogws *ws;\n+\t\tuintptr_t base;\n+\n+\t\t/* Free memory prior to re-allocation if needed */\n+\t\tif (event_dev->data->ports[i] != NULL) {\n+\t\t\tws = event_dev->data->ports[i];\n+\t\t\trte_free(ws);\n+\t\t\tws = NULL;\n+\t\t}\n+\n+\t\t/* Allocate event port memory */\n+\t\tws = rte_zmalloc_socket(\"otx2_sso_ws\",\n+\t\t\t\t\tsizeof(struct otx2_ssogws),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n+\t\t\t\t\tevent_dev->data->socket_id);\n+\t\tif (ws == NULL) {\n+\t\t\totx2_err(\"Failed to alloc memory for port=%d\", i);\n+\t\t\trc = -ENOMEM;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tws->port = i;\n+\t\tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);\n+\t\tsso_set_port_ops(ws, base);\n+\n+\t\tevent_dev->data->ports[i] = ws;\n+\t}\n+\n+\tif (rc < 0) {\n+\t\tsso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);\n+\t\tsso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);\n+\t}\n+\n \treturn rc;\n }\n \n@@ -459,6 +510,60 @@ otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,\n \treturn 0;\n }\n \n+static void\n+otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,\n+\t\t struct rte_event_port_conf *port_conf)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\n+\tRTE_SET_USED(port_id);\n+\tport_conf->new_event_threshold = dev->max_num_events;\n+\tport_conf->dequeue_depth = 1;\n+\tport_conf->enqueue_depth = 1;\n+}\n+\n+static int\n+otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,\n+\t\t const struct rte_event_port_conf *port_conf)\n+{\n+\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n+\tuintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};\n+\tuint64_t val;\n+\tuint16_t q;\n+\n+\tsso_func_trace(\"Port=%d\", port_id);\n+\tRTE_SET_USED(port_conf);\n+\n+\tif (event_dev->data->ports[port_id] == NULL) {\n+\t\totx2_err(\"Invalid port Id %d\", port_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (q = 0; q < dev->nb_event_queues; q++) {\n+\t\tgrps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);\n+\t\tif (grps_base[q] == 0) {\n+\t\t\totx2_err(\"Failed to get grp[%d] base addr\", q);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\t/* Set get_work timeout for HWS */\n+\tval = NSEC2USEC(dev->deq_tmo_ns) - 1;\n+\n+\tstruct otx2_ssogws *ws = event_dev->data->ports[port_id];\n+\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n+\n+\trte_memcpy(ws->grps_base, grps_base,\n+\t\t sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);\n+\tws->fc_mem = dev->fc_mem;\n+\tws->xaq_lmt = dev->xaq_lmt;\n+\totx2_write64(val, base + SSOW_LF_GWS_NW_TIM);\n+\n+\totx2_sso_dbg(\"Port=%d ws=%p\", port_id, event_dev->data->ports[port_id]);\n+\n+\treturn 0;\n+}\n+\n /* Initialize and register event driver with DPDK Application */\n static struct rte_eventdev_ops otx2_sso_ops = {\n \t.dev_infos_get = otx2_sso_info_get,\n@@ -466,6 +571,9 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \t.queue_def_conf = otx2_sso_queue_def_conf,\n \t.queue_setup = otx2_sso_queue_setup,\n \t.queue_release = otx2_sso_queue_release,\n+\t.port_def_conf = otx2_sso_port_def_conf,\n+\t.port_setup = otx2_sso_port_setup,\n+\t.port_release = otx2_sso_port_release,\n };\n \n #define OTX2_SSO_XAE_CNT\t\"xae_cnt\"\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex acc8b6b3e..3f4931ff1 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -38,6 +38,42 @@\n #define SSO_LF_GGRP_AQ_THR (0x1e0ull)\n #define SSO_LF_GGRP_MISC_CNT (0x200ull)\n \n+/* SSOW LF register offsets (BAR2) */\n+#define SSOW_LF_GWS_LINKS (0x10ull)\n+#define SSOW_LF_GWS_PENDWQP (0x40ull)\n+#define SSOW_LF_GWS_PENDSTATE (0x50ull)\n+#define SSOW_LF_GWS_NW_TIM (0x70ull)\n+#define SSOW_LF_GWS_GRPMSK_CHG (0x80ull)\n+#define SSOW_LF_GWS_INT (0x100ull)\n+#define SSOW_LF_GWS_INT_W1S (0x108ull)\n+#define SSOW_LF_GWS_INT_ENA_W1S (0x110ull)\n+#define SSOW_LF_GWS_INT_ENA_W1C (0x118ull)\n+#define SSOW_LF_GWS_TAG (0x200ull)\n+#define SSOW_LF_GWS_WQP (0x210ull)\n+#define SSOW_LF_GWS_SWTP (0x220ull)\n+#define SSOW_LF_GWS_PENDTAG (0x230ull)\n+#define SSOW_LF_GWS_OP_ALLOC_WE (0x400ull)\n+#define SSOW_LF_GWS_OP_GET_WORK (0x600ull)\n+#define SSOW_LF_GWS_OP_SWTAG_FLUSH (0x800ull)\n+#define SSOW_LF_GWS_OP_SWTAG_UNTAG (0x810ull)\n+#define SSOW_LF_GWS_OP_SWTP_CLR (0x820ull)\n+#define SSOW_LF_GWS_OP_UPD_WQP_GRP0 (0x830ull)\n+#define SSOW_LF_GWS_OP_UPD_WQP_GRP1 (0x838ull)\n+#define SSOW_LF_GWS_OP_DESCHED (0x880ull)\n+#define SSOW_LF_GWS_OP_DESCHED_NOSCH (0x8c0ull)\n+#define SSOW_LF_GWS_OP_SWTAG_DESCHED (0x980ull)\n+#define SSOW_LF_GWS_OP_SWTAG_NOSCHED (0x9c0ull)\n+#define SSOW_LF_GWS_OP_CLR_NSCHED0 (0xa00ull)\n+#define SSOW_LF_GWS_OP_CLR_NSCHED1 (0xa08ull)\n+#define SSOW_LF_GWS_OP_SWTP_SET (0xc00ull)\n+#define SSOW_LF_GWS_OP_SWTAG_NORM (0xc10ull)\n+#define SSOW_LF_GWS_OP_SWTAG_FULL0 (0xc20ull)\n+#define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull)\n+#define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull)\n+\n+#define OTX2_SSOW_GET_BASE_ADDR(_GW) ((_GW) - SSOW_LF_GWS_OP_GET_WORK)\n+\n+#define NSEC2USEC(__ns)\t\t\t((__ns) / 1E3)\n #define USEC2NSEC(__us) ((__us) * 1E3)\n \n enum otx2_sso_lf_type {\n@@ -70,6 +106,29 @@ struct otx2_sso_evdev {\n \tuint32_t iue;\n } __rte_cache_aligned;\n \n+#define OTX2_SSOGWS_OPS \\\n+\t/* WS ops */\t\t\t\\\n+\tuintptr_t getwrk_op;\t\t\\\n+\tuintptr_t tag_op;\t\t\\\n+\tuintptr_t wqp_op;\t\t\\\n+\tuintptr_t swtp_op;\t\t\\\n+\tuintptr_t swtag_norm_op;\t\\\n+\tuintptr_t swtag_desched_op;\t\\\n+\tuint8_t cur_tt;\t\t\t\\\n+\tuint8_t cur_grp\n+\n+/* Event port aka GWS */\n+struct otx2_ssogws {\n+\t/* Get Work Fastpath data */\n+\tOTX2_SSOGWS_OPS;\n+\tuint8_t swtag_req;\n+\tuint8_t port;\n+\t/* Add Work Fastpath data */\n+\tuint64_t xaq_lmt __rte_cache_aligned;\n+\tuint64_t *fc_mem;\n+\tuintptr_t grps_base[OTX2_SSO_MAX_VHGRP];\n+} __rte_cache_aligned;\n+\n static inline struct otx2_sso_evdev *\n sso_pmd_priv(const struct rte_eventdev *event_dev)\n {\n", "prefixes": [ "v3", "08/42" ] }