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{
    "id": 55328,
    "url": "http://patches.dpdk.org/api/patches/55328/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190625153217.24301-5-jasvinder.singh@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190625153217.24301-5-jasvinder.singh@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190625153217.24301-5-jasvinder.singh@intel.com",
    "date": "2019-06-25T15:31:53",
    "name": "[v2,04/28] sched: update port config API",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "2c7752abed57bb736d8d2c6b08f0a67a2f146148",
    "submitter": {
        "id": 285,
        "url": "http://patches.dpdk.org/api/people/285/?format=api",
        "name": "Jasvinder Singh",
        "email": "jasvinder.singh@intel.com"
    },
    "delegate": {
        "id": 10018,
        "url": "http://patches.dpdk.org/api/users/10018/?format=api",
        "username": "cristian_dumitrescu",
        "first_name": "Cristian",
        "last_name": "Dumitrescu",
        "email": "cristian.dumitrescu@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190625153217.24301-5-jasvinder.singh@intel.com/mbox/",
    "series": [
        {
            "id": 5160,
            "url": "http://patches.dpdk.org/api/series/5160/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5160",
            "date": "2019-06-25T15:31:49",
            "name": "sched: feature enhancements",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/5160/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/55328/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/55328/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6AAF81BA96;\n\tTue, 25 Jun 2019 17:32:13 +0200 (CEST)",
            "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id E1F4E1B9F6\n\tfor <dev@dpdk.org>; Tue, 25 Jun 2019 17:32:05 +0200 (CEST)",
            "from orsmga006.jf.intel.com ([10.7.209.51])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Jun 2019 08:32:05 -0700",
            "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.223.4])\n\tby orsmga006.jf.intel.com with ESMTP; 25 Jun 2019 08:32:04 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.63,416,1557212400\"; d=\"scan'208\";a=\"166711427\"",
        "From": "Jasvinder Singh <jasvinder.singh@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "cristian.dumitrescu@intel.com, Abraham Tovar <abrahamx.tovar@intel.com>, \n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>",
        "Date": "Tue, 25 Jun 2019 16:31:53 +0100",
        "Message-Id": "<20190625153217.24301-5-jasvinder.singh@intel.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190625153217.24301-1-jasvinder.singh@intel.com>",
        "References": "<20190528120553.2992-2-lukaszx.krakowiak@intel.com>\n\t<20190625153217.24301-1-jasvinder.singh@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH v2 04/28] sched: update port config API",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Update port configuration api implementation to allow\nconfiguration flexiblity for pipe traffic classes and queues,\nand subport level configuration of the pipe parameters.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Abraham Tovar <abrahamx.tovar@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n lib/librte_sched/rte_sched.c | 223 +++++++----------------------------\n 1 file changed, 41 insertions(+), 182 deletions(-)",
    "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex c81d59947..aea938899 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -366,57 +366,39 @@ pipe_profile_check(struct rte_sched_pipe_params *params,\n static int\n rte_sched_port_check_params(struct rte_sched_port_params *params)\n {\n-\tuint32_t i;\n-\n-\tif (params == NULL)\n-\t\treturn -1;\n+\tif (params == NULL) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for parameter params \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n \n \t/* socket */\n-\tif (params->socket < 0)\n-\t\treturn -3;\n+\tif (params->socket < 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for socket id \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n \n \t/* rate */\n-\tif (params->rate == 0)\n-\t\treturn -4;\n+\tif (params->rate == 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for rate \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n \n \t/* mtu */\n-\tif (params->mtu == 0)\n-\t\treturn -5;\n+\tif (params->mtu == 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for mtu \\n\", __func__);\n+\t\treturn -EINVAL;\n+\t}\n \n \t/* n_subports_per_port: non-zero, limited to 16 bits, power of 2 */\n \tif (params->n_subports_per_port == 0 ||\n-\t    params->n_subports_per_port > 1u << 16 ||\n-\t    !rte_is_power_of_2(params->n_subports_per_port))\n-\t\treturn -6;\n-\n-\t/* n_pipes_per_subport: non-zero, power of 2 */\n-\tif (params->n_pipes_per_subport == 0 ||\n-\t    !rte_is_power_of_2(params->n_pipes_per_subport))\n-\t\treturn -7;\n-\n-\t/* qsize: non-zero, power of 2,\n-\t * no bigger than 32K (due to 16-bit read/write pointers)\n-\t */\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tuint16_t qsize = params->qsize[i];\n-\n-\t\tif (qsize == 0 || !rte_is_power_of_2(qsize))\n-\t\t\treturn -8;\n-\t}\n-\n-\t/* pipe_profiles and n_pipe_profiles */\n-\tif (params->pipe_profiles == NULL ||\n-\t    params->n_pipe_profiles == 0 ||\n-\t    params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_PORT)\n-\t\treturn -9;\n-\n-\tfor (i = 0; i < params->n_pipe_profiles; i++) {\n-\t\tstruct rte_sched_pipe_params *p = params->pipe_profiles + i;\n-\t\tint status;\n-\n-\t\tstatus = pipe_profile_check(p, params->rate);\n-\t\tif (status != 0)\n-\t\t\treturn status;\n+\t    !rte_is_power_of_2(params->n_subports_per_port)) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Incorrect value for number of subports \\n\", __func__);\n+\t\treturn -EINVAL;\n \t}\n \n \treturn 0;\n@@ -502,36 +484,6 @@ rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)\n \treturn size0 + size1;\n }\n \n-static void\n-rte_sched_port_config_qsize(struct rte_sched_port *port)\n-{\n-\t/* TC 0 */\n-\tport->qsize_add[0] = 0;\n-\tport->qsize_add[1] = port->qsize_add[0] + port->qsize[0];\n-\tport->qsize_add[2] = port->qsize_add[1] + port->qsize[0];\n-\tport->qsize_add[3] = port->qsize_add[2] + port->qsize[0];\n-\n-\t/* TC 1 */\n-\tport->qsize_add[4] = port->qsize_add[3] + port->qsize[0];\n-\tport->qsize_add[5] = port->qsize_add[4] + port->qsize[1];\n-\tport->qsize_add[6] = port->qsize_add[5] + port->qsize[1];\n-\tport->qsize_add[7] = port->qsize_add[6] + port->qsize[1];\n-\n-\t/* TC 2 */\n-\tport->qsize_add[8] = port->qsize_add[7] + port->qsize[1];\n-\tport->qsize_add[9] = port->qsize_add[8] + port->qsize[2];\n-\tport->qsize_add[10] = port->qsize_add[9] + port->qsize[2];\n-\tport->qsize_add[11] = port->qsize_add[10] + port->qsize[2];\n-\n-\t/* TC 3 */\n-\tport->qsize_add[12] = port->qsize_add[11] + port->qsize[2];\n-\tport->qsize_add[13] = port->qsize_add[12] + port->qsize[3];\n-\tport->qsize_add[14] = port->qsize_add[13] + port->qsize[3];\n-\tport->qsize_add[15] = port->qsize_add[14] + port->qsize[3];\n-\n-\tport->qsize_sum = port->qsize_add[15] + port->qsize[3];\n-}\n-\n static void\n rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n {\n@@ -638,84 +590,37 @@ rte_sched_pipe_profile_convert(struct rte_sched_pipe_params *src,\n \t}\n }\n \n-static void\n-rte_sched_port_config_pipe_profile_table(struct rte_sched_port *port,\n-\tstruct rte_sched_port_params *params)\n-{\n-\tuint32_t i;\n-\n-\tfor (i = 0; i < port->n_pipe_profiles; i++) {\n-\t\tstruct rte_sched_pipe_params *src = params->pipe_profiles + i;\n-\t\tstruct rte_sched_pipe_profile *dst = port->pipe_profiles + i;\n-\n-\t\trte_sched_pipe_profile_convert(src, dst, params->rate);\n-\t\trte_sched_port_log_pipe_profile(port, i);\n-\t}\n-\n-\tport->pipe_tc3_rate_max = 0;\n-\tfor (i = 0; i < port->n_pipe_profiles; i++) {\n-\t\tstruct rte_sched_pipe_params *src = params->pipe_profiles + i;\n-\t\tuint32_t pipe_tc3_rate = src->tc_rate[3];\n-\n-\t\tif (port->pipe_tc3_rate_max < pipe_tc3_rate)\n-\t\t\tport->pipe_tc3_rate_max = pipe_tc3_rate;\n-\t}\n-}\n-\n struct rte_sched_port *\n rte_sched_port_config(struct rte_sched_port_params *params)\n {\n \tstruct rte_sched_port *port = NULL;\n-\tuint32_t mem_size, bmp_mem_size, n_queues_per_port, i, cycles_per_byte;\n+\tuint32_t size0, size1;\n+\tuint32_t cycles_per_byte;\n+\tint status;\n \n-\t/* Check user parameters. Determine the amount of memory to allocate */\n-\tmem_size = rte_sched_port_get_memory_footprint(params);\n-\tif (mem_size == 0)\n+\tstatus = rte_sched_port_check_params(params);\n+\tif (status != 0) {\n+\t\tRTE_LOG(ERR, SCHED,\n+\t\t\t\"%s: Port scheduler params check failed (%d)\\n\",\n+\t\t\t__func__, status);\n \t\treturn NULL;\n+\t}\n+\n+\tsize0 = sizeof(struct rte_sched_port);\n+\tsize1 = params->n_subports_per_port * sizeof(struct rte_sched_subport *);\n \n \t/* Allocate memory to store the data structures */\n-\tport = rte_zmalloc_socket(\"qos_params\", mem_size, RTE_CACHE_LINE_SIZE,\n-\t\tparams->socket);\n+\tport = rte_zmalloc_socket(\"qos_params\", size0 + size1,\n+\t\tRTE_CACHE_LINE_SIZE, params->socket);\n \tif (port == NULL)\n \t\treturn NULL;\n \n-\t/* compile time checks */\n-\tRTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS == 0);\n-\tRTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS & (RTE_SCHED_PORT_N_GRINDERS - 1));\n-\n \t/* User parameters */\n \tport->n_subports_per_port = params->n_subports_per_port;\n-\tport->n_pipes_per_subport = params->n_pipes_per_subport;\n-\tport->n_pipes_per_subport_log2 =\n-\t\t\t__builtin_ctz(params->n_pipes_per_subport);\n+\tport->socket = params->socket;\n \tport->rate = params->rate;\n \tport->mtu = params->mtu + params->frame_overhead;\n \tport->frame_overhead = params->frame_overhead;\n-\tmemcpy(port->qsize, params->qsize, sizeof(params->qsize));\n-\tport->n_pipe_profiles = params->n_pipe_profiles;\n-\n-#ifdef RTE_SCHED_RED\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tuint32_t j;\n-\n-\t\tfor (j = 0; j < RTE_COLORS; j++) {\n-\t\t\t/* if min/max are both zero, then RED is disabled */\n-\t\t\tif ((params->red_params[i][j].min_th |\n-\t\t\t     params->red_params[i][j].max_th) == 0) {\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\n-\t\t\tif (rte_red_config_init(&port->red_config[i][j],\n-\t\t\t\tparams->red_params[i][j].wq_log2,\n-\t\t\t\tparams->red_params[i][j].min_th,\n-\t\t\t\tparams->red_params[i][j].max_th,\n-\t\t\t\tparams->red_params[i][j].maxp_inv) != 0) {\n-\t\t\t\trte_free(port);\n-\t\t\t\treturn NULL;\n-\t\t\t}\n-\t\t}\n-\t}\n-#endif\n \n \t/* Timing */\n \tport->time_cpu_cycles = rte_get_tsc_cycles();\n@@ -726,57 +631,11 @@ rte_sched_port_config(struct rte_sched_port_params *params)\n \t\t/ params->rate;\n \tport->inv_cycles_per_byte = rte_reciprocal_value(cycles_per_byte);\n \n-\t/* Scheduling loop detection */\n-\tport->pipe_loop = RTE_SCHED_PIPE_INVALID;\n-\tport->pipe_exhaustion = 0;\n-\n-\t/* Grinders */\n-\tport->busy_grinders = 0;\n \tport->pkts_out = NULL;\n \tport->n_pkts_out = 0;\n+\tport->subport_id = 0;\n \n-\t/* Queue base calculation */\n-\trte_sched_port_config_qsize(port);\n-\n-\t/* Large data structures */\n-\tport->subport = (struct rte_sched_subport *)\n-\t\t(port->memory + rte_sched_port_get_array_base(params,\n-\t\t\t\t\t\t\t      e_RTE_SCHED_PORT_ARRAY_SUBPORT));\n-\tport->pipe = (struct rte_sched_pipe *)\n-\t\t(port->memory + rte_sched_port_get_array_base(params,\n-\t\t\t\t\t\t\t      e_RTE_SCHED_PORT_ARRAY_PIPE));\n-\tport->queue = (struct rte_sched_queue *)\n-\t\t(port->memory + rte_sched_port_get_array_base(params,\n-\t\t\t\t\t\t\t      e_RTE_SCHED_PORT_ARRAY_QUEUE));\n-\tport->queue_extra = (struct rte_sched_queue_extra *)\n-\t\t(port->memory + rte_sched_port_get_array_base(params,\n-\t\t\t\t\t\t\t      e_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA));\n-\tport->pipe_profiles = (struct rte_sched_pipe_profile *)\n-\t\t(port->memory + rte_sched_port_get_array_base(params,\n-\t\t\t\t\t\t\t      e_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES));\n-\tport->bmp_array =  port->memory\n-\t\t+ rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_BMP_ARRAY);\n-\tport->queue_array = (struct rte_mbuf **)\n-\t\t(port->memory + rte_sched_port_get_array_base(params,\n-\t\t\t\t\t\t\t      e_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY));\n-\n-\t/* Pipe profile table */\n-\trte_sched_port_config_pipe_profile_table(port, params);\n-\n-\t/* Bitmap */\n-\tn_queues_per_port = rte_sched_port_queues_per_port(port);\n-\tbmp_mem_size = rte_bitmap_get_memory_footprint(n_queues_per_port);\n-\tport->bmp = rte_bitmap_init(n_queues_per_port, port->bmp_array,\n-\t\t\t\t    bmp_mem_size);\n-\tif (port->bmp == NULL) {\n-\t\tRTE_LOG(ERR, SCHED, \"Bitmap init error\\n\");\n-\t\trte_free(port);\n-\t\treturn NULL;\n-\t}\n-\n-\tfor (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++)\n-\t\tport->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;\n-\n+\tport->max_subport_pipes_log2 = 0;\n \n \treturn port;\n }\n",
    "prefixes": [
        "v2",
        "04/28"
    ]
}