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GET /api/patches/55327/?format=api
{ "id": 55327, "url": "http://patches.dpdk.org/api/patches/55327/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190625153217.24301-4-jasvinder.singh@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190625153217.24301-4-jasvinder.singh@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190625153217.24301-4-jasvinder.singh@intel.com", "date": "2019-06-25T15:31:52", "name": "[v2,03/28] sched: update internal data structures", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "bb893e5dc0cc1a5b736db58c60c370e1724069a4", "submitter": { "id": 285, "url": "http://patches.dpdk.org/api/people/285/?format=api", "name": "Jasvinder Singh", "email": "jasvinder.singh@intel.com" }, "delegate": { "id": 10018, "url": "http://patches.dpdk.org/api/users/10018/?format=api", "username": "cristian_dumitrescu", "first_name": "Cristian", "last_name": "Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190625153217.24301-4-jasvinder.singh@intel.com/mbox/", "series": [ { "id": 5160, "url": "http://patches.dpdk.org/api/series/5160/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5160", "date": "2019-06-25T15:31:49", "name": "sched: feature enhancements", "version": 2, "mbox": "http://patches.dpdk.org/series/5160/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/55327/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/55327/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A43D11BA83;\n\tTue, 25 Jun 2019 17:32:10 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id 597EF1B9FA\n\tfor <dev@dpdk.org>; Tue, 25 Jun 2019 17:32:04 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Jun 2019 08:32:03 -0700", "from silpixa00381635.ir.intel.com (HELO\n\tsilpixa00381635.ger.corp.intel.com) ([10.237.223.4])\n\tby orsmga006.jf.intel.com with ESMTP; 25 Jun 2019 08:32:02 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.63,416,1557212400\"; d=\"scan'208\";a=\"166711415\"", "From": "Jasvinder Singh <jasvinder.singh@intel.com>", "To": "dev@dpdk.org", "Cc": "cristian.dumitrescu@intel.com, Abraham Tovar <abrahamx.tovar@intel.com>, \n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>", "Date": "Tue, 25 Jun 2019 16:31:52 +0100", "Message-Id": "<20190625153217.24301-4-jasvinder.singh@intel.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190625153217.24301-1-jasvinder.singh@intel.com>", "References": "<20190528120553.2992-2-lukaszx.krakowiak@intel.com>\n\t<20190625153217.24301-1-jasvinder.singh@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 03/28] sched: update internal data structures", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update internal data structures of the scheduler to allow configuration\nflexiblity for pipe traffic classes and queues, and subport level\nconfiguration of the pipe parameters.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Abraham Tovar <abrahamx.tovar@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n lib/librte_sched/rte_sched.c | 162 +++++++++++++++++++++++------------\n 1 file changed, 109 insertions(+), 53 deletions(-)", "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex a60ddf97e..c81d59947 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -37,6 +37,8 @@\n \n #define RTE_SCHED_TB_RATE_CONFIG_ERR (1e-7)\n #define RTE_SCHED_WRR_SHIFT 3\n+#define RTE_SCHED_MAX_QUEUES_PER_TC RTE_SCHED_BE_QUEUES_PER_PIPE\n+#define RTE_SCHED_TRAFFIC_CLASS_BE (RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE - 1)\n #define RTE_SCHED_GRINDER_PCACHE_SIZE (64 / RTE_SCHED_QUEUES_PER_PIPE)\n #define RTE_SCHED_PIPE_INVALID UINT32_MAX\n #define RTE_SCHED_BMP_POS_INVALID UINT32_MAX\n@@ -46,6 +48,52 @@\n */\n #define RTE_SCHED_TIME_SHIFT\t\t 8\n \n+enum grinder_state {\n+\te_GRINDER_PREFETCH_PIPE = 0,\n+\te_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,\n+\te_GRINDER_PREFETCH_MBUF,\n+\te_GRINDER_READ_MBUF\n+};\n+\n+struct rte_sched_grinder {\n+\t/* Pipe cache */\n+\tuint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];\n+\tuint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];\n+\tuint32_t pcache_w;\n+\tuint32_t pcache_r;\n+\n+\t/* Current pipe */\n+\tuint32_t pindex;\n+\tstruct rte_sched_pipe *pipe;\n+\tstruct rte_sched_pipe_profile *pipe_params;\n+\tstruct rte_sched_subport *subport;\n+\n+\t/* Grinder state*/\n+\tenum grinder_state state;\n+\tuint32_t productive;\n+\n+\t/* TC cache */\n+\tuint8_t tccache_qmask[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n+\tuint32_t tccache_qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n+\tuint32_t tccache_w;\n+\tuint32_t tccache_r;\n+\n+\t/* Current TC */\n+\tuint32_t tc_index;\n+\tuint32_t qpos;\n+\tstruct rte_sched_queue *queue[RTE_SCHED_MAX_QUEUES_PER_TC];\n+\tstruct rte_mbuf **qbase[RTE_SCHED_MAX_QUEUES_PER_TC];\n+\tuint32_t qindex[RTE_SCHED_MAX_QUEUES_PER_TC];\n+\tuint16_t qsize;\n+\tuint32_t qmask;\n+\tstruct rte_mbuf *pkt;\n+\n+\t/* WRR */\n+\tuint16_t wrr_tokens[RTE_SCHED_BE_QUEUES_PER_PIPE];\n+\tuint16_t wrr_mask[RTE_SCHED_BE_QUEUES_PER_PIPE];\n+\tuint8_t wrr_cost[RTE_SCHED_BE_QUEUES_PER_PIPE];\n+};\n+\n struct rte_sched_subport {\n \t/* Token bucket (TB) */\n \tuint64_t tb_time; /* time of last update */\n@@ -71,7 +119,42 @@ struct rte_sched_subport {\n \n \t/* Statistics */\n \tstruct rte_sched_subport_stats stats;\n-};\n+\n+\t/* Subport Pipes*/\n+\tuint32_t n_subport_pipes;\n+\n+\tuint16_t qsize[RTE_SCHED_QUEUES_PER_PIPE];\n+\tuint32_t n_pipe_profiles;\n+\tuint32_t n_max_pipe_profiles;\n+\tuint32_t pipe_tc_be_rate_max;\n+#ifdef RTE_SCHED_RED\n+\tstruct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];\n+#endif\n+\n+\t/* Scheduling loop detection */\n+\tuint32_t pipe_loop;\n+\tuint32_t pipe_exhaustion;\n+\n+\t/* Bitmap */\n+\tstruct rte_bitmap *bmp;\n+\tuint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;\n+\n+\t/* Grinders */\n+\tstruct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];\n+\tuint32_t busy_grinders;\n+\n+\t/* Queue base calculation */\n+\tuint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];\n+\tuint32_t qsize_sum;\n+\n+\tstruct rte_sched_pipe *pipe;\n+\tstruct rte_sched_queue *queue;\n+\tstruct rte_sched_queue_extra *queue_extra;\n+\tstruct rte_sched_pipe_profile *pipe_profiles;\n+\tuint8_t *bmp_array;\n+\tstruct rte_mbuf **queue_array;\n+\tuint8_t memory[0] __rte_cache_aligned;\n+} __rte_cache_aligned;\n \n struct rte_sched_pipe_profile {\n \t/* Token bucket (TB) */\n@@ -84,8 +167,10 @@ struct rte_sched_pipe_profile {\n \tuint32_t tc_credits_per_period[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \tuint8_t tc_ov_weight;\n \n-\t/* Pipe queues */\n-\tuint8_t wrr_cost[RTE_SCHED_QUEUES_PER_PIPE];\n+\t/* Pipe best-effort traffic class queues */\n+\tuint8_t n_be_queues;\n+\n+\tuint8_t wrr_cost[RTE_SCHED_BE_QUEUES_PER_PIPE];\n };\n \n struct rte_sched_pipe {\n@@ -100,8 +185,10 @@ struct rte_sched_pipe {\n \tuint64_t tc_time; /* time of next update */\n \tuint32_t tc_credits[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n \n+\tuint8_t n_be_queues; /* Best effort traffic class queues */\n+\n \t/* Weighted Round Robin (WRR) */\n-\tuint8_t wrr_tokens[RTE_SCHED_QUEUES_PER_PIPE];\n+\tuint8_t wrr_tokens[RTE_SCHED_BE_QUEUES_PER_PIPE];\n \n \t/* TC oversubscription */\n \tuint32_t tc_ov_credits;\n@@ -121,55 +208,12 @@ struct rte_sched_queue_extra {\n #endif\n };\n \n-enum grinder_state {\n-\te_GRINDER_PREFETCH_PIPE = 0,\n-\te_GRINDER_PREFETCH_TC_QUEUE_ARRAYS,\n-\te_GRINDER_PREFETCH_MBUF,\n-\te_GRINDER_READ_MBUF\n-};\n-\n-struct rte_sched_grinder {\n-\t/* Pipe cache */\n-\tuint16_t pcache_qmask[RTE_SCHED_GRINDER_PCACHE_SIZE];\n-\tuint32_t pcache_qindex[RTE_SCHED_GRINDER_PCACHE_SIZE];\n-\tuint32_t pcache_w;\n-\tuint32_t pcache_r;\n-\n-\t/* Current pipe */\n-\tenum grinder_state state;\n-\tuint32_t productive;\n-\tuint32_t pindex;\n-\tstruct rte_sched_subport *subport;\n-\tstruct rte_sched_pipe *pipe;\n-\tstruct rte_sched_pipe_profile *pipe_params;\n-\n-\t/* TC cache */\n-\tuint8_t tccache_qmask[4];\n-\tuint32_t tccache_qindex[4];\n-\tuint32_t tccache_w;\n-\tuint32_t tccache_r;\n-\n-\t/* Current TC */\n-\tuint32_t tc_index;\n-\tstruct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tstruct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tuint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tuint16_t qsize;\n-\tuint32_t qmask;\n-\tuint32_t qpos;\n-\tstruct rte_mbuf *pkt;\n-\n-\t/* WRR */\n-\tuint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-\tuint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-\tuint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-};\n-\n struct rte_sched_port {\n \t/* User parameters */\n \tuint32_t n_subports_per_port;\n \tuint32_t n_pipes_per_subport;\n \tuint32_t n_pipes_per_subport_log2;\n+\tint socket;\n \tuint32_t rate;\n \tuint32_t mtu;\n \tuint32_t frame_overhead;\n@@ -199,6 +243,9 @@ struct rte_sched_port {\n \tuint32_t busy_grinders;\n \tstruct rte_mbuf **pkts_out;\n \tuint32_t n_pkts_out;\n+\tuint32_t subport_id;\n+\n+\tuint32_t max_subport_pipes_log2; /* Max number of subport pipes */\n \n \t/* Queue base calculation */\n \tuint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];\n@@ -212,6 +259,7 @@ struct rte_sched_port {\n \tstruct rte_sched_pipe_profile *pipe_profiles;\n \tuint8_t *bmp_array;\n \tstruct rte_mbuf **queue_array;\n+\tstruct rte_sched_subport *subports[0];\n \tuint8_t memory[0] __rte_cache_aligned;\n } __rte_cache_aligned;\n \n@@ -226,6 +274,16 @@ enum rte_sched_port_array {\n \te_RTE_SCHED_PORT_ARRAY_TOTAL,\n };\n \n+enum rte_sched_subport_array {\n+\te_RTE_SCHED_SUBPORT_ARRAY_PIPE = 0,\n+\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE,\n+\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE_EXTRA,\n+\te_RTE_SCHED_SUBPORT_ARRAY_PIPE_PROFILES,\n+\te_RTE_SCHED_SUBPORT_ARRAY_BMP_ARRAY,\n+\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE_ARRAY,\n+\te_RTE_SCHED_SUBPORT_ARRAY_TOTAL,\n+};\n+\n #ifdef RTE_SCHED_COLLECT_STATS\n \n static inline uint32_t\n@@ -483,7 +541,7 @@ rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n \t\t\" Token bucket: period = %u, credits per period = %u, size = %u\\n\"\n \t\t\" Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\\n\"\n \t\t\" Traffic class 3 oversubscription: weight = %hhu\\n\"\n-\t\t\" WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu]\\n\",\n+\t\t\" WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu],\\n\",\n \t\ti,\n \n \t\t/* Token bucket */\n@@ -502,10 +560,8 @@ rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n \t\tp->tc_ov_weight,\n \n \t\t/* WRR */\n-\t\tp->wrr_cost[ 0], p->wrr_cost[ 1], p->wrr_cost[ 2], p->wrr_cost[ 3],\n-\t\tp->wrr_cost[ 4], p->wrr_cost[ 5], p->wrr_cost[ 6], p->wrr_cost[ 7],\n-\t\tp->wrr_cost[ 8], p->wrr_cost[ 9], p->wrr_cost[10], p->wrr_cost[11],\n-\t\tp->wrr_cost[12], p->wrr_cost[13], p->wrr_cost[14], p->wrr_cost[15]);\n+\t\tp->wrr_cost[0], p->wrr_cost[1], p->wrr_cost[2], p->wrr_cost[3],\n+\t\tp->wrr_cost[4], p->wrr_cost[5], p->wrr_cost[6], p->wrr_cost[7]);\n }\n \n static inline uint64_t\n", "prefixes": [ "v2", "03/28" ] }