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GET /api/patches/54896/?format=api
{ "id": 54896, "url": "http://patches.dpdk.org/api/patches/54896/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1560841489-77908-2-git-send-email-beilei.xing@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1560841489-77908-2-git-send-email-beilei.xing@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1560841489-77908-2-git-send-email-beilei.xing@intel.com", "date": "2019-06-18T07:04:48", "name": "[v3,1/2] net/ice: support Tx checksum offload for tunneling packets", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "732d2ce234e8d41dcfcd787f4b98a8ed5a51f639", "submitter": { "id": 410, "url": "http://patches.dpdk.org/api/people/410/?format=api", "name": "Xing, Beilei", "email": "beilei.xing@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1560841489-77908-2-git-send-email-beilei.xing@intel.com/mbox/", "series": [ { "id": 5046, "url": "http://patches.dpdk.org/api/series/5046/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=5046", "date": "2019-06-18T07:04:47", "name": "net/ice: support Tx checksum offload", "version": 3, "mbox": "http://patches.dpdk.org/series/5046/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54896/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54896/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0E49B1C0B3;\n\tTue, 18 Jun 2019 09:07:08 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby dpdk.org (Postfix) with ESMTP id 4C3D31BF4B\n\tfor <dev@dpdk.org>; Tue, 18 Jun 2019 09:07:04 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t18 Jun 2019 00:07:03 -0700", "from unknown (HELO dpdk9.sh.intel.com) ([10.67.118.52])\n\tby fmsmga008.fm.intel.com with ESMTP; 18 Jun 2019 00:07:02 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Beilei Xing <beilei.xing@intel.com>", "To": "qi.z.zhang@intel.com,\n\tjohn.mcnamara@intel.com", "Cc": "dev@dpdk.org", "Date": "Tue, 18 Jun 2019 15:04:48 +0800", "Message-Id": "<1560841489-77908-2-git-send-email-beilei.xing@intel.com>", "X-Mailer": "git-send-email 2.5.5", "In-Reply-To": "<1560841489-77908-1-git-send-email-beilei.xing@intel.com>", "References": "<1560827647-59239-1-git-send-email-beilei.xing@intel.com>\n\t<1560841489-77908-1-git-send-email-beilei.xing@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 1/2] net/ice: support Tx checksum offload for\n\ttunneling packets", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Enable Tx checksum offload for tunneling packets by\nconfiguring tunneling parameters in Tx descriptors,\nincluding outer L3/L4 checksum offload.\n\nSigned-off-by: Beilei Xing <beilei.xing@intel.com>\n---\n drivers/net/ice/ice_ethdev.c | 3 +-\n drivers/net/ice/ice_rxtx.c | 78 +++++++++++++++++++++++++++++++++++++++++---\n 2 files changed, 76 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 19fbbc3..b6a473f 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -2051,7 +2051,8 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\n \t\t\tDEV_TX_OFFLOAD_TCP_CKSUM |\n \t\t\tDEV_TX_OFFLOAD_SCTP_CKSUM |\n-\t\t\tDEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;\n+\t\t\tDEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |\n+\t\t\tDEV_TX_OFFLOAD_OUTER_UDP_CKSUM;\n \t\tdev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;\n \t}\n \ndiff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c\nindex 620a5ea..7ff3ff8 100644\n--- a/drivers/net/ice/ice_rxtx.c\n+++ b/drivers/net/ice/ice_rxtx.c\n@@ -1742,14 +1742,71 @@ ice_recv_pkts(void *rx_queue,\n }\n \n static inline void\n+ice_parse_tunneling_params(uint64_t ol_flags,\n+\t\t\t union ice_tx_offload tx_offload,\n+\t\t\t uint32_t *cd_tunneling)\n+{\n+\t/* EIPT: External (outer) IP header type */\n+\tif (ol_flags & PKT_TX_OUTER_IP_CKSUM)\n+\t\t*cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;\n+\telse if (ol_flags & PKT_TX_OUTER_IPV4)\n+\t\t*cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;\n+\telse if (ol_flags & PKT_TX_OUTER_IPV6)\n+\t\t*cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;\n+\n+\t/* EIPLEN: External (outer) IP header length, in DWords */\n+\t*cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<\n+\t\tICE_TXD_CTX_QW0_EIPLEN_S;\n+\n+\t/* L4TUNT: L4 Tunneling Type */\n+\tswitch (ol_flags & PKT_TX_TUNNEL_MASK) {\n+\tcase PKT_TX_TUNNEL_IPIP:\n+\t\t/* for non UDP / GRE tunneling, set to 00b */\n+\t\tbreak;\n+\tcase PKT_TX_TUNNEL_VXLAN:\n+\tcase PKT_TX_TUNNEL_GENEVE:\n+\t\t*cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;\n+\t\tbreak;\n+\tcase PKT_TX_TUNNEL_GRE:\n+\t\t*cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;\n+\t\tbreak;\n+\tdefault:\n+\t\tPMD_TX_LOG(ERR, \"Tunnel type not supported\");\n+\t\treturn;\n+\t}\n+\n+\t/* L4TUNLEN: L4 Tunneling Length, in Words\n+\t *\n+\t * We depend on app to set rte_mbuf.l2_len correctly.\n+\t * For IP in GRE it should be set to the length of the GRE\n+\t * header;\n+\t * For MAC in GRE or MAC in UDP it should be set to the length\n+\t * of the GRE or UDP headers plus the inner MAC up to including\n+\t * its last Ethertype.\n+\t * If MPLS labels exists, it should include them as well.\n+\t */\n+\t*cd_tunneling |= (tx_offload.l2_len >> 1) <<\n+\t\tICE_TXD_CTX_QW0_NATLEN_S;\n+\n+\tif ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&\n+\t (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&\n+\t (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))\n+\t\t*cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;\n+}\n+\n+static inline void\n ice_txd_enable_checksum(uint64_t ol_flags,\n \t\t\tuint32_t *td_cmd,\n \t\t\tuint32_t *td_offset,\n \t\t\tunion ice_tx_offload tx_offload)\n {\n-\t/* L2 length must be set. */\n-\t*td_offset |= (tx_offload.l2_len >> 1) <<\n-\t\t ICE_TX_DESC_LEN_MACLEN_S;\n+\t/* Set MACLEN */\n+\tif (ol_flags & PKT_TX_TUNNEL_MASK)\n+\t\t*td_offset |= (tx_offload.outer_l2_len >> 1)\n+\t\t\t<< ICE_TX_DESC_LEN_MACLEN_S;\n+\telse\n+\t\t*td_offset |= (tx_offload.l2_len >> 1)\n+\t\t\t<< ICE_TX_DESC_LEN_MACLEN_S;\n \n \t/* Enable L3 checksum offloads */\n \tif (ol_flags & PKT_TX_IP_CKSUM) {\n@@ -1863,7 +1920,10 @@ ice_build_ctob(uint32_t td_cmd,\n static inline uint16_t\n ice_calc_context_desc(uint64_t flags)\n {\n-\tstatic uint64_t mask = PKT_TX_TCP_SEG | PKT_TX_QINQ;\n+\tstatic uint64_t mask = PKT_TX_TCP_SEG |\n+\t\tPKT_TX_QINQ |\n+\t\tPKT_TX_OUTER_IP_CKSUM |\n+\t\tPKT_TX_TUNNEL_MASK;\n \n \treturn (flags & mask) ? 1 : 0;\n }\n@@ -1909,6 +1969,7 @@ ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \tstruct ice_tx_entry *txe, *txn;\n \tstruct rte_mbuf *tx_pkt;\n \tstruct rte_mbuf *m_seg;\n+\tuint32_t cd_tunneling_params;\n \tuint16_t tx_id;\n \tuint16_t nb_tx;\n \tuint16_t nb_used;\n@@ -1979,6 +2040,12 @@ ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\t\ttd_tag = tx_pkt->vlan_tci;\n \t\t}\n \n+\t\t/* Fill in tunneling parameters if necessary */\n+\t\tcd_tunneling_params = 0;\n+\t\tif (ol_flags & PKT_TX_TUNNEL_MASK)\n+\t\t\tice_parse_tunneling_params(ol_flags, tx_offload,\n+\t\t\t\t\t\t &cd_tunneling_params);\n+\n \t\t/* Enable checksum offloading */\n \t\tif (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {\n \t\t\tice_txd_enable_checksum(ol_flags, &td_cmd,\n@@ -2004,6 +2071,9 @@ ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\t\t\tcd_type_cmd_tso_mss |=\n \t\t\t\t\tice_set_tso_ctx(tx_pkt, tx_offload);\n \n+\t\t\tctx_txd->tunneling_params =\n+\t\t\t\trte_cpu_to_le_32(cd_tunneling_params);\n+\n \t\t\t/* TX context descriptor based double VLAN insert */\n \t\t\tif (ol_flags & PKT_TX_QINQ) {\n \t\t\t\tcd_l2tag2 = tx_pkt->vlan_tci_outer;\n", "prefixes": [ "v3", "1/2" ] }