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GET /api/patches/54156/?format=api
{ "id": 54156, "url": "http://patches.dpdk.org/api/patches/54156/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190603103429.814-2-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190603103429.814-2-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190603103429.814-2-pbhagavatula@marvell.com", "date": "2019-06-03T10:34:23", "name": "[v2,1/6] event/octeontx2: add event eth Rx adapter support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "443d024409523f0ab9890ed13454f80acd04123d", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190603103429.814-2-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4861, "url": "http://patches.dpdk.org/api/series/4861/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4861", "date": "2019-06-03T10:34:22", "name": "event/octeontx2: add Rx/Tx adapter support", "version": 2, "mbox": "http://patches.dpdk.org/series/4861/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54156/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54156/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C5A9D1B94E;\n\tMon, 3 Jun 2019 12:34:36 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id D80D01B945\n\tfor <dev@dpdk.org>; Mon, 3 Jun 2019 12:34:35 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx53AUGSP023399 for <dev@dpdk.org>; Mon, 3 Jun 2019 03:34:35 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk7nv7-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Mon, 03 Jun 2019 03:34:35 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tMon, 3 Jun 2019 03:34:33 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Mon, 3 Jun 2019 03:34:33 -0700", "from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.20.231])\n\tby maili.marvell.com (Postfix) with ESMTP id 628B03F703F;\n\tMon, 3 Jun 2019 03:34:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=Ziqk6vDvOEzcpdVu5ZLOZgx/3WHyaxh4PqDQpYBGeGY=;\n\tb=Cx3RoGjO0HLys6NQl2aH6nc/G7dTs7kdrKmv/15ip86mOR9Zm6ZjqS74TMchZKe1WFKZ\n\tmA2ivs26qI+Ehice0Wor058MaCTk0DvlRO9A881j+Cq5Eu0IMVHefq/sTa/9/GtoO69R\n\tLV++94d3N1hZPQuPRbvXCQk4TDfwigt7XJrlXnTVsQSBPfdOkU/7VxmtraSHL/bJ91Ld\n\tM4xpdcZUrPWyxyGBSJIgH0gqaIIpzki9htA0MA3bNDLrjhlbga4uijm1AOCAQJuH3WDz\n\tvSZHHIYAP7YStxCZNoS+3exez9ULjEteFld++j8SuM4bvl0vtss2eDiZdmT/5dfqk+0z\n\tbg== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Mon, 3 Jun 2019 16:04:23 +0530", "Message-ID": "<20190603103429.814-2-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190603103429.814-1-pbhagavatula@marvell.com>", "References": "<20190603103429.814-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-03_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v2 1/6] event/octeontx2: add event eth Rx adapter\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd event eth Rx adapter capabilities, queue add and delete functions.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n drivers/event/octeontx2/Makefile | 4 +-\n drivers/event/octeontx2/meson.build | 2 +-\n drivers/event/octeontx2/otx2_evdev.c | 4 +\n drivers/event/octeontx2/otx2_evdev.h | 15 ++\n drivers/event/octeontx2/otx2_evdev_adptr.c | 254 +++++++++++++++++++++\n 5 files changed, 276 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile\nindex d01da6b11..20d7c2fee 100644\n--- a/drivers/event/octeontx2/Makefile\n+++ b/drivers/event/octeontx2/Makefile\n@@ -40,7 +40,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_selftest.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev_irq.c\n \n LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci -lrte_kvargs\n-LDLIBS += -lrte_mempool -lrte_eventdev -lrte_mbuf\n-LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2\n+LDLIBS += -lrte_mempool -lrte_eventdev -lrte_mbuf -lrte_ethdev\n+LDLIBS += -lrte_common_octeontx2 -lrte_mempool_octeontx2 -lrte_pmd_octeontx2\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build\nindex bdb5beed6..e94bc5944 100644\n--- a/drivers/event/octeontx2/meson.build\n+++ b/drivers/event/octeontx2/meson.build\n@@ -26,4 +26,4 @@ foreach flag: extra_flags\n \tendif\n endforeach\n \n-deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2']\n+deps += ['bus_pci', 'common_octeontx2', 'mempool_octeontx2', 'pmd_octeontx2']\ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nindex 534ac4a6b..2ddc007f3 100644\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -1118,6 +1118,10 @@ static struct rte_eventdev_ops otx2_sso_ops = {\n \t.port_unlink = otx2_sso_port_unlink,\n \t.timeout_ticks = otx2_sso_timeout_ticks,\n \n+\t.eth_rx_adapter_caps_get = otx2_sso_rx_adapter_caps_get,\n+\t.eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,\n+\t.eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,\n+\n \t.timer_adapter_caps_get = otx2_tim_caps_get,\n \n \t.xstats_get = otx2_sso_xstats_get,\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nindex eeb65f03f..d1e99b9d9 100644\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -6,9 +6,12 @@\n #define __OTX2_EVDEV_H__\n \n #include <rte_eventdev.h>\n+#include <rte_eventdev_pmd.h>\n+#include <rte_event_eth_rx_adapter.h>\n \n #include \"otx2_common.h\"\n #include \"otx2_dev.h\"\n+#include \"otx2_ethdev.h\"\n #include \"otx2_mempool.h\"\n \n #define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev\n@@ -234,6 +237,18 @@ void sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data,\n \t\t uint32_t event_type);\n int sso_xae_reconfigure(struct rte_eventdev *event_dev);\n void sso_fastpath_fns_set(struct rte_eventdev *event_dev);\n+\n+int otx2_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,\n+\t\t\t\t const struct rte_eth_dev *eth_dev,\n+\t\t\t\t uint32_t *caps);\n+int otx2_sso_rx_adapter_queue_add(const struct rte_eventdev *event_dev,\n+\t\t\t\t const struct rte_eth_dev *eth_dev,\n+\t\t\t\t int32_t rx_queue_id,\n+\t\tconst struct rte_event_eth_rx_adapter_queue_conf *queue_conf);\n+int otx2_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n+\t\t\t\t const struct rte_eth_dev *eth_dev,\n+\t\t\t\t int32_t rx_queue_id);\n+\n /* Clean up API's */\n typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev);\n void ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id,\ndiff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c\nindex 810722f89..1aef864fe 100644\n--- a/drivers/event/octeontx2/otx2_evdev_adptr.c\n+++ b/drivers/event/octeontx2/otx2_evdev_adptr.c\n@@ -4,6 +4,197 @@\n \n #include \"otx2_evdev.h\"\n \n+int\n+otx2_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,\n+\t\t\t const struct rte_eth_dev *eth_dev, uint32_t *caps)\n+{\n+\tint rc;\n+\n+\tRTE_SET_USED(event_dev);\n+\trc = strncmp(eth_dev->device->driver->name, \"net_octeontx2\", 13);\n+\tif (rc)\n+\t\t*caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;\n+\telse\n+\t\t*caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT;\n+\n+\treturn 0;\n+}\n+\n+static inline int\n+sso_rxq_enable(struct otx2_eth_dev *dev, uint16_t qid, uint8_t tt, uint8_t ggrp,\n+\t uint16_t eth_port_id)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_aq_enq_req *aq;\n+\tint rc;\n+\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = qid;\n+\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\taq->cq.ena = 0;\n+\taq->cq.caching = 0;\n+\n+\totx2_mbox_memset(&aq->cq_mask, 0, sizeof(struct nix_cq_ctx_s));\n+\taq->cq_mask.ena = ~(aq->cq_mask.ena);\n+\taq->cq_mask.caching = ~(aq->cq_mask.caching);\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc < 0) {\n+\t\totx2_err(\"failed to disable cq context\");\n+\t\tgoto fail;\n+\t}\n+\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = qid;\n+\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\taq->rq.sso_ena = 1;\n+\taq->rq.sso_tt = tt;\n+\taq->rq.sso_grp = ggrp;\n+\taq->rq.ena_wqwd = 1;\n+\t/* Mbuf Header generation :\n+\t * > FIRST_SKIP is a super set of WQE_SKIP, dont modify first skip as\n+\t * it already has data related to mbuf size, headroom, private area.\n+\t * > Using WQE_SKIP we can directly assign\n+\t *\t\tmbuf = wqe - sizeof(struct mbuf);\n+\t * so that mbuf header will not have unpredicted values while headroom\n+\t * and private data starts at the begining of wqe_data.\n+\t */\n+\taq->rq.wqe_skip = 1;\n+\taq->rq.wqe_caching = 1;\n+\taq->rq.spb_ena = 0;\n+\taq->rq.flow_tagw = 20; /* 20-bits */\n+\n+\t/* Flow Tag calculation :\n+\t *\n+\t * rq_tag <31:24> = good/bad_tag<8:0>;\n+\t * rq_tag <23:0> = [ltag]\n+\t *\n+\t * flow_tag_mask<31:0> = (1 << flow_tagw) - 1; <31:20>\n+\t * tag<31:0> = (~flow_tag_mask & rq_tag) | (flow_tag_mask & flow_tag);\n+\t *\n+\t * Setup :\n+\t * ltag<23:0> = (eth_port_id & 0xF) << 20;\n+\t * good/bad_tag<8:0> =\n+\t *\t((eth_port_id >> 4) & 0xF) | (RTE_EVENT_TYPE_ETHDEV << 4);\n+\t *\n+\t * TAG<31:0> on getwork = <31:28>(RTE_EVENT_TYPE_ETHDEV) |\n+\t *\t\t\t\t<27:20> (eth_port_id) | <20:0> [TAG]\n+\t */\n+\n+\taq->rq.ltag = (eth_port_id & 0xF) << 20;\n+\taq->rq.good_utag = ((eth_port_id >> 4) & 0xF) |\n+\t\t\t\t(RTE_EVENT_TYPE_ETHDEV << 4);\n+\taq->rq.bad_utag = aq->rq.good_utag;\n+\n+\taq->rq.ena = 1;\n+\taq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */\n+\taq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */\n+\n+\totx2_mbox_memset(&aq->rq_mask, 0, sizeof(struct nix_rq_ctx_s));\n+\t/* mask the bits to write. */\n+\taq->rq_mask.sso_ena = ~(aq->rq_mask.sso_ena);\n+\taq->rq_mask.sso_tt = ~(aq->rq_mask.sso_tt);\n+\taq->rq_mask.sso_grp = ~(aq->rq_mask.sso_grp);\n+\taq->rq_mask.ena_wqwd = ~(aq->rq_mask.ena_wqwd);\n+\taq->rq_mask.wqe_skip = ~(aq->rq_mask.wqe_skip);\n+\taq->rq_mask.wqe_caching = ~(aq->rq_mask.wqe_caching);\n+\taq->rq_mask.spb_ena = ~(aq->rq_mask.spb_ena);\n+\taq->rq_mask.flow_tagw = ~(aq->rq_mask.flow_tagw);\n+\taq->rq_mask.ltag = ~(aq->rq_mask.ltag);\n+\taq->rq_mask.good_utag = ~(aq->rq_mask.good_utag);\n+\taq->rq_mask.bad_utag = ~(aq->rq_mask.bad_utag);\n+\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n+\taq->rq_mask.pb_caching = ~(aq->rq_mask.pb_caching);\n+\taq->rq_mask.xqe_imm_size = ~(aq->rq_mask.xqe_imm_size);\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc < 0) {\n+\t\totx2_err(\"failed to init rx adapter context\");\n+\t\tgoto fail;\n+\t}\n+\n+\treturn 0;\n+fail:\n+\treturn rc;\n+}\n+\n+static inline int\n+sso_rxq_disable(struct otx2_eth_dev *dev, uint16_t qid)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_aq_enq_req *aq;\n+\tint rc;\n+\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = qid;\n+\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\taq->op = NIX_AQ_INSTOP_INIT;\n+\n+\taq->cq.ena = 1;\n+\taq->cq.caching = 1;\n+\n+\totx2_mbox_memset(&aq->cq_mask, 0, sizeof(struct nix_cq_ctx_s));\n+\taq->cq_mask.ena = ~(aq->cq_mask.ena);\n+\taq->cq_mask.caching = ~(aq->cq_mask.caching);\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc < 0) {\n+\t\totx2_err(\"failed to init cq context\");\n+\t\tgoto fail;\n+\t}\n+\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = qid;\n+\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\taq->rq.sso_ena = 0;\n+\taq->rq.sso_tt = SSO_TT_UNTAGGED;\n+\taq->rq.sso_grp = 0;\n+\taq->rq.ena_wqwd = 0;\n+\taq->rq.wqe_caching = 0;\n+\taq->rq.wqe_skip = 0;\n+\taq->rq.spb_ena = 0;\n+\taq->rq.flow_tagw = 0x20;\n+\taq->rq.ltag = 0;\n+\taq->rq.good_utag = 0;\n+\taq->rq.bad_utag = 0;\n+\taq->rq.ena = 1;\n+\taq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */\n+\taq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */\n+\n+\totx2_mbox_memset(&aq->rq_mask, 0, sizeof(struct nix_rq_ctx_s));\n+\t/* mask the bits to write. */\n+\taq->rq_mask.sso_ena = ~(aq->rq_mask.sso_ena);\n+\taq->rq_mask.sso_tt = ~(aq->rq_mask.sso_tt);\n+\taq->rq_mask.sso_grp = ~(aq->rq_mask.sso_grp);\n+\taq->rq_mask.ena_wqwd = ~(aq->rq_mask.ena_wqwd);\n+\taq->rq_mask.wqe_caching = ~(aq->rq_mask.wqe_caching);\n+\taq->rq_mask.wqe_skip = ~(aq->rq_mask.wqe_skip);\n+\taq->rq_mask.spb_ena = ~(aq->rq_mask.spb_ena);\n+\taq->rq_mask.flow_tagw = ~(aq->rq_mask.flow_tagw);\n+\taq->rq_mask.ltag = ~(aq->rq_mask.ltag);\n+\taq->rq_mask.good_utag = ~(aq->rq_mask.good_utag);\n+\taq->rq_mask.bad_utag = ~(aq->rq_mask.bad_utag);\n+\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n+\taq->rq_mask.pb_caching = ~(aq->rq_mask.pb_caching);\n+\taq->rq_mask.xqe_imm_size = ~(aq->rq_mask.xqe_imm_size);\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc < 0) {\n+\t\totx2_err(\"failed to clear rx adapter context\");\n+\t\tgoto fail;\n+\t}\n+\n+\treturn 0;\n+fail:\n+\treturn rc;\n+}\n+\n void\n sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data, uint32_t event_type)\n {\n@@ -17,3 +208,66 @@ sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data, uint32_t event_type)\n \t\tbreak;\n \t}\n }\n+\n+int\n+otx2_sso_rx_adapter_queue_add(const struct rte_eventdev *event_dev,\n+\t\t\t const struct rte_eth_dev *eth_dev,\n+\t\t\t int32_t rx_queue_id,\n+\t\tconst struct rte_event_eth_rx_adapter_queue_conf *queue_conf)\n+{\n+\tstruct otx2_eth_dev *otx2_eth_dev = eth_dev->data->dev_private;\n+\tuint16_t port = eth_dev->data->port_id;\n+\tint i, rc;\n+\n+\tRTE_SET_USED(event_dev);\n+\trc = strncmp(eth_dev->device->driver->name, \"net_octeontx2\", 13);\n+\tif (rc)\n+\t\treturn -EINVAL;\n+\n+\tif (rx_queue_id < 0) {\n+\t\tfor (i = 0 ; i < eth_dev->data->nb_rx_queues; i++) {\n+\t\t\trc |= sso_rxq_enable(otx2_eth_dev, i,\n+\t\t\t\t\t queue_conf->ev.sched_type,\n+\t\t\t\t\t queue_conf->ev.queue_id, port);\n+\t\t}\n+\t} else {\n+\t\trc |= sso_rxq_enable(otx2_eth_dev, (uint16_t)rx_queue_id,\n+\t\t\t\t queue_conf->ev.sched_type,\n+\t\t\t\t queue_conf->ev.queue_id, port);\n+\t}\n+\n+\tif (rc < 0) {\n+\t\totx2_err(\"Failed to configure Rx adapter port=%d, q=%d\", port,\n+\t\t\t queue_conf->ev.queue_id);\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n+\t\t\t const struct rte_eth_dev *eth_dev,\n+\t\t\t int32_t rx_queue_id)\n+{\n+\tstruct otx2_eth_dev *dev = eth_dev->data->dev_private;\n+\tint i, rc;\n+\n+\tRTE_SET_USED(event_dev);\n+\trc = strncmp(eth_dev->device->driver->name, \"net_octeontx2\", 13);\n+\tif (rc)\n+\t\treturn -EINVAL;\n+\n+\tif (rx_queue_id < 0) {\n+\t\tfor (i = 0 ; i < eth_dev->data->nb_rx_queues; i++)\n+\t\t\trc = sso_rxq_disable(dev, i);\n+\t} else {\n+\t\trc = sso_rxq_disable(dev, (uint16_t)rx_queue_id);\n+\t}\n+\n+\tif (rc < 0)\n+\t\totx2_err(\"Failed to clear Rx adapter config port=%d, q=%d\",\n+\t\t\t eth_dev->data->port_id, rx_queue_id);\n+\n+\treturn rc;\n+}\n", "prefixes": [ "v2", "1/6" ] }