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GET /api/patches/54127/?format=api
{ "id": 54127, "url": "http://patches.dpdk.org/api/patches/54127/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602174247.32368-12-lance.richardson@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602174247.32368-12-lance.richardson@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602174247.32368-12-lance.richardson@broadcom.com", "date": "2019-06-02T17:42:46", "name": "[11/11] net/bnxt: enable RSS for thor-based adapters", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "501702296974309ffeff71d4b57c920ea2e37022", "submitter": { "id": 1323, "url": "http://patches.dpdk.org/api/people/1323/?format=api", "name": "Lance Richardson", "email": "lance.richardson@broadcom.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602174247.32368-12-lance.richardson@broadcom.com/mbox/", "series": [ { "id": 4850, "url": "http://patches.dpdk.org/api/series/4850/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4850", "date": "2019-06-02T17:42:35", "name": "add support for BCM57508 controller", "version": 1, "mbox": "http://patches.dpdk.org/series/4850/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54127/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54127/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4644F1B9C3;\n\tSun, 2 Jun 2019 19:43:29 +0200 (CEST)", "from mail-yb1-f193.google.com (mail-yb1-f193.google.com\n\t[209.85.219.193]) by dpdk.org (Postfix) with ESMTP id E02FC1B95A\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 19:43:13 +0200 (CEST)", "by mail-yb1-f193.google.com with SMTP id x32so3192958ybh.1\n\tfor <dev@dpdk.org>; Sun, 02 Jun 2019 10:43:13 -0700 (PDT)", "from lrichardson-VirtualBox.attlocal.net\n\t(69-218-223-106.lightspeed.rlghnc.sbcglobal.net. [69.218.223.106])\n\tby smtp.gmail.com with ESMTPSA id\n\tn78sm1000819ywd.2.2019.06.02.10.43.11\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 02 Jun 2019 10:43:12 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com;\n\ts=google; \n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=mFjP71NsU32VqyB6f1FJ7rzfR/Zj2vAjEgkhXzIKnyE=;\n\tb=RHL72NQLMZZ/6WYZuG7uxSyTbm92F9wuevwRqJQf+S2+T4yjy3b7ULkIEKHd6fKanW\n\ttNYNz5yvy4rI7CycN6VQOuB4AdJ/b1FyY8R/OwGOXOM4vfktd7nzbv8F5SezS0ym7mCS\n\tUMLdF1gIAvUh94Zt4+UBEcF+9+0sRuXJr/jQE=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=mFjP71NsU32VqyB6f1FJ7rzfR/Zj2vAjEgkhXzIKnyE=;\n\tb=mpYKUQc3z79J5cxGok+hkBIpB19Q1I8nWNugih472KBqImEPd9KXZIsLFCxcQC3yaE\n\txSIBxvOs82b0ibC7PJVFfIXJqAGlIJuUWc5luxGFTY8jqmtuzgT2pG5Y9UE76yTdAph/\n\t1Od85ImSml9Vd782zH5vOGIPiRTtAFW/x1bONsOXRYeI9ytbFdQtED64Axrx59irkGEX\n\t86ru3nVTRBpItBl+NI7IyZJP9REeGw1eTe1WOPYM5lTMUMQ9lREDhmoytDuVEwQHk95y\n\tTJY/hFSTK5vYOg1hH7AWFsZeKrDPl1O28nSxPsLtTh8KOyIJzNQSvJVn2kaV2vySZORZ\n\tIaQA==", "X-Gm-Message-State": "APjAAAVX1IZVBH9CjCX5bUXFxHb9ZwwE5USSHJ9MBRdhLH0XEUCA4het\n\tpm5L+DuCx3/CEjJko3dbpcCKxFCRJdiFDRRRll2LElktnOdK94uayoTaZaPTqI9kCd+GQEQmI4Q\n\tC6jMaJZmsi9dBQVn2zy0UatE3h2yIB1uXD5YchPypIUAOt+1WcV/UIH6Rf2PGQIZv", "X-Google-Smtp-Source": "APXvYqwuqmA0qVRCXGsyg2N9fF2NzjRV0L/3BuYP7mubd7vaH7n+nBNioHEXQX8qigKbiGj7hY6mVQ==", "X-Received": "by 2002:a25:e656:: with SMTP id\n\td83mr10657366ybh.178.1559497392803; \n\tSun, 02 Jun 2019 10:43:12 -0700 (PDT)", "From": "Lance Richardson <lance.richardson@broadcom.com>", "To": "dev@dpdk.org", "Cc": "ajit.khaparde@broadcom.com, ferruh.yigit@intel.com,\n\tLance Richardson <lance.richardson@broadcom.com>", "Date": "Sun, 2 Jun 2019 13:42:46 -0400", "Message-Id": "<20190602174247.32368-12-lance.richardson@broadcom.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190602174247.32368-1-lance.richardson@broadcom.com>", "References": "<20190602174247.32368-1-lance.richardson@broadcom.com>", "Subject": "[dpdk-dev] [PATCH 11/11] net/bnxt: enable RSS for thor-based\n\tadapters", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Enable rss support for thor-based adapters.\n\nSigned-off-by: Lance Richardson <lance.richardson@broadcom.com>\nReviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt_ethdev.c | 69 ++++++++++--\n drivers/net/bnxt/bnxt_hwrm.c | 190 +++++++++++++++++++++++++++------\n drivers/net/bnxt/bnxt_hwrm.h | 6 +-\n drivers/net/bnxt/bnxt_vnic.c | 15 ++-\n drivers/net/bnxt/bnxt_vnic.h | 1 +\n 5 files changed, 235 insertions(+), 46 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c\nindex d26066062..749763c25 100644\n--- a/drivers/net/bnxt/bnxt_ethdev.c\n+++ b/drivers/net/bnxt/bnxt_ethdev.c\n@@ -171,6 +171,24 @@ static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);\n * High level utility functions\n */\n \n+static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)\n+{\n+\tif (!BNXT_CHIP_THOR(bp))\n+\t\treturn 1;\n+\n+\treturn RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,\n+\t\t\t\t BNXT_RSS_ENTRIES_PER_CTX_THOR) /\n+\t\t\t\t BNXT_RSS_ENTRIES_PER_CTX_THOR;\n+}\n+\n+static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)\n+{\n+\tif (!BNXT_CHIP_THOR(bp))\n+\t\treturn HW_HASH_INDEX_SIZE;\n+\n+\treturn bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;\n+}\n+\n static void bnxt_free_mem(struct bnxt *bp)\n {\n \tbnxt_free_filter_mem(bp);\n@@ -290,13 +308,21 @@ static int bnxt_init_chip(struct bnxt *bp)\n \n \t\t/* Alloc RSS context only if RSS mode is enabled */\n \t\tif (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {\n-\t\t\trc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);\n+\t\t\tint j, nr_ctxs = bnxt_rss_ctxts(bp);\n+\n+\t\t\trc = 0;\n+\t\t\tfor (j = 0; j < nr_ctxs; j++) {\n+\t\t\t\trc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);\n+\t\t\t\tif (rc)\n+\t\t\t\t\tbreak;\n+\t\t\t}\n \t\t\tif (rc) {\n \t\t\t\tPMD_DRV_LOG(ERR,\n-\t\t\t\t\t\"HWRM vnic %d ctx alloc failure rc: %x\\n\",\n-\t\t\t\t\ti, rc);\n+\t\t\t\t \"HWRM vnic %d ctx %d alloc failure rc: %x\\n\",\n+\t\t\t\t i, j, rc);\n \t\t\t\tgoto err_out;\n \t\t\t}\n+\t\t\tvnic->num_lb_ctxts = nr_ctxs;\n \t\t}\n \n \t\t/*\n@@ -470,7 +496,7 @@ static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,\n \t/* For the sake of symmetry, max_rx_queues = max_tx_queues */\n \tdev_info->max_rx_queues = max_rx_rings;\n \tdev_info->max_tx_queues = max_rx_rings;\n-\tdev_info->reta_size = HW_HASH_INDEX_SIZE;\n+\tdev_info->reta_size = bnxt_rss_hash_tbl_size(bp);\n \tdev_info->hash_key_size = 40;\n \tmax_vnics = bp->max_vnics;\n \n@@ -1004,11 +1030,20 @@ static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)\n /* Return rxq corresponding to a given rss table ring/group ID. */\n static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)\n {\n+\tstruct bnxt_rx_queue *rxq;\n \tunsigned int i;\n \n-\tfor (i = 0; i < bp->rx_nr_rings; i++) {\n-\t\tif (bp->grp_info[i].fw_grp_id == fwr)\n-\t\t\treturn i;\n+\tif (!BNXT_HAS_RING_GRPS(bp)) {\n+\t\tfor (i = 0; i < bp->rx_nr_rings; i++) {\n+\t\t\trxq = bp->eth_dev->data->rx_queues[i];\n+\t\t\tif (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)\n+\t\t\t\treturn rxq->index;\n+\t\t}\n+\t} else {\n+\t\tfor (i = 0; i < bp->rx_nr_rings; i++) {\n+\t\t\tif (bp->grp_info[i].fw_grp_id == fwr)\n+\t\t\t\treturn i;\n+\t\t}\n \t}\n \n \treturn INVALID_HW_RING_ID;\n@@ -1021,7 +1056,7 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,\n \tstruct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;\n \tstruct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;\n \tstruct bnxt_vnic_info *vnic = &bp->vnic_info[0];\n-\tuint16_t tbl_size = HW_HASH_INDEX_SIZE;\n+\tuint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);\n \tuint16_t idx, sft;\n \tint i;\n \n@@ -1053,6 +1088,16 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,\n \t\t\treturn -EINVAL;\n \t\t}\n \n+\t\tif (BNXT_CHIP_THOR(bp)) {\n+\t\t\tvnic->rss_table[i * 2] =\n+\t\t\t\trxq->rx_ring->rx_ring_struct->fw_ring_id;\n+\t\t\tvnic->rss_table[i * 2 + 1] =\n+\t\t\t\trxq->cp_ring->cp_ring_struct->fw_ring_id;\n+\t\t} else {\n+\t\t\tvnic->rss_table[i] =\n+\t\t\t vnic->fw_grp_ids[reta_conf[idx].reta[sft]];\n+\t\t}\n+\n \t\tvnic->rss_table[i] =\n \t\t vnic->fw_grp_ids[reta_conf[idx].reta[sft]];\n \t}\n@@ -1067,7 +1112,7 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,\n {\n \tstruct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;\n \tstruct bnxt_vnic_info *vnic = &bp->vnic_info[0];\n-\tuint16_t tbl_size = HW_HASH_INDEX_SIZE;\n+\tuint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);\n \tuint16_t idx, sft, i;\n \n \t/* Retrieve from the default VNIC */\n@@ -1090,7 +1135,11 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,\n \t\tif (reta_conf[idx].mask & (1ULL << sft)) {\n \t\t\tuint16_t qid;\n \n-\t\t\tqid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);\n+\t\t\tif (BNXT_CHIP_THOR(bp))\n+\t\t\t\tqid = bnxt_rss_to_qid(bp,\n+\t\t\t\t\t\t vnic->rss_table[i * 2]);\n+\t\t\telse\n+\t\t\t\tqid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);\n \n \t\t\tif (qid == INVALID_HW_RING_ID) {\n \t\t\t\tPMD_DRV_LOG(ERR, \"Inv. entry in rss table.\\n\");\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c\nindex f5b7e4593..a4c879b35 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.c\n+++ b/drivers/net/bnxt/bnxt_hwrm.c\n@@ -1638,9 +1638,11 @@ int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,\n \treturn rc;\n }\n \n-int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n+int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,\n+\t\t\t struct bnxt_vnic_info *vnic, uint16_t ctx_idx)\n {\n \tint rc = 0;\n+\tuint16_t ctx_id;\n \tstruct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };\n \tstruct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =\n \t\t\t\t\t\tbp->hwrm_cmd_resp_addr;\n@@ -1648,38 +1650,40 @@ int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \tHWRM_PREP(req, VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n-\n \tHWRM_CHECK_RESULT();\n \n-\tvnic->rss_rule = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);\n+\tctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);\n+\tif (!BNXT_HAS_RING_GRPS(bp))\n+\t\tvnic->fw_grp_ids[ctx_idx] = ctx_id;\n+\telse if (ctx_idx == 0)\n+\t\tvnic->rss_rule = ctx_id;\n+\n \tHWRM_UNLOCK();\n-\tPMD_DRV_LOG(DEBUG, \"VNIC RSS Rule %x\\n\", vnic->rss_rule);\n \n \treturn rc;\n }\n \n-int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n+int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,\n+\t\t\t struct bnxt_vnic_info *vnic, uint16_t ctx_idx)\n {\n \tint rc = 0;\n \tstruct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };\n \tstruct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =\n \t\t\t\t\t\tbp->hwrm_cmd_resp_addr;\n \n-\tif (vnic->rss_rule == (uint16_t)HWRM_NA_SIGNATURE) {\n+\tif (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {\n \t\tPMD_DRV_LOG(DEBUG, \"VNIC RSS Rule %x\\n\", vnic->rss_rule);\n \t\treturn rc;\n \t}\n \tHWRM_PREP(req, VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);\n \n-\treq.rss_cos_lb_ctx_id = rte_cpu_to_le_16(vnic->rss_rule);\n+\treq.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);\n \n \trc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);\n \n \tHWRM_CHECK_RESULT();\n \tHWRM_UNLOCK();\n \n-\tvnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;\n-\n \treturn rc;\n }\n \n@@ -1711,6 +1715,47 @@ int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n \treturn rc;\n }\n \n+static int\n+bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n+{\n+\tint i;\n+\tint rc = 0;\n+\tint nr_ctxs = bp->max_ring_grps;\n+\tstruct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };\n+\tstruct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n+\n+\tif (!(vnic->rss_table && vnic->hash_type))\n+\t\treturn 0;\n+\n+\tHWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n+\n+\treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n+\treq.hash_type = rte_cpu_to_le_32(vnic->hash_type);\n+\treq.hash_mode_flags = vnic->hash_mode;\n+\n+\treq.hash_key_tbl_addr =\n+\t rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);\n+\n+\tfor (i = 0; i < nr_ctxs; i++) {\n+\t\treq.ring_grp_tbl_addr =\n+\t\t\trte_cpu_to_le_64(vnic->rss_table_dma_addr +\n+\t\t\t\t\t i * HW_HASH_INDEX_SIZE);\n+\t\treq.ring_table_pair_index = i;\n+\t\treq.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);\n+\n+\t\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req),\n+\t\t\t\t\t BNXT_USE_CHIMP_MB);\n+\n+\t\tHWRM_CHECK_RESULT();\n+\t\tif (rc)\n+\t\t\tbreak;\n+\t}\n+\n+\tHWRM_UNLOCK();\n+\n+\treturn rc;\n+}\n+\n int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,\n \t\t\t struct bnxt_vnic_info *vnic)\n {\n@@ -1718,6 +1763,9 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,\n \tstruct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };\n \tstruct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n \n+\tif (BNXT_CHIP_THOR(bp))\n+\t\treturn bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);\n+\n \tHWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n \n \treq.hash_type = rte_cpu_to_le_32(vnic->hash_type);\n@@ -2247,7 +2295,7 @@ void bnxt_free_tunnel_ports(struct bnxt *bp)\n \n void bnxt_free_all_hwrm_resources(struct bnxt *bp)\n {\n-\tint i;\n+\tint i, j;\n \n \tif (bp->vnic_info == NULL)\n \t\treturn;\n@@ -2263,7 +2311,16 @@ void bnxt_free_all_hwrm_resources(struct bnxt *bp)\n \n \t\tbnxt_clear_hwrm_vnic_filters(bp, vnic);\n \n-\t\tbnxt_hwrm_vnic_ctx_free(bp, vnic);\n+\t\tif (!BNXT_CHIP_THOR(bp)) {\n+\t\t\tfor (j = 0; j < vnic->num_lb_ctxts; j++) {\n+\t\t\t\tbnxt_hwrm_vnic_ctx_free(bp, vnic,\n+\t\t\t\t\t\t\tvnic->fw_grp_ids[j]);\n+\t\t\t\tvnic->fw_grp_ids[j] = INVALID_HW_RING_ID;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tbnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);\n+\t\t\tvnic->rss_rule = INVALID_HW_RING_ID;\n+\t\t}\n \n \t\tbnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);\n \n@@ -4037,32 +4094,105 @@ int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,\n \treturn 0;\n }\n \n-int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n+static int\n+bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n {\n-\tunsigned int rss_idx, fw_idx, i;\n+\tstruct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;\n+\tuint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;\n+\tstruct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };\n+\tint nr_ctxs = bp->max_ring_grps;\n+\tstruct bnxt_rx_queue **rxqs = bp->rx_queues;\n+\tuint16_t *ring_tbl = vnic->rss_table;\n+\tint max_rings = bp->rx_nr_rings;\n+\tint i, j, k, cnt;\n+\tint rc = 0;\n \n-\tif (vnic->rss_table && vnic->hash_type) {\n-\t\t/*\n-\t\t * Fill the RSS hash & redirection table with\n-\t\t * ring group ids for all VNICs\n-\t\t */\n-\t\tfor (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;\n-\t\t\trss_idx++, fw_idx++) {\n-\t\t\tfor (i = 0; i < bp->rx_cp_nr_rings; i++) {\n-\t\t\t\tfw_idx %= bp->rx_cp_nr_rings;\n-\t\t\t\tif (vnic->fw_grp_ids[fw_idx] !=\n-\t\t\t\t INVALID_HW_RING_ID)\n+\tHWRM_PREP(req, VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);\n+\n+\treq.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);\n+\treq.hash_type = rte_cpu_to_le_32(vnic->hash_type);\n+\treq.hash_mode_flags = vnic->hash_mode;\n+\n+\treq.ring_grp_tbl_addr =\n+\t rte_cpu_to_le_64(vnic->rss_table_dma_addr);\n+\treq.hash_key_tbl_addr =\n+\t rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);\n+\n+\tfor (i = 0, k = 0; i < nr_ctxs; i++) {\n+\t\tstruct bnxt_rx_ring_info *rxr;\n+\t\tstruct bnxt_cp_ring_info *cpr;\n+\n+\t\treq.ring_table_pair_index = i;\n+\t\treq.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);\n+\n+\t\tfor (j = 0; j < 64; j++) {\n+\t\t\tuint16_t ring_id;\n+\n+\t\t\t/* Find next active ring. */\n+\t\t\tfor (cnt = 0; cnt < max_rings; cnt++) {\n+\t\t\t\tif (rx_queue_state[k] !=\n+\t\t\t\t\t\tRTE_ETH_QUEUE_STATE_STOPPED)\n \t\t\t\t\tbreak;\n-\t\t\t\tfw_idx++;\n+\t\t\t\tif (++k == max_rings)\n+\t\t\t\t\tk = 0;\n \t\t\t}\n-\t\t\tif (i == bp->rx_cp_nr_rings)\n+\n+\t\t\t/* Return if no rings are active. */\n+\t\t\tif (cnt == max_rings)\n \t\t\t\treturn 0;\n-\t\t\tvnic->rss_table[rss_idx] =\n-\t\t\t\tvnic->fw_grp_ids[fw_idx];\n+\n+\t\t\t/* Add rx/cp ring pair to RSS table. */\n+\t\t\trxr = rxqs[k]->rx_ring;\n+\t\t\tcpr = rxqs[k]->cp_ring;\n+\n+\t\t\tring_id = rxr->rx_ring_struct->fw_ring_id;\n+\t\t\t*ring_tbl++ = rte_cpu_to_le_16(ring_id);\n+\t\t\tring_id = cpr->cp_ring_struct->fw_ring_id;\n+\t\t\t*ring_tbl++ = rte_cpu_to_le_16(ring_id);\n+\n+\t\t\tif (++k == max_rings)\n+\t\t\t\tk = 0;\n \t\t}\n-\t\treturn bnxt_hwrm_vnic_rss_cfg(bp, vnic);\n+\t\trc = bnxt_hwrm_send_message(bp, &req, sizeof(req),\n+\t\t\t\t\t BNXT_USE_CHIMP_MB);\n+\n+\t\tHWRM_CHECK_RESULT();\n+\t\tif (rc)\n+\t\t\tbreak;\n \t}\n-\treturn 0;\n+\n+\tHWRM_UNLOCK();\n+\n+\treturn rc;\n+}\n+\n+int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)\n+{\n+\tunsigned int rss_idx, fw_idx, i;\n+\n+\tif (!(vnic->rss_table && vnic->hash_type))\n+\t\treturn 0;\n+\n+\tif (BNXT_CHIP_THOR(bp))\n+\t\treturn bnxt_vnic_rss_configure_thor(bp, vnic);\n+\n+\t/*\n+\t * Fill the RSS hash & redirection table with\n+\t * ring group ids for all VNICs\n+\t */\n+\tfor (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;\n+\t\trss_idx++, fw_idx++) {\n+\t\tfor (i = 0; i < bp->rx_cp_nr_rings; i++) {\n+\t\t\tfw_idx %= bp->rx_cp_nr_rings;\n+\t\t\tif (vnic->fw_grp_ids[fw_idx] != INVALID_HW_RING_ID)\n+\t\t\t\tbreak;\n+\t\t\tfw_idx++;\n+\t\t}\n+\t\tif (i == bp->rx_cp_nr_rings)\n+\t\t\treturn 0;\n+\t\tvnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];\n+\t}\n+\treturn bnxt_hwrm_vnic_rss_cfg(bp, vnic);\n }\n \n static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,\ndiff --git a/drivers/net/bnxt/bnxt_hwrm.h b/drivers/net/bnxt/bnxt_hwrm.h\nindex ffd99de34..f286bcd8b 100644\n--- a/drivers/net/bnxt/bnxt_hwrm.h\n+++ b/drivers/net/bnxt/bnxt_hwrm.h\n@@ -101,8 +101,10 @@ int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic);\n int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic);\n int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,\n \t\t\t\tint16_t fw_vf_id);\n-int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic);\n-int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic);\n+int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic,\n+\t\t\t uint16_t ctx_idx);\n+int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic,\n+\t\t\t uint16_t ctx_idx);\n int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic);\n int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,\n \t\t\t struct bnxt_vnic_info *vnic);\ndiff --git a/drivers/net/bnxt/bnxt_vnic.c b/drivers/net/bnxt/bnxt_vnic.c\nindex 2cf5f0b5b..262cfc18d 100644\n--- a/drivers/net/bnxt/bnxt_vnic.c\n+++ b/drivers/net/bnxt/bnxt_vnic.c\n@@ -113,14 +113,21 @@ int bnxt_alloc_vnic_attributes(struct bnxt *bp)\n \tstruct rte_pci_device *pdev = bp->pdev;\n \tconst struct rte_memzone *mz;\n \tchar mz_name[RTE_MEMZONE_NAMESIZE];\n-\tuint32_t entry_length = RTE_CACHE_LINE_ROUNDUP(\n-\t\t\t\tHW_HASH_INDEX_SIZE * sizeof(*vnic->rss_table) +\n-\t\t\t\tHW_HASH_KEY_SIZE +\n-\t\t\t\tBNXT_MAX_MC_ADDRS * RTE_ETHER_ADDR_LEN);\n+\tuint32_t entry_length;\n \tuint16_t max_vnics;\n \tint i;\n \trte_iova_t mz_phys_addr;\n \n+\tentry_length = HW_HASH_KEY_SIZE +\n+\t\t BNXT_MAX_MC_ADDRS * RTE_ETHER_ADDR_LEN;\n+\n+\tif (BNXT_CHIP_THOR(bp))\n+\t\tentry_length += BNXT_RSS_TBL_SIZE_THOR *\n+\t\t\t\t2 * sizeof(*vnic->rss_table);\n+\telse\n+\t\tentry_length += HW_HASH_INDEX_SIZE * sizeof(*vnic->rss_table);\n+\tentry_length = RTE_CACHE_LINE_ROUNDUP(entry_length);\n+\n \tmax_vnics = bp->max_vnics;\n \tsnprintf(mz_name, RTE_MEMZONE_NAMESIZE,\n \t\t \"bnxt_%04x:%02x:%02x:%02x_vnicattr\", pdev->addr.domain,\ndiff --git a/drivers/net/bnxt/bnxt_vnic.h b/drivers/net/bnxt/bnxt_vnic.h\nindex 9029f78c3..16a0d5763 100644\n--- a/drivers/net/bnxt/bnxt_vnic.h\n+++ b/drivers/net/bnxt/bnxt_vnic.h\n@@ -18,6 +18,7 @@ struct bnxt_vnic_info {\n \tuint16_t\tstart_grp_id;\n \tuint16_t\tend_grp_id;\n \tuint16_t\t*fw_grp_ids;\n+\tuint16_t\tnum_lb_ctxts;\n \tuint16_t\tdflt_ring_grp;\n \tuint16_t\tmru;\n \tuint16_t\thash_type;\n", "prefixes": [ "11/11" ] }