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GET /api/patches/54105/?format=api
{ "id": 54105, "url": "http://patches.dpdk.org/api/patches/54105/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-32-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-32-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-32-jerinj@marvell.com", "date": "2019-06-02T15:24:07", "name": "[v1,31/58] net/octeontx2: add PTP base support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4d87214c78056ba845f88322f615fe2346c95518", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-32-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54105/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54105/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id AF8B71B9EC;\n\tSun, 2 Jun 2019 17:26:17 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id E76D21BAB9\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:26:12 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FJjgP021271; Sun, 2 Jun 2019 08:26:12 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2supqkvqhy-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:26:12 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:26:11 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:26:11 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 512973F7041;\n\tSun, 2 Jun 2019 08:26:09 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=fkRWhlPJul17g2hVf8eNFQhQV944MB+bCYH4DXwTpbQ=;\n\tb=Ssk75/ZYkkY7bpExIa2V50W8EkfvIfCYctCsUQJqSaPgqW4yeS/5+0GybK1JC9zi9dfl\n\tPr4ZGiav4YMb7CPqO22IY8K7RJ9epYdAJFLnQ+1BthDgs7jA/J32tu3Lj8FRlgU/ydTt\n\tFrOwr5WhyGUetr6RdArBQMUpNb9oo/boqDnZhDe6QSAfOy/3OK4sMtk/tE87jRZu6eOq\n\tquGG9+DnTAphK/S35SZaTU/Gldz7Et8zbCbmFzHqrswWzDwSex8rsQWpDSigvLyzzHQe\n\tWM0NI00LcJjt9WvUOgPpTFSAngVmQYg7K/Aq0biUKvpffOMXn3C61y6KPKgRIbWPGZQ8\n\tgw== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>, Harman Kalra <hkalra@marvell.com>, Zyta Szpak\n\t<zyta@marvell.com>", "Date": "Sun, 2 Jun 2019 20:54:07 +0530", "Message-ID": "<20190602152434.23996-32-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 31/58] net/octeontx2: add PTP base support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Harman Kalra <hkalra@marvell.com>\n\nAdd PTP enable and disable operations.\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\nSigned-off-by: Zyta Szpak <zyta@marvell.com>\n---\n drivers/net/octeontx2/Makefile | 1 +\n drivers/net/octeontx2/meson.build | 1 +\n drivers/net/octeontx2/otx2_ethdev.c | 22 ++++-\n drivers/net/octeontx2/otx2_ethdev.h | 17 ++++\n drivers/net/octeontx2/otx2_ptp.c | 135 ++++++++++++++++++++++++++++\n drivers/net/octeontx2/otx2_rx.h | 11 +++\n 6 files changed, 184 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/octeontx2/otx2_ptp.c", "diff": "diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex 1d3788466..b1c8e4e52 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -33,6 +33,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n \totx2_tm.c\t\\\n \totx2_rss.c\t\\\n \totx2_mac.c\t\\\n+\totx2_ptp.c\t\\\n \totx2_link.c\t\\\n \totx2_stats.c\t\\\n \totx2_lookup.c\t\\\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex e4fcac763..57d6c0a58 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -6,6 +6,7 @@ sources = files(\n \t\t'otx2_tm.c',\n \t\t'otx2_rss.c',\n \t\t'otx2_mac.c',\n+\t\t'otx2_ptp.c',\n \t\t'otx2_link.c',\n \t\t'otx2_stats.c',\n \t\t'otx2_lookup.c',\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 97e0e3465..683aecd4e 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -336,9 +336,7 @@ nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)\n static inline int\n nix_get_data_off(struct otx2_eth_dev *dev)\n {\n-\tRTE_SET_USED(dev);\n-\n-\treturn 0;\n+\treturn otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;\n }\n \n uint64_t\n@@ -450,6 +448,7 @@ otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,\n \trxq->qlen = nix_qsize_to_val(qsize);\n \trxq->qsize = qsize;\n \trxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();\n+\trxq->tstamp = &dev->tstamp;\n \n \t/* Alloc completion queue */\n \trc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);\n@@ -716,6 +715,7 @@ otx2_nix_form_default_desc(struct otx2_eth_txq *txq)\n \t\t\tsend_mem->dsz = 0x0;\n \t\t\tsend_mem->wmem = 0x1;\n \t\t\tsend_mem->alg = NIX_SENDMEMALG_SETTSTMP;\n+\t\t\tsend_mem->addr = txq->dev->tstamp.tx_tstamp_iova;\n \t\t}\n \t\tsg = (union nix_send_sg_s *)&txq->cmd[4];\n \t} else {\n@@ -1137,6 +1137,16 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto free_nix_lf;\n \t}\n \n+\t/* Enable PTP if it was requested by the app or if it is already\n+\t * enabled in PF owning this VF\n+\t */\n+\tmemset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));\n+\tif ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||\n+\t otx2_ethdev_is_ptp_en(dev))\n+\t\totx2_nix_timesync_enable(eth_dev);\n+\telse\n+\t\totx2_nix_timesync_disable(eth_dev);\n+\n \t/*\n \t * Restore queue config when reconfigure followed by\n \t * reconfigure and no queue configure invoked from application case.\n@@ -1317,6 +1327,8 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.get_module_eeprom = otx2_nix_get_module_eeprom,\n \t.flow_ctrl_get = otx2_nix_flow_ctrl_get,\n \t.flow_ctrl_set = otx2_nix_flow_ctrl_set,\n+\t.timesync_enable = otx2_nix_timesync_enable,\n+\t.timesync_disable = otx2_nix_timesync_disable,\n };\n \n static inline int\n@@ -1521,6 +1533,10 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n \t/* Disable nix bpid config */\n \totx2_nix_rxchan_bpid_cfg(eth_dev, false);\n \n+\t/* Disable PTP if already enabled */\n+\tif (otx2_ethdev_is_ptp_en(dev))\n+\t\totx2_nix_timesync_disable(eth_dev);\n+\n \t/* Free up SQs */\n \tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n \t\totx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex fad151b54..809a9656f 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -13,6 +13,7 @@\n #include <rte_mbuf.h>\n #include <rte_mempool.h>\n #include <rte_string_fns.h>\n+#include <rte_time.h>\n \n #include \"otx2_common.h\"\n #include \"otx2_dev.h\"\n@@ -109,6 +110,12 @@\n #define NIX_DEFAULT_RSS_CTX_GROUP 0\n #define NIX_DEFAULT_RSS_MCAM_IDX -1\n \n+#define otx2_ethdev_is_ptp_en(dev)\t((dev)->ptp_en)\n+\n+#define NIX_TIMESYNC_TX_CMD_LEN\t\t8\n+/* Additional timesync values. */\n+#define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL\n+\n enum nix_q_size_e {\n \tnix_q_size_16,\t/* 16 entries */\n \tnix_q_size_64,\t/* 64 entries */\n@@ -214,6 +221,12 @@ struct otx2_eth_dev {\n \tstruct otx2_eth_qconf *tx_qconf;\n \tstruct otx2_eth_qconf *rx_qconf;\n \tstruct rte_eth_dev *eth_dev;\n+\t/* PTP counters */\n+\tbool ptp_en;\n+\tstruct otx2_timesync_info tstamp;\n+\tstruct rte_timecounter systime_tc;\n+\tstruct rte_timecounter rx_tstamp_tc;\n+\tstruct rte_timecounter tx_tstamp_tc;\n } __rte_cache_aligned;\n \n struct otx2_eth_txq {\n@@ -396,4 +409,8 @@ int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,\n /* Rx and Tx routines */\n void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);\n \n+/* Timesync - PTP routines */\n+int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);\n+int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);\n+\n #endif /* __OTX2_ETHDEV_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_ptp.c b/drivers/net/octeontx2/otx2_ptp.c\nnew file mode 100644\nindex 000000000..105067949\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_ptp.c\n@@ -0,0 +1,135 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_ethdev_driver.h>\n+\n+#include \"otx2_ethdev.h\"\n+\n+#define PTP_FREQ_ADJUST (1 << 9)\n+\n+static void\n+nix_start_timecounters(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\n+\tmemset(&dev->systime_tc, 0, sizeof(struct rte_timecounter));\n+\tmemset(&dev->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n+\tmemset(&dev->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n+\n+\tdev->systime_tc.cc_mask = OTX2_CYCLECOUNTER_MASK;\n+\tdev->rx_tstamp_tc.cc_mask = OTX2_CYCLECOUNTER_MASK;\n+\tdev->tx_tstamp_tc.cc_mask = OTX2_CYCLECOUNTER_MASK;\n+}\n+\n+static int\n+nix_ptp_config(struct rte_eth_dev *eth_dev, int en)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tuint8_t rc = 0;\n+\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn rc;\n+\n+\tif (en) {\n+\t\t/* Enable time stamping of sent PTP packets. */\n+\t\totx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(mbox);\n+\t\trc = otx2_mbox_process(mbox);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"MBOX ptp tx conf enable failed: err %d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t\t/* Enable time stamping of received PTP packets. */\n+\t\totx2_mbox_alloc_msg_cgx_ptp_rx_enable(mbox);\n+\t} else {\n+\t\t/* Disable time stamping of sent PTP packets. */\n+\t\totx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(mbox);\n+\t\trc = otx2_mbox_process(mbox);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"MBOX ptp tx conf disable failed: err %d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t\t/* Disable time stamping of received PTP packets. */\n+\t\totx2_mbox_alloc_msg_cgx_ptp_rx_disable(mbox);\n+\t}\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n+int\n+otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint i, rc = 0;\n+\n+\tif (otx2_ethdev_is_ptp_en(dev)) {\n+\t\totx2_info(\"PTP mode is already enabled \");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* If we are VF, no further action can be taken */\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn -EINVAL;\n+\n+\tif (!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)) {\n+\t\totx2_err(\"Ptype offload is disabled, it should be enabled\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Allocating a iova address for tx tstamp */\n+\tconst struct rte_memzone *ts;\n+\tts = rte_eth_dma_zone_reserve(eth_dev, \"otx2_ts\",\n+\t\t\t\t 0, OTX2_ALIGN, OTX2_ALIGN,\n+\t\t\t\t dev->node);\n+\tif (ts == NULL)\n+\t\totx2_err(\"Failed to allocate mem for tx tstamp addr\");\n+\n+\tdev->tstamp.tx_tstamp_iova = ts->iova;\n+\tdev->tstamp.tx_tstamp = ts->addr;\n+\n+\t/* System time should be already on by default */\n+\tnix_start_timecounters(eth_dev);\n+\n+\tdev->rx_offloads |= DEV_RX_OFFLOAD_TIMESTAMP;\n+\tdev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;\n+\tdev->tx_offload_flags |= NIX_TX_OFFLOAD_TSTAMP_F;\n+\n+\trc = nix_ptp_config(eth_dev, 1);\n+\tif (!rc) {\n+\t\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\t\tstruct otx2_eth_txq *txq = eth_dev->data->tx_queues[i];\n+\t\t\totx2_nix_form_default_desc(txq);\n+\t\t}\n+\t}\n+\treturn rc;\n+}\n+\n+int\n+otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint i, rc = 0;\n+\n+\tif (!otx2_ethdev_is_ptp_en(dev)) {\n+\t\totx2_nix_dbg(\"PTP mode is disabled\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* If we are VF, nothing else can be done */\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn -EINVAL;\n+\n+\tdev->rx_offloads &= ~DEV_RX_OFFLOAD_TIMESTAMP;\n+\tdev->rx_offload_flags &= ~NIX_RX_OFFLOAD_TSTAMP_F;\n+\tdev->tx_offload_flags &= ~NIX_TX_OFFLOAD_TSTAMP_F;\n+\n+\trc = nix_ptp_config(eth_dev, 0);\n+\tif (!rc) {\n+\t\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\t\tstruct otx2_eth_txq *txq = eth_dev->data->tx_queues[i];\n+\t\t\totx2_nix_form_default_desc(txq);\n+\t\t}\n+\t}\n+\treturn rc;\n+}\ndiff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h\nindex 1283fdf37..0c3627c12 100644\n--- a/drivers/net/octeontx2/otx2_rx.h\n+++ b/drivers/net/octeontx2/otx2_rx.h\n@@ -13,5 +13,16 @@\n \t\t\t\t\t sizeof(uint16_t))\n \n #define NIX_RX_OFFLOAD_PTYPE_F BIT(1)\n+#define NIX_RX_OFFLOAD_TSTAMP_F BIT(5)\n+\n+#define NIX_TIMESYNC_RX_OFFSET\t\t8\n+\n+struct otx2_timesync_info {\n+\tuint64_t\trx_tstamp;\n+\trte_iova_t\ttx_tstamp_iova;\n+\tuint64_t\t*tx_tstamp;\n+\tuint8_t\t\ttx_ready;\n+\tuint8_t\t\trx_ready;\n+} __rte_cache_aligned;\n \n #endif /* __OTX2_RX_H__ */\n", "prefixes": [ "v1", "31/58" ] }