Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/54074/?format=api
{ "id": 54074, "url": "http://patches.dpdk.org/api/patches/54074/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-19-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-19-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-19-jerinj@marvell.com", "date": "2019-06-02T15:23:54", "name": "[v1,18/58] net/octeontx2: add Tx queue setup and release", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "71d2e6ef52ddb63aebc8ac38b3ae69ce7303eed3", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-19-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54074/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54074/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5B4221B9D8;\n\tSun, 2 Jun 2019 17:25:35 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 1D4111B9D6\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:25:34 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FK6kH020260; Sun, 2 Jun 2019 08:25:33 -0700", "from sc-exch04.marvell.com ([199.233.58.184])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk493x-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:33 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com\n\t(10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:31 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:31 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 64EE63F703F;\n\tSun, 2 Jun 2019 08:25:30 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=NIRJZTqLLxDVmnZmwKdvWlIMgJUFvP0VT1WkL3ywm0k=;\n\tb=Mzmk0/6+7GIg/BLLeOWZTRESwxwYZJbsphEaevDva3zRbaxJ+c3z6HhKFKM28Q2aONZ7\n\tfANyOZP0rFjpMVR/311wccCoubuYhqyXyUwKgQIvas4e2bVpBphIgKi3UX7DzpjBfTja\n\tJRkrCgF1aPcqL8usr8KAC/UG6d+xiHtRZYYgU2FtRLey0OaTykVAdbITFRjQCrorfabd\n\tvP7W6fb5mnhondUjRsnwY/AlVhOo2azrCcq8BjIxOSxKz0+HRPztrIJO1vEcp5n7nOVw\n\tO7l9O1U3VkOL+5knUl1D0iW9CWeIsSsJm9+QhUiSqfAnlLH5U0dVgjAHwRV7wEolo1gi\n\tfQ== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>", "Date": "Sun, 2 Jun 2019 20:53:54 +0530", "Message-ID": "<20190602152434.23996-19-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 18/58] net/octeontx2: add Tx queue setup and\n\trelease", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd Tx queue setup and release.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/octeontx2/otx2_ethdev.c | 384 +++++++++++++++++++++++++++-\n drivers/net/octeontx2/otx2_ethdev.h | 24 ++\n drivers/net/octeontx2/otx2_tx.h | 28 ++\n 3 files changed, 435 insertions(+), 1 deletion(-)\n create mode 100644 drivers/net/octeontx2/otx2_tx.h", "diff": "diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex dbbc2263d..b501ba865 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -422,6 +422,372 @@ otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,\n \treturn rc;\n }\n \n+static inline uint8_t\n+nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)\n+{\n+\t/*\n+\t * Maximum three segments can be supported with W8, Choose\n+\t * NIX_MAXSQESZ_W16 for multi segment offload.\n+\t */\n+\tif (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)\n+\t\treturn NIX_MAXSQESZ_W16;\n+\telse\n+\t\treturn NIX_MAXSQESZ_W8;\n+}\n+\n+static int\n+nix_sq_init(struct otx2_eth_txq *txq)\n+{\n+\tstruct otx2_eth_dev *dev = txq->dev;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_aq_enq_req *sq;\n+\n+\tif (txq->sqb_pool->pool_id == 0)\n+\t\treturn -EINVAL;\n+\n+\tsq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\tsq->qidx = txq->sq;\n+\tsq->ctype = NIX_AQ_CTYPE_SQ;\n+\tsq->op = NIX_AQ_INSTOP_INIT;\n+\tsq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);\n+\n+\tsq->sq.default_chan = dev->tx_chan_base;\n+\tsq->sq.sqe_stype = NIX_STYPE_STF;\n+\tsq->sq.ena = 1;\n+\tif (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)\n+\t\tsq->sq.sqe_stype = NIX_STYPE_STP;\n+\tsq->sq.sqb_aura =\n+\t\tnpa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);\n+\tsq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);\n+\tsq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);\n+\tsq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);\n+\tsq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);\n+\n+\t/* Many to one reduction */\n+\tsq->sq.qint_idx = txq->sq % dev->qints;\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n+static int\n+nix_sq_uninit(struct otx2_eth_txq *txq)\n+{\n+\tstruct otx2_eth_dev *dev = txq->dev;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct ndc_sync_op *ndc_req;\n+\tstruct nix_aq_enq_rsp *rsp;\n+\tstruct nix_aq_enq_req *aq;\n+\tuint16_t sqes_per_sqb;\n+\tvoid *sqb_buf;\n+\tint rc, count;\n+\n+\totx2_nix_dbg(\"Cleaning up sq %u\", txq->sq);\n+\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = txq->sq;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_READ;\n+\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Check if sq is already cleaned up */\n+\tif (!rsp->sq.ena)\n+\t\treturn 0;\n+\n+\t/* Disable sq */\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = txq->sq;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\taq->sq_mask.ena = ~aq->sq_mask.ena;\n+\taq->sq.ena = 0;\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Read SQ and free sqb's */\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = txq->sq;\n+\taq->ctype = NIX_AQ_CTYPE_SQ;\n+\taq->op = NIX_AQ_INSTOP_READ;\n+\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (aq->sq.smq_pend)\n+\t\trte_panic(\"otx2: sq has pending sqe's\");\n+\n+\tcount = aq->sq.sqb_count;\n+\tsqes_per_sqb = 1 << txq->sqes_per_sqb_log2;\n+\t/* Free SQB's that are used */\n+\tsqb_buf = (void *)rsp->sq.head_sqb;\n+\twhile (count) {\n+\t\tvoid *next_sqb;\n+\n+\t\tnext_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *\n+\t\t\t\t nix_sq_max_sqe_sz(txq)));\n+\t\tnpa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,\n+\t\t\t\t (uint64_t)sqb_buf);\n+\t\tsqb_buf = next_sqb;\n+\t\tcount--;\n+\t}\n+\n+\t/* Free next to use sqb */\n+\tif (rsp->sq.next_sqb)\n+\t\tnpa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,\n+\t\t\t\t rsp->sq.next_sqb);\n+\n+\t/* Sync NDC-NIX-TX for LF */\n+\tndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);\n+\tndc_req->nix_lf_tx_sync = 1;\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc)\n+\t\totx2_err(\"Error on NDC-NIX-TX LF sync, rc %d\", rc);\n+\n+\treturn rc;\n+}\n+\n+static int\n+nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)\n+{\n+\tstruct otx2_eth_dev *dev = txq->dev;\n+\tuint16_t sqes_per_sqb, nb_sqb_bufs;\n+\tchar name[RTE_MEMPOOL_NAMESIZE];\n+\tstruct rte_mempool_objsz sz;\n+\tstruct npa_aura_s *aura;\n+\tuint32_t tmp, blk_sz;\n+\n+\taura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);\n+\tsnprintf(name, sizeof(name), \"otx2_sqb_pool_%d_%d\", port, txq->sq);\n+\tblk_sz = dev->sqb_size;\n+\n+\tif (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)\n+\t\tsqes_per_sqb = (dev->sqb_size / 8) / 16;\n+\telse\n+\t\tsqes_per_sqb = (dev->sqb_size / 8) / 8;\n+\n+\tnb_sqb_bufs = nb_desc / sqes_per_sqb;\n+\t/* Clamp up to minimum SQB buffers */\n+\tnb_sqb_bufs = RTE_MAX(NIX_MIN_SQB, nb_sqb_bufs + NIX_SQB_LIST_SPACE);\n+\n+\ttxq->sqb_pool = rte_mempool_create_empty(name, nb_sqb_bufs, blk_sz,\n+\t\t\t\t\t\t 0, 0, dev->node,\n+\t\t\t\t\t\t MEMPOOL_F_NO_SPREAD);\n+\ttxq->nb_sqb_bufs = nb_sqb_bufs;\n+\ttxq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);\n+\ttxq->nb_sqb_bufs_adj = nb_sqb_bufs -\n+\t\tRTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;\n+\ttxq->nb_sqb_bufs_adj =\n+\t\t(NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;\n+\n+\tif (txq->sqb_pool == NULL) {\n+\t\totx2_err(\"Failed to allocate sqe mempool\");\n+\t\tgoto fail;\n+\t}\n+\n+\tmemset(aura, 0, sizeof(*aura));\n+\taura->fc_ena = 1;\n+\taura->fc_addr = txq->fc_iova;\n+\taura->fc_hyst_bits = 0; /* Store count on all updates */\n+\tif (rte_mempool_set_ops_byname(txq->sqb_pool, \"octeontx2_npa\", aura)) {\n+\t\totx2_err(\"Failed to set ops for sqe mempool\");\n+\t\tgoto fail;\n+\t}\n+\tif (rte_mempool_populate_default(txq->sqb_pool) < 0) {\n+\t\totx2_err(\"Failed to populate sqe mempool\");\n+\t\tgoto fail;\n+\t}\n+\n+\ttmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);\n+\tif (dev->sqb_size != sz.elt_size) {\n+\t\totx2_err(\"sqe pool block size is not expected %d != %d\",\n+\t\t\t dev->sqb_size, tmp);\n+\t\tgoto fail;\n+\t}\n+\n+\treturn 0;\n+fail:\n+\treturn -ENOMEM;\n+}\n+\n+void\n+otx2_nix_form_default_desc(struct otx2_eth_txq *txq)\n+{\n+\tstruct nix_send_ext_s *send_hdr_ext;\n+\tstruct nix_send_hdr_s *send_hdr;\n+\tstruct nix_send_mem_s *send_mem;\n+\tunion nix_send_sg_s *sg;\n+\n+\t/* Initialize the fields based on basic single segment packet */\n+\tmemset(&txq->cmd, 0, sizeof(txq->cmd));\n+\n+\tif (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {\n+\t\tsend_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];\n+\t\t/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */\n+\t\tsend_hdr->w0.sizem1 = 2;\n+\n+\t\tsend_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];\n+\t\tsend_hdr_ext->w0.subdc = NIX_SUBDC_EXT;\n+\t\tif (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n+\t\t\t/* Default: one seg packet would have:\n+\t\t\t * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)\n+\t\t\t * => 8/2 - 1 = 3\n+\t\t\t */\n+\t\t\tsend_hdr->w0.sizem1 = 3;\n+\t\t\tsend_hdr_ext->w0.tstmp = 1;\n+\n+\t\t\t/* To calculate the offset for send_mem,\n+\t\t\t * send_hdr->w0.sizem1 * 2\n+\t\t\t */\n+\t\t\tsend_mem = (struct nix_send_mem_s *)(txq->cmd +\n+\t\t\t\t\t\t(send_hdr->w0.sizem1 << 1));\n+\t\t\tsend_mem->subdc = NIX_SUBDC_MEM;\n+\t\t\tsend_mem->dsz = 0x0;\n+\t\t\tsend_mem->wmem = 0x1;\n+\t\t\tsend_mem->alg = NIX_SENDMEMALG_SETTSTMP;\n+\t\t}\n+\t\tsg = (union nix_send_sg_s *)&txq->cmd[4];\n+\t} else {\n+\t\tsend_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];\n+\t\t/* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */\n+\t\tsend_hdr->w0.sizem1 = 1;\n+\t\tsg = (union nix_send_sg_s *)&txq->cmd[2];\n+\t}\n+\n+\tsend_hdr->w0.sq = txq->sq;\n+\tsg->subdc = NIX_SUBDC_SG;\n+\tsg->segs = 1;\n+\tsg->ld_type = NIX_SENDLDTYPE_LDD;\n+\n+\trte_smp_wmb();\n+}\n+\n+static void\n+otx2_nix_tx_queue_release(void *_txq)\n+{\n+\tstruct otx2_eth_txq *txq = _txq;\n+\n+\tif (!txq)\n+\t\treturn;\n+\n+\totx2_nix_dbg(\"Releasing txq %u\", txq->sq);\n+\n+\t/* Free sqb's and disable sq */\n+\tnix_sq_uninit(txq);\n+\n+\tif (txq->sqb_pool) {\n+\t\trte_mempool_free(txq->sqb_pool);\n+\t\ttxq->sqb_pool = NULL;\n+\t}\n+\trte_free(txq);\n+}\n+\n+\n+static int\n+otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,\n+\t\t\tuint16_t nb_desc, unsigned int socket_id,\n+\t\t\tconst struct rte_eth_txconf *tx_conf)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tconst struct rte_memzone *fc;\n+\tstruct otx2_eth_txq *txq;\n+\tuint64_t offloads;\n+\tint rc;\n+\n+\trc = -EINVAL;\n+\n+\t/* Compile time check to make sure all fast path elements in a CL */\n+\tRTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);\n+\n+\tif (tx_conf->tx_deferred_start) {\n+\t\totx2_err(\"Tx deferred start is not supported\");\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Free memory prior to re-allocation if needed. */\n+\tif (eth_dev->data->tx_queues[sq] != NULL) {\n+\t\totx2_nix_dbg(\"Freeing memory prior to re-allocation %d\", sq);\n+\t\totx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);\n+\t\teth_dev->data->tx_queues[sq] = NULL;\n+\t}\n+\n+\t/* Find the expected offloads for this queue */\n+\toffloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;\n+\n+\t/* Allocating tx queue data structure */\n+\ttxq = rte_zmalloc_socket(\"otx2_ethdev TX queue\", sizeof(*txq),\n+\t\t\t\t OTX2_ALIGN, socket_id);\n+\tif (txq == NULL) {\n+\t\totx2_err(\"Failed to alloc txq=%d\", sq);\n+\t\trc = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n+\ttxq->sq = sq;\n+\ttxq->dev = dev;\n+\ttxq->sqb_pool = NULL;\n+\ttxq->offloads = offloads;\n+\tdev->tx_offloads |= offloads;\n+\n+\t/*\n+\t * Allocate memory for flow control updates from HW.\n+\t * Alloc one cache line, so that fits all FC_STYPE modes.\n+\t */\n+\tfc = rte_eth_dma_zone_reserve(eth_dev, \"fcmem\", sq,\n+\t\t\t\t OTX2_ALIGN + sizeof(struct npa_aura_s),\n+\t\t\t\t OTX2_ALIGN, dev->node);\n+\tif (fc == NULL) {\n+\t\totx2_err(\"Failed to allocate mem for fcmem\");\n+\t\trc = -ENOMEM;\n+\t\tgoto free_txq;\n+\t}\n+\ttxq->fc_iova = fc->iova;\n+\ttxq->fc_mem = fc->addr;\n+\n+\t/* Initialize the aura sqb pool */\n+\trc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to alloc sqe pool rc=%d\", rc);\n+\t\tgoto free_txq;\n+\t}\n+\n+\t/* Initialize the SQ */\n+\trc = nix_sq_init(txq);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to init sq=%d context\", sq);\n+\t\tgoto free_txq;\n+\t}\n+\n+\ttxq->fc_cache_pkts = 0;\n+\ttxq->io_addr = dev->base + NIX_LF_OP_SENDX(0);\n+\t/* Evenly distribute LMT slot for each sq */\n+\ttxq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));\n+\n+\ttxq->qconf.socket_id = socket_id;\n+\ttxq->qconf.nb_desc = nb_desc;\n+\tmemcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));\n+\n+\totx2_nix_form_default_desc(txq);\n+\n+\totx2_nix_dbg(\"sq=%d fc=%p offload=0x%\" PRIx64 \" sqb=0x%\" PRIx64 \"\"\n+\t\t \" lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d\", sq,\n+\t\t fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,\n+\t\t txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);\n+\teth_dev->data->tx_queues[sq] = txq;\n+\teth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\treturn 0;\n+\n+free_txq:\n+\totx2_nix_tx_queue_release(txq);\n+fail:\n+\treturn rc;\n+}\n+\n+\n static int\n otx2_nix_configure(struct rte_eth_dev *eth_dev)\n {\n@@ -549,6 +915,8 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.dev_infos_get = otx2_nix_info_get,\n \t.dev_configure = otx2_nix_configure,\n \t.link_update = otx2_nix_link_update,\n+\t.tx_queue_setup = otx2_nix_tx_queue_setup,\n+\t.tx_queue_release = otx2_nix_tx_queue_release,\n \t.rx_queue_setup = otx2_nix_rx_queue_setup,\n \t.rx_queue_release = otx2_nix_rx_queue_release,\n \t.stats_get = otx2_nix_dev_stats_get,\n@@ -763,12 +1131,26 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n {\n \tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n \tstruct rte_pci_device *pci_dev;\n-\tint rc;\n+\tint rc, i;\n \n \t/* Nothing to be done for secondary processes */\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\t/* Free up SQs */\n+\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\totx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);\n+\t\teth_dev->data->tx_queues[i] = NULL;\n+\t}\n+\teth_dev->data->nb_tx_queues = 0;\n+\n+\t/* Free up RQ's and CQ's */\n+\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n+\t\totx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);\n+\t\teth_dev->data->rx_queues[i] = NULL;\n+\t}\n+\teth_dev->data->nb_rx_queues = 0;\n+\n \t/* Unregister queue irqs */\n \toxt2_nix_unregister_queue_irqs(eth_dev);\n \ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 562724b4e..4ec950100 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -19,6 +19,7 @@\n #include \"otx2_irq.h\"\n #include \"otx2_mempool.h\"\n #include \"otx2_rx.h\"\n+#include \"otx2_tx.h\"\n \n #define OTX2_ETH_DEV_PMD_VERSION\t\"1.0\"\n \n@@ -54,6 +55,8 @@\n #define NIX_RX_NB_SEG_MAX\t\t6\n #define NIX_CQ_ENTRY_SZ\t\t\t128\n #define NIX_CQ_ALIGN\t\t\t512\n+#define NIX_SQB_LOWER_THRESH\t\t90\n+#define LMT_SLOT_MASK\t\t\t0x7f\n \n /* If PTP is enabled additional SEND MEM DESC is required which\n * takes 2 words, hence max 7 iova address are possible\n@@ -185,6 +188,24 @@ struct otx2_eth_dev {\n \tstruct rte_eth_dev *eth_dev;\n } __rte_cache_aligned;\n \n+struct otx2_eth_txq {\n+\tuint64_t cmd[8];\n+\tint64_t fc_cache_pkts;\n+\tuint64_t *fc_mem;\n+\tvoid *lmt_addr;\n+\trte_iova_t io_addr;\n+\trte_iova_t fc_iova;\n+\tuint16_t sqes_per_sqb_log2;\n+\tint16_t nb_sqb_bufs_adj;\n+\tMARKER slow_path_start;\n+\tuint16_t nb_sqb_bufs;\n+\tuint16_t sq;\n+\tuint64_t offloads;\n+\tstruct otx2_eth_dev *dev;\n+\tstruct rte_mempool *sqb_pool;\n+\tstruct otx2_eth_qconf qconf;\n+} __rte_cache_aligned;\n+\n struct otx2_eth_rxq {\n \tuint64_t mbuf_initializer;\n \tuint64_t data_off;\n@@ -310,4 +331,7 @@ int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);\n int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,\n \t\t\t struct otx2_eth_dev *dev);\n \n+/* Rx and Tx routines */\n+void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);\n+\n #endif /* __OTX2_ETHDEV_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_tx.h b/drivers/net/octeontx2/otx2_tx.h\nnew file mode 100644\nindex 000000000..4d0993f87\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_tx.h\n@@ -0,0 +1,28 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_TX_H__\n+#define __OTX2_TX_H__\n+\n+#define NIX_TX_OFFLOAD_NONE\t\t(0)\n+#define NIX_TX_OFFLOAD_L3_L4_CSUM_F\tBIT(0)\n+#define NIX_TX_OFFLOAD_OL3_OL4_CSUM_F\tBIT(1)\n+#define NIX_TX_OFFLOAD_VLAN_QINQ_F\tBIT(2)\n+#define NIX_TX_OFFLOAD_MBUF_NOFF_F\tBIT(3)\n+#define NIX_TX_OFFLOAD_TSTAMP_F\t\tBIT(4)\n+\n+/* Flags to control xmit_prepare function.\n+ * Defining it from backwards to denote its been\n+ * not used as offload flags to pick function\n+ */\n+#define NIX_TX_MULTI_SEG_F\t\tBIT(15)\n+\n+#define NIX_TX_NEED_SEND_HDR_W1\t\\\n+\t(NIX_TX_OFFLOAD_L3_L4_CSUM_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |\t\\\n+\t NIX_TX_OFFLOAD_VLAN_QINQ_F)\n+\n+#define NIX_TX_NEED_EXT_HDR \\\n+\t(NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSTAMP_F)\n+\n+#endif /* __OTX2_TX_H__ */\n", "prefixes": [ "v1", "18/58" ] }