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GET /api/patches/54073/?format=api
{ "id": 54073, "url": "http://patches.dpdk.org/api/patches/54073/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-18-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-18-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-18-jerinj@marvell.com", "date": "2019-06-02T15:23:53", "name": "[v1,17/58] net/octeontx2: add Rx queue setup and release", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "416179e97290a5bd967a1f5e3984ffb55c7a6de4", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-18-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54073/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54073/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C9A661B964;\n\tSun, 2 Jun 2019 17:25:32 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id CC9FD1B9D4\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:25:30 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FJtoI021289; Sun, 2 Jun 2019 08:25:30 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2supqkvqfk-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:29 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:29 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:29 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 6471F3F703F;\n\tSun, 2 Jun 2019 08:25:27 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=PZ/VTjpZ8udtpLgEPqxD/fiEyVoVkqKrPRSGALshVWo=;\n\tb=QJCOl25WChnmbyvB8lqYrB+J1ZXzsfcp5569TXCcqiVVCCuVrUATwUwU9UBkGmPYPQde\n\tLH/37iVBYp0+Y/lTG/KvhAww6CBV+wCLi5pRj7qD5oIZzuhsOj9PuOhS8SPLWuQYBQfQ\n\tURo2gnkcPgd8pRaUT0hk2DpLH0b/nZj1iHuuR3SFmt0wVcSckLk/J20VvV82tYxS0SrC\n\tocbfs5slIw1ZQkWkszLUrSIsR+g7SPh618Pqb7ODHJqOpxsRrLvIWHf7dx7lYTV6AE49\n\t3oRnaZR18q0OJXfiAZhwchKTq25pFhmfJiVcpyK2R+uFXrZPqLd5pswHg+LbDOjz20z0\n\tmg== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>, Vamsi Attunuru <vattunuru@marvell.com>", "Date": "Sun, 2 Jun 2019 20:53:53 +0530", "Message-ID": "<20190602152434.23996-18-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 17/58] net/octeontx2: add Rx queue setup and\n\trelease", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd Rx queue setup and release.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/net/octeontx2/otx2_ethdev.c | 310 ++++++++++++++++++++++++++++\n drivers/net/octeontx2/otx2_ethdev.h | 51 +++++\n 2 files changed, 361 insertions(+)", "diff": "diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 5289c79e8..dbbc2263d 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -2,9 +2,15 @@\n * Copyright(C) 2019 Marvell International Ltd.\n */\n \n+#include <inttypes.h>\n+#include <math.h>\n+\n #include <rte_ethdev_pci.h>\n #include <rte_io.h>\n #include <rte_malloc.h>\n+#include <rte_mbuf.h>\n+#include <rte_mbuf_pool_ops.h>\n+#include <rte_mempool.h>\n \n #include \"otx2_ethdev.h\"\n \n@@ -114,6 +120,308 @@ nix_lf_free(struct otx2_eth_dev *dev)\n \treturn otx2_mbox_process(mbox);\n }\n \n+static inline void\n+nix_rx_queue_reset(struct otx2_eth_rxq *rxq)\n+{\n+\trxq->head = 0;\n+\trxq->available = 0;\n+}\n+\n+static inline uint32_t\n+nix_qsize_to_val(enum nix_q_size_e qsize)\n+{\n+\treturn (16UL << (qsize * 2));\n+}\n+\n+static inline enum nix_q_size_e\n+nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)\n+{\n+\tint i;\n+\n+\tif (otx2_ethdev_fixup_is_min_4k_q(dev))\n+\t\ti = nix_q_size_4K;\n+\telse\n+\t\ti = nix_q_size_16;\n+\n+\tfor (; i < nix_q_size_max; i++)\n+\t\tif (val <= nix_qsize_to_val(i))\n+\t\t\tbreak;\n+\n+\tif (i >= nix_q_size_max)\n+\t\ti = nix_q_size_max - 1;\n+\n+\treturn i;\n+}\n+\n+static int\n+nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,\n+\t uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tconst struct rte_memzone *rz;\n+\tuint32_t ring_size, cq_size;\n+\tstruct nix_aq_enq_req *aq;\n+\tuint16_t first_skip;\n+\tint rc;\n+\n+\tcq_size = rxq->qlen;\n+\tring_size = cq_size * NIX_CQ_ENTRY_SZ;\n+\trz = rte_eth_dma_zone_reserve(eth_dev, \"cq\", qid, ring_size,\n+\t\t\t\t NIX_CQ_ALIGN, dev->node);\n+\tif (rz == NULL) {\n+\t\totx2_err(\"Failed to allocate mem for cq hw ring\");\n+\t\trc = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n+\tmemset(rz->addr, 0, rz->len);\n+\trxq->desc = (uintptr_t)rz->addr;\n+\trxq->qmask = cq_size - 1;\n+\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = qid;\n+\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\taq->op = NIX_AQ_INSTOP_INIT;\n+\n+\taq->cq.ena = 1;\n+\taq->cq.caching = 1;\n+\taq->cq.qsize = rxq->qsize;\n+\taq->cq.base = rz->iova;\n+\taq->cq.avg_level = 0xff;\n+\taq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);\n+\taq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);\n+\n+\t/* Many to one reduction */\n+\taq->cq.qint_idx = qid % dev->qints;\n+\n+\tif (otx2_ethdev_fixup_is_limit_cq_full(dev)) {\n+\t\tuint16_t min_rx_drop;\n+\t\tconst float rx_cq_skid = 1024 * 256;\n+\n+\t\tmin_rx_drop = ceil(rx_cq_skid / (float)cq_size);\n+\t\taq->cq.drop = min_rx_drop;\n+\t\taq->cq.drop_ena = 1;\n+\t}\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to init cq context\");\n+\t\tgoto fail;\n+\t}\n+\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = qid;\n+\taq->ctype = NIX_AQ_CTYPE_RQ;\n+\taq->op = NIX_AQ_INSTOP_INIT;\n+\n+\taq->rq.sso_ena = 0;\n+\taq->rq.cq = qid; /* RQ to CQ 1:1 mapped */\n+\taq->rq.spb_ena = 0;\n+\taq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);\n+\tfirst_skip = (sizeof(struct rte_mbuf));\n+\tfirst_skip += RTE_PKTMBUF_HEADROOM;\n+\tfirst_skip += rte_pktmbuf_priv_size(mp);\n+\trxq->data_off = first_skip;\n+\n+\tfirst_skip /= 8; /* Expressed in number of dwords */\n+\taq->rq.first_skip = first_skip;\n+\taq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);\n+\taq->rq.flow_tagw = 32; /* 32-bits */\n+\taq->rq.lpb_sizem1 = rte_pktmbuf_data_room_size(mp);\n+\taq->rq.lpb_sizem1 += rte_pktmbuf_priv_size(mp);\n+\taq->rq.lpb_sizem1 += sizeof(struct rte_mbuf);\n+\taq->rq.lpb_sizem1 /= 8;\n+\taq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */\n+\taq->rq.ena = 1;\n+\taq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */\n+\taq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */\n+\taq->rq.rq_int_ena = 0;\n+\t/* Many to one reduction */\n+\taq->rq.qint_idx = qid % dev->qints;\n+\n+\tif (otx2_ethdev_fixup_is_limit_cq_full(dev))\n+\t\taq->rq.xqe_drop_ena = 1;\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to init rq context\");\n+\t\tgoto fail;\n+\t}\n+\n+\treturn 0;\n+fail:\n+\treturn rc;\n+}\n+\n+static int\n+nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_aq_enq_req *aq;\n+\tint rc;\n+\n+\t/* RQ is already disabled */\n+\t/* Disable CQ */\n+\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n+\taq->qidx = rxq->rq;\n+\taq->ctype = NIX_AQ_CTYPE_CQ;\n+\taq->op = NIX_AQ_INSTOP_WRITE;\n+\n+\taq->cq.ena = 0;\n+\taq->cq_mask.ena = ~(aq->cq_mask.ena);\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Failed to disable cq context\");\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static inline int\n+nix_get_data_off(struct otx2_eth_dev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\n+\treturn 0;\n+}\n+\n+uint64_t\n+otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)\n+{\n+\tstruct rte_mbuf mb_def;\n+\tuint64_t *tmp;\n+\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -\n+\t\t\t\toffsetof(struct rte_mbuf, data_off) != 2);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -\n+\t\t\t\toffsetof(struct rte_mbuf, data_off) != 4);\n+\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -\n+\t\t\t\toffsetof(struct rte_mbuf, data_off) != 6);\n+\tmb_def.nb_segs = 1;\n+\tmb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);\n+\tmb_def.port = port_id;\n+\trte_mbuf_refcnt_set(&mb_def, 1);\n+\n+\t/* Prevent compiler reordering: rearm_data covers previous fields */\n+\trte_compiler_barrier();\n+\ttmp = (uint64_t *)&mb_def.rearm_data;\n+\n+\treturn *tmp;\n+}\n+\n+static void\n+otx2_nix_rx_queue_release(void *rx_queue)\n+{\n+\tstruct otx2_eth_rxq *rxq = rx_queue;\n+\n+\tif (!rxq)\n+\t\treturn;\n+\n+\totx2_nix_dbg(\"Releasing rxq %u\", rxq->rq);\n+\tnix_cq_rq_uninit(rxq->eth_dev, rxq);\n+\trte_free(rx_queue);\n+}\n+\n+static int\n+otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,\n+\t\t\tuint16_t nb_desc, unsigned int socket,\n+\t\t\tconst struct rte_eth_rxconf *rx_conf,\n+\t\t\tstruct rte_mempool *mp)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct rte_mempool_ops *ops;\n+\tstruct otx2_eth_rxq *rxq;\n+\tconst char *platform_ops;\n+\tenum nix_q_size_e qsize;\n+\tuint64_t offloads;\n+\tint rc;\n+\n+\trc = -EINVAL;\n+\n+\t/* Compile time check to make sure all fast path elements in a CL */\n+\tRTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);\n+\n+\t/* Sanity checks */\n+\tif (rx_conf->rx_deferred_start == 1) {\n+\t\totx2_err(\"Deferred Rx start is not supported\");\n+\t\tgoto fail;\n+\t}\n+\n+\tplatform_ops = rte_mbuf_platform_mempool_ops();\n+\t/* This driver needs octeontx2_npa mempool ops to work */\n+\tops = rte_mempool_get_ops(mp->ops_index);\n+\tif (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {\n+\t\totx2_err(\"mempool ops should be of octeontx2_npa type\");\n+\t\tgoto fail;\n+\t}\n+\n+\tif (mp->pool_id == 0) {\n+\t\totx2_err(\"Invalid pool_id\");\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Free memory prior to re-allocation if needed */\n+\tif (eth_dev->data->rx_queues[rq] != NULL) {\n+\t\totx2_nix_dbg(\"Freeing memory prior to re-allocation %d\", rq);\n+\t\totx2_nix_rx_queue_release(eth_dev->data->rx_queues[rq]);\n+\t\teth_dev->data->rx_queues[rq] = NULL;\n+\t}\n+\n+\toffloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;\n+\tdev->rx_offloads |= offloads;\n+\n+\t/* Find the CQ queue size */\n+\tqsize = nix_qsize_clampup_get(dev, nb_desc);\n+\t/* Allocate rxq memory */\n+\trxq = rte_zmalloc_socket(\"otx2 rxq\", sizeof(*rxq), OTX2_ALIGN, socket);\n+\tif (rxq == NULL) {\n+\t\totx2_err(\"Failed to allocate rq=%d\", rq);\n+\t\trc = -ENOMEM;\n+\t\tgoto fail;\n+\t}\n+\n+\trxq->eth_dev = eth_dev;\n+\trxq->rq = rq;\n+\trxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;\n+\trxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);\n+\trxq->wdata = (uint64_t)rq << 32;\n+\trxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);\n+\trxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,\n+\t\t\t\t\t\t\teth_dev->data->port_id);\n+\trxq->offloads = offloads;\n+\trxq->pool = mp;\n+\trxq->qlen = nix_qsize_to_val(qsize);\n+\trxq->qsize = qsize;\n+\n+\t/* Alloc completion queue */\n+\trc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to allocate rxq=%u\", rq);\n+\t\tgoto free_rxq;\n+\t}\n+\n+\trxq->qconf.socket_id = socket;\n+\trxq->qconf.nb_desc = nb_desc;\n+\trxq->qconf.mempool = mp;\n+\tmemcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));\n+\n+\tnix_rx_queue_reset(rxq);\n+\totx2_nix_dbg(\"rq=%d pool=%s qsize=%d nb_desc=%d->%d\",\n+\t\t rq, mp->name, qsize, nb_desc, rxq->qlen);\n+\n+\teth_dev->data->rx_queues[rq] = rxq;\n+\teth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\treturn 0;\n+\n+free_rxq:\n+\totx2_nix_rx_queue_release(rxq);\n+fail:\n+\treturn rc;\n+}\n+\n static int\n otx2_nix_configure(struct rte_eth_dev *eth_dev)\n {\n@@ -241,6 +549,8 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {\n \t.dev_infos_get = otx2_nix_info_get,\n \t.dev_configure = otx2_nix_configure,\n \t.link_update = otx2_nix_link_update,\n+\t.rx_queue_setup = otx2_nix_rx_queue_setup,\n+\t.rx_queue_release = otx2_nix_rx_queue_release,\n \t.stats_get = otx2_nix_dev_stats_get,\n \t.stats_reset = otx2_nix_dev_stats_reset,\n \t.get_reg = otx2_nix_dev_get_reg,\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 67b164740..562724b4e 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -10,6 +10,9 @@\n #include <rte_common.h>\n #include <rte_ethdev.h>\n #include <rte_kvargs.h>\n+#include <rte_mbuf.h>\n+#include <rte_mempool.h>\n+#include <rte_string_fns.h>\n \n #include \"otx2_common.h\"\n #include \"otx2_dev.h\"\n@@ -50,6 +53,7 @@\n #define NIX_RX_MIN_DESC_ALIGN\t\t16\n #define NIX_RX_NB_SEG_MAX\t\t6\n #define NIX_CQ_ENTRY_SZ\t\t\t128\n+#define NIX_CQ_ALIGN\t\t\t512\n \n /* If PTP is enabled additional SEND MEM DESC is required which\n * takes 2 words, hence max 7 iova address are possible\n@@ -98,6 +102,19 @@\n #define NIX_DEFAULT_RSS_CTX_GROUP 0\n #define NIX_DEFAULT_RSS_MCAM_IDX -1\n \n+enum nix_q_size_e {\n+\tnix_q_size_16,\t/* 16 entries */\n+\tnix_q_size_64,\t/* 64 entries */\n+\tnix_q_size_256,\n+\tnix_q_size_1K,\n+\tnix_q_size_4K,\n+\tnix_q_size_16K,\n+\tnix_q_size_64K,\n+\tnix_q_size_256K,\n+\tnix_q_size_1M,\t/* Million entries */\n+\tnix_q_size_max\n+};\n+\n struct otx2_qint {\n \tstruct rte_eth_dev *eth_dev;\n \tuint8_t qintx;\n@@ -113,6 +130,16 @@ struct otx2_rss_info {\n \tuint8_t key[NIX_HASH_KEY_SIZE];\n };\n \n+struct otx2_eth_qconf {\n+\tunion {\n+\t\tstruct rte_eth_txconf tx;\n+\t\tstruct rte_eth_rxconf rx;\n+\t} conf;\n+\tvoid *mempool;\n+\tuint32_t socket_id;\n+\tuint16_t nb_desc;\n+};\n+\n struct otx2_npc_flow_info {\n \tuint16_t channel; /*rx channel */\n \tuint16_t flow_prealloc_size;\n@@ -158,6 +185,29 @@ struct otx2_eth_dev {\n \tstruct rte_eth_dev *eth_dev;\n } __rte_cache_aligned;\n \n+struct otx2_eth_rxq {\n+\tuint64_t mbuf_initializer;\n+\tuint64_t data_off;\n+\tuintptr_t desc;\n+\tvoid *lookup_mem;\n+\tuintptr_t cq_door;\n+\tuint64_t wdata;\n+\tint64_t *cq_status;\n+\tuint32_t head;\n+\tuint32_t qmask;\n+\tuint32_t available;\n+\tuint16_t rq;\n+\tstruct otx2_timesync_info *tstamp;\n+\tMARKER slow_path_start;\n+\tuint64_t aura;\n+\tuint64_t offloads;\n+\tuint32_t qlen;\n+\tstruct rte_mempool *pool;\n+\tenum nix_q_size_e qsize;\n+\tstruct rte_eth_dev *eth_dev;\n+\tstruct otx2_eth_qconf qconf;\n+} __rte_cache_aligned;\n+\n static inline struct otx2_eth_dev *\n otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)\n {\n@@ -173,6 +223,7 @@ void otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);\n void otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);\n void otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);\n void otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);\n+uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);\n \n /* Link */\n void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);\n", "prefixes": [ "v1", "17/58" ] }