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GET /api/patches/54064/?format=api
{ "id": 54064, "url": "http://patches.dpdk.org/api/patches/54064/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-9-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-9-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-9-jerinj@marvell.com", "date": "2019-06-02T15:23:44", "name": "[v1,08/58] net/octeontx2: handle queue specific error interrupts", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "889222a41d74939add27b0e29eda7a678056951d", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-9-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54064/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54064/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6884A1B9A0;\n\tSun, 2 Jun 2019 17:25:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 7BA201B99E\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:25:02 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FK7Go020263; Sun, 2 Jun 2019 08:25:02 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk491n-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:25:01 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:25:00 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:25:00 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 224543F703F;\n\tSun, 2 Jun 2019 08:24:58 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=URmNuRDHtFmB6eHuLOiyUBYAX5YRh5QL3MsjsR3laQQ=;\n\tb=KUr9nRQPoxTGWSX2+SB9LwnzfDRG5kdmQWkdzsWwo/lDIXrtUMA3Pyx7jR9/saW45OVq\n\tsnReYLl1S8xkQ2D1V1UZI0z4RJAR4DQSmxcEPZMT1Iqe6zoBl8wLZRD6Q5q9a+PXR9+i\n\t8hz9x2i9z7BnHV5TjDwQKd5t+a1oubYdWxqKMlerEX7rm82RU8jl/a1Amnlrc5I2+6IN\n\tpL139RR/ldzvp0M9bDT9EMM080x33fVkRfwnXhCVlEVmk1mOz6agZ93eQ5PLX9nXylUj\n\tM8GW44eRKvlpF14Lao1wtB/SJMLDYgDDTH6Rv1UfUpw8gwFVjhwgcKfAkia1/rHZiJAl\n\tXg== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>", "CC": "<ferruh.yigit@intel.com>", "Date": "Sun, 2 Jun 2019 20:53:44 +0530", "Message-ID": "<20190602152434.23996-9-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 08/58] net/octeontx2: handle queue specific\n\terror interrupts", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nHandle queue specific error interrupts.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/octeontx2/otx2_ethdev.c | 16 +-\n drivers/net/octeontx2/otx2_ethdev.h | 9 ++\n drivers/net/octeontx2/otx2_ethdev_irq.c | 191 ++++++++++++++++++++++++\n 3 files changed, 215 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 65d72a47f..045855c2e 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -163,8 +163,10 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t}\n \n \t/* Free the resources allocated from the previous configure */\n-\tif (dev->configured == 1)\n+\tif (dev->configured == 1) {\n+\t\toxt2_nix_unregister_queue_irqs(eth_dev);\n \t\tnix_lf_free(dev);\n+\t}\n \n \tif (otx2_dev_is_A0(dev) &&\n \t (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&\n@@ -189,6 +191,13 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \t\tgoto fail;\n \t}\n \n+\t/* Register queue IRQs */\n+\trc = oxt2_nix_register_queue_irqs(eth_dev);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to register queue interrupts rc=%d\", rc);\n+\t\tgoto free_nix_lf;\n+\t}\n+\n \t/* Update the mac address */\n \tea = eth_dev->data->mac_addrs;\n \tmemcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);\n@@ -210,6 +219,8 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)\n \tdev->configured_nb_tx_qs = data->nb_tx_queues;\n \treturn 0;\n \n+free_nix_lf:\n+\trc = nix_lf_free(dev);\n fail:\n \treturn rc;\n }\n@@ -413,6 +424,9 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\t/* Unregister queue irqs */\n+\toxt2_nix_unregister_queue_irqs(eth_dev);\n+\n \trc = nix_lf_free(dev);\n \tif (rc)\n \t\totx2_err(\"Failed to free nix lf, rc=%d\", rc);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex 27cad971c..ca0587a63 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -86,6 +86,11 @@\n \tDEV_RX_OFFLOAD_QINQ_STRIP | \\\n \tDEV_RX_OFFLOAD_TIMESTAMP)\n \n+struct otx2_qint {\n+\tstruct rte_eth_dev *eth_dev;\n+\tuint8_t qintx;\n+};\n+\n struct otx2_rss_info {\n \tuint16_t rss_size;\n \tuint8_t rss_grps;\n@@ -114,6 +119,7 @@ struct otx2_eth_dev {\n \tuint16_t cints;\n \tuint16_t qints;\n \tuint8_t configured;\n+\tuint8_t configured_qints;\n \tuint8_t configured_nb_rx_qs;\n \tuint8_t configured_nb_tx_qs;\n \tuint16_t nix_msixoff;\n@@ -126,6 +132,7 @@ struct otx2_eth_dev {\n \tuint64_t tx_offloads;\n \tuint64_t rx_offload_capa;\n \tuint64_t tx_offload_capa;\n+\tstruct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];\n \tstruct otx2_rss_info rss_info;\n \tstruct otx2_npc_flow_info npc_flow;\n } __rte_cache_aligned;\n@@ -142,7 +149,9 @@ void otx2_nix_info_get(struct rte_eth_dev *eth_dev,\n \n /* IRQ */\n int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);\n+int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);\n void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);\n+void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);\n \n /* CGX */\n int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c\nindex 33fed93c4..476c7ea78 100644\n--- a/drivers/net/octeontx2/otx2_ethdev_irq.c\n+++ b/drivers/net/octeontx2/otx2_ethdev_irq.c\n@@ -112,6 +112,197 @@ nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)\n \totx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);\n }\n \n+static inline uint8_t\n+nix_lf_q_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t q,\n+\t\t\t uint32_t off, uint64_t mask)\n+{\n+\tuint64_t reg, wdata;\n+\tuint8_t qint;\n+\n+\twdata = (uint64_t)q << 44;\n+\treg = otx2_atomic64_add_nosync(wdata, (int64_t *)(dev->base + off));\n+\n+\tif (reg & BIT_ULL(42) /* OP_ERR */) {\n+\t\totx2_err(\"Failed execute irq get off=0x%x\", off);\n+\t\treturn 0;\n+\t}\n+\n+\tqint = reg & 0xff;\n+\twdata &= mask;\n+\totx2_write64(wdata, dev->base + off);\n+\n+\treturn qint;\n+}\n+\n+static inline uint8_t\n+nix_lf_rq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t rq)\n+{\n+\treturn nix_lf_q_irq_get_and_clear(dev, rq, NIX_LF_RQ_OP_INT, ~0xff00);\n+}\n+\n+static inline uint8_t\n+nix_lf_cq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t cq)\n+{\n+\treturn nix_lf_q_irq_get_and_clear(dev, cq, NIX_LF_CQ_OP_INT, ~0xff00);\n+}\n+\n+static inline uint8_t\n+nix_lf_sq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t sq)\n+{\n+\treturn nix_lf_q_irq_get_and_clear(dev, sq, NIX_LF_SQ_OP_INT, ~0x1ff00);\n+}\n+\n+static inline void\n+nix_lf_sq_debug_reg(struct otx2_eth_dev *dev, uint32_t off)\n+{\n+\tuint64_t reg;\n+\n+\treg = otx2_read64(dev->base + off);\n+\tif (reg & BIT_ULL(44))\n+\t\totx2_err(\"SQ=%d err_code=0x%x\",\n+\t\t\t (int)((reg >> 8) & 0xfffff), (uint8_t)(reg & 0xff));\n+}\n+\n+static void\n+nix_lf_q_irq(void *param)\n+{\n+\tstruct otx2_qint *qint = (struct otx2_qint *)param;\n+\tstruct rte_eth_dev *eth_dev = qint->eth_dev;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tuint8_t irq, qintx = qint->qintx;\n+\tint q, cq, rq, sq;\n+\tuint64_t intr;\n+\n+\tintr = otx2_read64(dev->base + NIX_LF_QINTX_INT(qintx));\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_err(\"Queue_intr=0x%\" PRIx64 \" qintx=%d pf=%d, vf=%d\",\n+\t\t intr, qintx, dev->pf, dev->vf);\n+\n+\t/* Handle RQ interrupts */\n+\tfor (q = 0; q < eth_dev->data->nb_rx_queues; q++) {\n+\t\trq = q % dev->qints;\n+\t\tirq = nix_lf_rq_irq_get_and_clear(dev, rq);\n+\n+\t\tif (irq & BIT_ULL(NIX_RQINT_DROP))\n+\t\t\totx2_err(\"RQ=%d NIX_RQINT_DROP\", rq);\n+\n+\t\tif (irq & BIT_ULL(NIX_RQINT_RED))\n+\t\t\totx2_err(\"RQ=%d NIX_RQINT_RED\",\trq);\n+\t}\n+\n+\t/* Handle CQ interrupts */\n+\tfor (q = 0; q < eth_dev->data->nb_rx_queues; q++) {\n+\t\tcq = q % dev->qints;\n+\t\tirq = nix_lf_cq_irq_get_and_clear(dev, cq);\n+\n+\t\tif (irq & BIT_ULL(NIX_CQERRINT_DOOR_ERR))\n+\t\t\totx2_err(\"CQ=%d NIX_CQERRINT_DOOR_ERR\", cq);\n+\n+\t\tif (irq & BIT_ULL(NIX_CQERRINT_WR_FULL))\n+\t\t\totx2_err(\"CQ=%d NIX_CQERRINT_WR_FULL\", cq);\n+\n+\t\tif (irq & BIT_ULL(NIX_CQERRINT_CQE_FAULT))\n+\t\t\totx2_err(\"CQ=%d NIX_CQERRINT_CQE_FAULT\", cq);\n+\t}\n+\n+\t/* Handle SQ interrupts */\n+\tfor (q = 0; q < eth_dev->data->nb_tx_queues; q++) {\n+\t\tsq = q % dev->qints;\n+\t\tirq = nix_lf_sq_irq_get_and_clear(dev, sq);\n+\n+\t\tif (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) {\n+\t\t\totx2_err(\"SQ=%d NIX_SQINT_LMT_ERR\", sq);\n+\t\t\tnix_lf_sq_debug_reg(dev, NIX_LF_SQ_OP_ERR_DBG);\n+\t\t}\n+\t\tif (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) {\n+\t\t\totx2_err(\"SQ=%d NIX_SQINT_MNQ_ERR\", sq);\n+\t\t\tnix_lf_sq_debug_reg(dev, NIX_LF_MNQ_ERR_DBG);\n+\t\t}\n+\t\tif (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) {\n+\t\t\totx2_err(\"SQ=%d NIX_SQINT_SEND_ERR\", sq);\n+\t\t\tnix_lf_sq_debug_reg(dev, NIX_LF_SEND_ERR_DBG);\n+\t\t}\n+\t\tif (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) {\n+\t\t\totx2_err(\"SQ=%d NIX_SQINT_SQB_ALLOC_FAIL\", sq);\n+\t\t\tnix_lf_sq_debug_reg(dev, NIX_LF_SEND_ERR_DBG);\n+\t\t}\n+\t}\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, dev->base + NIX_LF_QINTX_INT(qintx));\n+}\n+\n+int\n+oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint vec, q, sqs, rqs, qs, rc = 0;\n+\n+\t/* Figure out max qintx required */\n+\trqs = RTE_MIN(dev->qints, eth_dev->data->nb_rx_queues);\n+\tsqs = RTE_MIN(dev->qints, eth_dev->data->nb_tx_queues);\n+\tqs = RTE_MAX(rqs, sqs);\n+\n+\tdev->configured_qints = qs;\n+\n+\tfor (q = 0; q < qs; q++) {\n+\t\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_QINT_START + q;\n+\n+\t\t/* Clear QINT CNT */\n+\t\totx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\totx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1C(q));\n+\n+\t\tdev->qints_mem[q].eth_dev = eth_dev;\n+\t\tdev->qints_mem[q].qintx = q;\n+\n+\t\t/* Sync qints_mem update */\n+\t\trte_smp_wmb();\n+\n+\t\t/* Register queue irq vector */\n+\t\trc = otx2_register_irq(handle, nix_lf_q_irq,\n+\t\t\t\t &dev->qints_mem[q], vec);\n+\t\tif (rc)\n+\t\t\tbreak;\n+\n+\t\totx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));\n+\t\totx2_write64(0, dev->base + NIX_LF_QINTX_INT(q));\n+\t\t/* Enable QINT interrupt */\n+\t\totx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1S(q));\n+\t}\n+\n+\treturn rc;\n+}\n+\n+void\n+oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tint vec, q;\n+\n+\tfor (q = 0; q < dev->configured_qints; q++) {\n+\t\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_QINT_START + q;\n+\n+\t\t/* Clear QINT CNT */\n+\t\totx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));\n+\t\totx2_write64(0, dev->base + NIX_LF_QINTX_INT(q));\n+\n+\t\t/* Clear interrupt */\n+\t\totx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1C(q));\n+\n+\t\t/* Unregister queue irq vector */\n+\t\totx2_unregister_irq(handle, nix_lf_q_irq,\n+\t\t\t\t &dev->qints_mem[q], vec);\n+\t}\n+}\n+\n int\n otx2_nix_register_irqs(struct rte_eth_dev *eth_dev)\n {\n", "prefixes": [ "v1", "08/58" ] }