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GET /api/patches/54059/?format=api
{ "id": 54059, "url": "http://patches.dpdk.org/api/patches/54059/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-4-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190602152434.23996-4-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190602152434.23996-4-jerinj@marvell.com", "date": "2019-06-02T15:23:39", "name": "[v1,03/58] net/octeontx2: add device init and uninit", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8312a9dffdde27e2f4d065f13d4225c22899995d", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190602152434.23996-4-jerinj@marvell.com/mbox/", "series": [ { "id": 4848, "url": "http://patches.dpdk.org/api/series/4848/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4848", "date": "2019-06-02T15:23:36", "name": "OCTEON TX2 Ethdev driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4848/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54059/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54059/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8263F1B945;\n\tSun, 2 Jun 2019 17:24:47 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 31513559A\n\tfor <dev@dpdk.org>; Sun, 2 Jun 2019 17:24:46 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx52FKKoj020361; Sun, 2 Jun 2019 08:24:45 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk490j-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tSun, 02 Jun 2019 08:24:45 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSun, 2 Jun 2019 08:24:44 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sun, 2 Jun 2019 08:24:44 -0700", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 1D28A3F703F;\n\tSun, 2 Jun 2019 08:24:41 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=P2EljxBolAn/AMeVz7IzadQ1tLrLvm61D05eibgNfGM=;\n\tb=bR5U7JvYhKqQEU2zli9TA5hdrsQXttFtLPL4pK1nvvIY890NfS9xEmq6QBE4VUVgvy8N\n\tBACmftXAcCZdXLKn+A1OVOe4KCyqZ2jIMtT5UALgiUviaq7AOeBhWfmfVtAWh9hvO7Y+\n\t8EidszirszqgXKbSCwUyqzBzZ10psKGV6nzWL1OHbD5TqIMHUiR1cXho3Dwxdn5EBk3E\n\twER7zdwiFfCEO8dK61r2/kD4my4CA1QY/fF7k+3du4cyBM7LqvYadExBAt+QOqSqJn2D\n\tv6suIoASnUyHOCHdMC6SujginzMJRiz0/1EMiibNuY8as0XGHKIpuWUbFIz5jx2LtaT3\n\tDQ== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>,\n\t\"Anatoly Burakov\" <anatoly.burakov@intel.com>", "CC": "<ferruh.yigit@intel.com>, Sunil Kumar Kori <skori@marvell.com>, \"Vamsi\n\tAttunuru\" <vattunuru@marvell.com>", "Date": "Sun, 2 Jun 2019 20:53:39 +0530", "Message-ID": "<20190602152434.23996-4-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190602152434.23996-1-jerinj@marvell.com>", "References": "<20190602152434.23996-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-02_09:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 03/58] net/octeontx2: add device init and\n\tuninit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAdd basic init and uninit function which includes\nattaching LF device to probed PCIe device.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/net/octeontx2/Makefile | 1 +\n drivers/net/octeontx2/meson.build | 1 +\n drivers/net/octeontx2/otx2_ethdev.c | 277 +++++++++++++++++++++++++++-\n drivers/net/octeontx2/otx2_ethdev.h | 72 ++++++++\n drivers/net/octeontx2/otx2_mac.c | 72 ++++++++\n 5 files changed, 418 insertions(+), 5 deletions(-)\n create mode 100644 drivers/net/octeontx2/otx2_mac.c", "diff": "diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile\nindex 0a606d27b..9ca1eea99 100644\n--- a/drivers/net/octeontx2/Makefile\n+++ b/drivers/net/octeontx2/Makefile\n@@ -30,6 +30,7 @@ LIBABIVER := 1\n # all source are stored in SRCS-y\n #\n SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \\\n+\totx2_mac.c\t\\\n \totx2_ethdev.c\n \n LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_common_octeontx2 -lm\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\nindex 0bd32446b..6cdd036e9 100644\n--- a/drivers/net/octeontx2/meson.build\n+++ b/drivers/net/octeontx2/meson.build\n@@ -3,6 +3,7 @@\n #\n \n sources = files(\n+\t\t'otx2_mac.c',\n \t\t'otx2_ethdev.c',\n \t\t)\n \ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\nindex 05fa8988e..08f03b4c3 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ b/drivers/net/octeontx2/otx2_ethdev.c\n@@ -8,27 +8,277 @@\n \n #include \"otx2_ethdev.h\"\n \n+static inline void\n+otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n+{\n+\tRTE_SET_USED(eth_dev);\n+}\n+\n+static inline void\n+otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n+{\n+\tRTE_SET_USED(eth_dev);\n+}\n+\n+static inline uint64_t\n+nix_get_rx_offload_capa(struct otx2_eth_dev *dev)\n+{\n+\tuint64_t capa = NIX_RX_OFFLOAD_CAPA;\n+\n+\tif (otx2_dev_is_vf(dev))\n+\t\tcapa &= ~DEV_RX_OFFLOAD_TIMESTAMP;\n+\n+\treturn capa;\n+}\n+\n+static inline uint64_t\n+nix_get_tx_offload_capa(struct otx2_eth_dev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\n+\treturn NIX_TX_OFFLOAD_CAPA;\n+}\n+\n+static int\n+nix_lf_free(struct otx2_eth_dev *dev)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_lf_free_req *req;\n+\tstruct ndc_sync_op *ndc_req;\n+\tint rc;\n+\n+\t/* Sync NDC-NIX for LF */\n+\tndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);\n+\tndc_req->nix_lf_tx_sync = 1;\n+\tndc_req->nix_lf_rx_sync = 1;\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc)\n+\t\totx2_err(\"Error on NDC-NIX-[TX, RX] LF sync, rc %d\", rc);\n+\n+\treq = otx2_mbox_alloc_msg_nix_lf_free(mbox);\n+\t/* Let AF driver free all this nix lf's\n+\t * NPC entries allocated using NPC MBOX.\n+\t */\n+\treq->flags = 0;\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n+static inline int\n+nix_lf_attach(struct otx2_eth_dev *dev)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct rsrc_attach_req *req;\n+\n+\t/* Attach NIX(lf) */\n+\treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n+\treq->modify = true;\n+\treq->nixlf = true;\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n+static inline int\n+nix_lf_get_msix_offset(struct otx2_eth_dev *dev)\n+{\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct msix_offset_rsp *msix_rsp;\n+\tint rc;\n+\n+\t/* Get NPA and NIX MSIX vector offsets */\n+\totx2_mbox_alloc_msg_msix_offset(mbox);\n+\n+\trc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);\n+\n+\tdev->nix_msixoff = msix_rsp->nix_msixoff;\n+\n+\treturn rc;\n+}\n+\n+static inline int\n+otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)\n+{\n+\tstruct rsrc_detach_req *req;\n+\n+\treq = otx2_mbox_alloc_msg_detach_resources(mbox);\n+\n+\t/* Detach all except npa lf */\n+\treq->partial = true;\n+\treq->nixlf = true;\n+\treq->sso = true;\n+\treq->ssow = true;\n+\treq->timlfs = true;\n+\treq->cptlfs = true;\n+\n+\treturn otx2_mbox_process(mbox);\n+}\n+\n static int\n otx2_eth_dev_init(struct rte_eth_dev *eth_dev)\n {\n-\tRTE_SET_USED(eth_dev);\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct rte_pci_device *pci_dev;\n+\tint rc, max_entries;\n \n-\treturn -ENODEV;\n+\t/* For secondary processes, the primary has done all the work */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n+\t\t/* Setup callbacks for secondary process */\n+\t\totx2_eth_set_tx_function(eth_dev);\n+\t\totx2_eth_set_rx_function(eth_dev);\n+\t\treturn 0;\n+\t}\n+\n+\tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\n+\trte_eth_copy_pci_info(eth_dev, pci_dev);\n+\teth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;\n+\n+\t/* Zero out everything after OTX2_DEV to allow proper dev_reset() */\n+\tmemset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -\n+\t\toffsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));\n+\n+\tif (!dev->mbox_active) {\n+\t\t/* Initialize the base otx2_dev object\n+\t\t * only if already present\n+\t\t */\n+\t\trc = otx2_dev_init(pci_dev, dev);\n+\t\tif (rc) {\n+\t\t\totx2_err(\"Failed to initialize otx2_dev rc=%d\", rc);\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n+\n+\t/* Grab the NPA LF if required */\n+\trc = otx2_npa_lf_init(pci_dev, dev);\n+\tif (rc)\n+\t\tgoto otx2_dev_uninit;\n+\n+\tdev->configured = 0;\n+\tdev->drv_inited = true;\n+\tdev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);\n+\tdev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);\n+\n+\t/* Attach NIX LF */\n+\trc = nix_lf_attach(dev);\n+\tif (rc)\n+\t\tgoto otx2_npa_uninit;\n+\n+\t/* Get NIX MSIX offset */\n+\trc = nix_lf_get_msix_offset(dev);\n+\tif (rc)\n+\t\tgoto otx2_npa_uninit;\n+\n+\t/* Get maximum number of supported MAC entries */\n+\tmax_entries = otx2_cgx_mac_max_entries_get(dev);\n+\tif (max_entries < 0) {\n+\t\totx2_err(\"Failed to get max entries for mac addr\");\n+\t\trc = -ENOTSUP;\n+\t\tgoto mbox_detach;\n+\t}\n+\n+\t/* For VFs, returned max_entries will be 0. But to keep default MAC\n+\t * address, one entry must be allocated. So setting up to 1.\n+\t */\n+\tif (max_entries == 0)\n+\t\tmax_entries = 1;\n+\n+\teth_dev->data->mac_addrs = rte_zmalloc(\"mac_addr\", max_entries *\n+\t\t\t\t\t RTE_ETHER_ADDR_LEN, 0);\n+\tif (eth_dev->data->mac_addrs == NULL) {\n+\t\totx2_err(\"Failed to allocate memory for mac addr\");\n+\t\trc = -ENOMEM;\n+\t\tgoto mbox_detach;\n+\t}\n+\n+\tdev->max_mac_entries = max_entries;\n+\n+\trc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);\n+\tif (rc)\n+\t\tgoto free_mac_addrs;\n+\n+\t/* Update the mac address */\n+\tmemcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);\n+\n+\t/* Also sync same MAC address to CGX table */\n+\totx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);\n+\n+\tdev->tx_offload_capa = nix_get_tx_offload_capa(dev);\n+\tdev->rx_offload_capa = nix_get_rx_offload_capa(dev);\n+\n+\tif (otx2_dev_is_A0(dev)) {\n+\t\tdev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;\n+\t\tdev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;\n+\t}\n+\n+\totx2_nix_dbg(\"Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%\" PRIx64\n+\t\t \" rxoffload_capa=0x%\" PRIx64 \" txoffload_capa=0x%\" PRIx64,\n+\t\t eth_dev->data->port_id, dev->pf, dev->vf,\n+\t\t OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,\n+\t\t dev->rx_offload_capa, dev->tx_offload_capa);\n+\treturn 0;\n+\n+free_mac_addrs:\n+\trte_free(eth_dev->data->mac_addrs);\n+mbox_detach:\n+\totx2_eth_dev_lf_detach(dev->mbox);\n+otx2_npa_uninit:\n+\totx2_npa_lf_fini();\n+otx2_dev_uninit:\n+\totx2_dev_fini(pci_dev, dev);\n+error:\n+\totx2_err(\"Failed to init nix eth_dev rc=%d\", rc);\n+\treturn rc;\n }\n \n static int\n otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n {\n-\tRTE_SET_USED(eth_dev);\n-\tRTE_SET_USED(mbox_close);\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct rte_pci_device *pci_dev;\n+\tint rc;\n \n-\treturn -ENODEV;\n+\t/* Nothing to be done for secondary processes */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\trc = nix_lf_free(dev);\n+\tif (rc)\n+\t\totx2_err(\"Failed to free nix lf, rc=%d\", rc);\n+\n+\trc = otx2_npa_lf_fini();\n+\tif (rc)\n+\t\totx2_err(\"Failed to cleanup npa lf, rc=%d\", rc);\n+\n+\trte_free(eth_dev->data->mac_addrs);\n+\teth_dev->data->mac_addrs = NULL;\n+\tdev->drv_inited = false;\n+\n+\tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n+\n+\trc = otx2_eth_dev_lf_detach(dev->mbox);\n+\tif (rc)\n+\t\totx2_err(\"Failed to detach resources, rc=%d\", rc);\n+\n+\t/* Check if mbox close is needed */\n+\tif (!mbox_close)\n+\t\treturn 0;\n+\n+\tif (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {\n+\t\t/* Will be freed later by PMD */\n+\t\teth_dev->data->dev_private = NULL;\n+\t\treturn 0;\n+\t}\n+\n+\totx2_dev_fini(pci_dev, dev);\n+\treturn 0;\n }\n \n static int\n nix_remove(struct rte_pci_device *pci_dev)\n {\n \tstruct rte_eth_dev *eth_dev;\n+\tstruct otx2_idev_cfg *idev;\n+\tstruct otx2_dev *otx2_dev;\n \tint rc;\n \n \teth_dev = rte_eth_dev_allocated(pci_dev->device.name);\n@@ -45,7 +295,24 @@ nix_remove(struct rte_pci_device *pci_dev)\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n \n+\t/* Check for common resources */\n+\tidev = otx2_intra_dev_get_cfg();\n+\tif (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)\n+\t\treturn 0;\n+\n+\totx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);\n+\n+\tif (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))\n+\t\tgoto exit;\n+\n+\t/* Safe to cleanup mbox as no more users */\n+\totx2_dev_fini(pci_dev, otx2_dev);\n+\trte_free(otx2_dev);\n \treturn 0;\n+\n+exit:\n+\totx2_info(\"%s: common resource in use by other devices\", pci_dev->name);\n+\treturn -EAGAIN;\n }\n \n static int\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\nindex fd01a3254..d9f72686a 100644\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ b/drivers/net/octeontx2/otx2_ethdev.h\n@@ -8,14 +8,76 @@\n #include <stdint.h>\n \n #include <rte_common.h>\n+#include <rte_ethdev.h>\n \n #include \"otx2_common.h\"\n #include \"otx2_dev.h\"\n #include \"otx2_irq.h\"\n #include \"otx2_mempool.h\"\n \n+#define OTX2_ETH_DEV_PMD_VERSION\t\"1.0\"\n+\n+/* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */\n+\n+/* Minimum CQ size should be 4K */\n+#define OTX2_FIXUP_F_MIN_4K_Q\t\tBIT_ULL(63)\n+#define otx2_ethdev_fixup_is_min_4k_q(dev)\t\\\n+\t\t\t\t((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)\n+/* Limit CQ being full */\n+#define OTX2_FIXUP_F_LIMIT_CQ_FULL\tBIT_ULL(62)\n+#define otx2_ethdev_fixup_is_limit_cq_full(dev) \\\n+\t\t\t\t((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)\n+\n+/* Used for struct otx2_eth_dev::flags */\n+#define OTX2_LINK_CFG_IN_PROGRESS_F\tBIT_ULL(0)\n+\n+#define NIX_TX_OFFLOAD_CAPA ( \\\n+\tDEV_TX_OFFLOAD_MBUF_FAST_FREE\t| \\\n+\tDEV_TX_OFFLOAD_MT_LOCKFREE\t| \\\n+\tDEV_TX_OFFLOAD_VLAN_INSERT\t| \\\n+\tDEV_TX_OFFLOAD_QINQ_INSERT\t| \\\n+\tDEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \\\n+\tDEV_TX_OFFLOAD_OUTER_UDP_CKSUM | \\\n+\tDEV_TX_OFFLOAD_TCP_CKSUM\t| \\\n+\tDEV_TX_OFFLOAD_UDP_CKSUM\t| \\\n+\tDEV_TX_OFFLOAD_SCTP_CKSUM\t| \\\n+\tDEV_TX_OFFLOAD_MULTI_SEGS\t| \\\n+\tDEV_TX_OFFLOAD_IPV4_CKSUM)\n+\n+#define NIX_RX_OFFLOAD_CAPA ( \\\n+\tDEV_RX_OFFLOAD_CHECKSUM\t\t| \\\n+\tDEV_RX_OFFLOAD_SCTP_CKSUM\t| \\\n+\tDEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \\\n+\tDEV_RX_OFFLOAD_SCATTER\t\t| \\\n+\tDEV_RX_OFFLOAD_JUMBO_FRAME\t| \\\n+\tDEV_RX_OFFLOAD_OUTER_UDP_CKSUM | \\\n+\tDEV_RX_OFFLOAD_VLAN_STRIP | \\\n+\tDEV_RX_OFFLOAD_VLAN_FILTER | \\\n+\tDEV_RX_OFFLOAD_QINQ_STRIP | \\\n+\tDEV_RX_OFFLOAD_TIMESTAMP)\n+\n struct otx2_eth_dev {\n \tOTX2_DEV; /* Base class */\n+\tMARKER otx2_eth_dev_data_start;\n+\tuint16_t sqb_size;\n+\tuint16_t rx_chan_base;\n+\tuint16_t tx_chan_base;\n+\tuint8_t rx_chan_cnt;\n+\tuint8_t tx_chan_cnt;\n+\tuint8_t lso_tsov4_idx;\n+\tuint8_t lso_tsov6_idx;\n+\tuint8_t mac_addr[RTE_ETHER_ADDR_LEN];\n+\tuint8_t max_mac_entries;\n+\tuint8_t configured;\n+\tuint16_t nix_msixoff;\n+\tuintptr_t base;\n+\tuintptr_t lmt_addr;\n+\tuint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */\n+\tuint64_t rx_offloads;\n+\tuint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */\n+\tuint64_t tx_offloads;\n+\tuint64_t rx_offload_capa;\n+\tuint64_t tx_offload_capa;\n } __rte_cache_aligned;\n \n static inline struct otx2_eth_dev *\n@@ -24,4 +86,14 @@ otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)\n \treturn eth_dev->data->dev_private;\n }\n \n+/* CGX */\n+int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);\n+int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);\n+int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,\n+\t\t\t struct rte_ether_addr *addr);\n+\n+/* Mac address handling */\n+int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);\n+int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);\n+\n #endif /* __OTX2_ETHDEV_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_mac.c b/drivers/net/octeontx2/otx2_mac.c\nnew file mode 100644\nindex 000000000..89b0ca6b0\n--- /dev/null\n+++ b/drivers/net/octeontx2/otx2_mac.c\n@@ -0,0 +1,72 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_common.h>\n+\n+#include \"otx2_dev.h\"\n+#include \"otx2_ethdev.h\"\n+\n+int\n+otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct cgx_mac_addr_set_or_get *req;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tint rc;\n+\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn -ENOTSUP;\n+\n+\tif (otx2_dev_active_vfs(dev))\n+\t\treturn -ENOTSUP;\n+\n+\treq = otx2_mbox_alloc_msg_cgx_mac_addr_set(mbox);\n+\totx2_mbox_memcpy(req->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN);\n+\n+\trc = otx2_mbox_process(mbox);\n+\tif (rc)\n+\t\totx2_err(\"Failed to set mac address in CGX, rc=%d\", rc);\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev)\n+{\n+\tstruct cgx_max_dmac_entries_get_rsp *rsp;\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tint rc;\n+\n+\tif (otx2_dev_is_vf(dev))\n+\t\treturn 0;\n+\n+\totx2_mbox_alloc_msg_cgx_mac_max_entries_get(mbox);\n+\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn rsp->max_dmac_filters;\n+}\n+\n+int\n+otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr)\n+{\n+\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct nix_get_mac_addr_rsp *rsp;\n+\tint rc;\n+\n+\totx2_mbox_alloc_msg_nix_get_mac_addr(mbox);\n+\totx2_mbox_msg_send(mbox, 0);\n+\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp);\n+\tif (rc) {\n+\t\totx2_err(\"Failed to get mac address, rc=%d\", rc);\n+\t\tgoto done;\n+\t}\n+\n+\totx2_mbox_memcpy(addr, rsp->mac_addr, RTE_ETHER_ADDR_LEN);\n+\n+done:\n+\treturn rc;\n+}\n", "prefixes": [ "v1", "03/58" ] }