Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/54045/?format=api
{ "id": 54045, "url": "http://patches.dpdk.org/api/patches/54045/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-34-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190601185355.370-34-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190601185355.370-34-pbhagavatula@marvell.com", "date": "2019-06-01T18:53:43", "name": "[33/44] event/octeontx2: add TIM IRQ handlers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1a3bb425ea400c14f39e2bc524efe912e0f1180a", "submitter": { "id": 1183, "url": "http://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601185355.370-34-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 4847, "url": "http://patches.dpdk.org/api/series/4847/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4847", "date": "2019-06-01T18:53:10", "name": "OCTEON TX2 event device driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4847/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/54045/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/54045/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 68BAA1BACE;\n\tSat, 1 Jun 2019 20:57:06 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 862E51B9E0\n\tfor <dev@dpdk.org>; Sat, 1 Jun 2019 20:56:25 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx51It9ns029954 for <dev@dpdk.org>; Sat, 1 Jun 2019 11:56:25 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2survk12h8-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 01 Jun 2019 11:56:24 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 1 Jun 2019 11:56:23 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 1 Jun 2019 11:56:23 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.28])\n\tby maili.marvell.com (Postfix) with ESMTP id 260913F7040;\n\tSat, 1 Jun 2019 11:56:21 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=szKBnj4QL/abcDjQGNhLUuQCO64USaDVMkaJOoh+mqA=;\n\tb=amTQ7fRzZJ9VgdVyA/BSpPFzbd3wh5f92HbfFJgaEmQf2eVFgewNLK/bTdHxPkbqoNwb\n\tBJhENc6+n8olT4mDdh5rLApn7GIIa1oCXLLmt5iotweivdWVh8RetNYFx4e/JbETTbH0\n\tCjqFdBKTTi1N/nhf3Es+C4tvMgVPhDsaP8IWhEQlNGK0WxQbjOKboFK636Zo7/Y4dniB\n\t0oxfKqOhDAdmrxzbH40MjZyA6z24xiWT3c31sbhnh/1TpzNhNkEdLErdA+btRLxcgJ9F\n\t17sd5DcHH8N80POSROdVCFaoopLZYJjBL1wkK7CNjyoKGNQtZwUbI0DXSLLyfPAbseCC\n\t8Q== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Sun, 2 Jun 2019 00:23:43 +0530", "Message-ID": "<20190601185355.370-34-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190601185355.370-1-pbhagavatula@marvell.com>", "References": "<20190601185355.370-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0", "Subject": "[dpdk-dev] [PATCH 33/44] event/octeontx2: add TIM IRQ handlers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nRegister and implement TIM IRQ handlers for error interrupts\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_evdev_irq.c | 99 ++++++++++++++++++++++++\n drivers/event/octeontx2/otx2_tim_evdev.c | 37 +++++++++\n drivers/event/octeontx2/otx2_tim_evdev.h | 14 ++++\n 3 files changed, 150 insertions(+)", "diff": "diff --git a/drivers/event/octeontx2/otx2_evdev_irq.c b/drivers/event/octeontx2/otx2_evdev_irq.c\nindex e10389703..80de2f407 100644\n--- a/drivers/event/octeontx2/otx2_evdev_irq.c\n+++ b/drivers/event/octeontx2/otx2_evdev_irq.c\n@@ -3,6 +3,7 @@\n */\n \n #include \"otx2_evdev.h\"\n+#include \"otx2_tim_evdev.h\"\n \n static void\n sso_lf_irq(void *param)\n@@ -177,3 +178,101 @@ sso_unregister_irqs(const struct rte_eventdev *event_dev)\n \t\tssow_lf_unregister_irq(event_dev, dev->ssow_msixoff[i], base);\n \t}\n }\n+\n+static void\n+tim_lf_irq(void *param)\n+{\n+\tuintptr_t base = (uintptr_t)param;\n+\tuint64_t intr;\n+\tuint8_t ring;\n+\n+\tring = (base >> 12) & 0xFF;\n+\n+\tintr = otx2_read64(base + TIM_LF_NRSPERR_INT);\n+\totx2_err(\"TIM RING %d TIM_LF_NRSPERR_INT=0x%\" PRIx64 \"\", ring, intr);\n+\tintr = otx2_read64(base + TIM_LF_RAS_INT);\n+\totx2_err(\"TIM RING %d TIM_LF_RAS_INT=0x%\" PRIx64 \"\", ring, intr);\n+\n+\t/* Clear interrupt */\n+\totx2_write64(intr, base + TIM_LF_NRSPERR_INT);\n+\totx2_write64(intr, base + TIM_LF_RAS_INT);\n+\n+\tabort();\n+}\n+\n+static int\n+tim_lf_register_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,\n+\t\t uintptr_t base)\n+{\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint rc, vec;\n+\n+\tvec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, base + TIM_LF_NRSPERR_INT);\n+\t/* Set used interrupt vectors */\n+\trc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);\n+\t/* Enable hw interrupt */\n+\totx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S);\n+\n+\tvec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, base + TIM_LF_RAS_INT);\n+\t/* Set used interrupt vectors */\n+\trc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);\n+\t/* Enable hw interrupt */\n+\totx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+tim_lf_unregister_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,\n+\t\t uintptr_t base)\n+{\n+\tstruct rte_intr_handle *handle = &pci_dev->intr_handle;\n+\tint vec;\n+\n+\tvec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1C);\n+\totx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);\n+\n+\tvec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;\n+\n+\t/* Clear err interrupt */\n+\totx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1C);\n+\totx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);\n+}\n+\n+int\n+tim_register_irq(uint16_t ring_id)\n+{\n+\tstruct otx2_tim_evdev *dev = otx2_tim_priv_get();\n+\tint rc = -EINVAL;\n+\tuintptr_t base;\n+\n+\tif (dev->tim_msixoff[ring_id] == MSIX_VECTOR_INVALID) {\n+\t\totx2_err(\"Invalid TIMLF MSIX offset[%d] vector: 0x%x\",\n+\t\t\t ring_id, dev->tim_msixoff[ring_id]);\n+\t\tgoto fail;\n+\t}\n+\n+\tbase = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);\n+\trc = tim_lf_register_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);\n+fail:\n+\treturn rc;\n+}\n+\n+void\n+tim_unregister_irq(uint16_t ring_id)\n+{\n+\tstruct otx2_tim_evdev *dev = otx2_tim_priv_get();\n+\tuintptr_t base;\n+\n+\tbase = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);\n+\ttim_lf_unregister_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);\n+}\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex bba6cc609..cf3f29880 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -11,6 +11,24 @@\n \n static struct rte_event_timer_adapter_ops otx2_tim_ops;\n \n+static inline int\n+tim_get_msix_offsets(void)\n+{\n+\tstruct otx2_tim_evdev *dev = otx2_tim_priv_get();\n+\tstruct otx2_mbox *mbox = dev->mbox;\n+\tstruct msix_offset_rsp *msix_rsp;\n+\tint i, rc;\n+\n+\t/* Get TIM MSIX vector offsets */\n+\totx2_mbox_alloc_msg_msix_offset(mbox);\n+\trc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);\n+\n+\tfor (i = 0; i < dev->nb_rings; i++)\n+\t\tdev->tim_msixoff[i] = msix_rsp->timlf_msixoff[i];\n+\n+\treturn rc;\n+}\n+\n static void\n tim_optimze_bkt_param(struct otx2_tim_ring *tim_ring)\n {\n@@ -288,6 +306,10 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \ttim_ring->base = dev->bar2 +\n \t\t(RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);\n \n+\trc = tim_register_irq(tim_ring->ring_id);\n+\tif (rc < 0)\n+\t\tgoto chnk_mem_err;\n+\n \totx2_write64((uint64_t)tim_ring->bkt,\n \t\t tim_ring->base + TIM_LF_RING_BASE);\n \totx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);\n@@ -316,6 +338,8 @@ otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)\n \tif (dev == NULL)\n \t\treturn -ENODEV;\n \n+\ttim_unregister_irq(tim_ring->ring_id);\n+\n \treq = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);\n \treq->ring = tim_ring->ring_id;\n \n@@ -379,6 +403,7 @@ void\n otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n {\n \tstruct rsrc_attach_req *atch_req;\n+\tstruct rsrc_detach_req *dtch_req;\n \tstruct free_rsrcs_rsp *rsrc_cnt;\n \tconst struct rte_memzone *mz;\n \tstruct otx2_tim_evdev *dev;\n@@ -426,6 +451,12 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n \t\tgoto mz_free;\n \t}\n \n+\trc = tim_get_msix_offsets();\n+\tif (rc < 0) {\n+\t\totx2_err(\"Unable to get MSIX offsets for TIM.\");\n+\t\tgoto detach;\n+\t}\n+\n \tif (!dev->chunk_slots)\n \t\tdev->chunk_sz = OTX2_TIM_RING_DEF_CHNK_SZ;\n \telse\n@@ -434,6 +465,12 @@ otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n \n \treturn;\n \n+detach:\n+\tdtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);\n+\tdtch_req->partial = true;\n+\tdtch_req->timlfs = true;\n+\n+\totx2_mbox_process(dev->mbox);\n mz_free:\n \trte_memzone_free(mz);\n }\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex 617902a0b..5d183b8b2 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -16,6 +16,14 @@\n \n #define TIM_LF_RING_AURA\t\t(0x0)\n #define TIM_LF_RING_BASE\t\t(0x130)\n+#define TIM_LF_NRSPERR_INT\t\t(0x200)\n+#define TIM_LF_NRSPERR_INT_W1S\t\t(0x208)\n+#define TIM_LF_NRSPERR_INT_ENA_W1S\t(0x210)\n+#define TIM_LF_NRSPERR_INT_ENA_W1C\t(0x218)\n+#define TIM_LF_RAS_INT\t\t\t(0x300)\n+#define TIM_LF_RAS_INT_W1S\t\t(0x308)\n+#define TIM_LF_RAS_INT_ENA_W1S\t\t(0x310)\n+#define TIM_LF_RAS_INT_ENA_W1C\t\t(0x318)\n \n #define OTX2_MAX_TIM_RINGS\t\t(256)\n #define OTX2_TIM_MAX_BUCKETS\t\t(0xFFFFF)\n@@ -59,6 +67,8 @@ struct otx2_tim_evdev {\n \t/* Dev args */\n \tuint8_t disable_npa;\n \tuint16_t chunk_slots;\n+\t/* MSIX offsets */\n+\tuint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];\n };\n \n struct otx2_tim_ring {\n@@ -100,4 +110,8 @@ int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n \n void otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev);\n \n+/* TIM IRQ */\n+int tim_register_irq(uint16_t ring_id);\n+void tim_unregister_irq(uint16_t ring_id);\n+\n #endif /* __OTX2_TIM_EVDEV_H__ */\n", "prefixes": [ "33/44" ] }