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{
    "id": 54006,
    "url": "http://patches.dpdk.org/api/patches/54006/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190601182030.8282-6-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190601182030.8282-6-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190601182030.8282-6-jerinj@marvell.com",
    "date": "2019-06-01T18:20:26",
    "name": "[v1,5/9] raw/octeontx2_dma: add enqueue operation",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "a146c173d712404cef3bdac4073f6bf2220e8d8a",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190601182030.8282-6-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4846,
            "url": "http://patches.dpdk.org/api/series/4846/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4846",
            "date": "2019-06-01T18:20:21",
            "name": "OCTEON TX2 DMA driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4846/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/54006/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/54006/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
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        ],
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        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<skoteshwar@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "Date": "Sat, 1 Jun 2019 23:50:26 +0530",
        "Message-ID": "<20190601182030.8282-6-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190601182030.8282-1-jerinj@marvell.com>",
        "References": "<20190601182030.8282-1-jerinj@marvell.com>",
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        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-01_13:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v1 5/9] raw/octeontx2_dma: add enqueue operation",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nAdd enqueue operation.\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 166 ++++++++++++++++++++\n 1 file changed, 166 insertions(+)",
    "diff": "diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c\nindex e7e30825f..bfc95657b 100644\n--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c\n+++ b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c\n@@ -69,6 +69,171 @@ dma_queue_finish(struct dpi_vf_s *dpivf)\n \treturn DPI_DMA_QUEUE_SUCCESS;\n }\n \n+/* Write an arbitrary number of command words to a command queue */\n+static __rte_always_inline enum dpi_dma_queue_result_e\n+dma_queue_write(struct dpi_vf_s *dpi, uint16_t cmd_count, uint64_t *cmds)\n+{\n+\tif ((cmd_count < 1) || (cmd_count > 64))\n+\t\treturn DPI_DMA_QUEUE_INVALID_PARAM;\n+\n+\tif (cmds == NULL)\n+\t\treturn DPI_DMA_QUEUE_INVALID_PARAM;\n+\n+\t/* Room available in the current buffer for the command */\n+\tif (dpi->index + cmd_count < dpi->pool_size_m1) {\n+\t\tuint64_t *ptr = dpi->base_ptr;\n+\n+\t\tptr += dpi->index;\n+\t\tdpi->index += cmd_count;\n+\t\twhile (cmd_count--)\n+\t\t\t*ptr++ = *cmds++;\n+\t} else {\n+\t\tvoid *new_buffer;\n+\t\tuint64_t *ptr;\n+\t\tint count;\n+\n+\t\t/* Allocate new command buffer, return if failed */\n+\t\tif (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||\n+\t\t    new_buffer == NULL) {\n+\t\t\treturn DPI_DMA_QUEUE_NO_MEMORY;\n+\t\t}\n+\t\tptr = dpi->base_ptr;\n+\t\t/* Figure out how many command words will fit in this buffer.\n+\t\t * One location will be needed for the next buffer pointer.\n+\t\t **/\n+\t\tcount = dpi->pool_size_m1 - dpi->index;\n+\t\tptr += dpi->index;\n+\t\tcmd_count -= count;\n+\t\twhile (count--)\n+\t\t\t*ptr++ = *cmds++;\n+\t\t/* Chunk next ptr is 2DWORDs, second DWORD is reserved. */\n+\t\t*ptr++ = (uint64_t)new_buffer;\n+\t\t*ptr   = 0;\n+\t\t/* The current buffer is full and has a link to the next buffer.\n+\t\t * Time to write the rest of the commands into the new buffer.\n+\t\t **/\n+\t\tdpi->base_ptr = new_buffer;\n+\t\tdpi->index = cmd_count;\n+\t\tptr = new_buffer;\n+\t\twhile (cmd_count--)\n+\t\t\t*ptr++ = *cmds++;\n+\t\t/* queue index may greater than pool size */\n+\t\tif (dpi->index >= dpi->pool_size_m1) {\n+\t\t\tif (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||\n+\t\t\t    new_buffer == NULL) {\n+\t\t\t\treturn DPI_DMA_QUEUE_NO_MEMORY;\n+\t\t\t}\n+\t\t\t/* Write next buffer address */\n+\t\t\t*ptr = (uint64_t)new_buffer;\n+\t\t\tdpi->base_ptr = new_buffer;\n+\t\t\tdpi->index = 0;\n+\t\t}\n+\t}\n+\treturn DPI_DMA_QUEUE_SUCCESS;\n+}\n+\n+/* Submit a DMA command to the DMA queues. */\n+static __rte_always_inline int\n+dma_queue_submit(struct rte_rawdev *dev, uint16_t cmd_count, uint64_t *cmds)\n+{\n+\tstruct dpi_vf_s *dpivf = dev->dev_private;\n+\tenum dpi_dma_queue_result_e result;\n+\n+\tresult = dma_queue_write(dpivf, cmd_count, cmds);\n+\trte_wmb();\n+\tif (likely(result == DPI_DMA_QUEUE_SUCCESS))\n+\t\totx2_write64((uint64_t)cmd_count,\n+\t\t\t     dpivf->vf_bar0 + DPI_VDMA_DBELL);\n+\n+\treturn result;\n+}\n+\n+/* Enqueue buffers to DMA queue\n+ * returns number of buffers enqueued successfully\n+ */\n+static int\n+otx2_dpi_rawdev_enqueue_bufs(struct rte_rawdev *dev,\n+\t\t\t     struct rte_rawdev_buf **buffers,\n+\t\t\t     unsigned int count, rte_rawdev_obj_t context)\n+{\n+\tstruct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;\n+\tstruct dpi_dma_buf_ptr_s *cmd;\n+\tuint32_t c = 0;\n+\n+\tfor (c = 0; c < count; c++) {\n+\t\tuint64_t dpi_cmd[DPI_DMA_CMD_SIZE] = {0};\n+\t\tunion dpi_dma_instr_hdr_u *hdr;\n+\t\tuint16_t index = 0, i;\n+\n+\t\thdr = (union dpi_dma_instr_hdr_u *)&dpi_cmd[0];\n+\t\tcmd = (struct dpi_dma_buf_ptr_s *)buffers[c]->buf_addr;\n+\n+\t\thdr->s.xtype = ctx->xtype & DPI_XTYPE_MASK;\n+\t\thdr->s.pt = ctx->pt & DPI_HDR_PT_MASK;\n+\t\t/* Request initiated with byte write completion, but completion\n+\t\t * pointer not provided\n+\t\t */\n+\t\tif ((hdr->s.pt == DPI_HDR_PT_ZBW_CA ||\n+\t\t     hdr->s.pt == DPI_HDR_PT_ZBW_NC) && cmd->comp_ptr == NULL)\n+\t\t\treturn c;\n+\n+\t\tcmd->comp_ptr->cdata = DPI_REQ_CDATA;\n+\t\thdr->s.ptr = (uint64_t)cmd->comp_ptr;\n+\t\thdr->s.deallocv = ctx->deallocv;\n+\t\thdr->s.tt = ctx->tt & DPI_W0_TT_MASK;\n+\t\thdr->s.grp = ctx->grp & DPI_W0_GRP_MASK;\n+\n+\t\t/* If caller provides completion ring details, then only queue\n+\t\t * completion address for later polling.\n+\t\t */\n+\t\tif (ctx->c_ring) {\n+\t\t\tctx->c_ring->compl_data[ctx->c_ring->tail] =\n+\t\t\t\t\t\t\t\t cmd->comp_ptr;\n+\t\t\tSTRM_INC(ctx->c_ring);\n+\t\t}\n+\n+\t\tif (hdr->s.deallocv)\n+\t\t\thdr->s.pvfe = 1;\n+\n+\t\tif (hdr->s.pt == DPI_HDR_PT_WQP)\n+\t\t\thdr->s.ptr = hdr->s.ptr | DPI_HDR_PT_WQP_STATUSNC;\n+\n+\t\tindex += 4;\n+\t\thdr->s.fport = 0;\n+\t\thdr->s.lport = 0;\n+\n+\t\t/* For inbound case, src pointers are last pointers.\n+\t\t * For all other cases, src pointers are first pointers.\n+\t\t */\n+\t\tif (ctx->xtype ==  DPI_XTYPE_INBOUND) {\n+\t\t\thdr->s.nfst = cmd->wptr_cnt & DPI_MAX_POINTER;\n+\t\t\thdr->s.nlst = cmd->rptr_cnt & DPI_MAX_POINTER;\n+\t\t\tfor (i = 0; i < hdr->s.nfst; i++) {\n+\t\t\t\tdpi_cmd[index++] = cmd->wptr[i]->u[0];\n+\t\t\t\tdpi_cmd[index++] = cmd->wptr[i]->u[1];\n+\t\t\t}\n+\t\t\tfor (i = 0; i < hdr->s.nlst; i++) {\n+\t\t\t\tdpi_cmd[index++] = cmd->rptr[i]->u[0];\n+\t\t\t\tdpi_cmd[index++] = cmd->rptr[i]->u[1];\n+\t\t\t}\n+\t\t} else {\n+\t\t\thdr->s.nfst = cmd->rptr_cnt & DPI_MAX_POINTER;\n+\t\t\thdr->s.nlst = cmd->wptr_cnt & DPI_MAX_POINTER;\n+\t\t\tfor (i = 0; i < hdr->s.nfst; i++) {\n+\t\t\t\tdpi_cmd[index++] = cmd->rptr[i]->u[0];\n+\t\t\t\tdpi_cmd[index++] = cmd->rptr[i]->u[1];\n+\t\t\t}\n+\t\t\tfor (i = 0; i < hdr->s.nlst; i++) {\n+\t\t\t\tdpi_cmd[index++] = cmd->wptr[i]->u[0];\n+\t\t\t\tdpi_cmd[index++] = cmd->wptr[i]->u[1];\n+\t\t\t}\n+\t\t}\n+\t\tif (dma_queue_submit(dev, index, dpi_cmd))\n+\t\t\treturn c;\n+\t}\n+\treturn c;\n+}\n+\n static int\n otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config)\n {\n@@ -108,6 +273,7 @@ otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config)\n \n static const struct rte_rawdev_ops dpi_rawdev_ops = {\n \t.dev_configure = otx2_dpi_rawdev_configure,\n+\t.enqueue_bufs = otx2_dpi_rawdev_enqueue_bufs,\n };\n \n static int\n",
    "prefixes": [
        "v1",
        "5/9"
    ]
}