get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/53654/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 53654,
    "url": "http://patches.dpdk.org/api/patches/53654/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190523081339.56348-27-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190523081339.56348-27-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190523081339.56348-27-jerinj@marvell.com",
    "date": "2019-05-23T08:13:38",
    "name": "[v1,26/27] mempool/octeontx2: add devargs for max pool selection",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "75f92469dd3d4b55887df5ac4c8ab24998e6d1f5",
    "submitter": {
        "id": 1188,
        "url": "http://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190523081339.56348-27-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 4754,
            "url": "http://patches.dpdk.org/api/series/4754/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4754",
            "date": "2019-05-23T08:13:12",
            "name": "OCTEON TX2 common and mempool driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/4754/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/53654/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/53654/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id CB1DB1B9C1;\n\tThu, 23 May 2019 10:17:28 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id E3BCC1B9A6\n\tfor <dev@dpdk.org>; Thu, 23 May 2019 10:17:04 +0200 (CEST)",
            "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx4N89ev1019037; Thu, 23 May 2019 01:17:04 -0700",
            "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2smnwk0s80-15\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 23 May 2019 01:17:04 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 23 May 2019 01:16:20 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 23 May 2019 01:16:20 -0700",
            "from jerin-lab.marvell.com (unknown [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 41C873F703F;\n\tThu, 23 May 2019 01:16:19 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=4xEJY/5BkQjftI32K5M9cpH9eYN3GfgpBQsO/PJpimM=;\n\tb=EbCK/kGorM+VgNkBlOkp+0nYhKPa8almAuxLdIBdtBS8lhfArqB1kxN9CGQgcE8T0gX6\n\tk2PDBWgAVwAQnYZ220KB0qANqISWcq+1y7aWo9iHH3Iudi7Um6x7bogbFUEYsGGn7eeQ\n\tUZRZAeWWtUoQuQRPGjLuxNRxQrbl4YCTYaU3ax11JYtJCX9CEi4XE7tLJKtUic7sJSmD\n\t0t9DCQF3f3hfGhh4jQGCZPo7Tu0Eg16vEByIM88o7t+WaBKQerePhhq5uOzny3quWRqY\n\tHMtG9HuPGOiTMvVlkr5F712Qh2Ypq9SmfJs02xih5X0jolxO0GEczStkGYUAcIfEiK42\n\tAA== ",
        "From": "<jerinj@marvell.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<thomas@monjalon.net>, Jerin Jacob <jerinj@marvell.com>, Harman Kalra\n\t<hkalra@marvell.com>",
        "Date": "Thu, 23 May 2019 13:43:38 +0530",
        "Message-ID": "<20190523081339.56348-27-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190523081339.56348-1-jerinj@marvell.com>",
        "References": "<20190523081339.56348-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-05-23_08:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v1 26/27] mempool/octeontx2: add devargs for max\n\tpool selection",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThe maximum number of mempools per application needs to be configured\non HW during mempool driver initialization. HW can support up to 1M\nmempools, Since each mempool costs set of HW resources, the max_pools\ndevargs parameter is being introduced to configure the number of\nmempools required for the application.\nFor example:\n\n-w 0002:02:00.0,max_pools=512\n\nWith the above configuration, the driver will set up only 512 mempools\nfor the given application to save HW resources.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/mempool/octeontx2/otx2_mempool.c | 41 +++++++++++++++++++++++-\n 1 file changed, 40 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/mempool/octeontx2/otx2_mempool.c b/drivers/mempool/octeontx2/otx2_mempool.c\nindex 1bcb86cf4..ff7fcac85 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool.c\n+++ b/drivers/mempool/octeontx2/otx2_mempool.c\n@@ -7,6 +7,7 @@\n #include <rte_common.h>\n #include <rte_eal.h>\n #include <rte_io.h>\n+#include <rte_kvargs.h>\n #include <rte_malloc.h>\n #include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n@@ -142,6 +143,42 @@ otx2_aura_size_to_u32(uint8_t val)\n \treturn 1 << (val + 6);\n }\n \n+static int\n+parse_max_pools(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint32_t val;\n+\n+\tval = atoi(value);\n+\tif (val < otx2_aura_size_to_u32(NPA_AURA_SZ_128))\n+\t\tval = 128;\n+\tif (val > otx2_aura_size_to_u32(NPA_AURA_SZ_1M))\n+\t\tval = BIT_ULL(20);\n+\n+\t*(uint8_t *)extra_args = rte_log2_u32(val) - 6;\n+\treturn 0;\n+}\n+\n+#define OTX2_MAX_POOLS \"max_pools\"\n+\n+static uint8_t\n+otx2_parse_aura_size(struct rte_devargs *devargs)\n+{\n+\tuint8_t aura_sz = NPA_AURA_SZ_128;\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\tgoto exit;\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\tgoto exit;\n+\n+\trte_kvargs_process(kvlist, OTX2_MAX_POOLS, &parse_max_pools, &aura_sz);\n+\trte_kvargs_free(kvlist);\n+exit:\n+\treturn aura_sz;\n+}\n+\n static inline int\n npa_lf_attach(struct otx2_mbox *mbox)\n {\n@@ -234,7 +271,7 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n \t\tif (rc)\n \t\t\tgoto npa_detach;\n \n-\t\taura_sz = NPA_AURA_SZ_128;\n+\t\taura_sz = otx2_parse_aura_size(pci_dev->device.devargs);\n \t\tnr_pools = otx2_aura_size_to_u32(aura_sz);\n \n \t\tlf = &dev->npalf;\n@@ -397,3 +434,5 @@ static struct rte_pci_driver pci_npa = {\n RTE_PMD_REGISTER_PCI(mempool_octeontx2, pci_npa);\n RTE_PMD_REGISTER_PCI_TABLE(mempool_octeontx2, pci_npa_map);\n RTE_PMD_REGISTER_KMOD_DEP(mempool_octeontx2, \"vfio-pci\");\n+RTE_PMD_REGISTER_PARAM_STRING(mempool_octeontx2,\n+\t\t\t      OTX2_MAX_POOLS \"=<128-1048576>\");\n",
    "prefixes": [
        "v1",
        "26/27"
    ]
}