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GET /api/patches/53652/?format=api
{ "id": 53652, "url": "http://patches.dpdk.org/api/patches/53652/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190523081339.56348-26-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190523081339.56348-26-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190523081339.56348-26-jerinj@marvell.com", "date": "2019-05-23T08:13:37", "name": "[v1,25/27] mempool/octeontx2: add optimized dequeue operation for arm64", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "42f8a837d5f0819efc6b43ff83a584e88116a9d3", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190523081339.56348-26-jerinj@marvell.com/mbox/", "series": [ { "id": 4754, "url": "http://patches.dpdk.org/api/series/4754/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4754", "date": "2019-05-23T08:13:12", "name": "OCTEON TX2 common and mempool driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4754/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/53652/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/53652/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 320421B9C8;\n\tThu, 23 May 2019 10:17:24 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 8C44B1B999\n\tfor <dev@dpdk.org>; Thu, 23 May 2019 10:17:04 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx4N89ev0019037; Thu, 23 May 2019 01:17:03 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2smnwk0s80-14\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 23 May 2019 01:17:03 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 23 May 2019 01:16:17 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 23 May 2019 01:16:17 -0700", "from jerin-lab.marvell.com (unknown [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 2AD823F703F;\n\tThu, 23 May 2019 01:16:15 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=owiqHAYhpQ/aqBrMgBg6URLUalHkrMmorxVknBTTAcc=;\n\tb=WNj1KiDII0YJIf1EyY9d5qJsgBT3/f4N4BXfhu6zpQZheqdns7v6+yrWAyZyEgB+Y4XQ\n\tHJ2ctAoTYNOPaq69BUQFFPhqP+gxuAPKM7MuOdVHTiTD0agUy4Ih/Kw06UGHL0WJtMiV\n\tu/x5mGOlgflROclidKZdkHPcIHBbrGrkRmuKpjoxslw20Mvc5IN+ce/kMzX6RUrM/cOf\n\twJuH09QWsO03JVfmsSea+7AiwgP3ORnymlFL3d+/8EBnKc37CNUCvUeX1GaYFKqpEmuW\n\tmnHxj9lR1rD1KjtHxAlSAOQ0k1i1rR3HuJAxT9jRSzNT5VUvK9X5d7zML0LQrRERvxHW\n\tUA== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, Pavan Nikhilesh <pbhagavatula@marvell.com>,\n\t\"Olivier Matz\" <olivier.matz@6wind.com>,\n\tJerin Jacob <jerinj@marvell.com>, \n\t\"Vamsi Attunuru\" <vattunuru@marvell.com>", "Date": "Thu, 23 May 2019 13:43:37 +0530", "Message-ID": "<20190523081339.56348-26-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190523081339.56348-1-jerinj@marvell.com>", "References": "<20190523081339.56348-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-05-23_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 25/27] mempool/octeontx2: add optimized\n\tdequeue operation for arm64", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nThis patch adds an optimized arm64 instruction based routine to leverage\nCPU pipeline characteristics of octeontx2. The theme is to fill the\npipeline with CASP operations as much HW can do so that HW can do alloc()\nHW ops in full throttle.\n\nCc: Olivier Matz <olivier.matz@6wind.com>\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/mempool/octeontx2/otx2_mempool_ops.c | 291 +++++++++++++++++++\n 1 file changed, 291 insertions(+)", "diff": "diff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c b/drivers/mempool/octeontx2/otx2_mempool_ops.c\nindex c59bd73c0..ebe90d122 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool_ops.c\n+++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c\n@@ -37,6 +37,293 @@ npa_lf_aura_op_alloc_one(const int64_t wdata, int64_t * const addr,\n \treturn -ENOENT;\n }\n \n+#if defined(RTE_ARCH_ARM64)\n+static __rte_noinline int\n+npa_lf_aura_op_search_alloc(const int64_t wdata, int64_t * const addr,\n+\t\tvoid **obj_table, unsigned int n)\n+{\n+\tuint8_t i;\n+\n+\tfor (i = 0; i < n; i++) {\n+\t\tif (obj_table[i] != NULL)\n+\t\t\tcontinue;\n+\t\tif (npa_lf_aura_op_alloc_one(wdata, addr, obj_table, i))\n+\t\t\treturn -ENOENT;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static __attribute__((optimize(\"-O3\"))) __rte_noinline int __hot\n+npa_lf_aura_op_alloc_bulk(const int64_t wdata, int64_t * const addr,\n+\t\t\t unsigned int n, void **obj_table)\n+{\n+\tconst __uint128_t wdata128 = ((__uint128_t)wdata << 64) | wdata;\n+\tuint64x2_t failed = vdupq_n_u64(~0);\n+\n+\tswitch (n) {\n+\tcase 32:\n+\t{\n+\t\t__uint128_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;\n+\t\t__uint128_t t10, t11;\n+\n+\t\tasm volatile (\n+\t\t\".cpu generic+lse\\n\"\n+\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t4], %H[t4], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t5], %H[t5], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t6], %H[t6], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t7], %H[t7], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t8], %H[t8], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t9], %H[t9], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t10], %H[t10], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t11], %H[t11], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"fmov d16, %[t0]\\n\"\n+\t\t\"fmov v16.D[1], %H[t0]\\n\"\n+\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"fmov d17, %[t1]\\n\"\n+\t\t\"fmov v17.D[1], %H[t1]\\n\"\n+\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"fmov d18, %[t2]\\n\"\n+\t\t\"fmov v18.D[1], %H[t2]\\n\"\n+\t\t\"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"fmov d19, %[t3]\\n\"\n+\t\t\"fmov v19.D[1], %H[t3]\\n\"\n+\t\t\"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n+\t\t\"fmov d20, %[t4]\\n\"\n+\t\t\"fmov v20.D[1], %H[t4]\\n\"\n+\t\t\"fmov d21, %[t5]\\n\"\n+\t\t\"fmov v21.D[1], %H[t5]\\n\"\n+\t\t\"fmov d22, %[t6]\\n\"\n+\t\t\"fmov v22.D[1], %H[t6]\\n\"\n+\t\t\"fmov d23, %[t7]\\n\"\n+\t\t\"fmov v23.D[1], %H[t7]\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v20.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v21.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v22.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v23.16B\\n\"\n+\t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n+\t\t\"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\\n\"\n+\t\t\"fmov d16, %[t8]\\n\"\n+\t\t\"fmov v16.D[1], %H[t8]\\n\"\n+\t\t\"fmov d17, %[t9]\\n\"\n+\t\t\"fmov v17.D[1], %H[t9]\\n\"\n+\t\t\"fmov d18, %[t10]\\n\"\n+\t\t\"fmov v18.D[1], %H[t10]\\n\"\n+\t\t\"fmov d19, %[t11]\\n\"\n+\t\t\"fmov v19.D[1], %H[t11]\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n+\t\t\"fmov d20, %[t0]\\n\"\n+\t\t\"fmov v20.D[1], %H[t0]\\n\"\n+\t\t\"fmov d21, %[t1]\\n\"\n+\t\t\"fmov v21.D[1], %H[t1]\\n\"\n+\t\t\"fmov d22, %[t2]\\n\"\n+\t\t\"fmov v22.D[1], %H[t2]\\n\"\n+\t\t\"fmov d23, %[t3]\\n\"\n+\t\t\"fmov v23.D[1], %H[t3]\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v20.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v21.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v22.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v23.16B\\n\"\n+\t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n+\t\t\"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\\n\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n+\t\t[t0] \"=&r\" (t0), [t1] \"=&r\" (t1), [t2] \"=&r\" (t2),\n+\t\t[t3] \"=&r\" (t3), [t4] \"=&r\" (t4), [t5] \"=&r\" (t5),\n+\t\t[t6] \"=&r\" (t6), [t7] \"=&r\" (t7), [t8] \"=&r\" (t8),\n+\t\t[t9] \"=&r\" (t9), [t10] \"=&r\" (t10), [t11] \"=&r\" (t11)\n+\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n+\t\t[loc] \"r\" (addr)\n+\t\t: \"memory\", \"v16\", \"v17\", \"v18\",\n+\t\t\"v19\", \"v20\", \"v21\", \"v22\", \"v23\"\n+\t\t);\n+\t\tbreak;\n+\t}\n+\tcase 16:\n+\t{\n+\t\t__uint128_t t0, t1, t2, t3, t4, t5, t6, t7;\n+\n+\t\tasm volatile (\n+\t\t\".cpu generic+lse\\n\"\n+\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t4], %H[t4], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t5], %H[t5], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t6], %H[t6], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t7], %H[t7], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"fmov d16, %[t0]\\n\"\n+\t\t\"fmov v16.D[1], %H[t0]\\n\"\n+\t\t\"fmov d17, %[t1]\\n\"\n+\t\t\"fmov v17.D[1], %H[t1]\\n\"\n+\t\t\"fmov d18, %[t2]\\n\"\n+\t\t\"fmov v18.D[1], %H[t2]\\n\"\n+\t\t\"fmov d19, %[t3]\\n\"\n+\t\t\"fmov v19.D[1], %H[t3]\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n+\t\t\"fmov d20, %[t4]\\n\"\n+\t\t\"fmov v20.D[1], %H[t4]\\n\"\n+\t\t\"fmov d21, %[t5]\\n\"\n+\t\t\"fmov v21.D[1], %H[t5]\\n\"\n+\t\t\"fmov d22, %[t6]\\n\"\n+\t\t\"fmov v22.D[1], %H[t6]\\n\"\n+\t\t\"fmov d23, %[t7]\\n\"\n+\t\t\"fmov v23.D[1], %H[t7]\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v20.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v21.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v22.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v23.16B\\n\"\n+\t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n+\t\t\"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\\n\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n+\t\t[t0] \"=&r\" (t0), [t1] \"=&r\" (t1), [t2] \"=&r\" (t2),\n+\t\t[t3] \"=&r\" (t3), [t4] \"=&r\" (t4), [t5] \"=&r\" (t5),\n+\t\t[t6] \"=&r\" (t6), [t7] \"=&r\" (t7)\n+\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n+\t\t[loc] \"r\" (addr)\n+\t\t: \"memory\", \"v16\", \"v17\", \"v18\", \"v19\",\n+\t\t \"v20\", \"v21\", \"v22\", \"v23\"\n+\t\t);\n+\t\tbreak;\n+\t}\n+\tcase 8:\n+\t{\n+\t\t__uint128_t t0, t1, t2, t3;\n+\n+\t\tasm volatile (\n+\t\t\".cpu generic+lse\\n\"\n+\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t2], %H[t2], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t3], %H[t3], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"fmov d16, %[t0]\\n\"\n+\t\t\"fmov v16.D[1], %H[t0]\\n\"\n+\t\t\"fmov d17, %[t1]\\n\"\n+\t\t\"fmov v17.D[1], %H[t1]\\n\"\n+\t\t\"fmov d18, %[t2]\\n\"\n+\t\t\"fmov v18.D[1], %H[t2]\\n\"\n+\t\t\"fmov d19, %[t3]\\n\"\n+\t\t\"fmov v19.D[1], %H[t3]\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n+\t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n+\t\t[t0] \"=&r\" (t0), [t1] \"=&r\" (t1), [t2] \"=&r\" (t2),\n+\t\t[t3] \"=&r\" (t3)\n+\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n+\t\t[loc] \"r\" (addr)\n+\t\t: \"memory\", \"v16\", \"v17\", \"v18\", \"v19\"\n+\t\t);\n+\t\tbreak;\n+\t}\n+\tcase 4:\n+\t{\n+\t\t__uint128_t t0, t1;\n+\n+\t\tasm volatile (\n+\t\t\".cpu generic+lse\\n\"\n+\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"casp %[t1], %H[t1], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"fmov d16, %[t0]\\n\"\n+\t\t\"fmov v16.D[1], %H[t0]\\n\"\n+\t\t\"fmov d17, %[t1]\\n\"\n+\t\t\"fmov v17.D[1], %H[t1]\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n+\t\t\"st1 { v16.2d, v17.2d}, [%[dst]], 32\\n\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n+\t\t[t0] \"=&r\" (t0), [t1] \"=&r\" (t1)\n+\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n+\t\t[loc] \"r\" (addr)\n+\t\t: \"memory\", \"v16\", \"v17\"\n+\t\t);\n+\t\tbreak;\n+\t}\n+\tcase 2:\n+\t{\n+\t\t__uint128_t t0;\n+\n+\t\tasm volatile (\n+\t\t\".cpu generic+lse\\n\"\n+\t\t\"casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\\n\"\n+\t\t\"fmov d16, %[t0]\\n\"\n+\t\t\"fmov v16.D[1], %H[t0]\\n\"\n+\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n+\t\t\"st1 { v16.2d}, [%[dst]], 16\\n\"\n+\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed),\n+\t\t[t0] \"=&r\" (t0)\n+\t\t: [wdata] \"r\" (wdata128), [dst] \"r\" (obj_table),\n+\t\t[loc] \"r\" (addr)\n+\t\t: \"memory\", \"v16\"\n+\t\t);\n+\t\tbreak;\n+\t}\n+\tcase 1:\n+\t\treturn npa_lf_aura_op_alloc_one(wdata, addr, obj_table, 0);\n+\t}\n+\n+\tif (unlikely(!(((uint64_t *) &failed)[0] & ((uint64_t *) &failed)[1])))\n+\t\treturn npa_lf_aura_op_search_alloc(wdata, addr, (void **)\n+\t\t\t((char *)obj_table - (sizeof(uint64_t) * n)), n);\n+\n+\treturn 0;\n+}\n+\n+static __rte_noinline void\n+otx2_npa_clear_alloc(struct rte_mempool *mp, void **obj_table, unsigned int n)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < n; i++) {\n+\t\tif (obj_table[i] != NULL) {\n+\t\t\totx2_npa_enq(mp, &obj_table[i], 1);\n+\t\t\tobj_table[i] = NULL;\n+\t\t}\n+\t}\n+}\n+\n+static inline int __hot\n+otx2_npa_deq_arm64(struct rte_mempool *mp, void **obj_table, unsigned int n)\n+{\n+\tconst int64_t wdata = npa_lf_aura_handle_to_aura(mp->pool_id);\n+\tvoid **obj_table_bak = obj_table;\n+\tconst unsigned int nfree = n;\n+\tunsigned int parts;\n+\n+\tint64_t * const addr = (int64_t * const)\n+\t\t\t(npa_lf_aura_handle_to_base(mp->pool_id) +\n+\t\t\t\tNPA_LF_AURA_OP_ALLOCX(0));\n+\twhile (n) {\n+\t\tparts = n > 31 ? 32 : rte_align32prevpow2(n);\n+\t\tn -= parts;\n+\t\tif (unlikely(npa_lf_aura_op_alloc_bulk(wdata, addr,\n+\t\t\t\tparts, obj_table))) {\n+\t\t\totx2_npa_clear_alloc(mp, obj_table_bak, nfree - n);\n+\t\t\treturn -ENOENT;\n+\t\t}\n+\t\tobj_table += parts;\n+\t}\n+\n+\treturn 0;\n+}\n+#endif\n+\n static inline int __hot\n otx2_npa_deq(struct rte_mempool *mp, void **obj_table, unsigned int n)\n {\n@@ -463,7 +750,11 @@ static struct rte_mempool_ops otx2_npa_ops = {\n \t.get_count = otx2_npa_get_count,\n \t.calc_mem_size = otx2_npa_calc_mem_size,\n \t.populate = otx2_npa_populate,\n+#if defined(RTE_ARCH_ARM64)\n+\t.dequeue = otx2_npa_deq_arm64,\n+#else\n \t.dequeue = otx2_npa_deq,\n+#endif\n };\n \n MEMPOOL_REGISTER_OPS(otx2_npa_ops);\n", "prefixes": [ "v1", "25/27" ] }