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GET /api/patches/53646/?format=api
{ "id": 53646, "url": "http://patches.dpdk.org/api/patches/53646/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190523081339.56348-11-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190523081339.56348-11-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190523081339.56348-11-jerinj@marvell.com", "date": "2019-05-23T08:13:22", "name": "[v1,10/27] common/octeontx2: add AF to PF mailbox IRQ and msg handlers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a447f0dbd82f1833911b8f0c3729d4ad541e829e", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190523081339.56348-11-jerinj@marvell.com/mbox/", "series": [ { "id": 4754, "url": "http://patches.dpdk.org/api/series/4754/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4754", "date": "2019-05-23T08:13:12", "name": "OCTEON TX2 common and mempool driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4754/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/53646/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/53646/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id EF4C61B95B;\n\tThu, 23 May 2019 10:17:01 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 9E1921B94B\n\tfor <dev@dpdk.org>; Thu, 23 May 2019 10:16:51 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx4N8F29v021710; Thu, 23 May 2019 01:16:50 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2sneqj28r6-6\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 23 May 2019 01:16:50 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 23 May 2019 01:15:32 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 23 May 2019 01:15:32 -0700", "from jerin-lab.marvell.com (unknown [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id 18CD53F703F;\n\tThu, 23 May 2019 01:15:30 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=umkiU3pPJXW5HrgdsN6oDC+3zoxFbpljFnk8yVsrn8A=;\n\tb=EDl0003woL8iHNE6trgaO6+Z3g6x3dkZT5UtsD6JFcSoEpr+cuyebGtE5EeReiu3s1fX\n\towxWVjYZLYrwtII6BZ8g4gQfxi8NaRfmS7EFmqsXFf2ryo+Ihvp7VaFpcEEj7FOWap7k\n\tlDYlOJh1nIPXqAsQxQpJ63tvH4rjgrSox1WqfAM4Nw97t+c7JjrXJFUqAuQxs1T7AJFh\n\tJMSa3P0MkNXmueLtJpwFgOoSpZLPJi4JsbnQUCs8P7M8//xnvt5nBXyO24upQrRbVuis\n\tPUv489qMKm27ruPhhLuOC2aSlqaSH6k0JAnLGeyo+av9XKWNaBQBwcKIWV1ISB6p+UPV\n\tKw== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, Nithin Dabilpuram <ndabilpuram@marvell.com>,\n\t\"Vamsi Attunuru\" <vattunuru@marvell.com>", "Date": "Thu, 23 May 2019 13:43:22 +0530", "Message-ID": "<20190523081339.56348-11-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190523081339.56348-1-jerinj@marvell.com>", "References": "<20190523081339.56348-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-05-23_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 10/27] common/octeontx2: add AF to PF mailbox\n\tIRQ and msg handlers", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Nithin Dabilpuram <ndabilpuram@marvell.com>\n\nThis patch adds support for AF to PF mailbox interrupt and message\nhandling. PF writes the message on mapped mailbox region\nfollowed by writing the mailbox doorbell register. Upon receiving,\nthe mailbox request in AF(In Linux kernel), It processes the messages\nand update the counter memory and update the AF mbox doorbell\nregister. That would trigger a VFIO interrupt to userspace and\notx2_process_msgs() will handle it.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\n---\n drivers/common/octeontx2/otx2_dev.c | 120 +++++++++++++++++++++++++++-\n 1 file changed, 119 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/octeontx2/otx2_dev.c b/drivers/common/octeontx2/otx2_dev.c\nindex 59bd988d1..ba4fd9547 100644\n--- a/drivers/common/octeontx2/otx2_dev.c\n+++ b/drivers/common/octeontx2/otx2_dev.c\n@@ -14,6 +14,9 @@\n #include \"otx2_dev.h\"\n #include \"otx2_mbox.h\"\n \n+#define RVU_MAX_VF\t\t64 /* RVU_PF_VFPF_MBOX_INT(0..1) */\n+#define RVU_MAX_INT_RETRY\t3\n+\n /* PF/VF message handling timer */\n #define VF_PF_MBOX_TIMER_MS\t(20 * 1000)\n \n@@ -47,6 +50,108 @@ mbox_mem_unmap(void *va, size_t size)\n \t\tmunmap(va, size);\n }\n \n+static void\n+otx2_process_msgs(struct otx2_dev *dev, struct otx2_mbox *mbox)\n+{\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n+\tstruct mbox_hdr *req_hdr;\n+\tstruct mbox_msghdr *msg;\n+\tint msgs_acked = 0;\n+\tint offset;\n+\tuint16_t i;\n+\n+\treq_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n+\tif (req_hdr->num_msgs == 0)\n+\t\treturn;\n+\n+\toffset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);\n+\tfor (i = 0; i < req_hdr->num_msgs; i++) {\n+\t\tmsg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n+\n+\t\tmsgs_acked++;\n+\t\totx2_base_dbg(\"Message 0x%x (%s) pf:%d/vf:%d\",\n+\t\t\t msg->id, otx2_mbox_id2name(msg->id),\n+\t\t\t otx2_get_pf(msg->pcifunc),\n+\t\t\t otx2_get_vf(msg->pcifunc));\n+\n+\t\tswitch (msg->id) {\n+\t\t\t/* Add message id's that are handled here */\n+\t\tcase MBOX_MSG_READY:\n+\t\t\t/* Get our identity */\n+\t\t\tdev->pf_func = msg->pcifunc;\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\tif (msg->rc)\n+\t\t\t\totx2_err(\"Message (%s) response has err=%d\",\n+\t\t\t\t\t otx2_mbox_id2name(msg->id), msg->rc);\n+\t\t\tbreak;\n+\t\t}\n+\t\toffset = mbox->rx_start + msg->next_msgoff;\n+\t}\n+\n+\totx2_mbox_reset(mbox, 0);\n+\t/* Update acked if someone is waiting a message */\n+\tmdev->msgs_acked = msgs_acked;\n+\trte_wmb();\n+}\n+\n+static void\n+otx2_af_pf_mbox_irq(void *param)\n+{\n+\tstruct otx2_dev *dev = param;\n+\tuint64_t intr;\n+\n+\tintr = otx2_read64(dev->bar2 + RVU_PF_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\totx2_write64(intr, dev->bar2 + RVU_PF_INT);\n+\n+\totx2_base_dbg(\"Irq 0x%\" PRIx64 \"(pf:%d,vf:%d)\", intr, dev->pf, dev->vf);\n+\tif (intr)\n+\t\t/* First process all configuration messages */\n+\t\totx2_process_msgs(dev, dev->mbox);\n+}\n+\n+static int\n+mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\tint rc;\n+\n+\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);\n+\n+\tdev->timer_set = 0;\n+\n+\t/* MBOX interrupt AF <-> PF */\n+\trc = otx2_register_irq(intr_handle, otx2_af_pf_mbox_irq,\n+\t\t\t dev, RVU_PF_INT_VEC_AFPF_MBOX);\n+\tif (rc) {\n+\t\totx2_err(\"Fail to register AF<->PF mbox irq\");\n+\t\treturn rc;\n+\t}\n+\n+\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT);\n+\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);\n+\n+\treturn rc;\n+}\n+\n+static void\n+mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n+{\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n+\n+\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);\n+\n+\tdev->timer_set = 0;\n+\n+\t/* MBOX interrupt AF <-> PF */\n+\totx2_unregister_irq(intr_handle, otx2_af_pf_mbox_irq, dev,\n+\t\t\t RVU_PF_INT_VEC_AFPF_MBOX);\n+}\n+\n static void\n otx2_update_pass_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n {\n@@ -120,10 +225,15 @@ otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n \tif (rc)\n \t\tgoto error;\n \n+\t/* Register mbox interrupts */\n+\trc = mbox_register_irq(pci_dev, dev);\n+\tif (rc)\n+\t\tgoto mbox_fini;\n+\n \t/* Check the readiness of PF/VF */\n \trc = otx2_send_ready_msg(dev->mbox, &dev->pf_func);\n \tif (rc)\n-\t\tgoto mbox_fini;\n+\t\tgoto mbox_unregister;\n \n \tdev->pf = otx2_get_pf(dev->pf_func);\n \tdev->vf = otx2_get_vf(dev->pf_func);\n@@ -162,6 +272,8 @@ otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n \n iounmap:\n \tmbox_mem_unmap(hwbase, MBOX_SIZE * pci_dev->max_vfs);\n+mbox_unregister:\n+\tmbox_unregister_irq(pci_dev, dev);\n mbox_fini:\n \totx2_mbox_fini(dev->mbox);\n \totx2_mbox_fini(&dev->mbox_up);\n@@ -176,6 +288,7 @@ otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n void\n otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev)\n {\n+\tstruct rte_intr_handle *intr_handle = &pci_dev->intr_handle;\n \tstruct otx2_dev *dev = otx2_dev;\n \tstruct otx2_idev_cfg *idev;\n \tstruct otx2_mbox *mbox;\n@@ -185,6 +298,8 @@ otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev)\n \tif (idev->npa_lf && idev->npa_lf->pci_dev == pci_dev)\n \t\tidev->npa_lf = NULL;\n \n+\tmbox_unregister_irq(pci_dev, dev);\n+\n \t/* Release PF - VF */\n \tmbox = &dev->mbox_vfpf;\n \tif (mbox->hwbase && mbox->dev)\n@@ -200,4 +315,7 @@ otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev)\n \tmbox = &dev->mbox_up;\n \totx2_mbox_fini(mbox);\n \tdev->mbox_active = 0;\n+\n+\t/* Disable MSIX vectors */\n+\totx2_disable_irqs(intr_handle);\n }\n", "prefixes": [ "v1", "10/27" ] }