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GET /api/patches/53638/?format=api
{ "id": 53638, "url": "http://patches.dpdk.org/api/patches/53638/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190523081339.56348-3-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190523081339.56348-3-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190523081339.56348-3-jerinj@marvell.com", "date": "2019-05-23T08:13:14", "name": "[v1,02/27] common/octeontx2: add IO handling APIs", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "30841cb5a18910d287b690c04dd122dc81f82b23", "submitter": { "id": 1188, "url": "http://patches.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": null, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190523081339.56348-3-jerinj@marvell.com/mbox/", "series": [ { "id": 4754, "url": "http://patches.dpdk.org/api/series/4754/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4754", "date": "2019-05-23T08:13:12", "name": "OCTEON TX2 common and mempool driver", "version": 1, "mbox": "http://patches.dpdk.org/series/4754/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/53638/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/53638/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B92591B949;\n\tThu, 23 May 2019 10:16:09 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 76020493D\n\tfor <dev@dpdk.org>; Thu, 23 May 2019 10:16:08 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx4N89euj019037; Thu, 23 May 2019 01:16:07 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2smnwk0s7y-3\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 23 May 2019 01:16:07 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 23 May 2019 01:15:06 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 23 May 2019 01:15:06 -0700", "from jerin-lab.marvell.com (unknown [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id D08C73F7040;\n\tThu, 23 May 2019 01:15:04 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=JYDhz2UKFEH8oF6chFr7y9Sa0uejul/AhTH8sKDDYG4=;\n\tb=uPyt1Nxu0oI3mP4tbZrbP00q4P70Sl7mYVhjmxOhsAj/8AJt8+e+seCQyAttZzipT3Lt\n\tin9qGArQ4lQyejT/GoLriKhO1cInRv8F8hOAf6+ePpATRFPDonAPTnQbJHTvvtxiAU+p\n\tlLzxQjUVEa/mVeDJW6yMwXre/0WznNHy3eLZQ6ISq37VISYygvLZhRlnkRQbiJb3RW4c\n\tRH1NV2zJA5Ko/uUNGoM833I2y/Cugqb/oeP0lvJ0lUG5wc6AzPEDndvigA7diol50HHq\n\th4iGjGvL6ZBLxKaGoyIzAdUzI6hGvl2cjIsUbinU3Npx3iQIkAdyph88cIeHZm6RbWdc\n\tVw== ", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, Jerin Jacob <jerinj@marvell.com>,\n\tNithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "Date": "Thu, 23 May 2019 13:43:14 +0530", "Message-ID": "<20190523081339.56348-3-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190523081339.56348-1-jerinj@marvell.com>", "References": "<20190523081339.56348-1-jerinj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-05-23_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v1 02/27] common/octeontx2: add IO handling APIs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nVarious octeontx2 drivers use IO handling API, added octeontx2\nspecific IO handling routines in the common code.\n\nSince some of those implementations are based on arm64 instructions\nadded the stub to compile the code on non arm64 ISA.\nThe non arm64 ISA stub is possible due to the fact that\nit is an integrated controller i.e runs only on Marvell HW.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/common/octeontx2/otx2_common.h | 12 +++\n drivers/common/octeontx2/otx2_io_arm64.h | 95 ++++++++++++++++++++++\n drivers/common/octeontx2/otx2_io_generic.h | 63 ++++++++++++++\n 3 files changed, 170 insertions(+)\n create mode 100644 drivers/common/octeontx2/otx2_io_arm64.h\n create mode 100644 drivers/common/octeontx2/otx2_io_generic.h", "diff": "diff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h\nindex b4e008b14..b0c19266b 100644\n--- a/drivers/common/octeontx2/otx2_common.h\n+++ b/drivers/common/octeontx2/otx2_common.h\n@@ -6,6 +6,8 @@\n #define _OTX2_COMMON_H_\n \n #include <rte_common.h>\n+#include <rte_io.h>\n+#include <rte_memory.h>\n \n #include \"hw/otx2_rvu.h\"\n #include \"hw/otx2_nix.h\"\n@@ -31,4 +33,14 @@\n #define __hot __attribute__((hot))\n #endif\n \n+/* IO Access */\n+#define otx2_read64(addr) rte_read64_relaxed((void *)(addr))\n+#define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))\n+\n+#if defined(RTE_ARCH_ARM64)\n+#include \"otx2_io_arm64.h\"\n+#else\n+#include \"otx2_io_generic.h\"\n+#endif\n+\n #endif /* _OTX2_COMMON_H_ */\ndiff --git a/drivers/common/octeontx2/otx2_io_arm64.h b/drivers/common/octeontx2/otx2_io_arm64.h\nnew file mode 100644\nindex 000000000..468243c04\n--- /dev/null\n+++ b/drivers/common/octeontx2/otx2_io_arm64.h\n@@ -0,0 +1,95 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_IO_ARM64_H_\n+#define _OTX2_IO_ARM64_H_\n+\n+#define otx2_load_pair(val0, val1, addr) ({\t\t\\\n+\tasm volatile(\t\t\t\t\t\\\n+\t\"ldp %x[x0], %x[x1], [%x[p1]]\"\t\t\t\\\n+\t:[x0]\"=r\"(val0), [x1]\"=r\"(val1)\t\t\t\\\n+\t:[p1]\"r\"(addr)\t\t\t\t\t\\\n+\t); })\n+\n+#define otx2_store_pair(val0, val1, addr) ({\t\t\\\n+\tasm volatile(\t\t\t\t\t\\\n+\t\"stp %x[x0], %x[x1], [%x[p1]]\"\t\t\t\\\n+\t::[x0]\"r\"(val0), [x1]\"r\"(val1), [p1]\"r\"(addr)\t\\\n+\t); })\n+\n+#define otx2_prefetch_store_keep(ptr) ({\\\n+\tasm volatile(\"prfm pstl1keep, [%x0]\\n\" : : \"r\" (ptr)); })\n+\n+static __rte_always_inline uint64_t\n+otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr)\n+{\n+\tuint64_t result;\n+\n+\t/* Atomic add with no ordering */\n+\tasm volatile (\n+\t\t\".cpu generic+lse\\n\"\n+\t\t\"ldadd %x[i], %x[r], [%[b]]\"\n+\t\t: [r] \"=r\" (result), \"+m\" (*ptr)\n+\t\t: [i] \"r\" (incr), [b] \"r\" (ptr)\n+\t\t: \"memory\");\n+\treturn result;\n+}\n+\n+static __rte_always_inline uint64_t\n+otx2_atomic64_add_sync(int64_t incr, int64_t *ptr)\n+{\n+\tuint64_t result;\n+\n+\t/* Atomic add with ordering */\n+\tasm volatile (\n+\t\t\".cpu generic+lse\\n\"\n+\t\t\"ldadda %x[i], %x[r], [%[b]]\"\n+\t\t: [r] \"=r\" (result), \"+m\" (*ptr)\n+\t\t: [i] \"r\" (incr), [b] \"r\" (ptr)\n+\t\t: \"memory\");\n+\treturn result;\n+}\n+\n+static __rte_always_inline uint64_t\n+otx2_lmt_submit(rte_iova_t io_address)\n+{\n+\tuint64_t result;\n+\n+\tasm volatile (\n+\t\t\".cpu generic+lse\\n\"\n+\t\t\"ldeor xzr,%x[rf],[%[rs]]\" :\n+\t\t [rf] \"=r\"(result): [rs] \"r\"(io_address));\n+\treturn result;\n+}\n+\n+static __rte_always_inline void\n+otx2_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n+{\n+\tvolatile const __uint128_t *src128 = (const __uint128_t *)in;\n+\tvolatile __uint128_t *dst128 = (__uint128_t *)out;\n+\tdst128[0] = src128[0];\n+\tdst128[1] = src128[1];\n+\t/* lmtext receives following value:\n+\t * 1: NIX_SUBDC_EXT needed i.e. tx vlan case\n+\t * 2: NIX_SUBDC_EXT + NIX_SUBDC_MEM i.e. tstamp case\n+\t */\n+\tif (lmtext) {\n+\t\tdst128[2] = src128[2];\n+\t\tif (lmtext > 1)\n+\t\t\tdst128[3] = src128[3];\n+\t}\n+}\n+\n+static __rte_always_inline void\n+otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)\n+{\n+\tvolatile const __uint128_t *src128 = (const __uint128_t *)in;\n+\tvolatile __uint128_t *dst128 = (__uint128_t *)out;\n+\tuint8_t i;\n+\n+\tfor (i = 0; i < segdw; i++)\n+\t\tdst128[i] = src128[i];\n+}\n+\n+#endif /* _OTX2_IO_ARM64_H_ */\ndiff --git a/drivers/common/octeontx2/otx2_io_generic.h b/drivers/common/octeontx2/otx2_io_generic.h\nnew file mode 100644\nindex 000000000..b1d754008\n--- /dev/null\n+++ b/drivers/common/octeontx2/otx2_io_generic.h\n@@ -0,0 +1,63 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_IO_GENERIC_H_\n+#define _OTX2_IO_GENERIC_H_\n+\n+#define otx2_load_pair(val0, val1, addr)\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\\\n+\tval0 = rte_read64_relaxed((void *)(addr));\t\t\\\n+\tval1 = rte_read64_relaxed((uint8_t *)(addr) + 8);\t\\\n+} while (0)\n+\n+#define otx2_store_pair(val0, val1, addr)\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\\\n+\trte_write64_relaxed(val0, (void *)(addr));\t\t\\\n+\trte_write64_relaxed(val1, (((uint8_t *)(addr)) + 8));\t\\\n+} while (0)\n+\n+#define otx2_prefetch_store_keep(ptr) do {} while (0)\n+\n+static inline uint64_t\n+otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr)\n+{\n+\tRTE_SET_USED(ptr);\n+\tRTE_SET_USED(incr);\n+\n+\treturn 0;\n+}\n+\n+static inline uint64_t\n+otx2_atomic64_add_sync(int64_t incr, int64_t *ptr)\n+{\n+\tRTE_SET_USED(ptr);\n+\tRTE_SET_USED(incr);\n+\n+\treturn 0;\n+}\n+\n+static inline int64_t\n+otx2_lmt_submit(uint64_t io_address)\n+{\n+\tRTE_SET_USED(io_address);\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline void\n+otx2_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n+{\n+\tRTE_SET_USED(out);\n+\tRTE_SET_USED(in);\n+\tRTE_SET_USED(lmtext);\n+}\n+\n+static __rte_always_inline void\n+otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)\n+{\n+\tRTE_SET_USED(out);\n+\tRTE_SET_USED(in);\n+\tRTE_SET_USED(segdw);\n+}\n+#endif /* _OTX2_IO_GENERIC_H_ */\n", "prefixes": [ "v1", "02/27" ] }