Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/53444/?format=api
{ "id": 53444, "url": "http://patches.dpdk.org/api/patches/53444/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190515180817.71523-5-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190515180817.71523-5-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190515180817.71523-5-ajit.khaparde@broadcom.com", "date": "2019-05-15T18:08:15", "name": "[4/6] net/bnxt: fix a couple of issues with Tx batching", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "00cf8505ca543926c86424d575f5b081c1089c27", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190515180817.71523-5-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 4678, "url": "http://patches.dpdk.org/api/series/4678/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4678", "date": "2019-05-15T18:08:11", "name": "bnxt patchset for Tx performance optimization", "version": 1, "mbox": "http://patches.dpdk.org/series/4678/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/53444/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/53444/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 217965F28;\n\tWed, 15 May 2019 20:08:30 +0200 (CEST)", "from rnd-relay.smtp.broadcom.com (rnd-relay.smtp.broadcom.com\n\t[192.19.229.170]) by dpdk.org (Postfix) with ESMTP id BBC9D5B36\n\tfor <dev@dpdk.org>; Wed, 15 May 2019 20:08:24 +0200 (CEST)", "from nis-sj1-27.broadcom.com (nis-sj1-27.lvn.broadcom.net\n\t[10.75.144.136])\n\tby rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id 7FF3D30C0B1;\n\tWed, 15 May 2019 11:08:22 -0700 (PDT)", "from C02VPB22HTD6.wifi.broadcom.net (c02vpb22htd6.wifi.broadcom.net\n\t[10.69.74.102])\n\tby nis-sj1-27.broadcom.com (Postfix) with ESMTP id 5CD9BAC07C0;\n\tWed, 15 May 2019 11:08:23 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com 7FF3D30C0B1", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n\ts=dkimrelay; t=1557943702;\n\tbh=bndTDeJfGFvI3ctLU1bh9giJHGBCV7VOo4H6B7NNYEk=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=lUKzmWo/2iN4ShpVr2QETWrLAxA8qqZn/zuACeZ5jLiJM/XCojXKhlNvnrVZLrx2q\n\tLYL07uSFXp2J8AOcM2D8VVZ46USHmZsBB8z4SrleUbgxwXrIn9aehyfAhfYH6jixAD\n\thg7NEMN3S+RYw/SaHpyAzWmQa2rmJg21tNdA+1bA=", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com,\n\tSriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>,\n\tAjit Kumar Khaparde <ajit.khaparde@broadcom.com>", "Date": "Wed, 15 May 2019 11:08:15 -0700", "Message-Id": "<20190515180817.71523-5-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.20.1 (Apple Git-117)", "In-Reply-To": "<20190515180817.71523-1-ajit.khaparde@broadcom.com>", "References": "<20190515180817.71523-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 4/6] net/bnxt: fix a couple of issues with Tx\n\tbatching", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>\n\nThis patch addresses the following issues with Tx batching:\n\n1. Tx stall observed in some conditions:\n\nThe batching code doesn't request for a completion when only a partial\nchain of packets is transmitted due to mbuf allocation errors. Because\nof this, Tx consumer index is not updated correctly and it eventually\nleads to qfull condition. Fix this by requesting a completion for the\nlast packet in the partial chain that is transmitted successfully.\n\n2. Tx stall seen with Jumbo frames:\n\nWith jumbo frames, number of TxBDs is > 1. While setting up these\nadditional BDs in bnxt_start_xmit(), the flags field is being set using\nthe OR-assignment operator. We end up using a stale value of the flags\nfield (from a previous use of that descriptor). This results in an\ninvalid completion and eventually leads to tx stall. Fix this to just\nassign the flags field with the right value.\n\nFixes: 5735eb241947 (\"net/bnxt: support Tx batching\")\nSigned-off-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>\nReviewed-by: Ajit Kumar Khaparde <ajit.khaparde@broadcom.com>\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/bnxt_txq.h | 1 -\n drivers/net/bnxt/bnxt_txr.c | 57 ++++++++++++++++++++++---------------\n 2 files changed, 34 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt_txq.h b/drivers/net/bnxt/bnxt_txq.h\nindex f2c712a75..720ca90cf 100644\n--- a/drivers/net/bnxt/bnxt_txq.h\n+++ b/drivers/net/bnxt/bnxt_txq.h\n@@ -24,7 +24,6 @@ struct bnxt_tx_queue {\n \tuint8_t\t\t\twthresh; /* Write-back threshold reg */\n \tuint32_t\t\tctx_curr; /* Hardware context states */\n \tuint8_t\t\t\ttx_deferred_start; /* not in global dev start */\n-\tuint8_t\t\t\tcmpl_next; /* Next BD to trigger a compl */\n \n \tstruct bnxt\t\t*bp;\n \tint\t\t\tindex;\ndiff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c\nindex 9684fb177..186934136 100644\n--- a/drivers/net/bnxt/bnxt_txr.c\n+++ b/drivers/net/bnxt/bnxt_txr.c\n@@ -103,26 +103,33 @@ int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id)\n \treturn 0;\n }\n \n-static inline uint32_t bnxt_tx_avail(struct bnxt_tx_ring_info *txr)\n+static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)\n+{\n+\treturn ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &\n+\t\ttxq->tx_ring->tx_ring_struct->ring_mask);\n+}\n+\n+static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)\n {\n \t/* Tell compiler to fetch tx indices from memory. */\n \trte_compiler_barrier();\n \n-\treturn txr->tx_ring_struct->ring_size -\n-\t\t((txr->tx_prod - txr->tx_cons) &\n-\t\t\ttxr->tx_ring_struct->ring_mask) - 1;\n+\treturn ((txq->tx_ring->tx_ring_struct->ring_size -\n+\t\t bnxt_tx_bds_in_hw(txq)) - 1);\n }\n \n static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,\n \t\t\t\tstruct bnxt_tx_queue *txq,\n \t\t\t\tuint16_t *coal_pkts,\n-\t\t\t\tuint16_t *cmpl_next)\n+\t\t\t\tuint16_t *cmpl_next,\n+\t\t\t\tstruct tx_bd_long **last_txbd)\n {\n \tstruct bnxt_tx_ring_info *txr = txq->tx_ring;\n \tstruct tx_bd_long *txbd;\n \tstruct tx_bd_long_hi *txbd1 = NULL;\n \tuint32_t vlan_tag_flags, cfa_action;\n \tbool long_bd = false;\n+\tunsigned short nr_bds = 0;\n \tstruct rte_mbuf *m_seg;\n \tstruct bnxt_sw_tx_bd *tx_buf;\n \tstatic const uint32_t lhint_arr[4] = {\n@@ -139,15 +146,14 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,\n \t\t\t\tPKT_TX_TUNNEL_GENEVE))\n \t\tlong_bd = true;\n \n-\ttx_buf = &txr->tx_buf_ring[txr->tx_prod];\n-\ttx_buf->mbuf = tx_pkt;\n-\ttx_buf->nr_bds = long_bd + tx_pkt->nb_segs;\n+\tnr_bds = long_bd + tx_pkt->nb_segs;\n+\tif (unlikely(bnxt_tx_avail(txq) < nr_bds))\n+\t\treturn -ENOMEM;\n \n \t/* Check if number of Tx descriptors is above HW limit */\n-\tif (unlikely(tx_buf->nr_bds > BNXT_MAX_TSO_SEGS)) {\n+\tif (unlikely(nr_bds > BNXT_MAX_TSO_SEGS)) {\n \t\tPMD_DRV_LOG(ERR,\n-\t\t\t \"Num descriptors %d exceeds HW limit\\n\",\n-\t\t\t tx_buf->nr_bds);\n+\t\t\t \"Num descriptors %d exceeds HW limit\\n\", nr_bds);\n \t\treturn -ENOSPC;\n \t}\n \n@@ -170,12 +176,13 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,\n \t/* Check non zero data_len */\n \tRTE_VERIFY(tx_pkt->data_len);\n \n-\tif (unlikely(bnxt_tx_avail(txr) < tx_buf->nr_bds))\n-\t\treturn -ENOMEM;\n+\ttx_buf = &txr->tx_buf_ring[txr->tx_prod];\n+\ttx_buf->mbuf = tx_pkt;\n+\ttx_buf->nr_bds = nr_bds;\n \n \ttxbd = &txr->tx_desc_ring[txr->tx_prod];\n \ttxbd->opaque = *coal_pkts;\n-\ttxbd->flags_type = tx_buf->nr_bds << TX_BD_LONG_FLAGS_BD_CNT_SFT;\n+\ttxbd->flags_type = nr_bds << TX_BD_LONG_FLAGS_BD_CNT_SFT;\n \ttxbd->flags_type |= TX_BD_SHORT_FLAGS_COAL_NOW;\n \tif (!*cmpl_next) {\n \t\ttxbd->flags_type |= TX_BD_LONG_FLAGS_NO_CMPL;\n@@ -189,6 +196,7 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,\n \telse\n \t\ttxbd->flags_type |= lhint_arr[tx_pkt->pkt_len >> 9];\n \ttxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova(tx_buf->mbuf));\n+\t*last_txbd = txbd;\n \n \tif (long_bd) {\n \t\ttxbd->flags_type |= TX_BD_LONG_TYPE_TX_BD_LONG;\n@@ -321,7 +329,7 @@ static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,\n \n \t\ttxbd = &txr->tx_desc_ring[txr->tx_prod];\n \t\ttxbd->address = rte_cpu_to_le_64(rte_mbuf_data_iova(m_seg));\n-\t\ttxbd->flags_type |= TX_BD_SHORT_TYPE_TX_BD_SHORT;\n+\t\ttxbd->flags_type = TX_BD_SHORT_TYPE_TX_BD_SHORT;\n \t\ttxbd->len = m_seg->data_len;\n \n \t\tm_seg = m_seg->next;\n@@ -371,8 +379,7 @@ static int bnxt_handle_tx_cp(struct bnxt_tx_queue *txq)\n \tuint32_t ring_mask = cp_ring_struct->ring_mask;\n \tuint32_t opaque = 0;\n \n-\tif (((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &\n-\t\ttxq->tx_ring->tx_ring_struct->ring_mask) < txq->tx_free_thresh)\n+\tif (bnxt_tx_bds_in_hw(txq) < txq->tx_free_thresh)\n \t\treturn 0;\n \n \tdo {\n@@ -411,7 +418,8 @@ uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tstruct bnxt_tx_queue *txq = tx_queue;\n \tuint16_t nb_tx_pkts = 0;\n \tuint16_t coal_pkts = 0;\n-\tuint16_t cmpl_next = txq->cmpl_next;\n+\tuint16_t cmpl_next = 0;\n+\tstruct tx_bd_long *last_txbd = NULL;\n \n \t/* Handle TX completions */\n \tbnxt_handle_tx_cp(txq);\n@@ -422,20 +430,23 @@ uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\treturn 0;\n \t}\n \n-\ttxq->cmpl_next = 0;\n \t/* Handle TX burst request */\n \tfor (nb_tx_pkts = 0; nb_tx_pkts < nb_pkts; nb_tx_pkts++) {\n \t\tint rc;\n \n-\t\t/* Request a completion on first and last packet */\n+\t\t/* Request a completion on the last packet */\n \t\tcmpl_next |= (nb_pkts == nb_tx_pkts + 1);\n \t\tcoal_pkts++;\n \t\trc = bnxt_start_xmit(tx_pkts[nb_tx_pkts], txq,\n-\t\t\t\t&coal_pkts, &cmpl_next);\n+\t\t\t\t &coal_pkts, &cmpl_next, &last_txbd);\n \n \t\tif (unlikely(rc)) {\n-\t\t\t/* Request a completion in next cycle */\n-\t\t\ttxq->cmpl_next = 1;\n+\t\t\t/* Request a completion on the last successfully\n+\t\t\t * enqueued packet\n+\t\t\t */\n+\t\t\tif (last_txbd)\n+\t\t\t\tlast_txbd->flags_type &=\n+\t\t\t\t\t~TX_BD_LONG_FLAGS_NO_CMPL;\n \t\t\tbreak;\n \t\t}\n \t}\n", "prefixes": [ "4/6" ] }