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GET /api/patches/52765/?format=api
{ "id": 52765, "url": "http://patches.dpdk.org/api/patches/52765/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1555276357-4892-4-git-send-email-orika@mellanox.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1555276357-4892-4-git-send-email-orika@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1555276357-4892-4-git-send-email-orika@mellanox.com", "date": "2019-04-14T21:12:31", "name": "[3/9] net/mlx5: add Direct Rules configuration support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4e6d638201ef9b8869eed01077beca305cd71a3f", "submitter": { "id": 795, "url": "http://patches.dpdk.org/api/people/795/?format=api", "name": "Ori Kam", "email": "orika@mellanox.com" }, "delegate": { "id": 6624, "url": "http://patches.dpdk.org/api/users/6624/?format=api", "username": "shahafs", "first_name": "Shahaf", "last_name": "Shuler", "email": "shahafs@mellanox.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1555276357-4892-4-git-send-email-orika@mellanox.com/mbox/", "series": [ { "id": 4308, "url": "http://patches.dpdk.org/api/series/4308/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=4308", "date": "2019-04-14T21:12:28", "name": "net/mlx5: add Direct Verbs E-Switch support", "version": 1, "mbox": "http://patches.dpdk.org/series/4308/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/52765/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/52765/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A03C75F17;\n\tSun, 14 Apr 2019 23:13:23 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 80BBF5B2C\n\tfor <dev@dpdk.org>; Sun, 14 Apr 2019 23:13:08 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\torika@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 15 Apr 2019 00:13:02 +0300", "from pegasus03.mtr.labs.mlnx (pegasus03.mtr.labs.mlnx\n\t[10.210.16.124])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x3ELD10n027116;\n\tMon, 15 Apr 2019 00:13:01 +0300" ], "From": "Ori Kam <orika@mellanox.com>", "To": "yskoh@mellanox.com, shahafs@mellanox.com, matan@mellanox.com,\n\tviacheslavo@mellanox.com, motih@mellanox.com", "Cc": "dev@dpdk.org, orika@mellanox.com", "Date": "Sun, 14 Apr 2019 21:12:31 +0000", "Message-Id": "<1555276357-4892-4-git-send-email-orika@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1555276357-4892-1-git-send-email-orika@mellanox.com>", "References": "<1555276357-4892-1-git-send-email-orika@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 3/9] net/mlx5: add Direct Rules configuration\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit provides the basic configuration needed in order to\nsupport Direct Rules eswitch.\n\nSigned-off-by: Ori Kam <orika@mellanox.com>\n---\n drivers/net/mlx5/Makefile | 5 +\n drivers/net/mlx5/meson.build | 2 +\n drivers/net/mlx5/mlx5.c | 52 +++++-\n drivers/net/mlx5/mlx5.h | 12 ++\n drivers/net/mlx5/mlx5_devx_cmds.c | 42 +++++\n drivers/net/mlx5/mlx5_flow.c | 2 +-\n drivers/net/mlx5/mlx5_prm.h | 328 ++++++++++++++++++++++++++++++++++++++\n 7 files changed, 437 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/Makefile b/drivers/net/mlx5/Makefile\nindex 93bc869..2b72a33 100644\n--- a/drivers/net/mlx5/Makefile\n+++ b/drivers/net/mlx5/Makefile\n@@ -161,6 +161,11 @@ mlx5_autoconf.h.new: $(RTE_SDK)/buildtools/auto-config-h.sh\n \t\tenum MLX5DV_DR_NS_TYPE_TERMINATING \\\n \t\t$(AUTOCONF_OUTPUT)\n \t$Q sh -- '$<' '$@' \\\n+\t\tHAVE_MLX5DV_DR_ESWITCH \\\n+\t\tinfiniband/mlx5dv.h \\\n+\t\tenum MLX5DV_DR_NS_DOMAIN_FDB_BYPASS \\\n+\t\t$(AUTOCONF_OUTPUT)\n+\t$Q sh -- '$<' '$@' \\\n \t\tHAVE_IBV_DEVX_OBJ \\\n \t\tinfiniband/mlx5dv.h \\\n \t\tfunc mlx5dv_devx_obj_create \\\ndiff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build\nindex 0037e15..9dfd28d 100644\n--- a/drivers/net/mlx5/meson.build\n+++ b/drivers/net/mlx5/meson.build\n@@ -113,6 +113,8 @@ if build\n \t\t'MLX5DV_FLOW_ACTION_COUNTERS_DEVX' ],\n \t\t[ 'HAVE_MLX5DV_DR', 'infiniband/mlx5dv.h',\n \t\t'MLX5DV_DR_NS_TYPE_TERMINATING' ],\n+\t\t[ 'HAVE_MLX5DV_DR_ESWITCH', 'infiniband/mlx5dv.h',\n+\t\t'MLX5DV_DR_NS_DOMAIN_FDB_BYPASS' ],\n \t\t[ 'HAVE_SUPPORTED_40000baseKR4_Full', 'linux/ethtool.h',\n \t\t'SUPPORTED_40000baseKR4_Full' ],\n \t\t[ 'HAVE_SUPPORTED_40000baseCR4_Full', 'linux/ethtool.h',\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 9ff50df..938ba1c 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -101,6 +101,9 @@\n /* Allow L3 VXLAN flow creation. */\n #define MLX5_L3_VXLAN_EN \"l3_vxlan_en\"\n \n+/* Activate DV eswitch flow steering. */\n+#define MLX5_DV_ESWITCH_EN \"dv_eswitch_en\"\n+\n /* Activate DV flow steering. */\n #define MLX5_DV_FLOW_EN \"dv_flow_en\"\n \n@@ -344,6 +347,18 @@ struct mlx5_dev_spawn_data {\n \t}\n \tpthread_mutex_init(&sh->dv_mutex, NULL);\n \tsh->tx_ns = ns;\n+#ifdef HAVE_MLX5DV_DR_ESWITCH\n+\tif (priv->config.dv_eswitch_en) {\n+\t\tns = mlx5_glue->dr_create_ns(sh->ctx,\n+\t\t\t\t\t MLX5DV_DR_NS_DOMAIN_FDB_BYPASS);\n+\t\tif (!ns) {\n+\t\t\tDRV_LOG(ERR, \"FDB mlx5dv_dr_create_ns failed\");\n+\t\t\terr = errno;\n+\t\t\tgoto error;\n+\t\t}\n+\t\tsh->fdb_ns = ns;\n+\t}\n+#endif\n \tsh->dv_refcnt++;\n \tpriv->dr_shared = 1;\n \treturn 0;\n@@ -358,6 +373,10 @@ struct mlx5_dev_spawn_data {\n \t\tmlx5dv_dr_destroy_ns(sh->tx_ns);\n \t\tsh->tx_ns = NULL;\n \t}\n+\tif (sh->fdb_ns) {\n+\t\tmlx5_glue->dr_destroy_ns(sh->fdb_ns);\n+\t\tsh->fdb_ns = NULL;\n+\t}\n \treturn err;\n #else\n \t(void)priv;\n@@ -393,6 +412,12 @@ struct mlx5_dev_spawn_data {\n \t\tmlx5dv_dr_destroy_ns(sh->tx_ns);\n \t\tsh->tx_ns = NULL;\n \t}\n+#ifdef HAVE_MLX5DV_DR_ESWITCH\n+\tif (sh->fdb_ns) {\n+\t\tmlx5_glue->dr_destroy_ns(sh->fdb_ns);\n+\t\tsh->fdb_ns = NULL;\n+\t}\n+#endif\n \tpthread_mutex_destroy(&sh->dv_mutex);\n #else\n \t(void)priv;\n@@ -861,6 +886,8 @@ struct mlx5_dev_spawn_data {\n \t\tconfig->l3_vxlan_en = !!tmp;\n \t} else if (strcmp(MLX5_VF_NL_EN, key) == 0) {\n \t\tconfig->vf_nl_en = !!tmp;\n+\t} else if (strcmp(MLX5_DV_ESWITCH_EN, key) == 0) {\n+\t\tconfig->dv_eswitch_en = !!tmp;\n \t} else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {\n \t\tconfig->dv_flow_en = !!tmp;\n \t} else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {\n@@ -905,6 +932,7 @@ struct mlx5_dev_spawn_data {\n \t\tMLX5_RX_VEC_EN,\n \t\tMLX5_L3_VXLAN_EN,\n \t\tMLX5_VF_NL_EN,\n+\t\tMLX5_DV_ESWITCH_EN,\n \t\tMLX5_DV_FLOW_EN,\n \t\tMLX5_MR_EXT_MEMSEG_EN,\n \t\tMLX5_REPRESENTOR,\n@@ -1458,11 +1486,6 @@ struct mlx5_dev_spawn_data {\n \t\t\tpriv->tcf_context = NULL;\n \t\t}\n \t}\n-\tif (config.dv_flow_en) {\n-\t\terr = mlx5_alloc_shared_dr(priv);\n-\t\tif (err)\n-\t\t\tgoto error;\n-\t}\n \tTAILQ_INIT(&priv->flows);\n \tTAILQ_INIT(&priv->ctrl_flows);\n \t/* Hint libmlx5 to use PMD allocator for data plane resources */\n@@ -1484,8 +1507,26 @@ struct mlx5_dev_spawn_data {\n \t * Verbs context returned by ibv_open_device().\n \t */\n \tmlx5_link_update(eth_dev, 0);\n+#ifdef HAVE_IBV_DEVX_OBJ\n+\terr = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);\n+\tif (err) {\n+\t\terr = -err;\n+\t\tgoto error;\n+\t}\n+#endif\n+#ifdef HAVE_MLX5DV_DR_ESWITCH\n+\tif (!config.hca_attr.eswitch_manager)\n+\t\tconfig.dv_eswitch_en = 0;\n+#else\n+\tconfig.dv_eswitch_en = 0;\n+#endif\n \t/* Store device configuration on private structure. */\n \tpriv->config = config;\n+\tif (config.dv_flow_en) {\n+\t\terr = mlx5_alloc_shared_dr(priv);\n+\t\tif (err)\n+\t\t\tgoto error;\n+\t}\n \t/* Supported Verbs flow priority number detection. */\n \terr = mlx5_flow_discover_priorities(eth_dev);\n \tif (err < 0) {\n@@ -1876,6 +1917,7 @@ struct mlx5_dev_spawn_data {\n \t\t\t.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,\n \t\t\t.min_rxqs_num = MLX5_MPRQ_MIN_RXQS,\n \t\t},\n+\t\t.dv_eswitch_en = 1,\n \t};\n \t/* Device specific configuration. */\n \tswitch (pci_dev->id.device_id) {\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 14c7f3c..33a4127 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -138,6 +138,11 @@ struct mlx5_devx_counter_set {\n \tint id; /* Flow counter ID */\n };\n \n+/* HCA attributes. */\n+struct mlx5_hca_attr {\n+\tuint32_t eswitch_manager:1;\n+};\n+\n /* Flow list . */\n TAILQ_HEAD(mlx5_flows, rte_flow);\n \n@@ -171,6 +176,7 @@ struct mlx5_dev_config {\n \t/* Whether memseg should be extended for MR creation. */\n \tunsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */\n \tunsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */\n+\tunsigned int dv_eswitch_en:1; /* Enable eswitch DV flow. */\n \tunsigned int dv_flow_en:1; /* Enable DV flow. */\n \tunsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */\n \tunsigned int devx:1; /* Whether devx interface is available or not. */\n@@ -192,6 +198,7 @@ struct mlx5_dev_config {\n \tint txqs_inline; /* Queue number threshold for inlining. */\n \tint txqs_vec; /* Queue number threshold for vectorized Tx. */\n \tint inline_max_packet_sz; /* Max packet size for inlining. */\n+\tstruct mlx5_hca_attr hca_attr; /* HCA attributes. */\n };\n \n /**\n@@ -241,6 +248,7 @@ struct mlx5_flow_tbl_resource {\n };\n \n #define MLX5_MAX_TABLES 1024\n+#define MLX5_MAX_TABLES_FDB 32\n #define MLX5_GROUP_FACTOR 1\n \n /*\n@@ -260,6 +268,8 @@ struct mlx5_ibv_shared {\n \t/* Shared DV/DR flow data section. */\n \tpthread_mutex_t dv_mutex; /* DV context mutex. */\n \tuint32_t dv_refcnt; /* DV/DR data reference counter. */\n+\tvoid *fdb_ns; /* FDB Direct Rules name space handle. */\n+\tstruct mlx5_flow_tbl_resource fdb_tbl[MLX5_MAX_TABLES_FDB];\n \tvoid *rx_ns; /* RX Direct Rules name space handle. */\n \tstruct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES];\n \t/* RX Direct Rules tables. */\n@@ -539,4 +549,6 @@ int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,\n int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx,\n \t\t\t\t int clear,\n \t\t\t\t uint64_t *pkts, uint64_t *bytes);\n+int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,\n+\t\t\t\t struct mlx5_hca_attr *attr);\n #endif /* RTE_PMD_MLX5_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c\nindex a9dff58..3caea41 100644\n--- a/drivers/net/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.c\n@@ -105,3 +105,45 @@ int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj)\n \t*bytes = MLX5_GET64(traffic_counter, stats, octets);\n \treturn 0;\n }\n+\n+/**\n+ * Query HCA attributes.\n+ *\n+ * @param[in] ctx\n+ * ibv contexts returned from mlx5dv_open_device.\n+ * @param[out] attr\n+ * Attributes device values.\n+ *\n+ * @return\n+ * 0 on success, a negative value otherwise.\n+ */\n+int\n+mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,\n+\t\t\t struct mlx5_hca_attr *attr)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};\n+\tvoid *hcattr;\n+\tint status, syndrome, rc;\n+\n+\tMLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);\n+\tMLX5_SET(query_hca_cap_in, in, op_mod,\n+\t\t MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |\n+\t\t MLX5_HCA_CAP_OPMOD_GET_CUR);\n+\n+\trc = mlx5_glue->devx_general_cmd(ctx,\n+\t\t\t\t\t in, sizeof(in), out, sizeof(out));\n+\tif (rc)\n+\t\treturn rc;\n+\tstatus = MLX5_GET(query_hca_cap_out, out, status);\n+\tsyndrome = MLX5_GET(query_hca_cap_out, out, syndrome);\n+\tif (status) {\n+\t\tDRV_LOG(DEBUG, \"Failed to query devx HCA capabilities, \"\n+\t\t\t\"status %x, syndrome = %x\",\n+\t\t\tstatus, syndrome);\n+\t\treturn -1;\n+\t}\n+\thcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n+\tattr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);\n+\treturn 0;\n+}\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex a0683ee..83abc14 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -1784,7 +1784,7 @@ uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tenum mlx5_flow_drv_type type = MLX5_FLOW_TYPE_MAX;\n \n-\tif (attr->transfer)\n+\tif (attr->transfer && !priv->config.dv_eswitch_en)\n \t\ttype = MLX5_FLOW_TYPE_TCF;\n \telse\n \t\ttype = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV :\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex b15266f..b25d4e8 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -529,6 +529,7 @@ enum {\n };\n \n enum {\n+\tMLX5_CMD_OP_QUERY_HCA_CAP = 0x100,\n \tMLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,\n \tMLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,\n };\n@@ -591,6 +592,333 @@ struct mlx5_ifc_query_flow_counter_in_bits {\n \tu8 flow_counter_id[0x20];\n };\n \n+enum {\n+\tMLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,\n+\tMLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,\n+};\n+\n+enum {\n+\tMLX5_HCA_CAP_OPMOD_GET_MAX = 0,\n+\tMLX5_HCA_CAP_OPMOD_GET_CUR = 1,\n+};\n+\n+struct mlx5_ifc_cmd_hca_cap_bits {\n+\tu8 reserved_at_0[0x30];\n+\tu8 vhca_id[0x10];\n+\tu8 reserved_at_40[0x40];\n+\tu8 log_max_srq_sz[0x8];\n+\tu8 log_max_qp_sz[0x8];\n+\tu8 reserved_at_90[0xb];\n+\tu8 log_max_qp[0x5];\n+\tu8 reserved_at_a0[0xb];\n+\tu8 log_max_srq[0x5];\n+\tu8 reserved_at_b0[0x10];\n+\tu8 reserved_at_c0[0x8];\n+\tu8 log_max_cq_sz[0x8];\n+\tu8 reserved_at_d0[0xb];\n+\tu8 log_max_cq[0x5];\n+\tu8 log_max_eq_sz[0x8];\n+\tu8 reserved_at_e8[0x2];\n+\tu8 log_max_mkey[0x6];\n+\tu8 reserved_at_f0[0x8];\n+\tu8 dump_fill_mkey[0x1];\n+\tu8 reserved_at_f9[0x3];\n+\tu8 log_max_eq[0x4];\n+\tu8 max_indirection[0x8];\n+\tu8 fixed_buffer_size[0x1];\n+\tu8 log_max_mrw_sz[0x7];\n+\tu8 force_teardown[0x1];\n+\tu8 reserved_at_111[0x1];\n+\tu8 log_max_bsf_list_size[0x6];\n+\tu8 umr_extended_translation_offset[0x1];\n+\tu8 null_mkey[0x1];\n+\tu8 log_max_klm_list_size[0x6];\n+\tu8 reserved_at_120[0xa];\n+\tu8 log_max_ra_req_dc[0x6];\n+\tu8 reserved_at_130[0xa];\n+\tu8 log_max_ra_res_dc[0x6];\n+\tu8 reserved_at_140[0xa];\n+\tu8 log_max_ra_req_qp[0x6];\n+\tu8 reserved_at_150[0xa];\n+\tu8 log_max_ra_res_qp[0x6];\n+\tu8 end_pad[0x1];\n+\tu8 cc_query_allowed[0x1];\n+\tu8 cc_modify_allowed[0x1];\n+\tu8 start_pad[0x1];\n+\tu8 cache_line_128byte[0x1];\n+\tu8 reserved_at_165[0xa];\n+\tu8 qcam_reg[0x1];\n+\tu8 gid_table_size[0x10];\n+\tu8 out_of_seq_cnt[0x1];\n+\tu8 vport_counters[0x1];\n+\tu8 retransmission_q_counters[0x1];\n+\tu8 debug[0x1];\n+\tu8 modify_rq_counter_set_id[0x1];\n+\tu8 rq_delay_drop[0x1];\n+\tu8 max_qp_cnt[0xa];\n+\tu8 pkey_table_size[0x10];\n+\tu8 vport_group_manager[0x1];\n+\tu8 vhca_group_manager[0x1];\n+\tu8 ib_virt[0x1];\n+\tu8 eth_virt[0x1];\n+\tu8 vnic_env_queue_counters[0x1];\n+\tu8 ets[0x1];\n+\tu8 nic_flow_table[0x1];\n+\tu8 eswitch_manager[0x1];\n+\tu8 device_memory[0x1];\n+\tu8 mcam_reg[0x1];\n+\tu8 pcam_reg[0x1];\n+\tu8 local_ca_ack_delay[0x5];\n+\tu8 port_module_event[0x1];\n+\tu8 enhanced_error_q_counters[0x1];\n+\tu8 ports_check[0x1];\n+\tu8 reserved_at_1b3[0x1];\n+\tu8 disable_link_up[0x1];\n+\tu8 beacon_led[0x1];\n+\tu8 port_type[0x2];\n+\tu8 num_ports[0x8];\n+\tu8 reserved_at_1c0[0x1];\n+\tu8 pps[0x1];\n+\tu8 pps_modify[0x1];\n+\tu8 log_max_msg[0x5];\n+\tu8 reserved_at_1c8[0x4];\n+\tu8 max_tc[0x4];\n+\tu8 temp_warn_event[0x1];\n+\tu8 dcbx[0x1];\n+\tu8 general_notification_event[0x1];\n+\tu8 reserved_at_1d3[0x2];\n+\tu8 fpga[0x1];\n+\tu8 rol_s[0x1];\n+\tu8 rol_g[0x1];\n+\tu8 reserved_at_1d8[0x1];\n+\tu8 wol_s[0x1];\n+\tu8 wol_g[0x1];\n+\tu8 wol_a[0x1];\n+\tu8 wol_b[0x1];\n+\tu8 wol_m[0x1];\n+\tu8 wol_u[0x1];\n+\tu8 wol_p[0x1];\n+\tu8 stat_rate_support[0x10];\n+\tu8 reserved_at_1f0[0xc];\n+\tu8 cqe_version[0x4];\n+\tu8 compact_address_vector[0x1];\n+\tu8 striding_rq[0x1];\n+\tu8 reserved_at_202[0x1];\n+\tu8 ipoib_enhanced_offloads[0x1];\n+\tu8 ipoib_basic_offloads[0x1];\n+\tu8 reserved_at_205[0x1];\n+\tu8 repeated_block_disabled[0x1];\n+\tu8 umr_modify_entity_size_disabled[0x1];\n+\tu8 umr_modify_atomic_disabled[0x1];\n+\tu8 umr_indirect_mkey_disabled[0x1];\n+\tu8 umr_fence[0x2];\n+\tu8 reserved_at_20c[0x3];\n+\tu8 drain_sigerr[0x1];\n+\tu8 cmdif_checksum[0x2];\n+\tu8 sigerr_cqe[0x1];\n+\tu8 reserved_at_213[0x1];\n+\tu8 wq_signature[0x1];\n+\tu8 sctr_data_cqe[0x1];\n+\tu8 reserved_at_216[0x1];\n+\tu8 sho[0x1];\n+\tu8 tph[0x1];\n+\tu8 rf[0x1];\n+\tu8 dct[0x1];\n+\tu8 qos[0x1];\n+\tu8 eth_net_offloads[0x1];\n+\tu8 roce[0x1];\n+\tu8 atomic[0x1];\n+\tu8 reserved_at_21f[0x1];\n+\tu8 cq_oi[0x1];\n+\tu8 cq_resize[0x1];\n+\tu8 cq_moderation[0x1];\n+\tu8 reserved_at_223[0x3];\n+\tu8 cq_eq_remap[0x1];\n+\tu8 pg[0x1];\n+\tu8 block_lb_mc[0x1];\n+\tu8 reserved_at_229[0x1];\n+\tu8 scqe_break_moderation[0x1];\n+\tu8 cq_period_start_from_cqe[0x1];\n+\tu8 cd[0x1];\n+\tu8 reserved_at_22d[0x1];\n+\tu8 apm[0x1];\n+\tu8 vector_calc[0x1];\n+\tu8 umr_ptr_rlky[0x1];\n+\tu8\t imaicl[0x1];\n+\tu8 reserved_at_232[0x4];\n+\tu8 qkv[0x1];\n+\tu8 pkv[0x1];\n+\tu8 set_deth_sqpn[0x1];\n+\tu8 reserved_at_239[0x3];\n+\tu8 xrc[0x1];\n+\tu8 ud[0x1];\n+\tu8 uc[0x1];\n+\tu8 rc[0x1];\n+\tu8 uar_4k[0x1];\n+\tu8 reserved_at_241[0x9];\n+\tu8 uar_sz[0x6];\n+\tu8 reserved_at_250[0x8];\n+\tu8 log_pg_sz[0x8];\n+\tu8 bf[0x1];\n+\tu8 driver_version[0x1];\n+\tu8 pad_tx_eth_packet[0x1];\n+\tu8 reserved_at_263[0x8];\n+\tu8 log_bf_reg_size[0x5];\n+\tu8 reserved_at_270[0xb];\n+\tu8 lag_master[0x1];\n+\tu8 num_lag_ports[0x4];\n+\tu8 reserved_at_280[0x10];\n+\tu8 max_wqe_sz_sq[0x10];\n+\tu8 reserved_at_2a0[0x10];\n+\tu8 max_wqe_sz_rq[0x10];\n+\tu8 max_flow_counter_31_16[0x10];\n+\tu8 max_wqe_sz_sq_dc[0x10];\n+\tu8 reserved_at_2e0[0x7];\n+\tu8 max_qp_mcg[0x19];\n+\tu8 reserved_at_300[0x10];\n+\tu8 flow_counter_bulk_alloc[0x08];\n+\tu8 log_max_mcg[0x8];\n+\tu8 reserved_at_320[0x3];\n+\tu8 log_max_transport_domain[0x5];\n+\tu8 reserved_at_328[0x3];\n+\tu8 log_max_pd[0x5];\n+\tu8 reserved_at_330[0xb];\n+\tu8 log_max_xrcd[0x5];\n+\tu8 nic_receive_steering_discard[0x1];\n+\tu8 receive_discard_vport_down[0x1];\n+\tu8 transmit_discard_vport_down[0x1];\n+\tu8 reserved_at_343[0x5];\n+\tu8 log_max_flow_counter_bulk[0x8];\n+\tu8 max_flow_counter_15_0[0x10];\n+\tu8 reserved_at_360[0x3];\n+\tu8 log_max_rq[0x5];\n+\tu8 reserved_at_368[0x3];\n+\tu8 log_max_sq[0x5];\n+\tu8 reserved_at_370[0x3];\n+\tu8 log_max_tir[0x5];\n+\tu8 reserved_at_378[0x3];\n+\tu8 log_max_tis[0x5];\n+\tu8 basic_cyclic_rcv_wqe[0x1];\n+\tu8 reserved_at_381[0x2];\n+\tu8 log_max_rmp[0x5];\n+\tu8 reserved_at_388[0x3];\n+\tu8 log_max_rqt[0x5];\n+\tu8 reserved_at_390[0x3];\n+\tu8 log_max_rqt_size[0x5];\n+\tu8 reserved_at_398[0x3];\n+\tu8 log_max_tis_per_sq[0x5];\n+\tu8 ext_stride_num_range[0x1];\n+\tu8 reserved_at_3a1[0x2];\n+\tu8 log_max_stride_sz_rq[0x5];\n+\tu8 reserved_at_3a8[0x3];\n+\tu8 log_min_stride_sz_rq[0x5];\n+\tu8 reserved_at_3b0[0x3];\n+\tu8 log_max_stride_sz_sq[0x5];\n+\tu8 reserved_at_3b8[0x3];\n+\tu8 log_min_stride_sz_sq[0x5];\n+\tu8 hairpin[0x1];\n+\tu8 reserved_at_3c1[0x2];\n+\tu8 log_max_hairpin_queues[0x5];\n+\tu8 reserved_at_3c8[0x3];\n+\tu8 log_max_hairpin_wq_data_sz[0x5];\n+\tu8 reserved_at_3d0[0x3];\n+\tu8 log_max_hairpin_num_packets[0x5];\n+\tu8 reserved_at_3d8[0x3];\n+\tu8 log_max_wq_sz[0x5];\n+\tu8 nic_vport_change_event[0x1];\n+\tu8 disable_local_lb_uc[0x1];\n+\tu8 disable_local_lb_mc[0x1];\n+\tu8 log_min_hairpin_wq_data_sz[0x5];\n+\tu8 reserved_at_3e8[0x3];\n+\tu8 log_max_vlan_list[0x5];\n+\tu8 reserved_at_3f0[0x3];\n+\tu8 log_max_current_mc_list[0x5];\n+\tu8 reserved_at_3f8[0x3];\n+\tu8 log_max_current_uc_list[0x5];\n+\tu8 general_obj_types[0x40];\n+\tu8 reserved_at_440[0x20];\n+\tu8 reserved_at_460[0x10];\n+\tu8 max_num_eqs[0x10];\n+\tu8 reserved_at_480[0x3];\n+\tu8 log_max_l2_table[0x5];\n+\tu8 reserved_at_488[0x8];\n+\tu8 log_uar_page_sz[0x10];\n+\tu8 reserved_at_4a0[0x20];\n+\tu8 device_frequency_mhz[0x20];\n+\tu8 device_frequency_khz[0x20];\n+\tu8 reserved_at_500[0x20];\n+\tu8\t num_of_uars_per_page[0x20];\n+\tu8 flex_parser_protocols[0x20];\n+\tu8 reserved_at_560[0x20];\n+\tu8 reserved_at_580[0x3c];\n+\tu8 mini_cqe_resp_stride_index[0x1];\n+\tu8 cqe_128_always[0x1];\n+\tu8 cqe_compression_128[0x1];\n+\tu8 cqe_compression[0x1];\n+\tu8 cqe_compression_timeout[0x10];\n+\tu8 cqe_compression_max_num[0x10];\n+\tu8 reserved_at_5e0[0x10];\n+\tu8 tag_matching[0x1];\n+\tu8 rndv_offload_rc[0x1];\n+\tu8 rndv_offload_dc[0x1];\n+\tu8 log_tag_matching_list_sz[0x5];\n+\tu8 reserved_at_5f8[0x3];\n+\tu8 log_max_xrq[0x5];\n+\tu8\t affiliate_nic_vport_criteria[0x8];\n+\tu8\t native_port_num[0x8];\n+\tu8\t num_vhca_ports[0x8];\n+\tu8\t reserved_at_618[0x6];\n+\tu8\t sw_owner_id[0x1];\n+\tu8\t reserved_at_61f[0x1e1];\n+};\n+\n+struct mlx5_ifc_qos_cap_bits {\n+\tu8 packet_pacing[0x1];\n+\tu8 esw_scheduling[0x1];\n+\tu8 esw_bw_share[0x1];\n+\tu8 esw_rate_limit[0x1];\n+\tu8 reserved_at_4[0x1];\n+\tu8 packet_pacing_burst_bound[0x1];\n+\tu8 packet_pacing_typical_size[0x1];\n+\tu8 flow_meter_srtcm[0x1];\n+\tu8 reserved_at_8[0x8];\n+\tu8 log_max_flow_meter[0x8];\n+\tu8 flow_meter_reg_id[0x8];\n+\tu8 reserved_at_25[0x20];\n+\tu8 packet_pacing_max_rate[0x20];\n+\tu8 packet_pacing_min_rate[0x20];\n+\tu8 reserved_at_80[0x10];\n+\tu8 packet_pacing_rate_table_size[0x10];\n+\tu8 esw_element_type[0x10];\n+\tu8 esw_tsar_type[0x10];\n+\tu8 reserved_at_c0[0x10];\n+\tu8 max_qos_para_vport[0x10];\n+\tu8 max_tsar_bw_share[0x20];\n+\tu8 reserved_at_100[0x6e8];\n+};\n+\n+union mlx5_ifc_hca_cap_union_bits {\n+\tstruct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;\n+\tstruct mlx5_ifc_qos_cap_bits qos_cap;\n+\tu8 reserved_at_0[0x8000];\n+};\n+\n+struct mlx5_ifc_query_hca_cap_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x40];\n+\tunion mlx5_ifc_hca_cap_union_bits capability;\n+};\n+\n+struct mlx5_ifc_query_hca_cap_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 reserved_at_10[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0x40];\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \n", "prefixes": [ "3/9" ] }