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GET /api/patches/51696/?format=api
{ "id": 51696, "url": "http://patches.dpdk.org/api/patches/51696/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1553581011-94181-9-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1553581011-94181-9-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1553581011-94181-9-git-send-email-wenzhuo.lu@intel.com", "date": "2019-03-26T06:16:51", "name": "[v7,8/8] net/ice: support vector AVX2 in TX", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f45ad192c33897bcc2614f9387a6bc78b78c3f39", "submitter": { "id": 258, "url": "http://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1553581011-94181-9-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 3914, "url": "http://patches.dpdk.org/api/series/3914/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=3914", "date": "2019-03-26T06:16:43", "name": "Support vector instructions on ICE", "version": 7, "mbox": "http://patches.dpdk.org/series/3914/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/51696/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/51696/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5DB9956A3;\n\tTue, 26 Mar 2019 07:11:46 +0100 (CET)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby dpdk.org (Postfix) with ESMTP id B872B3256\n\tfor <dev@dpdk.org>; Tue, 26 Mar 2019 07:11:26 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Mar 2019 23:11:25 -0700", "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby fmsmga001.fm.intel.com with ESMTP; 25 Mar 2019 23:11:25 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.60,271,1549958400\"; d=\"scan'208\";a=\"158420152\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "Date": "Tue, 26 Mar 2019 14:16:51 +0800", "Message-Id": "<1553581011-94181-9-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1553581011-94181-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1551340136-83843-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1553581011-94181-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v7 8/8] net/ice: support vector AVX2 in TX", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n doc/guides/nics/ice.rst | 18 ++++\n doc/guides/rel_notes/release_19_05.rst | 4 +\n drivers/net/ice/ice_rxtx.c | 13 ++-\n drivers/net/ice/ice_rxtx.h | 2 +\n drivers/net/ice/ice_rxtx_vec_avx2.c | 158 +++++++++++++++++++++++++++++++++\n 5 files changed, 193 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst\nindex 3998d5e..fdbc02e 100644\n--- a/doc/guides/nics/ice.rst\n+++ b/doc/guides/nics/ice.rst\n@@ -64,6 +64,24 @@ Driver compilation and testing\n Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`\n for details.\n \n+Features\n+--------\n+\n+Vector PMD\n+~~~~~~~~~~\n+\n+Vector PMD for RX and TX path are selected automatically. The paths\n+are chosen based on 2 conditions.\n+\n+- ``CPU``\n+ On the X86 platform, the driver checks if the CPU supports AVX2.\n+ If it's supported, AVX2 paths will be chosen. If not, SSE is chosen.\n+\n+- ``Offload features``\n+ The supported HW offload features are described in the document ice_vec.ini.\n+ If any not supported features are used, ICE vector PMD is disabled and the\n+ normal paths are chosen.\n+\n Sample Application Notes\n ------------------------\n \ndiff --git a/doc/guides/rel_notes/release_19_05.rst b/doc/guides/rel_notes/release_19_05.rst\nindex 6f76de3..fbea42f 100644\n--- a/doc/guides/rel_notes/release_19_05.rst\n+++ b/doc/guides/rel_notes/release_19_05.rst\n@@ -96,6 +96,10 @@ New Features\n Improved testpmd application performance on ARM platform. For ``macswap``\n forwarding mode, NEON intrinsics were used to do swap to save CPU cycles.\n \n+* **Added support of vector instructions on ICE.**\n+\n+ Added support of SSE and AVX2 instructions in ICE RX and TX path.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c\nindex 860155f..5264055 100644\n--- a/drivers/net/ice/ice_rxtx.c\n+++ b/drivers/net/ice/ice_rxtx.c\n@@ -2356,15 +2356,24 @@ void __attribute__((cold))\n #ifdef RTE_ARCH_X86\n \tstruct ice_tx_queue *txq;\n \tint i;\n+\tbool use_avx2 = false;\n \n \tif (!ice_tx_vec_dev_check(dev)) {\n \t\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n \t\t\ttxq = dev->data->tx_queues[i];\n \t\t\t(void)ice_txq_vec_setup(txq);\n \t\t}\n-\t\tPMD_DRV_LOG(DEBUG, \"Using Vector Tx (port %d).\",\n+\n+\t\tif (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||\n+\t\t rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)\n+\t\t\tuse_avx2 = true;\n+\n+\t\tPMD_DRV_LOG(DEBUG, \"Using %sVector Tx (port %d).\",\n+\t\t\t use_avx2 ? \"avx2 \" : \"\",\n \t\t\t dev->data->port_id);\n-\t\tdev->tx_pkt_burst = ice_xmit_pkts_vec;\n+\t\tdev->tx_pkt_burst = use_avx2 ?\n+\t\t\t\t ice_xmit_pkts_vec_avx2 :\n+\t\t\t\t ice_xmit_pkts_vec;\n \t\tdev->tx_pkt_prepare = NULL;\n \n \t\treturn;\ndiff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h\nindex dfc3224..64e9f20 100644\n--- a/drivers/net/ice/ice_rxtx.h\n+++ b/drivers/net/ice/ice_rxtx.h\n@@ -184,4 +184,6 @@ uint16_t ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,\n uint16_t ice_recv_scattered_pkts_vec_avx2(void *rx_queue,\n \t\t\t\t\t struct rte_mbuf **rx_pkts,\n \t\t\t\t\t uint16_t nb_pkts);\n+uint16_t ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t\tuint16_t nb_pkts);\n #endif /* _ICE_RXTX_H_ */\ndiff --git a/drivers/net/ice/ice_rxtx_vec_avx2.c b/drivers/net/ice/ice_rxtx_vec_avx2.c\nindex 2459ff3..fac869a 100644\n--- a/drivers/net/ice/ice_rxtx_vec_avx2.c\n+++ b/drivers/net/ice/ice_rxtx_vec_avx2.c\n@@ -684,3 +684,161 @@\n \treturn retval + ice_recv_scattered_burst_vec_avx2(rx_queue,\n \t\t\t\trx_pkts + retval, nb_pkts);\n }\n+\n+static inline void\n+ice_vtx1(volatile struct ice_tx_desc *txdp,\n+\t struct rte_mbuf *pkt, uint64_t flags)\n+{\n+\tuint64_t high_qw =\n+\t\t(ICE_TX_DESC_DTYPE_DATA |\n+\t\t ((uint64_t)flags << ICE_TXD_QW1_CMD_S) |\n+\t\t ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));\n+\n+\t__m128i descriptor = _mm_set_epi64x(high_qw,\n+\t\t\t\tpkt->buf_physaddr + pkt->data_off);\n+\t_mm_store_si128((__m128i *)txdp, descriptor);\n+}\n+\n+static inline void\n+ice_vtx(volatile struct ice_tx_desc *txdp,\n+\tstruct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)\n+{\n+\tconst uint64_t hi_qw_tmpl = (ICE_TX_DESC_DTYPE_DATA |\n+\t\t\t((uint64_t)flags << ICE_TXD_QW1_CMD_S));\n+\n+\t/* if unaligned on 32-bit boundary, do one to align */\n+\tif (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {\n+\t\tice_vtx1(txdp, *pkt, flags);\n+\t\tnb_pkts--, txdp++, pkt++;\n+\t}\n+\n+\t/* do two at a time while possible, in bursts */\n+\tfor (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {\n+\t\tuint64_t hi_qw3 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[3]->data_len <<\n+\t\t\t ICE_TXD_QW1_TX_BUF_SZ_S);\n+\t\tuint64_t hi_qw2 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[2]->data_len <<\n+\t\t\t ICE_TXD_QW1_TX_BUF_SZ_S);\n+\t\tuint64_t hi_qw1 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[1]->data_len <<\n+\t\t\t ICE_TXD_QW1_TX_BUF_SZ_S);\n+\t\tuint64_t hi_qw0 =\n+\t\t\thi_qw_tmpl |\n+\t\t\t((uint64_t)pkt[0]->data_len <<\n+\t\t\t ICE_TXD_QW1_TX_BUF_SZ_S);\n+\n+\t\t__m256i desc2_3 =\n+\t\t\t_mm256_set_epi64x\n+\t\t\t\t(hi_qw3,\n+\t\t\t\t pkt[3]->buf_physaddr + pkt[3]->data_off,\n+\t\t\t\t hi_qw2,\n+\t\t\t\t pkt[2]->buf_physaddr + pkt[2]->data_off);\n+\t\t__m256i desc0_1 =\n+\t\t\t_mm256_set_epi64x\n+\t\t\t\t(hi_qw1,\n+\t\t\t\t pkt[1]->buf_physaddr + pkt[1]->data_off,\n+\t\t\t\t hi_qw0,\n+\t\t\t\t pkt[0]->buf_physaddr + pkt[0]->data_off);\n+\t\t_mm256_store_si256((void *)(txdp + 2), desc2_3);\n+\t\t_mm256_store_si256((void *)txdp, desc0_1);\n+\t}\n+\n+\t/* do any last ones */\n+\twhile (nb_pkts) {\n+\t\tice_vtx1(txdp, *pkt, flags);\n+\t\ttxdp++, pkt++, nb_pkts--;\n+\t}\n+}\n+\n+static inline uint16_t\n+ice_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\tstruct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;\n+\tvolatile struct ice_tx_desc *txdp;\n+\tstruct ice_tx_entry *txep;\n+\tuint16_t n, nb_commit, tx_id;\n+\tuint64_t flags = ICE_TD_CMD;\n+\tuint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;\n+\n+\t/* cross rx_thresh boundary is not allowed */\n+\tnb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);\n+\n+\tif (txq->nb_tx_free < txq->tx_free_thresh)\n+\t\tice_tx_free_bufs(txq);\n+\n+\tnb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);\n+\tif (unlikely(nb_pkts == 0))\n+\t\treturn 0;\n+\n+\ttx_id = txq->tx_tail;\n+\ttxdp = &txq->tx_ring[tx_id];\n+\ttxep = &txq->sw_ring[tx_id];\n+\n+\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);\n+\n+\tn = (uint16_t)(txq->nb_tx_desc - tx_id);\n+\tif (nb_commit >= n) {\n+\t\tice_tx_backlog_entry(txep, tx_pkts, n);\n+\n+\t\tice_vtx(txdp, tx_pkts, n - 1, flags);\n+\t\ttx_pkts += (n - 1);\n+\t\ttxdp += (n - 1);\n+\n+\t\tice_vtx1(txdp, *tx_pkts++, rs);\n+\n+\t\tnb_commit = (uint16_t)(nb_commit - n);\n+\n+\t\ttx_id = 0;\n+\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n+\n+\t\t/* avoid reach the end of ring */\n+\t\ttxdp = &txq->tx_ring[tx_id];\n+\t\ttxep = &txq->sw_ring[tx_id];\n+\t}\n+\n+\tice_tx_backlog_entry(txep, tx_pkts, nb_commit);\n+\n+\tice_vtx(txdp, tx_pkts, nb_commit, flags);\n+\n+\ttx_id = (uint16_t)(tx_id + nb_commit);\n+\tif (tx_id > txq->tx_next_rs) {\n+\t\ttxq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=\n+\t\t\trte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<\n+\t\t\t\t\t ICE_TXD_QW1_CMD_S);\n+\t\ttxq->tx_next_rs =\n+\t\t\t(uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);\n+\t}\n+\n+\ttxq->tx_tail = tx_id;\n+\n+\tICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);\n+\n+\treturn nb_pkts;\n+}\n+\n+uint16_t\n+ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tuint16_t nb_tx = 0;\n+\tstruct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;\n+\n+\twhile (nb_pkts) {\n+\t\tuint16_t ret, num;\n+\n+\t\tnum = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);\n+\t\tret = ice_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],\n+\t\t\t\t\t\t num);\n+\t\tnb_tx += ret;\n+\t\tnb_pkts -= ret;\n+\t\tif (ret < num)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn nb_tx;\n+}\n", "prefixes": [ "v7", "8/8" ] }