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GET /api/patches/50990/?format=api
{ "id": 50990, "url": "http://patches.dpdk.org/api/patches/50990/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1552031797-146710-4-git-send-email-gavin.hu@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1552031797-146710-4-git-send-email-gavin.hu@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1552031797-146710-4-git-send-email-gavin.hu@arm.com", "date": "2019-03-08T07:56:37", "name": "[v8,3/3] spinlock: reimplement with atomic one-way barrier builtins", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "63946509d76413347b97f17d32b0f858b096d3a2", "submitter": { "id": 1018, "url": "http://patches.dpdk.org/api/people/1018/?format=api", "name": "Gavin Hu", "email": "gavin.hu@arm.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1552031797-146710-4-git-send-email-gavin.hu@arm.com/mbox/", "series": [ { "id": 3676, "url": "http://patches.dpdk.org/api/series/3676/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=3676", "date": "2019-03-08T07:56:34", "name": "generic spinlock optimization and test case enhancements", "version": 8, "mbox": "http://patches.dpdk.org/series/3676/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/50990/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/50990/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DB52F4CA9;\n\tFri, 8 Mar 2019 08:57:07 +0100 (CET)", "from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70])\n\tby dpdk.org (Postfix) with ESMTP id 69B794C94;\n\tFri, 8 Mar 2019 08:57:06 +0100 (CET)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D509B15BE;\n\tThu, 7 Mar 2019 23:57:05 -0800 (PST)", "from net-arm-thunderx2.shanghai.arm.com\n\t(net-arm-thunderx2.shanghai.arm.com [10.169.40.121])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t0A5423F71D; Thu, 7 Mar 2019 23:57:03 -0800 (PST)" ], "From": "Gavin Hu <gavin.hu@arm.com>", "To": "dev@dpdk.org", "Cc": "nd@arm.com, thomas@monjalon.net, jerinj@marvell.com,\n\themant.agrawal@nxp.com, nipun.gupta@nxp.com,\n\tHonnappa.Nagarahalli@arm.com, \n\tgavin.hu@arm.com, i.maximets@samsung.com, chaozhu@linux.vnet.ibm.com, \n\tstable@dpdk.org", "Date": "Fri, 8 Mar 2019 15:56:37 +0800", "Message-Id": "<1552031797-146710-4-git-send-email-gavin.hu@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": [ "<1552031797-146710-1-git-send-email-gavin.hu@arm.com>", "<20181220104246.5590-1-gavin.hu@arm.com>" ], "References": [ "<1552031797-146710-1-git-send-email-gavin.hu@arm.com>", "<20181220104246.5590-1-gavin.hu@arm.com>" ], "Subject": "[dpdk-dev] [PATCH v8 3/3] spinlock: reimplement with atomic one-way\n\tbarrier builtins", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The __sync builtin based implementation generates full memory barriers\n('dmb ish') on Arm platforms. Using C11 atomic builtins to generate one way\nbarriers.\n\nHere is the assembly code of __sync_compare_and_swap builtin.\n__sync_bool_compare_and_swap(dst, exp, src);\n 0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8]\n 0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6]\n 0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4]\n 0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff\n 0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0]\n 0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1\n 0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4\n<rte_atomic16_cmpset+52> // b.any\n 0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0]\n 0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0\n<rte_atomic16_cmpset+32>\n 0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish\n 0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq = none\n\nThe benchmarking results showed constant improvements on all available\nplatforms:\n1. Cavium ThunderX2: 126% performance;\n2. Hisilicon 1616: 30%;\n3. Qualcomm Falkor: 13%;\n4. Marvell ARMADA 8040 with A72 cores on macchiatobin: 3.7%\n\nHere is the example test result on TX2:\n$sudo ./build/app/test -l 16-27 -- i\nRTE>>spinlock_autotest\n\n*** spinlock_autotest without this patch ***\nTest with lock on 12 cores...\nCore [16] Cost Time = 53886 us\nCore [17] Cost Time = 53605 us\nCore [18] Cost Time = 53163 us\nCore [19] Cost Time = 49419 us\nCore [20] Cost Time = 34317 us\nCore [21] Cost Time = 53408 us\nCore [22] Cost Time = 53970 us\nCore [23] Cost Time = 53930 us\nCore [24] Cost Time = 53283 us\nCore [25] Cost Time = 51504 us\nCore [26] Cost Time = 50718 us\nCore [27] Cost Time = 51730 us\nTotal Cost Time = 612933 us\n\n*** spinlock_autotest with this patch ***\nTest with lock on 12 cores...\nCore [16] Cost Time = 18808 us\nCore [17] Cost Time = 29497 us\nCore [18] Cost Time = 29132 us\nCore [19] Cost Time = 26150 us\nCore [20] Cost Time = 21892 us\nCore [21] Cost Time = 24377 us\nCore [22] Cost Time = 27211 us\nCore [23] Cost Time = 11070 us\nCore [24] Cost Time = 29802 us\nCore [25] Cost Time = 15793 us\nCore [26] Cost Time = 7474 us\nCore [27] Cost Time = 29550 us\nTotal Cost Time = 270756 us\n\nIn the tests on ThunderX2, with more cores contending, the performance gain\nwas even higher, indicating the __atomic implementation scales up better\nthan __sync.\n\nFixes: af75078fece3 (\"first public release\")\nCc: stable@dpdk.org\n\nSigned-off-by: Gavin Hu <gavin.hu@arm.com>\nReviewed-by: Phil Yang <phil.yang@arm.com>\nReviewed-by: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>\nReviewed-by: Ola Liljedahl <Ola.Liljedahl@arm.com>\nReviewed-by: Steve Capper <Steve.Capper@arm.com>\n---\n lib/librte_eal/common/include/generic/rte_spinlock.h | 18 +++++++++++++-----\n 1 file changed, 13 insertions(+), 5 deletions(-)", "diff": "diff --git a/lib/librte_eal/common/include/generic/rte_spinlock.h b/lib/librte_eal/common/include/generic/rte_spinlock.h\nindex c4c3fc3..87ae7a4 100644\n--- a/lib/librte_eal/common/include/generic/rte_spinlock.h\n+++ b/lib/librte_eal/common/include/generic/rte_spinlock.h\n@@ -61,9 +61,14 @@ rte_spinlock_lock(rte_spinlock_t *sl);\n static inline void\n rte_spinlock_lock(rte_spinlock_t *sl)\n {\n-\twhile (__sync_lock_test_and_set(&sl->locked, 1))\n-\t\twhile(sl->locked)\n+\tint exp = 0;\n+\n+\twhile (!__atomic_compare_exchange_n(&sl->locked, &exp, 1, 0,\n+\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {\n+\t\twhile (__atomic_load_n(&sl->locked, __ATOMIC_RELAXED))\n \t\t\trte_pause();\n+\t\texp = 0;\n+\t}\n }\n #endif\n \n@@ -80,7 +85,7 @@ rte_spinlock_unlock (rte_spinlock_t *sl);\n static inline void\n rte_spinlock_unlock (rte_spinlock_t *sl)\n {\n-\t__sync_lock_release(&sl->locked);\n+\t__atomic_store_n(&sl->locked, 0, __ATOMIC_RELEASE);\n }\n #endif\n \n@@ -99,7 +104,10 @@ rte_spinlock_trylock (rte_spinlock_t *sl);\n static inline int\n rte_spinlock_trylock (rte_spinlock_t *sl)\n {\n-\treturn __sync_lock_test_and_set(&sl->locked,1) == 0;\n+\tint exp = 0;\n+\treturn __atomic_compare_exchange_n(&sl->locked, &exp, 1,\n+\t\t\t\t0, /* disallow spurious failure */\n+\t\t\t\t__ATOMIC_ACQUIRE, __ATOMIC_RELAXED);\n }\n #endif\n \n@@ -113,7 +121,7 @@ rte_spinlock_trylock (rte_spinlock_t *sl)\n */\n static inline int rte_spinlock_is_locked (rte_spinlock_t *sl)\n {\n-\treturn sl->locked;\n+\treturn __atomic_load_n(&sl->locked, __ATOMIC_ACQUIRE);\n }\n \n /**\n", "prefixes": [ "v8", "3/3" ] }