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GET /api/patches/50567/?format=api
{ "id": 50567, "url": "http://patches.dpdk.org/api/patches/50567/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190228055650.25237-9-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190228055650.25237-9-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190228055650.25237-9-qi.z.zhang@intel.com", "date": "2019-02-28T05:56:21", "name": "[08/37] net/ice/base: add more APIs in switch module", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "a9d9cf12976881a82c7837ec5a04b07b7ba3822c", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190228055650.25237-9-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 3567, "url": "http://patches.dpdk.org/api/series/3567/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=3567", "date": "2019-02-28T05:56:13", "name": "share code update.", "version": 1, "mbox": "http://patches.dpdk.org/series/3567/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/50567/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/50567/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D91594CC7;\n\tThu, 28 Feb 2019 06:55:23 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id 788EF4C6C\n\tfor <dev@dpdk.org>; Thu, 28 Feb 2019 06:55:16 +0100 (CET)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Feb 2019 21:55:16 -0800", "from dpdk51.sh.intel.com ([10.67.110.190])\n\tby fmsmga006.fm.intel.com with ESMTP; 27 Feb 2019 21:55:15 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.58,422,1544515200\"; d=\"scan'208\";a=\"322784273\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "paul.m.stillwell.jr@intel.com, dev@dpdk.org, ferruh.yigit@intel.com,\n\tQi Zhang <qi.z.zhang@intel.com>", "Date": "Thu, 28 Feb 2019 13:56:21 +0800", "Message-Id": "<20190228055650.25237-9-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190228055650.25237-1-qi.z.zhang@intel.com>", "References": "<20190228055650.25237-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 08/37] net/ice/base: add more APIs in switch\n\tmodule", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add below APIs in switch module\n\n1. ice_aq_get_vsi_params - get VSI context info\n2. ice_aq_add_update_mir_rule - add/update mirror rule\n3. ice_aq_delete_mir_rule - delete mirror rule\n4. ice_aq_set_storm_ctrl - set storm control configuration\n5. ice_aq_get_storm_ctrl - get storm control configuration\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 136 ++++++++++++++++++++\n drivers/net/ice/base/ice_switch.c | 228 ++++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_switch.h | 29 +++++\n 3 files changed, 393 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 056a9fbef..724657af6 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -177,6 +177,13 @@ struct ice_aqc_clear_pxe {\n };\n \n \n+/* Configure No-Drop Policy Command (direct 0x0112) */\n+struct ice_aqc_config_no_drop_policy {\n+\tu8 opts;\n+#define ICE_AQC_FORCE_NO_DROP\t\t\tBIT(0)\n+\tu8 rsvd[15];\n+};\n+\n /* Get switch configuration (0x0200) */\n struct ice_aqc_get_sw_cfg {\n \t/* Reserved for command and copy of request flags for response */\n@@ -350,6 +357,19 @@ struct ice_aqc_add_update_free_vsi_resp {\n };\n \n \n+struct ice_aqc_get_vsi_resp {\n+\t__le16 vsi_num;\n+\tu8 vf_id;\n+\t/* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.\n+\t * These are found above in struct ice_aqc_add_get_update_free_vsi.\n+\t */\n+\tu8 vsi_flags;\n+\t__le16 vsi_used;\n+\t__le16 vsi_free;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n \n struct ice_aqc_vsi_props {\n \t__le16 valid_sections;\n@@ -506,6 +526,110 @@ struct ice_aqc_vsi_props {\n };\n \n \n+/* Add/update mirror rule - direct (0x0260) */\n+#define ICE_AQC_RULE_ID_VALID_S\t\t7\n+#define ICE_AQC_RULE_ID_VALID_M\t\t(0x1 << ICE_AQC_RULE_ID_VALID_S)\n+#define ICE_AQC_RULE_ID_S\t\t0\n+#define ICE_AQC_RULE_ID_M\t\t(0x3F << ICE_AQC_RULE_ID_S)\n+\n+/* Following defines to be used while processing caller specified mirror list\n+ * of VSI indexes.\n+ */\n+/* Action: Byte.bit (1.7)\n+ *\t0 = Remove VSI from mirror rule\n+ *\t1 = Add VSI to mirror rule\n+ */\n+#define ICE_AQC_RULE_ACT_S\t15\n+#define ICE_AQC_RULE_ACT_M\t(0x1 << ICE_AQC_RULE_ACT_S)\n+/* Action: 1.2:0.0 = Mirrored VSI */\n+#define ICE_AQC_RULE_MIRRORED_VSI_S\t0\n+#define ICE_AQC_RULE_MIRRORED_VSI_M\t(0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)\n+\n+/* This is to be used by add/update mirror rule Admin Queue command.\n+ * In case of add mirror rule - if rule ID is specified as\n+ * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.\n+ * If specified rule_id is valid, then it is used. If specified rule_id\n+ * is in use then new mirroring rule is added.\n+ */\n+#define ICE_INVAL_MIRROR_RULE_ID\t0xFFFF\n+\n+struct ice_aqc_add_update_mir_rule {\n+\t__le16 rule_id;\n+\n+\t__le16 rule_type;\n+#define ICE_AQC_RULE_TYPE_S\t\t0\n+#define ICE_AQC_RULE_TYPE_M\t\t(0x7 << ICE_AQC_RULE_TYPE_S)\n+\t/* VPORT ingress/egress */\n+#define ICE_AQC_RULE_TYPE_VPORT_INGRESS\t0x1\n+#define ICE_AQC_RULE_TYPE_VPORT_EGRESS\t0x2\n+\t/* Physical port ingress mirroring.\n+\t * All traffic received by this port\n+\t */\n+#define ICE_AQC_RULE_TYPE_PPORT_INGRESS\t0x6\n+\t/* Physical port egress mirroring. All traffic sent by this port */\n+#define ICE_AQC_RULE_TYPE_PPORT_EGRESS\t0x7\n+\n+\t/* Number of mirrored entries.\n+\t * The values are in the command buffer\n+\t */\n+\t__le16 num_entries;\n+\n+\t/* Destination VSI */\n+\t__le16 dest;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+/* Delete mirror rule - direct(0x0261) */\n+struct ice_aqc_delete_mir_rule {\n+\t__le16 rule_id;\n+\t__le16 rsvd;\n+\n+\t/* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of\n+\t * the PF allocated resources, otherwise it is returned to the\n+\t * shared pool\n+\t */\n+#define ICE_AQC_FLAG_KEEP_ALLOCD_S\t0\n+#define ICE_AQC_FLAG_KEEP_ALLOCD_M\t(0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)\n+\t__le16 flags;\n+\n+\tu8 reserved[10];\n+};\n+\n+/* Set/Get storm config - (direct 0x0280, 0x0281) */\n+/* This structure holds get storm configuration response and same structure\n+ * is used to perform set_storm_cfg\n+ */\n+struct ice_aqc_storm_cfg {\n+\t__le32 bcast_thresh_size;\n+\t__le32 mcast_thresh_size;\n+\t/* Bit 18:0 - Traffic upper threshold size\n+\t * Bit 31:19 - Reserved\n+\t */\n+#define ICE_AQ_THRESHOLD_S\t0\n+#define ICE_AQ_THRESHOLD_M\t(0x7FFFF << ICE_AQ_THRESHOLD_S)\n+\n+\t__le32 storm_ctrl_ctrl;\n+\t/* Bit 0: MDIPW - Drop Multicast packets in previous window\n+\t * Bit 1: MDICW - Drop multicast packets in current window\n+\t * Bit 2: BDIPW - Drop broadcast packets in previous window\n+\t * Bit 3: BDICW - Drop broadcast packets in current window\n+\t */\n+#define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST\tBIT(0)\n+#define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST\tBIT(1)\n+#define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST\tBIT(2)\n+#define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST\tBIT(3)\n+\t/* Bit 7:5 : Reserved */\n+\t/* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The\n+\t * interval size for applying ingress broadcast or multicast storm\n+\t * control.\n+\t */\n+#define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S\t8\n+#define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M\t\\\n+\t\t\t(0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)\n+\t__le32 reserved;\n+};\n+\n \n #define ICE_MAX_NUM_RECIPES 64\n \n@@ -1771,6 +1895,9 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_manage_mac_read mac_read;\n \t\tstruct ice_aqc_manage_mac_write mac_write;\n \t\tstruct ice_aqc_clear_pxe clear_pxe;\n+\t\tstruct ice_aqc_config_no_drop_policy no_drop;\n+\t\tstruct ice_aqc_add_update_mir_rule add_update_rule;\n+\t\tstruct ice_aqc_delete_mir_rule del_rule;\n \t\tstruct ice_aqc_list_caps get_cap;\n \t\tstruct ice_aqc_get_phy_caps get_phy;\n \t\tstruct ice_aqc_set_phy_cfg set_phy;\n@@ -1778,6 +1905,7 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_set_port_id_led set_port_id_led;\n \t\tstruct ice_aqc_get_sw_cfg get_sw_conf;\n \t\tstruct ice_aqc_sw_rules sw_rules;\n+\t\tstruct ice_aqc_storm_cfg storm_conf;\n \t\tstruct ice_aqc_get_topo get_topo;\n \t\tstruct ice_aqc_sched_elem_cmd sched_elem_cmd;\n \t\tstruct ice_aqc_query_txsched_res query_sched_res;\n@@ -1795,6 +1923,7 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_txqs_cleanup txqs_cleanup;\n \t\tstruct ice_aqc_add_get_update_free_vsi vsi_cmd;\n \t\tstruct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;\n+\t\tstruct ice_aqc_get_vsi_resp get_vsi_resp;\n \t\tstruct ice_aqc_download_pkg download_pkg;\n \t\tstruct ice_aqc_get_pkg_info_list get_pkg_info_list;\n \t\tstruct ice_aqc_fw_logging fw_logging;\n@@ -1912,6 +2041,13 @@ enum ice_adminq_opc {\n \tice_aqc_opc_get_vsi_params\t\t\t= 0x0212,\n \tice_aqc_opc_free_vsi\t\t\t\t= 0x0213,\n \n+\t/* Mirroring rules - add/update, delete */\n+\tice_aqc_opc_add_update_mir_rule\t\t\t= 0x0260,\n+\tice_aqc_opc_del_mir_rule\t\t\t= 0x0261,\n+\n+\t/* storm configuration */\n+\tice_aqc_opc_set_storm_cfg\t\t\t= 0x0280,\n+\tice_aqc_opc_get_storm_cfg\t\t\t= 0x0281,\n \n \n \t/* switch rules population commands */\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex e6fc9fcee..34637c1be 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -566,7 +566,174 @@ ice_update_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,\n \treturn ice_aq_update_vsi(hw, vsi_ctx, cd);\n }\n \n+/**\n+ * ice_aq_get_vsi_params\n+ * @hw: pointer to the HW struct\n+ * @vsi_ctx: pointer to a VSI context struct\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get VSI context info from hardware (0x0212)\n+ */\n+enum ice_status\n+ice_aq_get_vsi_params(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,\n+\t\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_add_get_update_free_vsi *cmd;\n+\tstruct ice_aqc_get_vsi_resp *resp;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.vsi_cmd;\n+\tresp = &desc.params.get_vsi_resp;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_vsi_params);\n+\n+\tcmd->vsi_num = CPU_TO_LE16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,\n+\t\t\t\t sizeof(vsi_ctx->info), cd);\n+\tif (!status) {\n+\t\tvsi_ctx->vsi_num = LE16_TO_CPU(resp->vsi_num) &\n+\t\t\t\t\tICE_AQ_VSI_NUM_M;\n+\t\tvsi_ctx->vsis_allocd = LE16_TO_CPU(resp->vsi_used);\n+\t\tvsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_add_update_mir_rule - add/update a mirror rule\n+ * @hw: pointer to the HW struct\n+ * @rule_type: Rule Type\n+ * @dest_vsi: VSI number to which packets will be mirrored\n+ * @count: length of the list\n+ * @mr_buf: buffer for list of mirrored VSI numbers\n+ * @cd: pointer to command details structure or NULL\n+ * @rule_id: Rule ID\n+ *\n+ * Add/Update Mirror Rule (0x260).\n+ */\n+enum ice_status\n+ice_aq_add_update_mir_rule(struct ice_hw *hw, u16 rule_type, u16 dest_vsi,\n+\t\t\t u16 count, struct ice_mir_rule_buf *mr_buf,\n+\t\t\t struct ice_sq_cd *cd, u16 *rule_id)\n+{\n+\tstruct ice_aqc_add_update_mir_rule *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\t__le16 *mr_list = NULL;\n+\tu16 buf_size = 0;\n+\n+\tswitch (rule_type) {\n+\tcase ICE_AQC_RULE_TYPE_VPORT_INGRESS:\n+\tcase ICE_AQC_RULE_TYPE_VPORT_EGRESS:\n+\t\t/* Make sure count and mr_buf are set for these rule_types */\n+\t\tif (!(count && mr_buf))\n+\t\t\treturn ICE_ERR_PARAM;\n+\n+\t\tbuf_size = count * sizeof(__le16);\n+\t\tmr_list = (__le16 *)ice_malloc(hw, buf_size);\n+\t\tif (!mr_list)\n+\t\t\treturn ICE_ERR_NO_MEMORY;\n+\t\tbreak;\n+\tcase ICE_AQC_RULE_TYPE_PPORT_INGRESS:\n+\tcase ICE_AQC_RULE_TYPE_PPORT_EGRESS:\n+\t\t/* Make sure count and mr_buf are not set for these\n+\t\t * rule_types\n+\t\t */\n+\t\tif (count || mr_buf)\n+\t\t\treturn ICE_ERR_PARAM;\n+\t\tbreak;\n+\tdefault:\n+\t\tice_debug(hw, ICE_DBG_SW,\n+\t\t\t \"Error due to unsupported rule_type %u\\n\", rule_type);\n+\t\treturn ICE_ERR_OUT_OF_RANGE;\n+\t}\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_update_mir_rule);\n+\n+\t/* Pre-process 'mr_buf' items for add/update of virtual port\n+\t * ingress/egress mirroring (but not physical port ingress/egress\n+\t * mirroring)\n+\t */\n+\tif (mr_buf) {\n+\t\tint i;\n+\n+\t\tfor (i = 0; i < count; i++) {\n+\t\t\tu16 id;\n+\n+\t\t\tid = mr_buf[i].vsi_idx & ICE_AQC_RULE_MIRRORED_VSI_M;\n+\n+\t\t\t/* Validate specified VSI number, make sure it is less\n+\t\t\t * than ICE_MAX_VSI, if not return with error.\n+\t\t\t */\n+\t\t\tif (id >= ICE_MAX_VSI) {\n+\t\t\t\tice_debug(hw, ICE_DBG_SW,\n+\t\t\t\t\t \"Error VSI index (%u) out-of-range\\n\",\n+\t\t\t\t\t id);\n+\t\t\t\tice_free(hw, mr_list);\n+\t\t\t\treturn ICE_ERR_OUT_OF_RANGE;\n+\t\t\t}\n+\n+\t\t\t/* add VSI to mirror rule */\n+\t\t\tif (mr_buf[i].add)\n+\t\t\t\tmr_list[i] =\n+\t\t\t\t\tCPU_TO_LE16(id | ICE_AQC_RULE_ACT_M);\n+\t\t\telse /* remove VSI from mirror rule */\n+\t\t\t\tmr_list[i] = CPU_TO_LE16(id);\n+\t\t}\n+\t}\n+\n+\tcmd = &desc.params.add_update_rule;\n+\tif ((*rule_id) != ICE_INVAL_MIRROR_RULE_ID)\n+\t\tcmd->rule_id = CPU_TO_LE16(((*rule_id) & ICE_AQC_RULE_ID_M) |\n+\t\t\t\t\t ICE_AQC_RULE_ID_VALID_M);\n+\tcmd->rule_type = CPU_TO_LE16(rule_type & ICE_AQC_RULE_TYPE_M);\n+\tcmd->num_entries = CPU_TO_LE16(count);\n+\tcmd->dest = CPU_TO_LE16(dest_vsi);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, mr_list, buf_size, cd);\n+\tif (!status)\n+\t\t*rule_id = LE16_TO_CPU(cmd->rule_id) & ICE_AQC_RULE_ID_M;\n \n+\tice_free(hw, mr_list);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_delete_mir_rule - delete a mirror rule\n+ * @hw: pointer to the HW struct\n+ * @rule_id: Mirror rule ID (to be deleted)\n+ * @keep_allocd: if set, the VSI stays part of the PF allocated res,\n+ *\t\t otherwise it is returned to the shared pool\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Delete Mirror Rule (0x261).\n+ */\n+enum ice_status\n+ice_aq_delete_mir_rule(struct ice_hw *hw, u16 rule_id, bool keep_allocd,\n+\t\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_delete_mir_rule *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\t/* rule_id should be in the range 0...63 */\n+\tif (rule_id >= ICE_MAX_NUM_MIRROR_RULES)\n+\t\treturn ICE_ERR_OUT_OF_RANGE;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_del_mir_rule);\n+\n+\tcmd = &desc.params.del_rule;\n+\trule_id |= ICE_AQC_RULE_ID_VALID_M;\n+\tcmd->rule_id = CPU_TO_LE16(rule_id);\n+\n+\tif (keep_allocd)\n+\t\tcmd->flags = CPU_TO_LE16(ICE_AQC_FLAG_KEEP_ALLOCD_M);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n \n /**\n * ice_aq_alloc_free_vsi_list\n@@ -626,6 +793,67 @@ ice_aq_alloc_free_vsi_list(struct ice_hw *hw, u16 *vsi_list_id,\n \treturn status;\n }\n \n+/**\n+ * ice_aq_set_storm_ctrl - Sets storm control configuration\n+ * @hw: pointer to the HW struct\n+ * @bcast_thresh: represents the upper threshold for broadcast storm control\n+ * @mcast_thresh: represents the upper threshold for multicast storm control\n+ * @ctl_bitmask: storm control control knobs\n+ *\n+ * Sets the storm control configuration (0x0280)\n+ */\n+enum ice_status\n+ice_aq_set_storm_ctrl(struct ice_hw *hw, u32 bcast_thresh, u32 mcast_thresh,\n+\t\t u32 ctl_bitmask)\n+{\n+\tstruct ice_aqc_storm_cfg *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.storm_conf;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_storm_cfg);\n+\n+\tcmd->bcast_thresh_size = CPU_TO_LE32(bcast_thresh & ICE_AQ_THRESHOLD_M);\n+\tcmd->mcast_thresh_size = CPU_TO_LE32(mcast_thresh & ICE_AQ_THRESHOLD_M);\n+\tcmd->storm_ctrl_ctrl = CPU_TO_LE32(ctl_bitmask);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+}\n+\n+/**\n+ * ice_aq_get_storm_ctrl - gets storm control configuration\n+ * @hw: pointer to the HW struct\n+ * @bcast_thresh: represents the upper threshold for broadcast storm control\n+ * @mcast_thresh: represents the upper threshold for multicast storm control\n+ * @ctl_bitmask: storm control control knobs\n+ *\n+ * Gets the storm control configuration (0x0281)\n+ */\n+enum ice_status\n+ice_aq_get_storm_ctrl(struct ice_hw *hw, u32 *bcast_thresh, u32 *mcast_thresh,\n+\t\t u32 *ctl_bitmask)\n+{\n+\tenum ice_status status;\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_storm_cfg);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+\tif (!status) {\n+\t\tstruct ice_aqc_storm_cfg *resp = &desc.params.storm_conf;\n+\n+\t\tif (bcast_thresh)\n+\t\t\t*bcast_thresh = LE32_TO_CPU(resp->bcast_thresh_size) &\n+\t\t\t\tICE_AQ_THRESHOLD_M;\n+\t\tif (mcast_thresh)\n+\t\t\t*mcast_thresh = LE32_TO_CPU(resp->mcast_thresh_size) &\n+\t\t\t\tICE_AQ_THRESHOLD_M;\n+\t\tif (ctl_bitmask)\n+\t\t\t*ctl_bitmask = LE32_TO_CPU(resp->storm_ctrl_ctrl);\n+\t}\n+\n+\treturn status;\n+}\n \n /**\n * ice_aq_sw_rules - add/update/remove switch rules\ndiff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h\nindex b28e55a4f..ebcfaa120 100644\n--- a/drivers/net/ice/base/ice_switch.h\n+++ b/drivers/net/ice/base/ice_switch.h\n@@ -29,6 +29,19 @@ struct ice_vsi_ctx {\n \tstruct LIST_HEAD_TYPE rss_list_head;\n };\n \n+/* This is to be used by add/update mirror rule Admin Queue command */\n+struct ice_mir_rule_buf {\n+\tu16 vsi_idx; /* VSI index */\n+\n+\t/* For each VSI, user can specify whether corresponding VSI\n+\t * should be added/removed to/from mirror rule\n+\t *\n+\t * add mirror rule: this should always be TRUE.\n+\t * update mirror rule: add(true) or remove(false) VSI to/from\n+\t * mirror rule\n+\t */\n+\tu8 add;\n+};\n \n /* Switch recipe ID enum values are specific to hardware */\n enum ice_sw_lkup_type {\n@@ -290,6 +303,22 @@ ice_update_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,\n \t struct ice_sq_cd *cd);\n struct ice_vsi_ctx *ice_get_vsi_ctx(struct ice_hw *hw, u16 vsi_handle);\n void ice_clear_all_vsi_ctx(struct ice_hw *hw);\n+enum ice_status\n+ice_aq_get_vsi_params(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,\n+\t\t struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_add_update_mir_rule(struct ice_hw *hw, u16 rule_type, u16 dest_vsi,\n+\t\t\t u16 count, struct ice_mir_rule_buf *mr_buf,\n+\t\t\t struct ice_sq_cd *cd, u16 *rule_id);\n+enum ice_status\n+ice_aq_delete_mir_rule(struct ice_hw *hw, u16 rule_id, bool keep_allocd,\n+\t\t struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_get_storm_ctrl(struct ice_hw *hw, u32 *bcast_thresh, u32 *mcast_thresh,\n+\t\t u32 *ctl_bitmask);\n+enum ice_status\n+ice_aq_set_storm_ctrl(struct ice_hw *hw, u32 bcast_thresh, u32 mcast_thresh,\n+\t\t u32 ctl_bitmask);\n /* Switch config */\n enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw);\n \n", "prefixes": [ "08/37" ] }