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GET /api/patches/50561/?format=api
{ "id": 50561, "url": "http://patches.dpdk.org/api/patches/50561/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20190228055650.25237-4-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190228055650.25237-4-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190228055650.25237-4-qi.z.zhang@intel.com", "date": "2019-02-28T05:56:16", "name": "[03/37] net/ice/base: add two helper functions", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "5b160f4d6e2f14cff2c0318de5c63a40f57ec1d6", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20190228055650.25237-4-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 3567, "url": "http://patches.dpdk.org/api/series/3567/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=3567", "date": "2019-02-28T05:56:13", "name": "share code update.", "version": 1, "mbox": "http://patches.dpdk.org/series/3567/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/50561/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/50561/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E9C2237AF;\n\tThu, 28 Feb 2019 06:55:14 +0100 (CET)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id B18073576\n\tfor <dev@dpdk.org>; Thu, 28 Feb 2019 06:55:10 +0100 (CET)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Feb 2019 21:55:09 -0800", "from dpdk51.sh.intel.com ([10.67.110.190])\n\tby fmsmga006.fm.intel.com with ESMTP; 27 Feb 2019 21:55:08 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.58,422,1544515200\"; d=\"scan'208\";a=\"322784227\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "paul.m.stillwell.jr@intel.com, dev@dpdk.org, ferruh.yigit@intel.com,\n\tQi Zhang <qi.z.zhang@intel.com>", "Date": "Thu, 28 Feb 2019 13:56:16 +0800", "Message-Id": "<20190228055650.25237-4-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190228055650.25237-1-qi.z.zhang@intel.com>", "References": "<20190228055650.25237-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 03/37] net/ice/base: add two helper functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add two helper functions in common module.\n1. ice_aq_set_mac_cfg to help configure maximum frame size with AQ\ncommand\n2. ice_get_ctx help to extract context bits from a packet structure.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 20 +++\n drivers/net/ice/base/ice_common.c | 282 ++++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_common.h | 4 +\n 3 files changed, 306 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 5a599280e..feb980475 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1168,6 +1168,25 @@ struct ice_aqc_set_phy_cfg_data {\n };\n \n \n+/* Set MAC Config command data structure (direct 0x0603) */\n+struct ice_aqc_set_mac_cfg {\n+\t__le16 max_frame_size;\n+\tu8 params;\n+#define ICE_AQ_SET_MAC_PACE_S\t\t3\n+#define ICE_AQ_SET_MAC_PACE_M\t\t(0xF << ICE_AQ_SET_MAC_PACE_S)\n+#define ICE_AQ_SET_MAC_PACE_TYPE_M\tBIT(7)\n+#define ICE_AQ_SET_MAC_PACE_TYPE_RATE\t0\n+#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED\tICE_AQ_SET_MAC_PACE_TYPE_M\n+\tu8 tx_tmr_priority;\n+\t__le16 tx_tmr_value;\n+\t__le16 fc_refresh_threshold;\n+\tu8 drop_opts;\n+#define ICE_AQ_SET_MAC_AUTO_DROP_MASK\t\tBIT(0)\n+#define ICE_AQ_SET_MAC_AUTO_DROP_NONE\t\t0\n+#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS\tBIT(0)\n+\tu8 reserved[7];\n+};\n+\n \n /* Restart AN command data structure (direct 0x0605)\n * Also used for response, with only the lport_num field present.\n@@ -1782,6 +1801,7 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_get_clear_fw_log get_clear_fw_log;\n \t\tstruct ice_aqc_set_mac_lb set_mac_lb;\n \t\tstruct ice_aqc_alloc_free_res_cmd sw_res_ctrl;\n+\t\tstruct ice_aqc_set_mac_cfg set_mac_cfg;\n \t\tstruct ice_aqc_set_event_mask set_event_mask;\n \t\tstruct ice_aqc_get_link_status get_link_status;\n \t} params;\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex bcfa3014b..392183375 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -423,6 +423,74 @@ static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)\n \t}\n }\n \n+/**\n+ * ice_aq_set_mac_cfg\n+ * @hw: pointer to the HW struct\n+ * @max_frame_size: Maximum Frame Size to be supported\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Set MAC configuration (0x0603)\n+ */\n+enum ice_status\n+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd)\n+{\n+\tu16 fc_threshold_val, tx_timer_val;\n+\tstruct ice_aqc_set_mac_cfg *cmd;\n+\tstruct ice_port_info *pi;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\tu8 port_num = 0;\n+\tbool link_up;\n+\tu32 reg_val;\n+\n+\tcmd = &desc.params.set_mac_cfg;\n+\n+\tif (max_frame_size == 0)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_cfg);\n+\n+\tcmd->max_frame_size = CPU_TO_LE16(max_frame_size);\n+\n+\t/* Retrieve the current data_pacing value in FW*/\n+\tpi = &hw->port_info[port_num];\n+\n+\t/* We turn on the get_link_info so that ice_update_link_info(...)\n+\t * can be called.\n+\t */\n+\tpi->phy.get_link_info = 1;\n+\n+\tstatus = ice_get_link_status(pi, &link_up);\n+\n+\tif (status)\n+\t\treturn status;\n+\n+\tcmd->params = pi->phy.link_info.pacing;\n+\n+\t/* We read back the transmit timer and fc threshold value of\n+\t * LFC. Thus, we will use index =\n+\t * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX.\n+\t *\n+\t * Also, because we are opearating on transmit timer and fc\n+\t * threshold of LFC, we don't turn on any bit in tx_tmr_priority\n+\t */\n+#define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX\n+\n+\t/* Retrieve the transmit timer */\n+\treg_val = rd32(hw,\n+\t\t PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));\n+\ttx_timer_val = reg_val &\n+\t\tPRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M;\n+\tcmd->tx_tmr_value = CPU_TO_LE16(tx_timer_val);\n+\n+\t/* Retrieve the fc threshold */\n+\treg_val = rd32(hw,\n+\t\t PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));\n+\tfc_threshold_val = reg_val & MAKEMASK(0xFFFF, 0);\n+\tcmd->fc_refresh_threshold = CPU_TO_LE16(fc_threshold_val);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n \n /**\n * ice_init_fltr_mgmt_struct - initializes filter management list and locks\n@@ -3227,6 +3295,220 @@ ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n \n \n \n+/**\n+ * ice_read_byte - read context byte into struct\n+ * @src_ctx: the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info: a description of the struct to be filled\n+ */\n+static void\n+ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+{\n+\tu8 dest_byte, mask;\n+\tu8 *src, *target;\n+\tu16 shift_width;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\tmask = (u8)(BIT(ce_info->width) - 1);\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\n+\t/* get the current bits from the src bit string */\n+\tsrc = src_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&dest_byte, src, sizeof(dest_byte), ICE_DMA_TO_NONDMA);\n+\n+\tdest_byte &= ~(mask);\n+\n+\tdest_byte >>= shift_width;\n+\n+\t/* get the address from the struct field */\n+\ttarget = dest_ctx + ce_info->offset;\n+\n+\t/* put it back in the struct */\n+\tice_memcpy(target, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_read_word - read context word into struct\n+ * @src_ctx: the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info: a description of the struct to be filled\n+ */\n+static void\n+ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+{\n+\tu16 dest_word, mask;\n+\tu8 *src, *target;\n+\t__le16 src_word;\n+\tu16 shift_width;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\tmask = BIT(ce_info->width) - 1;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\n+\t/* get the current bits from the src bit string */\n+\tsrc = src_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&src_word, src, sizeof(src_word), ICE_DMA_TO_NONDMA);\n+\n+\t/* the data in the memory is stored as little endian so mask it\n+\t * correctly\n+\t */\n+\tsrc_word &= ~(CPU_TO_LE16(mask));\n+\n+\t/* get the data back into host order before shifting */\n+\tdest_word = LE16_TO_CPU(src_word);\n+\n+\tdest_word >>= shift_width;\n+\n+\t/* get the address from the struct field */\n+\ttarget = dest_ctx + ce_info->offset;\n+\n+\t/* put it back in the struct */\n+\tice_memcpy(target, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_read_dword - read context dword into struct\n+ * @src_ctx: the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info: a description of the struct to be filled\n+ */\n+static void\n+ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+{\n+\tu32 dest_dword, mask;\n+\t__le32 src_dword;\n+\tu8 *src, *target;\n+\tu16 shift_width;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\n+\t/* if the field width is exactly 32 on an x86 machine, then the shift\n+\t * operation will not work because the SHL instructions count is masked\n+\t * to 5 bits so the shift will do nothing\n+\t */\n+\tif (ce_info->width < 32)\n+\t\tmask = BIT(ce_info->width) - 1;\n+\telse\n+\t\tmask = (u32)~0;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\n+\t/* get the current bits from the src bit string */\n+\tsrc = src_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&src_dword, src, sizeof(src_dword), ICE_DMA_TO_NONDMA);\n+\n+\t/* the data in the memory is stored as little endian so mask it\n+\t * correctly\n+\t */\n+\tsrc_dword &= ~(CPU_TO_LE32(mask));\n+\n+\t/* get the data back into host order before shifting */\n+\tdest_dword = LE32_TO_CPU(src_dword);\n+\n+\tdest_dword >>= shift_width;\n+\n+\t/* get the address from the struct field */\n+\ttarget = dest_ctx + ce_info->offset;\n+\n+\t/* put it back in the struct */\n+\tice_memcpy(target, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_read_qword - read context qword into struct\n+ * @src_ctx: the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info: a description of the struct to be filled\n+ */\n+static void\n+ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+{\n+\tu64 dest_qword, mask;\n+\t__le64 src_qword;\n+\tu8 *src, *target;\n+\tu16 shift_width;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\n+\t/* if the field width is exactly 64 on an x86 machine, then the shift\n+\t * operation will not work because the SHL instructions count is masked\n+\t * to 6 bits so the shift will do nothing\n+\t */\n+\tif (ce_info->width < 64)\n+\t\tmask = BIT_ULL(ce_info->width) - 1;\n+\telse\n+\t\tmask = (u64)~0;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\n+\t/* get the current bits from the src bit string */\n+\tsrc = src_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&src_qword, src, sizeof(src_qword), ICE_DMA_TO_NONDMA);\n+\n+\t/* the data in the memory is stored as little endian so mask it\n+\t * correctly\n+\t */\n+\tsrc_qword &= ~(CPU_TO_LE64(mask));\n+\n+\t/* get the data back into host order before shifting */\n+\tdest_qword = LE64_TO_CPU(src_qword);\n+\n+\tdest_qword >>= shift_width;\n+\n+\t/* get the address from the struct field */\n+\ttarget = dest_ctx + ce_info->offset;\n+\n+\t/* put it back in the struct */\n+\tice_memcpy(target, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_get_ctx - extract context bits from a packed structure\n+ * @src_ctx: pointer to a generic packed context structure\n+ * @dest_ctx: pointer to a generic non-packed context structure\n+ * @ce_info: a description of the structure to be read from\n+ */\n+enum ice_status\n+ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info)\n+{\n+\tint f;\n+\n+\tfor (f = 0; ce_info[f].width; f++) {\n+\t\tswitch (ce_info[f].size_of) {\n+\t\tcase 1:\n+\t\t\tice_read_byte(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tcase 2:\n+\t\t\tice_read_word(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tcase 4:\n+\t\t\tice_read_dword(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tcase 8:\n+\t\t\tice_read_qword(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* nothing to do, just keep going */\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n \n /**\n * ice_ena_vsi_txq\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex f2ad86182..0b387cdbe 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -133,6 +133,8 @@ enum ice_status\n ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,\n \t\t\t struct ice_sq_cd *cd);\n enum ice_status\n+ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd);\n+enum ice_status\n ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n \t\t struct ice_link_status *link, struct ice_sq_cd *cd);\n enum ice_status\n@@ -149,6 +151,8 @@ ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,\n \n \n enum ice_status\n+ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info);\n+enum ice_status\n ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,\n \t\tu32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,\n \t\tstruct ice_sq_cd *cmd_details);\n", "prefixes": [ "03/37" ] }