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GET /api/patches/50200/?format=api
{ "id": 50200, "url": "http://patches.dpdk.org/api/patches/50200/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1549556983-10896-3-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1549556983-10896-3-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1549556983-10896-3-git-send-email-arybchenko@solarflare.com", "date": "2019-02-07T16:29:07", "name": "[02/38] net/sfc/base: update external port number calculation", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5c2b9ad733b528e79255710acc3b9a5ff842e92b", "submitter": { "id": 607, "url": "http://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1549556983-10896-3-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 3411, "url": "http://patches.dpdk.org/api/series/3411/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=3411", "date": "2019-02-07T16:29:05", "name": "net/sfc: update base driver", "version": 1, "mbox": "http://patches.dpdk.org/series/3411/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/50200/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/50200/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 238FC1B587;\n\tThu, 7 Feb 2019 17:30:42 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 63E681B578\n\tfor <dev@dpdk.org>; Thu, 7 Feb 2019 17:30:35 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\t0295FB40106 for <dev@dpdk.org>; Thu, 7 Feb 2019 16:30:34 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1395.4; Thu, 7 Feb 2019 08:30:30 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1395.4 via Frontend Transport; Thu, 7 Feb 2019 08:30:30 -0800", "from ukv-loginhost.uk.solarflarecom.com\n\t(ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tx17GUTdT015252; Thu, 7 Feb 2019 16:30:29 GMT", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n\tby ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id\n\t1FB541613E4; Thu, 7 Feb 2019 16:30:29 +0000 (GMT)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Richard Houldsworth <rhouldsworth@solarflare.com>", "Date": "Thu, 7 Feb 2019 16:29:07 +0000", "Message-ID": "<1549556983-10896-3-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1549556983-10896-1-git-send-email-arybchenko@solarflare.com>", "References": "<1549556983-10896-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.5.1010-24412.006", "X-TM-AS-Result": "No-12.968600-4.000000-10", "X-TMASE-MatchedRID": "7edFOx+7DPcdj9vNGYhpkTSwZ6aRtol7pfVcx39Kq+4T7lsB95pa6s6K\n\t3hN0lkr4ao5kf/D5ICvWgfnC0X3nEanYP7KwFAZ5bkgeRkAEcBTt/okBLaEo+B2OuJ8WKX6V0Vz\n\trGplW0Y/GmF+VTWRGnaCMQClFHGbbJuEmNVHRTfnJ5W6OZe5hhUCrr/LkAQ46zsQ8iRVyD47OK9\n\txcJmgY9gI9ZiAsJTXrGcVZQysa/eivvxILmKK/HBRFJJyf5BJe3QfwsVk0UbtuRXh7bFKB7vwzm\n\tTGOevZdmKEhqBobdQL52l8rTQTRj2xb8CVdLSmGS4W/MRhJ1X4=", "X-TM-AS-User-Approved-Sender": "No", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--12.968600-4.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.5.1010-24412.006", "X-MDID": "1549557034-4_g5OCschePw", "Subject": "[dpdk-dev] [PATCH 02/38] net/sfc/base: update external port number\n\tcalculation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Richard Houldsworth <rhouldsworth@solarflare.com>\n\nRevise the external port calculation to support all\nX2 port modes. The previous algorithm could not\nhandle different port numbering schemes on each cage.\n\nSigned-off-by: Richard Houldsworth <rhouldsworth@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_nic.c | 126 ++++++++++++++++----------------\n 1 file changed, 62 insertions(+), 64 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c\nindex 50e23b7d4..d68920638 100644\n--- a/drivers/net/sfc/base/ef10_nic.c\n+++ b/drivers/net/sfc/base/ef10_nic.c\n@@ -1441,6 +1441,9 @@ ef10_get_privilege_mask(\n }\n \n \n+#define\tEFX_EXT_PORT_MAX\t4\n+#define\tEFX_EXT_PORT_NA\t\t0xFF\n+\n /*\n * Table of mapping schemes from port number to external number.\n *\n@@ -1454,7 +1457,7 @@ ef10_get_privilege_mask(\n * port mapping (n:1)\n * |\n * v\n- * External port number (normally 1-based)\n+ * External port number (1-based)\n * |\n * fixed (1:1) or cable assembly (1:m)\n * |\n@@ -1466,9 +1469,8 @@ ef10_get_privilege_mask(\n * how to determine which external cage/magjack corresponds to the port\n * numbers used by the driver.\n *\n- * The count of adjacent port numbers that map to each external number,\n- * and the offset in the numbering, is determined by the chip family and\n- * current port mode.\n+ * The count of consecutive port numbers that map to each external number,\n+ * is determined by the chip family and the current port mode.\n *\n * For the Huntington family, the current port mode cannot be discovered,\n * but a single mapping is used by all modes for a given chip variant,\n@@ -1479,8 +1481,7 @@ ef10_get_privilege_mask(\n static struct ef10_external_port_map_s {\n \tefx_family_t\tfamily;\n \tuint32_t\tmodes_mask;\n-\tint32_t\t\tcount;\n-\tint32_t\t\toffset;\n+\tuint8_t\t\tbase_port[EFX_EXT_PORT_MAX];\n }\t__ef10_external_port_mappings[] = {\n \t/*\n \t * Modes used by Huntington family controllers where each port\n@@ -1499,8 +1500,7 @@ static struct ef10_external_port_map_s {\n \t\t(1U << TLV_PORT_MODE_10G) |\t\t\t/* mode 0 */\n \t\t(1U << TLV_PORT_MODE_10G_10G) |\t\t\t/* mode 2 */\n \t\t(1U << TLV_PORT_MODE_10G_10G_10G_10G),\t\t/* mode 4 */\n-\t\t1,\t/* ports per cage */\n-\t\t1\t/* first cage */\n+\t\t{ 0, 1, 2, 3 }\n \t},\n \t/*\n \t * Modes which for Huntington identify a chip variant where 2\n@@ -1517,8 +1517,7 @@ static struct ef10_external_port_map_s {\n \t\t(1U << TLV_PORT_MODE_40G_40G) |\t\t\t/* mode 3 */\n \t\t(1U << TLV_PORT_MODE_40G_10G_10G) |\t\t/* mode 6 */\n \t\t(1U << TLV_PORT_MODE_10G_10G_40G),\t\t/* mode 7 */\n-\t\t2,\t/* ports per cage */\n-\t\t1\t/* first cage */\n+\t\t{ 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n \t},\n \t/*\n \t * Modes that on Medford allocate each port number to a separate\n@@ -1531,9 +1530,9 @@ static struct ef10_external_port_map_s {\n \t{\n \t\tEFX_FAMILY_MEDFORD,\n \t\t(1U << TLV_PORT_MODE_1x1_NA) |\t\t\t/* mode 0 */\n+\t\t(1U << TLV_PORT_MODE_1x4_NA) |\t\t\t/* mode 1 */\n \t\t(1U << TLV_PORT_MODE_1x1_1x1),\t\t\t/* mode 2 */\n-\t\t1,\t/* ports per cage */\n-\t\t1\t/* first cage */\n+\t\t{ 0, 1, 2, 3 }\n \t},\n \t/*\n \t * Modes that on Medford allocate 2 adjacent port numbers to each\n@@ -1545,18 +1544,17 @@ static struct ef10_external_port_map_s {\n \t */\n \t{\n \t\tEFX_FAMILY_MEDFORD,\n-\t\t(1U << TLV_PORT_MODE_1x4_NA) |\t\t\t/* mode 1 */\n \t\t(1U << TLV_PORT_MODE_1x4_1x4) |\t\t\t/* mode 3 */\n+\t\t(1U << TLV_PORT_MODE_2x1_2x1) |\t\t\t/* mode 5 */\n \t\t(1U << TLV_PORT_MODE_1x4_2x1) |\t\t\t/* mode 6 */\n \t\t(1U << TLV_PORT_MODE_2x1_1x4) |\t\t\t/* mode 7 */\n \t\t/* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */\n \t\t(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),\t/* mode 9 */\n-\t\t2,\t/* ports per cage */\n-\t\t1\t/* first cage */\n+\t\t{ 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n \t},\n \t/*\n-\t * Modes that on Medford allocate 4 adjacent port numbers to each\n-\t * connector, starting on cage 1.\n+\t * Modes that on Medford allocate 4 adjacent port numbers to\n+\t * cage 1.\n \t *\tport 0 -> cage 1\n \t *\tport 1 -> cage 1\n \t *\tport 2 -> cage 1\n@@ -1564,15 +1562,13 @@ static struct ef10_external_port_map_s {\n \t */\n \t{\n \t\tEFX_FAMILY_MEDFORD,\n-\t\t(1U << TLV_PORT_MODE_2x1_2x1) |\t\t\t/* mode 5 */\n \t\t/* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */\n \t\t(1U << TLV_PORT_MODE_4x1_NA),\t\t\t/* mode 4 */\n-\t\t4,\t/* ports per cage */\n-\t\t1\t/* first cage */\n+\t\t{ 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n \t},\n \t/*\n-\t * Modes that on Medford allocate 4 adjacent port numbers to each\n-\t * connector, starting on cage 2.\n+\t * Modes that on Medford allocate 4 adjacent port numbers to\n+\t * cage 2.\n \t *\tport 0 -> cage 2\n \t *\tport 1 -> cage 2\n \t *\tport 2 -> cage 2\n@@ -1581,8 +1577,7 @@ static struct ef10_external_port_map_s {\n \t{\n \t\tEFX_FAMILY_MEDFORD,\n \t\t(1U << TLV_PORT_MODE_NA_4x1),\t\t\t/* mode 8 */\n-\t\t4,\t/* ports per cage */\n-\t\t2\t/* first cage */\n+\t\t{ EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n \t},\n \t/*\n \t * Modes that on Medford2 allocate each port number to a separate\n@@ -1597,23 +1592,29 @@ static struct ef10_external_port_map_s {\n \t\t(1U << TLV_PORT_MODE_1x1_NA) |\t\t\t/* mode 0 */\n \t\t(1U << TLV_PORT_MODE_1x4_NA) |\t\t\t/* mode 1 */\n \t\t(1U << TLV_PORT_MODE_1x1_1x1) |\t\t\t/* mode 2 */\n+\t\t(1U << TLV_PORT_MODE_1x4_1x4) |\t\t\t/* mode 3 */\n \t\t(1U << TLV_PORT_MODE_1x2_NA) |\t\t\t/* mode 10 */\n \t\t(1U << TLV_PORT_MODE_1x2_1x2) |\t\t\t/* mode 12 */\n \t\t(1U << TLV_PORT_MODE_1x4_1x2) |\t\t\t/* mode 15 */\n \t\t(1U << TLV_PORT_MODE_1x2_1x4),\t\t\t/* mode 16 */\n-\t\t1,\t/* ports per cage */\n-\t\t1\t/* first cage */\n+\t\t{ 0, 1, 2, 3 }\n \t},\n \t/*\n-\t * FIXME: Some port modes are not representable in this mapping:\n-\t * - TLV_PORT_MODE_1x2_2x1 (mode 17):\n+\t * Modes that on Medford2 allocate 1 port to cage 1 and the rest\n+\t * to cage 2.\n \t *\tport 0 -> cage 1\n \t *\tport 1 -> cage 2\n \t *\tport 2 -> cage 2\n \t */\n+\t{\n+\t\tEFX_FAMILY_MEDFORD2,\n+\t\t(1U << TLV_PORT_MODE_1x2_2x1) |\t\t\t/* mode 17 */\n+\t\t(1U << TLV_PORT_MODE_1x4_2x1),\t\t\t/* mode 6 */\n+\t\t{ 0, 1, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n+\t},\n \t/*\n-\t * Modes that on Medford2 allocate 2 adjacent port numbers to each\n-\t * cage, starting on cage 1.\n+\t * Modes that on Medford2 allocate 2 adjacent port numbers to cage 1\n+\t * and the rest to cage 2.\n \t *\tport 0 -> cage 1\n \t *\tport 1 -> cage 1\n \t *\tport 2 -> cage 2\n@@ -1621,30 +1622,15 @@ static struct ef10_external_port_map_s {\n \t */\n \t{\n \t\tEFX_FAMILY_MEDFORD2,\n-\t\t(1U << TLV_PORT_MODE_1x4_1x4) |\t\t\t/* mode 3 */\n \t\t(1U << TLV_PORT_MODE_2x1_2x1) |\t\t\t/* mode 4 */\n-\t\t(1U << TLV_PORT_MODE_1x4_2x1) |\t\t\t/* mode 6 */\n \t\t(1U << TLV_PORT_MODE_2x1_1x4) |\t\t\t/* mode 7 */\n \t\t(1U << TLV_PORT_MODE_2x2_NA) |\t\t\t/* mode 13 */\n \t\t(1U << TLV_PORT_MODE_2x1_1x2),\t\t\t/* mode 18 */\n-\t\t2,\t/* ports per cage */\n-\t\t1\t/* first cage */\n-\t},\n-\t/*\n-\t * Modes that on Medford2 allocate 2 adjacent port numbers to each\n-\t * cage, starting on cage 2.\n-\t *\tport 0 -> cage 2\n-\t *\tport 1 -> cage 2\n-\t */\n-\t{\n-\t\tEFX_FAMILY_MEDFORD2,\n-\t\t(1U << TLV_PORT_MODE_NA_2x2),\t\t\t/* mode 14 */\n-\t\t2,\t/* ports per cage */\n-\t\t2\t/* first cage */\n+\t\t{ 0, 2, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n \t},\n \t/*\n-\t * Modes that on Medford2 allocate 4 adjacent port numbers to each\n-\t * connector, starting on cage 1.\n+\t * Modes that on Medford2 allocate up to 4 adjacent port numbers\n+\t * to cage 1.\n \t *\tport 0 -> cage 1\n \t *\tport 1 -> cage 1\n \t *\tport 2 -> cage 1\n@@ -1653,12 +1639,11 @@ static struct ef10_external_port_map_s {\n \t{\n \t\tEFX_FAMILY_MEDFORD2,\n \t\t(1U << TLV_PORT_MODE_4x1_NA),\t\t\t/* mode 5 */\n-\t\t4,\t/* ports per cage */\n-\t\t1\t/* first cage */\n+\t\t{ 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n \t},\n \t/*\n-\t * Modes that on Medford2 allocate 4 adjacent port numbers to each\n-\t * connector, starting on cage 2.\n+\t * Modes that on Medford2 allocate up to 4 adjacent port numbers\n+\t * to cage 2.\n \t *\tport 0 -> cage 2\n \t *\tport 1 -> cage 2\n \t *\tport 2 -> cage 2\n@@ -1667,9 +1652,9 @@ static struct ef10_external_port_map_s {\n \t{\n \t\tEFX_FAMILY_MEDFORD2,\n \t\t(1U << TLV_PORT_MODE_NA_4x1) |\t\t\t/* mode 8 */\n-\t\t(1U << TLV_PORT_MODE_NA_1x2),\t\t\t/* mode 11 */\n-\t\t4,\t/* ports per cage */\n-\t\t2\t/* first cage */\n+\t\t(1U << TLV_PORT_MODE_NA_1x2) |\t\t\t/* mode 11 */\n+\t\t(1U << TLV_PORT_MODE_NA_2x2),\t\t\t/* mode 14 */\n+\t\t{ EFX_EXT_PORT_NA, 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }\n \t},\n };\n \n@@ -1684,8 +1669,8 @@ ef10_external_port_mapping(\n \tuint32_t port_modes;\n \tuint32_t matches;\n \tuint32_t current;\n-\tint32_t count = 1; /* Default 1-1 mapping */\n-\tint32_t offset = 1; /* Default starting external port number */\n+\tstruct ef10_external_port_map_s *mapp = NULL;\n+\tint ext_index = port; /* Default 1-1 mapping */\n \n \tif ((rc = efx_mcdi_get_port_modes(enp, &port_modes, ¤t,\n \t\t NULL)) != 0) {\n@@ -1722,8 +1707,7 @@ ef10_external_port_mapping(\n \t\t\t * there will be multiple matches. The mapping on the\n \t\t\t * last match is used.\n \t\t\t */\n-\t\t\tcount = eepmp->count;\n-\t\t\toffset = eepmp->offset;\n+\t\t\tmapp = eepmp;\n \t\t\tport_modes &= ~matches;\n \t\t}\n \t}\n@@ -1735,11 +1719,25 @@ ef10_external_port_mapping(\n \t}\n \n out:\n-\t/*\n-\t * Scale as required by last matched mode and then convert to\n-\t * correctly offset numbering\n-\t */\n-\t*external_portp = (uint8_t)((port / count) + offset);\n+\tif (mapp != NULL) {\n+\t\t/*\n+\t\t * External ports are assigned a sequence of consecutive\n+\t\t * port numbers, so find the one with the closest base_port.\n+\t\t */\n+\t\tuint32_t delta = EFX_EXT_PORT_NA;\n+\n+\t\tfor (i = 0; i < EFX_EXT_PORT_MAX; i++) {\n+\t\t\tuint32_t base = mapp->base_port[i];\n+\t\t\tif ((base != EFX_EXT_PORT_NA) && (base <= port)) {\n+\t\t\t\tif ((port - base) < delta) {\n+\t\t\t\t\tdelta = (port - base);\n+\t\t\t\t\text_index = i;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t}\n+\t*external_portp = (uint8_t)(ext_index + 1);\n+\n \treturn (0);\n \n fail1:\n", "prefixes": [ "02/38" ] }