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{
    "id": 48306,
    "url": "http://patches.dpdk.org/api/patches/48306/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1542956179-80951-2-git-send-email-wenzhuo.lu@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1542956179-80951-2-git-send-email-wenzhuo.lu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1542956179-80951-2-git-send-email-wenzhuo.lu@intel.com",
    "date": "2018-11-23T06:56:01",
    "name": "[01/19] net/ice: add base code",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8d9c2411c1d76a9ad2eac7795ecf918ff6a446ba",
    "submitter": {
        "id": 258,
        "url": "http://patches.dpdk.org/api/people/258/?format=api",
        "name": "Wenzhuo Lu",
        "email": "wenzhuo.lu@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1542956179-80951-2-git-send-email-wenzhuo.lu@intel.com/mbox/",
    "series": [
        {
            "id": 2547,
            "url": "http://patches.dpdk.org/api/series/2547/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=2547",
            "date": "2018-11-23T06:56:00",
            "name": "A new net PMD - ice",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/2547/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/48306/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/48306/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8959C1B51E;\n\tFri, 23 Nov 2018 11:54:03 +0100 (CET)",
            "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n\tby dpdk.org (Postfix) with ESMTP id 80C271B4BB\n\tfor <dev@dpdk.org>; Fri, 23 Nov 2018 07:51:48 +0100 (CET)",
            "from fmsmga006.fm.intel.com ([10.253.24.20])\n\tby fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t22 Nov 2018 22:51:47 -0800",
            "from dpdk26.sh.intel.com ([10.67.110.161])\n\tby fmsmga006.fm.intel.com with ESMTP; 22 Nov 2018 22:51:43 -0800"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.56,268,1539673200\"; d=\"scan'208\";a=\"283483433\"",
        "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>",
        "Date": "Fri, 23 Nov 2018 14:56:01 +0800",
        "Message-Id": "<1542956179-80951-2-git-send-email-wenzhuo.lu@intel.com>",
        "X-Mailer": "git-send-email 1.9.3",
        "In-Reply-To": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>",
        "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=UTF-8",
        "Content-Transfer-Encoding": "8bit",
        "X-Mailman-Approved-At": "Fri, 23 Nov 2018 11:54:02 +0100",
        "Subject": "[dpdk-dev] [PATCH 01/19] net/ice: add base code",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Current version 2018.10.30.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n MAINTAINERS                              |    6 +\n drivers/net/ice/base/README              |   22 +\n drivers/net/ice/base/ice_acl.c           |    4 +\n drivers/net/ice/base/ice_acl.h           |    7 +\n drivers/net/ice/base/ice_acl_ctrl.c      |    4 +\n drivers/net/ice/base/ice_adminq_cmd.h    | 1724 ++++++\n drivers/net/ice/base/ice_alloc.h         |   22 +\n drivers/net/ice/base/ice_bitops.h        |  233 +\n drivers/net/ice/base/ice_common.c        | 3332 ++++++++++\n drivers/net/ice/base/ice_common.h        |  159 +\n drivers/net/ice/base/ice_controlq.c      | 1098 ++++\n drivers/net/ice/base/ice_controlq.h      |   97 +\n drivers/net/ice/base/ice_devids.h        |   17 +\n drivers/net/ice/base/ice_flex_pipe.c     |    5 +\n drivers/net/ice/base/ice_flex_pipe.h     |   83 +\n drivers/net/ice/base/ice_flex_type.h     |   19 +\n drivers/net/ice/base/ice_flow.c          |    4 +\n drivers/net/ice/base/ice_flow.h          |    8 +\n drivers/net/ice/base/ice_hw_autogen.h    | 9815 ++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_impl_guide.c    |  167 +\n drivers/net/ice/base/ice_lan_tx_rx.h     | 2290 +++++++\n drivers/net/ice/base/ice_nvm.c           |  388 ++\n drivers/net/ice/base/ice_osdep.h         |  491 ++\n drivers/net/ice/base/ice_protocol_type.h |  237 +\n drivers/net/ice/base/ice_sbq_cmd.h       |   93 +\n drivers/net/ice/base/ice_sched.c         | 1715 ++++++\n drivers/net/ice/base/ice_sched.h         |   68 +\n drivers/net/ice/base/ice_sriov.c         |  129 +\n drivers/net/ice/base/ice_sriov.h         |   35 +\n drivers/net/ice/base/ice_status.h        |   45 +\n drivers/net/ice/base/ice_switch.c        | 2415 ++++++++\n drivers/net/ice/base/ice_switch.h        |  320 +\n drivers/net/ice/base/ice_type.h          |  789 +++\n drivers/net/ice/base/virtchnl.h          |  787 +++\n 34 files changed, 26628 insertions(+)\n create mode 100644 drivers/net/ice/base/README\n create mode 100644 drivers/net/ice/base/ice_acl.c\n create mode 100644 drivers/net/ice/base/ice_acl.h\n create mode 100644 drivers/net/ice/base/ice_acl_ctrl.c\n create mode 100644 drivers/net/ice/base/ice_adminq_cmd.h\n create mode 100644 drivers/net/ice/base/ice_alloc.h\n create mode 100644 drivers/net/ice/base/ice_bitops.h\n create mode 100644 drivers/net/ice/base/ice_common.c\n create mode 100644 drivers/net/ice/base/ice_common.h\n create mode 100644 drivers/net/ice/base/ice_controlq.c\n create mode 100644 drivers/net/ice/base/ice_controlq.h\n create mode 100644 drivers/net/ice/base/ice_devids.h\n create mode 100644 drivers/net/ice/base/ice_flex_pipe.c\n create mode 100644 drivers/net/ice/base/ice_flex_pipe.h\n create mode 100644 drivers/net/ice/base/ice_flex_type.h\n create mode 100644 drivers/net/ice/base/ice_flow.c\n create mode 100644 drivers/net/ice/base/ice_flow.h\n create mode 100644 drivers/net/ice/base/ice_hw_autogen.h\n create mode 100644 drivers/net/ice/base/ice_impl_guide.c\n create mode 100644 drivers/net/ice/base/ice_lan_tx_rx.h\n create mode 100644 drivers/net/ice/base/ice_nvm.c\n create mode 100644 drivers/net/ice/base/ice_osdep.h\n create mode 100644 drivers/net/ice/base/ice_protocol_type.h\n create mode 100644 drivers/net/ice/base/ice_sbq_cmd.h\n create mode 100644 drivers/net/ice/base/ice_sched.c\n create mode 100644 drivers/net/ice/base/ice_sched.h\n create mode 100644 drivers/net/ice/base/ice_sriov.c\n create mode 100644 drivers/net/ice/base/ice_sriov.h\n create mode 100644 drivers/net/ice/base/ice_status.h\n create mode 100644 drivers/net/ice/base/ice_switch.c\n create mode 100644 drivers/net/ice/base/ice_switch.h\n create mode 100644 drivers/net/ice/base/ice_type.h\n create mode 100644 drivers/net/ice/base/virtchnl.h",
    "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 19353ac..00a5e03 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -593,6 +593,12 @@ F: drivers/net/ifc/\n F: doc/guides/nics/ifc.rst\n F: doc/guides/nics/features/ifc*.ini\n \n+Intel ice\n+M: Qiming Yang <qiming.yang@intel.com>\n+M: Wenzhuo Lu <wenzhuo.lu@intel.com>\n+T: git://dpdk.org/next/dpdk-next-net-intel\n+F: drivers/net/ice/\n+\n Marvell mvpp2\n M: Tomasz Duszynski <tdu@semihalf.com>\n M: Dmitri Epshtein <dima@marvell.com>\ndiff --git a/drivers/net/ice/base/README b/drivers/net/ice/base/README\nnew file mode 100644\nindex 0000000..d8c7a9b\n--- /dev/null\n+++ b/drivers/net/ice/base/README\n@@ -0,0 +1,22 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+Intel® ICE driver\n+==================\n+\n+This directory contains source code of FreeBSD ice driver of version\n+2018.10.30 released by the team which develops\n+basic drivers for any ice NIC. The directory of base/ contains the\n+original source package.\n+This driver is valid for the product(s) listed below\n+\n+* Intel® Ethernet Network Adapters E810\n+\n+Updating the driver\n+===================\n+\n+NOTE: The source code in this directory should not be modified apart from\n+the following file(s):\n+\n+    ice_osdep.h\ndiff --git a/drivers/net/ice/base/ice_acl.c b/drivers/net/ice/base/ice_acl.c\nnew file mode 100644\nindex 0000000..49b22bc\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_acl.c\n@@ -0,0 +1,4 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\ndiff --git a/drivers/net/ice/base/ice_acl.h b/drivers/net/ice/base/ice_acl.h\nnew file mode 100644\nindex 0000000..730b593\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_acl.h\n@@ -0,0 +1,7 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_ACL_H_\n+#define _ICE_ACL_H_\n+#endif /* _ICE_ACL_H_ */\ndiff --git a/drivers/net/ice/base/ice_acl_ctrl.c b/drivers/net/ice/base/ice_acl_ctrl.c\nnew file mode 100644\nindex 0000000..49b22bc\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_acl_ctrl.c\n@@ -0,0 +1,4 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\ndiff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nnew file mode 100644\nindex 0000000..e711502\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -0,0 +1,1724 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_ADMINQ_CMD_H_\n+#define _ICE_ADMINQ_CMD_H_\n+\n+/* This header file defines the Admin Queue commands, error codes and\n+ * descriptor format. It is shared between Firmware and Software.\n+ */\n+\n+\n+#define ICE_MAX_VSI\t\t\t768\n+#define ICE_AQC_TOPO_MAX_LEVEL_NUM\t0x9\n+#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX\t9728\n+\n+\n+struct ice_aqc_generic {\n+\t__le32 param0;\n+\t__le32 param1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Get version (direct 0x0001) */\n+struct ice_aqc_get_ver {\n+\t__le32 rom_ver;\n+\t__le32 fw_build;\n+\tu8 fw_branch;\n+\tu8 fw_major;\n+\tu8 fw_minor;\n+\tu8 fw_patch;\n+\tu8 api_branch;\n+\tu8 api_major;\n+\tu8 api_minor;\n+\tu8 api_patch;\n+};\n+\n+\n+\n+/* Queue Shutdown (direct 0x0003) */\n+struct ice_aqc_q_shutdown {\n+\t__le32 driver_unloading;\n+#define ICE_AQC_DRIVER_UNLOADING\tBIT(0)\n+\tu8 reserved[12];\n+};\n+\n+\n+\n+\n+/* Request resource ownership (direct 0x0008)\n+ * Release resource ownership (direct 0x0009)\n+ */\n+struct ice_aqc_req_res {\n+\t__le16 res_id;\n+#define ICE_AQC_RES_ID_NVM\t\t1\n+#define ICE_AQC_RES_ID_SDP\t\t2\n+#define ICE_AQC_RES_ID_CHNG_LOCK\t3\n+#define ICE_AQC_RES_ID_GLBL_LOCK\t4\n+\t__le16 access_type;\n+#define ICE_AQC_RES_ACCESS_READ\t\t1\n+#define ICE_AQC_RES_ACCESS_WRITE\t2\n+\n+\t/* Upon successful completion, FW writes this value and driver is\n+\t * expected to release resource before timeout. This value is provided\n+\t * in milliseconds.\n+\t */\n+\t__le32 timeout;\n+#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS\t3000\n+#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS\t180000\n+#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS\t1000\n+#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS\t3000\n+\t/* For SDP: pin id of the SDP */\n+\t__le32 res_number;\n+\t/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */\n+\t__le16 status;\n+#define ICE_AQ_RES_GLBL_SUCCESS\t\t0\n+#define ICE_AQ_RES_GLBL_IN_PROG\t\t1\n+#define ICE_AQ_RES_GLBL_DONE\t\t2\n+\tu8 reserved[2];\n+};\n+\n+\n+/* Get function capabilities (indirect 0x000A)\n+ * Get device capabilities (indirect 0x000B)\n+ */\n+struct ice_aqc_list_caps {\n+\tu8 cmd_flags;\n+\tu8 pf_index;\n+\tu8 reserved[2];\n+\t__le32 count;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Device/Function buffer entry, repeated per reported capability */\n+struct ice_aqc_list_caps_elem {\n+\t__le16 cap;\n+#define ICE_AQC_CAPS_VALID_FUNCTIONS\t\t\t0x0005\n+#define ICE_AQC_CAPS_SRIOV\t\t\t\t0x0012\n+#define ICE_AQC_CAPS_VF\t\t\t\t\t0x0013\n+#define ICE_AQC_CAPS_VSI\t\t\t\t0x0017\n+#define ICE_AQC_CAPS_RSS\t\t\t\t0x0040\n+#define ICE_AQC_CAPS_RXQS\t\t\t\t0x0041\n+#define ICE_AQC_CAPS_TXQS\t\t\t\t0x0042\n+#define ICE_AQC_CAPS_MSIX\t\t\t\t0x0043\n+#define ICE_AQC_CAPS_MAX_MTU\t\t\t\t0x0047\n+\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\t/* Number of resources described by this capability */\n+\t__le32 number;\n+\t/* Only meaningful for some types of resources */\n+\t__le32 logical_id;\n+\t/* Only meaningful for some types of resources */\n+\t__le32 phys_id;\n+\t__le64 rsvd1;\n+\t__le64 rsvd2;\n+};\n+\n+\n+/* Manage MAC address, read command - indirect (0x0107)\n+ * This struct is also used for the response\n+ */\n+struct ice_aqc_manage_mac_read {\n+\t__le16 flags; /* Zeroed by device driver */\n+#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID\t\tBIT(4)\n+#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID\t\tBIT(5)\n+#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID\t\tBIT(6)\n+#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID\t\tBIT(7)\n+#define ICE_AQC_MAN_MAC_READ_S\t\t\t4\n+#define ICE_AQC_MAN_MAC_READ_M\t\t\t(0xF << ICE_AQC_MAN_MAC_READ_S)\n+\tu8 lport_num;\n+\tu8 lport_num_valid;\n+#define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID\tBIT(0)\n+\tu8 num_addr; /* Used in response */\n+\tu8 reserved[3];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Response buffer format for manage MAC read command */\n+struct ice_aqc_manage_mac_read_resp {\n+\tu8 lport_num;\n+\tu8 addr_type;\n+#define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN\t\t0\n+#define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL\t\t1\n+\tu8 mac_addr[ETH_ALEN];\n+};\n+\n+\n+/* Manage MAC address, write command - direct (0x0108) */\n+struct ice_aqc_manage_mac_write {\n+\tu8 port_num;\n+\tu8 flags;\n+#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN\t\tBIT(0)\n+#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP\tBIT(1)\n+#define ICE_AQC_MAN_MAC_WR_S\t\t6\n+#define ICE_AQC_MAN_MAC_WR_M\t\t(3 << ICE_AQC_MAN_MAC_WR_S)\n+#define ICE_AQC_MAN_MAC_UPDATE_LAA\t0\n+#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL\t(BIT(0) << ICE_AQC_MAN_MAC_WR_S)\n+\t/* High 16 bits of MAC address in big endian order */\n+\t__be16 sah;\n+\t/* Low 32 bits of MAC address in big endian order */\n+\t__be32 sal;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Clear PXE Command and response (direct 0x0110) */\n+struct ice_aqc_clear_pxe {\n+\tu8 rx_cnt;\n+#define ICE_AQC_CLEAR_PXE_RX_CNT\t\t0x2\n+\tu8 reserved[15];\n+};\n+\n+\n+/* Get switch configuration (0x0200) */\n+struct ice_aqc_get_sw_cfg {\n+\t/* Reserved for command and copy of request flags for response */\n+\t__le16 flags;\n+\t/* First desc in case of command and next_elem in case of response\n+\t * In case of response, if it is not zero, means all the configuration\n+\t * was not returned and new command shall be sent with this value in\n+\t * the 'first desc' field\n+\t */\n+\t__le16 element;\n+\t/* Reserved for command, only used for response */\n+\t__le16 num_elems;\n+\t__le16 rsvd;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Each entry in the response buffer is of the following type: */\n+struct ice_aqc_get_sw_cfg_resp_elem {\n+\t/* VSI/Port Number */\n+\t__le16 vsi_port_num;\n+#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S\t0\n+#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M\t\\\n+\t\t\t(0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)\n+#define ICE_AQC_GET_SW_CONF_RESP_TYPE_S\t14\n+#define ICE_AQC_GET_SW_CONF_RESP_TYPE_M\t(0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)\n+#define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT\t0\n+#define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT\t1\n+#define ICE_AQC_GET_SW_CONF_RESP_VSI\t\t2\n+\n+\t/* SWID VSI/Port belongs to */\n+\t__le16 swid;\n+\n+\t/* Bit 14..0 : PF/VF number VSI belongs to\n+\t * Bit 15 : VF indication bit\n+\t */\n+\t__le16 pf_vf_num;\n+#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S\t0\n+#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M\t\\\n+\t\t\t\t(0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)\n+#define ICE_AQC_GET_SW_CONF_RESP_IS_VF\t\tBIT(15)\n+};\n+\n+\n+/* The response buffer is as follows. Note that the length of the\n+ * elements array varies with the length of the command response.\n+ */\n+struct ice_aqc_get_sw_cfg_resp {\n+\tstruct ice_aqc_get_sw_cfg_resp_elem elements[1];\n+};\n+\n+\n+\n+/* These resource type defines are used for all switch resource\n+ * commands where a resource type is required, such as:\n+ * Get Resource Allocation command (indirect 0x0204)\n+ * Allocate Resources command (indirect 0x0208)\n+ * Free Resources command (indirect 0x0209)\n+ * Get Allocated Resource Descriptors Command (indirect 0x020A)\n+ */\n+#define ICE_AQC_RES_TYPE_VSI_LIST_REP\t\t\t0x03\n+#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE\t\t\t0x04\n+\n+#define ICE_AQC_RES_TYPE_FLAG_SHARED\t\t\tBIT(7)\n+#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM\t\tBIT(12)\n+#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX\t\tBIT(13)\n+\n+#define ICE_AQC_RES_TYPE_FLAG_DEDICATED\t\t\t0x00\n+\n+\n+\n+/* Allocate Resources command (indirect 0x0208)\n+ * Free Resources command (indirect 0x0209)\n+ */\n+struct ice_aqc_alloc_free_res_cmd {\n+\t__le16 num_entries; /* Number of Resource entries */\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Resource descriptor */\n+struct ice_aqc_res_elem {\n+\tunion {\n+\t\t__le16 sw_resp;\n+\t\t__le16 flu_resp;\n+\t} e;\n+};\n+\n+\n+/* Buffer for Allocate/Free Resources commands */\n+struct ice_aqc_alloc_free_res_elem {\n+\t__le16 res_type; /* Types defined above cmd 0x0204 */\n+#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S\t8\n+#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M\t\\\n+\t\t\t\t(0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)\n+\t__le16 num_elems;\n+\tstruct ice_aqc_res_elem elem[1];\n+};\n+\n+\n+\n+\n+/* Add VSI (indirect 0x0210)\n+ * Update VSI (indirect 0x0211)\n+ * Get VSI (indirect 0x0212)\n+ * Free VSI (indirect 0x0213)\n+ */\n+struct ice_aqc_add_get_update_free_vsi {\n+\t__le16 vsi_num;\n+#define ICE_AQ_VSI_NUM_S\t0\n+#define ICE_AQ_VSI_NUM_M\t(0x03FF << ICE_AQ_VSI_NUM_S)\n+#define ICE_AQ_VSI_IS_VALID\tBIT(15)\n+\t__le16 cmd_flags;\n+#define ICE_AQ_VSI_KEEP_ALLOC\t0x1\n+\tu8 vf_id;\n+\tu8 reserved;\n+\t__le16 vsi_flags;\n+#define ICE_AQ_VSI_TYPE_S\t0\n+#define ICE_AQ_VSI_TYPE_M\t(0x3 << ICE_AQ_VSI_TYPE_S)\n+#define ICE_AQ_VSI_TYPE_VF\t0x0\n+#define ICE_AQ_VSI_TYPE_VMDQ2\t0x1\n+#define ICE_AQ_VSI_TYPE_PF\t0x2\n+#define ICE_AQ_VSI_TYPE_EMP_MNG\t0x3\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Response descriptor for:\n+ * Add VSI (indirect 0x0210)\n+ * Update VSI (indirect 0x0211)\n+ * Free VSI (indirect 0x0213)\n+ */\n+struct ice_aqc_add_update_free_vsi_resp {\n+\t__le16 vsi_num;\n+\t__le16 ext_status;\n+\t__le16 vsi_used;\n+\t__le16 vsi_free;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+\n+struct ice_aqc_vsi_props {\n+\t__le16 valid_sections;\n+#define ICE_AQ_VSI_PROP_SW_VALID\t\tBIT(0)\n+#define ICE_AQ_VSI_PROP_SECURITY_VALID\t\tBIT(1)\n+#define ICE_AQ_VSI_PROP_VLAN_VALID\t\tBIT(2)\n+#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID\t\tBIT(3)\n+#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID\tBIT(4)\n+#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID\t\tBIT(5)\n+#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID\t\tBIT(6)\n+#define ICE_AQ_VSI_PROP_Q_OPT_VALID\t\tBIT(7)\n+#define ICE_AQ_VSI_PROP_OUTER_UP_VALID\t\tBIT(8)\n+#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID\t\tBIT(11)\n+#define ICE_AQ_VSI_PROP_PASID_VALID\t\tBIT(12)\n+\t/* switch section */\n+\tu8 sw_id;\n+\tu8 sw_flags;\n+#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB\t\tBIT(5)\n+#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB\t\tBIT(6)\n+#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE\t\tBIT(7)\n+\tu8 sw_flags2;\n+#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S\t0\n+#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M\t\\\n+\t\t\t\t(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)\n+#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA\tBIT(0)\n+#define ICE_AQ_VSI_SW_FLAG_LAN_ENA\t\tBIT(4)\n+\tu8 veb_stat_id;\n+#define ICE_AQ_VSI_SW_VEB_STAT_ID_S\t\t0\n+#define ICE_AQ_VSI_SW_VEB_STAT_ID_M\t(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)\n+#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID\t\tBIT(5)\n+\t/* security section */\n+\tu8 sec_flags;\n+#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD\tBIT(0)\n+#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF\tBIT(2)\n+#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S\t4\n+#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M\t(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)\n+#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA\tBIT(0)\n+\tu8 sec_reserved;\n+\t/* VLAN section */\n+\t__le16 pvid; /* VLANS include priority bits */\n+\tu8 pvlan_reserved[2];\n+\tu8 vlan_flags;\n+#define ICE_AQ_VSI_VLAN_MODE_S\t0\n+#define ICE_AQ_VSI_VLAN_MODE_M\t(0x3 << ICE_AQ_VSI_VLAN_MODE_S)\n+#define ICE_AQ_VSI_VLAN_MODE_UNTAGGED\t0x1\n+#define ICE_AQ_VSI_VLAN_MODE_TAGGED\t0x2\n+#define ICE_AQ_VSI_VLAN_MODE_ALL\t0x3\n+#define ICE_AQ_VSI_PVLAN_INSERT_PVID\tBIT(2)\n+#define ICE_AQ_VSI_VLAN_EMOD_S\t3\n+#define ICE_AQ_VSI_VLAN_EMOD_M\t(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)\n+#define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH\t(0x0 << ICE_AQ_VSI_VLAN_EMOD_S)\n+#define ICE_AQ_VSI_VLAN_EMOD_STR_UP\t(0x1 << ICE_AQ_VSI_VLAN_EMOD_S)\n+#define ICE_AQ_VSI_VLAN_EMOD_STR\t(0x2 << ICE_AQ_VSI_VLAN_EMOD_S)\n+#define ICE_AQ_VSI_VLAN_EMOD_NOTHING\t(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)\n+\tu8 pvlan_reserved2[3];\n+\t/* ingress egress up sections */\n+\t__le32 ingress_table; /* bitmap, 3 bits per up */\n+#define ICE_AQ_VSI_UP_TABLE_UP0_S\t0\n+#define ICE_AQ_VSI_UP_TABLE_UP0_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP1_S\t3\n+#define ICE_AQ_VSI_UP_TABLE_UP1_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP2_S\t6\n+#define ICE_AQ_VSI_UP_TABLE_UP2_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP3_S\t9\n+#define ICE_AQ_VSI_UP_TABLE_UP3_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP4_S\t12\n+#define ICE_AQ_VSI_UP_TABLE_UP4_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP5_S\t15\n+#define ICE_AQ_VSI_UP_TABLE_UP5_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP6_S\t18\n+#define ICE_AQ_VSI_UP_TABLE_UP6_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP7_S\t21\n+#define ICE_AQ_VSI_UP_TABLE_UP7_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)\n+\t__le32 egress_table;   /* same defines as for ingress table */\n+\t/* outer tags section */\n+\t__le16 outer_tag;\n+\tu8 outer_tag_flags;\n+#define ICE_AQ_VSI_OUTER_TAG_MODE_S\t0\n+#define ICE_AQ_VSI_OUTER_TAG_MODE_M\t(0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)\n+#define ICE_AQ_VSI_OUTER_TAG_NOTHING\t0x0\n+#define ICE_AQ_VSI_OUTER_TAG_REMOVE\t0x1\n+#define ICE_AQ_VSI_OUTER_TAG_COPY\t0x2\n+#define ICE_AQ_VSI_OUTER_TAG_TYPE_S\t2\n+#define ICE_AQ_VSI_OUTER_TAG_TYPE_M\t(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)\n+#define ICE_AQ_VSI_OUTER_TAG_NONE\t0x0\n+#define ICE_AQ_VSI_OUTER_TAG_STAG\t0x1\n+#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100\t0x2\n+#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100\t0x3\n+#define ICE_AQ_VSI_OUTER_TAG_INSERT\tBIT(4)\n+#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)\n+\tu8 outer_tag_reserved;\n+\t/* queue mapping section */\n+\t__le16 mapping_flags;\n+#define ICE_AQ_VSI_Q_MAP_CONTIG\t0x0\n+#define ICE_AQ_VSI_Q_MAP_NONCONTIG\tBIT(0)\n+\t__le16 q_mapping[16];\n+#define ICE_AQ_VSI_Q_S\t\t0\n+#define ICE_AQ_VSI_Q_M\t\t(0x7FF << ICE_AQ_VSI_Q_S)\n+\t__le16 tc_mapping[8];\n+#define ICE_AQ_VSI_TC_Q_OFFSET_S\t0\n+#define ICE_AQ_VSI_TC_Q_OFFSET_M\t(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)\n+#define ICE_AQ_VSI_TC_Q_NUM_S\t\t11\n+#define ICE_AQ_VSI_TC_Q_NUM_M\t\t(0xF << ICE_AQ_VSI_TC_Q_NUM_S)\n+\t/* queueing option section */\n+\tu8 q_opt_rss;\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S\t0\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI\t0x0\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF\t0x2\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL\t0x3\n+#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S\t2\n+#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M\t(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S\t6\n+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ\t(0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ\t(0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_XOR\t(0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_JHASH\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+\tu8 q_opt_tc;\n+#define ICE_AQ_VSI_Q_OPT_TC_OVR_S\t0\n+#define ICE_AQ_VSI_Q_OPT_TC_OVR_M\t(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)\n+#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR\tBIT(7)\n+\tu8 q_opt_flags;\n+#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN\tBIT(0)\n+\tu8 q_opt_reserved[3];\n+\t/* outer up section */\n+\t__le32 outer_up_table; /* same structure and defines as ingress tbl */\n+\t/* section 10 */\n+\t__le16 sect_10_reserved;\n+\t/* flow director section */\n+\t__le16 fd_options;\n+#define ICE_AQ_VSI_FD_ENABLE\t\tBIT(0)\n+#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE\tBIT(1)\n+#define ICE_AQ_VSI_FD_PROG_ENABLE\tBIT(3)\n+\t__le16 max_fd_fltr_dedicated;\n+\t__le16 max_fd_fltr_shared;\n+\t__le16 fd_def_q;\n+#define ICE_AQ_VSI_FD_DEF_Q_S\t\t0\n+#define ICE_AQ_VSI_FD_DEF_Q_M\t\t(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)\n+#define ICE_AQ_VSI_FD_DEF_GRP_S\t12\n+#define ICE_AQ_VSI_FD_DEF_GRP_M\t(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)\n+\t__le16 fd_report_opt;\n+#define ICE_AQ_VSI_FD_REPORT_Q_S\t0\n+#define ICE_AQ_VSI_FD_REPORT_Q_M\t(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)\n+#define ICE_AQ_VSI_FD_DEF_PRIORITY_S\t12\n+#define ICE_AQ_VSI_FD_DEF_PRIORITY_M\t(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)\n+#define ICE_AQ_VSI_FD_DEF_DROP\t\tBIT(15)\n+\t/* PASID section */\n+\t__le32 pasid_id;\n+#define ICE_AQ_VSI_PASID_ID_S\t\t0\n+#define ICE_AQ_VSI_PASID_ID_M\t\t(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)\n+#define ICE_AQ_VSI_PASID_ID_VALID\tBIT(31)\n+\tu8 reserved[24];\n+};\n+\n+\n+\n+#define ICE_MAX_NUM_RECIPES 64\n+\n+\n+/* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)\n+ */\n+struct ice_aqc_sw_rules {\n+\t/* ops: add switch rules, referring the number of rules.\n+\t * ops: update switch rules, referring the number of filters\n+\t * ops: remove switch rules, referring the entry index.\n+\t * ops: get switch rules, referring to the number of filters.\n+\t */\n+\t__le16 num_rules_fltr_entry_index;\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+#pragma pack(1)\n+/* Add/Update/Get/Remove lookup Rx/Tx command/response entry\n+ * This structures describes the lookup rules and associated actions. \"index\"\n+ * is returned as part of a response to a successful Add command, and can be\n+ * used to identify the rule for Update/Get/Remove commands.\n+ */\n+struct ice_sw_rule_lkup_rx_tx {\n+\t__le16 recipe_id;\n+#define ICE_SW_RECIPE_LOGICAL_PORT_FWD\t\t10\n+\t/* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */\n+\t__le16 src;\n+\t__le32 act;\n+\n+\t/* Bit 0:1 - Action type */\n+#define ICE_SINGLE_ACT_TYPE_S\t0x00\n+#define ICE_SINGLE_ACT_TYPE_M\t(0x3 << ICE_SINGLE_ACT_TYPE_S)\n+\n+\t/* Bit 2 - Loop back enable\n+\t * Bit 3 - LAN enable\n+\t */\n+#define ICE_SINGLE_ACT_LB_ENABLE\tBIT(2)\n+#define ICE_SINGLE_ACT_LAN_ENABLE\tBIT(3)\n+\n+\t/* Action type = 0 - Forward to VSI or VSI list */\n+#define ICE_SINGLE_ACT_VSI_FORWARDING\t0x0\n+\n+#define ICE_SINGLE_ACT_VSI_ID_S\t\t4\n+#define ICE_SINGLE_ACT_VSI_ID_M\t\t(0x3FF << ICE_SINGLE_ACT_VSI_ID_S)\n+#define ICE_SINGLE_ACT_VSI_LIST_ID_S\t4\n+#define ICE_SINGLE_ACT_VSI_LIST_ID_M\t(0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)\n+\t/* This bit needs to be set if action is forward to VSI list */\n+#define ICE_SINGLE_ACT_VSI_LIST\t\tBIT(14)\n+#define ICE_SINGLE_ACT_VALID_BIT\tBIT(17)\n+#define ICE_SINGLE_ACT_DROP\t\tBIT(18)\n+\n+\t/* Action type = 1 - Forward to Queue of Queue group */\n+#define ICE_SINGLE_ACT_TO_Q\t\t0x1\n+#define ICE_SINGLE_ACT_Q_INDEX_S\t4\n+#define ICE_SINGLE_ACT_Q_INDEX_M\t(0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)\n+#define ICE_SINGLE_ACT_Q_REGION_S\t15\n+#define ICE_SINGLE_ACT_Q_REGION_M\t(0x7 << ICE_SINGLE_ACT_Q_REGION_S)\n+#define ICE_SINGLE_ACT_Q_PRIORITY\tBIT(18)\n+\n+\t/* Action type = 2 - Prune */\n+#define ICE_SINGLE_ACT_PRUNE\t\t0x2\n+#define ICE_SINGLE_ACT_EGRESS\t\tBIT(15)\n+#define ICE_SINGLE_ACT_INGRESS\t\tBIT(16)\n+#define ICE_SINGLE_ACT_PRUNET\t\tBIT(17)\n+\t/* Bit 18 should be set to 0 for this action */\n+\n+\t/* Action type = 2 - Pointer */\n+#define ICE_SINGLE_ACT_PTR\t\t0x2\n+#define ICE_SINGLE_ACT_PTR_VAL_S\t4\n+#define ICE_SINGLE_ACT_PTR_VAL_M\t(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)\n+\t/* Bit 18 should be set to 1 */\n+#define ICE_SINGLE_ACT_PTR_BIT\t\tBIT(18)\n+\n+\t/* Action type = 3 - Other actions. Last two bits\n+\t * are other action identifier\n+\t */\n+#define ICE_SINGLE_ACT_OTHER_ACTS\t\t0x3\n+#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S\t17\n+#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M\t\\\n+\t\t\t\t(0x3 << \\ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)\n+\n+\t/* Bit 17:18 - Defines other actions */\n+\t/* Other action = 0 - Mirror VSI */\n+#define ICE_SINGLE_OTHER_ACT_MIRROR\t\t0\n+#define ICE_SINGLE_ACT_MIRROR_VSI_ID_S\t4\n+#define ICE_SINGLE_ACT_MIRROR_VSI_ID_M\t\\\n+\t\t\t\t(0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)\n+\n+\t/* Other action = 3 - Set Stat count */\n+#define ICE_SINGLE_OTHER_ACT_STAT_COUNT\t\t3\n+#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S\t4\n+#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M\t\\\n+\t\t\t\t(0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)\n+\n+\t__le16 index; /* The index of the rule in the lookup table */\n+\t/* Length and values of the header to be matched per recipe or\n+\t * lookup-type\n+\t */\n+\t__le16 hdr_len;\n+\tu8 hdr[1];\n+};\n+#pragma pack()\n+\n+\n+/* Add/Update/Remove large action command/response entry\n+ * \"index\" is returned as part of a response to a successful Add command, and\n+ * can be used to identify the action for Update/Get/Remove commands.\n+ */\n+struct ice_sw_rule_lg_act {\n+\t__le16 index; /* Index in large action table */\n+\t__le16 size;\n+\t__le32 act[1]; /* array of size for actions */\n+\t/* Max number of large actions */\n+#define ICE_MAX_LG_ACT\t4\n+\t/* Bit 0:1 - Action type */\n+#define ICE_LG_ACT_TYPE_S\t0\n+#define ICE_LG_ACT_TYPE_M\t(0x7 << ICE_LG_ACT_TYPE_S)\n+\n+\t/* Action type = 0 - Forward to VSI or VSI list */\n+#define ICE_LG_ACT_VSI_FORWARDING\t0\n+#define ICE_LG_ACT_VSI_ID_S\t\t3\n+#define ICE_LG_ACT_VSI_ID_M\t\t(0x3FF << ICE_LG_ACT_VSI_ID_S)\n+#define ICE_LG_ACT_VSI_LIST_ID_S\t3\n+#define ICE_LG_ACT_VSI_LIST_ID_M\t(0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)\n+\t/* This bit needs to be set if action is forward to VSI list */\n+#define ICE_LG_ACT_VSI_LIST\t\tBIT(13)\n+\n+#define ICE_LG_ACT_VALID_BIT\t\tBIT(16)\n+\n+\t/* Action type = 1 - Forward to Queue of Queue group */\n+#define ICE_LG_ACT_TO_Q\t\t\t0x1\n+#define ICE_LG_ACT_Q_INDEX_S\t\t3\n+#define ICE_LG_ACT_Q_INDEX_M\t\t(0x7FF << ICE_LG_ACT_Q_INDEX_S)\n+#define ICE_LG_ACT_Q_REGION_S\t\t14\n+#define ICE_LG_ACT_Q_REGION_M\t\t(0x7 << ICE_LG_ACT_Q_REGION_S)\n+#define ICE_LG_ACT_Q_PRIORITY_SET\tBIT(17)\n+\n+\t/* Action type = 2 - Prune */\n+#define ICE_LG_ACT_PRUNE\t\t0x2\n+#define ICE_LG_ACT_EGRESS\t\tBIT(14)\n+#define ICE_LG_ACT_INGRESS\t\tBIT(15)\n+#define ICE_LG_ACT_PRUNET\t\tBIT(16)\n+\n+\t/* Action type = 3 - Mirror VSI */\n+#define ICE_LG_OTHER_ACT_MIRROR\t\t0x3\n+#define ICE_LG_ACT_MIRROR_VSI_ID_S\t3\n+#define ICE_LG_ACT_MIRROR_VSI_ID_M\t(0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)\n+\n+\t/* Action type = 5 - Generic Value */\n+#define ICE_LG_ACT_GENERIC\t\t0x5\n+#define ICE_LG_ACT_GENERIC_VALUE_S\t3\n+#define ICE_LG_ACT_GENERIC_VALUE_M\t(0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)\n+#define ICE_LG_ACT_GENERIC_OFFSET_S\t19\n+#define ICE_LG_ACT_GENERIC_OFFSET_M\t(0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)\n+#define ICE_LG_ACT_GENERIC_PRIORITY_S\t22\n+#define ICE_LG_ACT_GENERIC_PRIORITY_M\t(0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)\n+#define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX\t7\n+\n+\t/* Action = 7 - Set Stat count */\n+#define ICE_LG_ACT_STAT_COUNT\t\t0x7\n+#define ICE_LG_ACT_STAT_COUNT_S\t\t3\n+#define ICE_LG_ACT_STAT_COUNT_M\t\t(0x7F << ICE_LG_ACT_STAT_COUNT_S)\n+};\n+\n+\n+/* Add/Update/Remove VSI list command/response entry\n+ * \"index\" is returned as part of a response to a successful Add command, and\n+ * can be used to identify the VSI list for Update/Get/Remove commands.\n+ */\n+struct ice_sw_rule_vsi_list {\n+\t__le16 index; /* Index of VSI/Prune list */\n+\t__le16 number_vsi;\n+\t__le16 vsi[1]; /* Array of number_vsi VSI numbers */\n+};\n+\n+\n+#pragma pack(1)\n+/* Query VSI list command/response entry */\n+struct ice_sw_rule_vsi_list_query {\n+\t__le16 index;\n+\tice_declare_bitmap(vsi_list, ICE_MAX_VSI);\n+};\n+#pragma pack()\n+\n+\n+/* Add switch rule response:\n+ * Content of return buffer is same as the input buffer. The status field and\n+ * LUT index are updated as part of the response\n+ */\n+struct ice_aqc_sw_rules_elem {\n+\t__le16 type; /* Switch rule type, one of T_... */\n+#define ICE_AQC_SW_RULES_T_LKUP_RX\t\t0x0\n+#define ICE_AQC_SW_RULES_T_LKUP_TX\t\t0x1\n+#define ICE_AQC_SW_RULES_T_LG_ACT\t\t0x2\n+#define ICE_AQC_SW_RULES_T_VSI_LIST_SET\t\t0x3\n+#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR\t0x4\n+#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET\t0x5\n+#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR\t0x6\n+\t__le16 status;\n+\tunion {\n+\t\tstruct ice_sw_rule_lkup_rx_tx lkup_tx_rx;\n+\t\tstruct ice_sw_rule_lg_act lg_act;\n+\t\tstruct ice_sw_rule_vsi_list vsi_list;\n+\t\tstruct ice_sw_rule_vsi_list_query vsi_list_query;\n+\t} __packed pdata;\n+};\n+\n+\n+\n+\n+/* Get Default Topology (indirect 0x0400) */\n+struct ice_aqc_get_topo {\n+\tu8 port_num;\n+\tu8 num_branches;\n+\t__le16 reserved1;\n+\t__le32 reserved2;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Update TSE (indirect 0x0403)\n+ * Get TSE (indirect 0x0404)\n+ * Add TSE (indirect 0x0401)\n+ * Delete TSE (indirect 0x040F)\n+ * Move TSE (indirect 0x0408)\n+ * Suspend Nodes (indirect 0x0409)\n+ * Resume Nodes (indirect 0x040A)\n+ */\n+struct ice_aqc_sched_elem_cmd {\n+\t__le16 num_elem_req;\t/* Used by commands */\n+\t__le16 num_elem_resp;\t/* Used by responses */\n+\t__le32 reserved;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* This is the buffer for:\n+ * Suspend Nodes (indirect 0x0409)\n+ * Resume Nodes (indirect 0x040A)\n+ */\n+struct ice_aqc_suspend_resume_elem {\n+\t__le32 teid[1];\n+};\n+\n+\n+\n+\n+struct ice_aqc_elem_info_bw {\n+\t__le16 bw_profile_idx;\n+\t__le16 bw_alloc;\n+};\n+\n+\n+struct ice_aqc_txsched_elem {\n+\tu8 elem_type; /* Special field, reserved for some aq calls */\n+#define ICE_AQC_ELEM_TYPE_UNDEFINED\t\t0x0\n+#define ICE_AQC_ELEM_TYPE_ROOT_PORT\t\t0x1\n+#define ICE_AQC_ELEM_TYPE_TC\t\t\t0x2\n+#define ICE_AQC_ELEM_TYPE_SE_GENERIC\t\t0x3\n+#define ICE_AQC_ELEM_TYPE_ENTRY_POINT\t\t0x4\n+#define ICE_AQC_ELEM_TYPE_LEAF\t\t\t0x5\n+#define ICE_AQC_ELEM_TYPE_SE_PADDED\t\t0x6\n+\tu8 valid_sections;\n+#define ICE_AQC_ELEM_VALID_GENERIC\t\tBIT(0)\n+#define ICE_AQC_ELEM_VALID_CIR\t\t\tBIT(1)\n+#define ICE_AQC_ELEM_VALID_EIR\t\t\tBIT(2)\n+#define ICE_AQC_ELEM_VALID_SHARED\t\tBIT(3)\n+\tu8 generic;\n+#define ICE_AQC_ELEM_GENERIC_MODE_M\t\t0x1\n+#define ICE_AQC_ELEM_GENERIC_PRIO_S\t\t0x1\n+#define ICE_AQC_ELEM_GENERIC_PRIO_M\t(0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)\n+#define ICE_AQC_ELEM_GENERIC_SP_S\t\t0x4\n+#define ICE_AQC_ELEM_GENERIC_SP_M\t(0x1 << ICE_AQC_ELEM_GENERIC_SP_S)\n+#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S\t0x5\n+#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M\t\\\n+\t(0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)\n+\tu8 flags; /* Special field, reserved for some aq calls */\n+#define ICE_AQC_ELEM_FLAG_SUSPEND_M\t\t0x1\n+\tstruct ice_aqc_elem_info_bw cir_bw;\n+\tstruct ice_aqc_elem_info_bw eir_bw;\n+\t__le16 srl_id;\n+\t__le16 reserved2;\n+};\n+\n+\n+struct ice_aqc_txsched_elem_data {\n+\t__le32 parent_teid;\n+\t__le32 node_teid;\n+\tstruct ice_aqc_txsched_elem data;\n+};\n+\n+\n+struct ice_aqc_txsched_topo_grp_info_hdr {\n+\t__le32 parent_teid;\n+\t__le16 num_elems;\n+\t__le16 reserved2;\n+};\n+\n+\n+struct ice_aqc_add_elem {\n+\tstruct ice_aqc_txsched_topo_grp_info_hdr hdr;\n+\tstruct ice_aqc_txsched_elem_data generic[1];\n+};\n+\n+\n+\n+struct ice_aqc_get_elem {\n+\tstruct ice_aqc_txsched_elem_data generic[1];\n+};\n+\n+\n+struct ice_aqc_get_topo_elem {\n+\tstruct ice_aqc_txsched_topo_grp_info_hdr hdr;\n+\tstruct ice_aqc_txsched_elem_data\n+\t\tgeneric[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n+};\n+\n+\n+struct ice_aqc_delete_elem {\n+\tstruct ice_aqc_txsched_topo_grp_info_hdr hdr;\n+\t__le32 teid[1];\n+};\n+\n+\n+\n+\n+\n+\n+\n+/* Query Scheduler Resource Allocation (indirect 0x0412)\n+ * This indirect command retrieves the scheduler resources allocated by\n+ * EMP Firmware to the given PF.\n+ */\n+struct ice_aqc_query_txsched_res {\n+\tu8 reserved[8];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+struct ice_aqc_generic_sched_props {\n+\t__le16 phys_levels;\n+\t__le16 logical_levels;\n+\tu8 flattening_bitmap;\n+\tu8 max_device_cgds;\n+\tu8 max_pf_cgds;\n+\tu8 rsvd0;\n+\t__le16 rdma_qsets;\n+\tu8 rsvd1[22];\n+};\n+\n+\n+struct ice_aqc_layer_props {\n+\tu8 logical_layer;\n+\tu8 chunk_size;\n+\t__le16 max_device_nodes;\n+\t__le16 max_pf_nodes;\n+\tu8 rsvd0[4];\n+\t__le16 max_sibl_grp_sz;\n+\t__le16 max_cir_rl_profiles;\n+\t__le16 max_eir_rl_profiles;\n+\t__le16 max_srl_profiles;\n+\tu8 rsvd1[14];\n+};\n+\n+\n+struct ice_aqc_query_txsched_res_resp {\n+\tstruct ice_aqc_generic_sched_props sched_props;\n+\tstruct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n+};\n+\n+\n+\n+/* Get PHY capabilities (indirect 0x0600) */\n+struct ice_aqc_get_phy_caps {\n+\tu8 lport_num;\n+\tu8 reserved;\n+\t__le16 param0;\n+\t/* 18.0 - Report qualified modules */\n+#define ICE_AQC_GET_PHY_RQM\t\tBIT(0)\n+\t/* 18.1 - 18.2 : Report mode\n+\t * 00b - Report NVM capabilities\n+\t * 01b - Report topology capabilities\n+\t * 10b - Report SW configured\n+\t */\n+#define ICE_AQC_REPORT_MODE_S\t\t1\n+#define ICE_AQC_REPORT_MODE_M\t\t(3 << ICE_AQC_REPORT_MODE_S)\n+#define ICE_AQC_REPORT_NVM_CAP\t\t0\n+#define ICE_AQC_REPORT_TOPO_CAP\t\tBIT(1)\n+#define ICE_AQC_REPORT_SW_CFG\t\tBIT(2)\n+\t__le32 reserved1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* This is #define of PHY type (Extended):\n+ * The first set of defines is for phy_type_low.\n+ */\n+#define ICE_PHY_TYPE_LOW_100BASE_TX\t\tBIT_ULL(0)\n+#define ICE_PHY_TYPE_LOW_100M_SGMII\t\tBIT_ULL(1)\n+#define ICE_PHY_TYPE_LOW_1000BASE_T\t\tBIT_ULL(2)\n+#define ICE_PHY_TYPE_LOW_1000BASE_SX\t\tBIT_ULL(3)\n+#define ICE_PHY_TYPE_LOW_1000BASE_LX\t\tBIT_ULL(4)\n+#define ICE_PHY_TYPE_LOW_1000BASE_KX\t\tBIT_ULL(5)\n+#define ICE_PHY_TYPE_LOW_1G_SGMII\t\tBIT_ULL(6)\n+#define ICE_PHY_TYPE_LOW_2500BASE_T\t\tBIT_ULL(7)\n+#define ICE_PHY_TYPE_LOW_2500BASE_X\t\tBIT_ULL(8)\n+#define ICE_PHY_TYPE_LOW_2500BASE_KX\t\tBIT_ULL(9)\n+#define ICE_PHY_TYPE_LOW_5GBASE_T\t\tBIT_ULL(10)\n+#define ICE_PHY_TYPE_LOW_5GBASE_KR\t\tBIT_ULL(11)\n+#define ICE_PHY_TYPE_LOW_10GBASE_T\t\tBIT_ULL(12)\n+#define ICE_PHY_TYPE_LOW_10G_SFI_DA\t\tBIT_ULL(13)\n+#define ICE_PHY_TYPE_LOW_10GBASE_SR\t\tBIT_ULL(14)\n+#define ICE_PHY_TYPE_LOW_10GBASE_LR\t\tBIT_ULL(15)\n+#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1\t\tBIT_ULL(16)\n+#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC\tBIT_ULL(17)\n+#define ICE_PHY_TYPE_LOW_10G_SFI_C2C\t\tBIT_ULL(18)\n+#define ICE_PHY_TYPE_LOW_25GBASE_T\t\tBIT_ULL(19)\n+#define ICE_PHY_TYPE_LOW_25GBASE_CR\t\tBIT_ULL(20)\n+#define ICE_PHY_TYPE_LOW_25GBASE_CR_S\t\tBIT_ULL(21)\n+#define ICE_PHY_TYPE_LOW_25GBASE_CR1\t\tBIT_ULL(22)\n+#define ICE_PHY_TYPE_LOW_25GBASE_SR\t\tBIT_ULL(23)\n+#define ICE_PHY_TYPE_LOW_25GBASE_LR\t\tBIT_ULL(24)\n+#define ICE_PHY_TYPE_LOW_25GBASE_KR\t\tBIT_ULL(25)\n+#define ICE_PHY_TYPE_LOW_25GBASE_KR_S\t\tBIT_ULL(26)\n+#define ICE_PHY_TYPE_LOW_25GBASE_KR1\t\tBIT_ULL(27)\n+#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC\tBIT_ULL(28)\n+#define ICE_PHY_TYPE_LOW_25G_AUI_C2C\t\tBIT_ULL(29)\n+#define ICE_PHY_TYPE_LOW_40GBASE_CR4\t\tBIT_ULL(30)\n+#define ICE_PHY_TYPE_LOW_40GBASE_SR4\t\tBIT_ULL(31)\n+#define ICE_PHY_TYPE_LOW_40GBASE_LR4\t\tBIT_ULL(32)\n+#define ICE_PHY_TYPE_LOW_40GBASE_KR4\t\tBIT_ULL(33)\n+#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC\tBIT_ULL(34)\n+#define ICE_PHY_TYPE_LOW_40G_XLAUI\t\tBIT_ULL(35)\n+#define ICE_PHY_TYPE_LOW_MAX_INDEX\t\t63\n+\n+struct ice_aqc_get_phy_caps_data {\n+\t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n+\t__le64 reserved;\n+\tu8 caps;\n+#define ICE_AQC_PHY_EN_TX_LINK_PAUSE\t\t\tBIT(0)\n+#define ICE_AQC_PHY_EN_RX_LINK_PAUSE\t\t\tBIT(1)\n+#define ICE_AQC_PHY_LOW_POWER_MODE\t\t\tBIT(2)\n+#define ICE_AQC_PHY_EN_LINK\t\t\t\tBIT(3)\n+#define ICE_AQC_PHY_AN_MODE\t\t\t\tBIT(4)\n+#define ICE_AQC_PHY_EN_MOD_QUAL\t\t\t\tBIT(5)\n+#define ICE_AQC_PHY_EN_LESM\t\t\t\tBIT(6)\n+#define ICE_AQC_PHY_EN_AUTO_FEC\t\t\t\tBIT(7)\n+#define ICE_AQC_PHY_CAPS_MASK\t\t\t\tMAKEMASK(0xff, 0)\n+\tu8 low_power_ctrl;\n+#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG\t\tBIT(0)\n+\t__le16 eee_cap;\n+#define ICE_AQC_PHY_EEE_EN_100BASE_TX\t\t\tBIT(0)\n+#define ICE_AQC_PHY_EEE_EN_1000BASE_T\t\t\tBIT(1)\n+#define ICE_AQC_PHY_EEE_EN_10GBASE_T\t\t\tBIT(2)\n+#define ICE_AQC_PHY_EEE_EN_1000BASE_KX\t\t\tBIT(3)\n+#define ICE_AQC_PHY_EEE_EN_10GBASE_KR\t\t\tBIT(4)\n+#define ICE_AQC_PHY_EEE_EN_25GBASE_KR\t\t\tBIT(5)\n+#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4\t\t\tBIT(6)\n+\t__le16 eeer_value;\n+\tu8 phy_id_oui[4]; /* PHY/Module ID connected on the port */\n+\tu8 phy_fw_ver[8];\n+\tu8 link_fec_options;\n+#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN\t\tBIT(0)\n+#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ\t\tBIT(1)\n+#define ICE_AQC_PHY_FEC_25G_RS_528_REQ\t\t\tBIT(2)\n+#define ICE_AQC_PHY_FEC_25G_KR_REQ\t\t\tBIT(3)\n+#define ICE_AQC_PHY_FEC_25G_RS_544_REQ\t\t\tBIT(4)\n+#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN\t\tBIT(6)\n+#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN\t\tBIT(7)\n+#define ICE_AQC_PHY_FEC_MASK\t\t\t\tMAKEMASK(0xdf, 0)\n+\tu8 extended_compliance_code;\n+#define ICE_MODULE_TYPE_TOTAL_BYTE\t\t\t3\n+\tu8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];\n+#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS\t\t\t0xA0\n+#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS\t\t0x80\n+#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE\tBIT(0)\n+#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE\tBIT(1)\n+#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR\t\tBIT(4)\n+#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR\t\tBIT(5)\n+#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM\t\tBIT(6)\n+#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER\t\tBIT(7)\n+#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS\t\t\t0xA0\n+#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS\t\t0x86\n+\tu8 qualified_module_count;\n+#define ICE_AQC_QUAL_MOD_COUNT_MAX\t\t\t16\n+\tstruct {\n+\t\tu8 v_oui[3];\n+\t\tu8 rsvd3;\n+\t\tu8 v_part[16];\n+\t\t__le32 v_rev;\n+\t\t__le64 rsvd8;\n+\t} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];\n+};\n+\n+\n+/* Set PHY capabilities (direct 0x0601)\n+ * NOTE: This command must be followed by setup link and restart auto-neg\n+ */\n+struct ice_aqc_set_phy_cfg {\n+\tu8 lport_num;\n+\tu8 reserved[7];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Set PHY config command data structure */\n+struct ice_aqc_set_phy_cfg_data {\n+\t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n+\t__le64 rsvd0;\n+\tu8 caps;\n+#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY\t\tBIT(0)\n+#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY\t\tBIT(1)\n+#define ICE_AQ_PHY_ENA_LOW_POWER\tBIT(2)\n+#define ICE_AQ_PHY_ENA_LINK\t\tBIT(3)\n+#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT\tBIT(5)\n+#define ICE_AQ_PHY_ENA_LESM\t\tBIT(6)\n+#define ICE_AQ_PHY_ENA_AUTO_FEC\t\tBIT(7)\n+\tu8 low_power_ctrl;\n+\t__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */\n+\t__le16 eeer_value;\n+\tu8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */\n+\tu8 rsvd1;\n+};\n+\n+\n+\n+/* Restart AN command data structure (direct 0x0605)\n+ * Also used for response, with only the lport_num field present.\n+ */\n+struct ice_aqc_restart_an {\n+\tu8 lport_num;\n+\tu8 reserved;\n+\tu8 cmd_flags;\n+#define ICE_AQC_RESTART_AN_LINK_RESTART\tBIT(1)\n+#define ICE_AQC_RESTART_AN_LINK_ENABLE\tBIT(2)\n+\tu8 reserved2[13];\n+};\n+\n+\n+/* Get link status (indirect 0x0607), also used for Link Status Event */\n+struct ice_aqc_get_link_status {\n+\tu8 lport_num;\n+\tu8 reserved;\n+\t__le16 cmd_flags;\n+#define ICE_AQ_LSE_M\t\t\t0x3\n+#define ICE_AQ_LSE_NOP\t\t\t0x0\n+#define ICE_AQ_LSE_DIS\t\t\t0x2\n+#define ICE_AQ_LSE_ENA\t\t\t0x3\n+\t/* only response uses this flag */\n+#define ICE_AQ_LSE_IS_ENABLED\t\t0x1\n+\t__le32 reserved2;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Get link status response data structure, also used for Link Status Event */\n+struct ice_aqc_get_link_status_data {\n+\tu8 topo_media_conflict;\n+#define ICE_AQ_LINK_TOPO_CONFLICT\tBIT(0)\n+#define ICE_AQ_LINK_MEDIA_CONFLICT\tBIT(1)\n+#define ICE_AQ_LINK_TOPO_CORRUPT\tBIT(2)\n+\tu8 reserved1;\n+\tu8 link_info;\n+#define ICE_AQ_LINK_UP\t\t\tBIT(0)\t/* Link Status */\n+#define ICE_AQ_LINK_FAULT\t\tBIT(1)\n+#define ICE_AQ_LINK_FAULT_TX\t\tBIT(2)\n+#define ICE_AQ_LINK_FAULT_RX\t\tBIT(3)\n+#define ICE_AQ_LINK_FAULT_REMOTE\tBIT(4)\n+#define ICE_AQ_LINK_UP_PORT\t\tBIT(5)\t/* External Port Link Status */\n+#define ICE_AQ_MEDIA_AVAILABLE\t\tBIT(6)\n+#define ICE_AQ_SIGNAL_DETECT\t\tBIT(7)\n+\tu8 an_info;\n+#define ICE_AQ_AN_COMPLETED\t\tBIT(0)\n+#define ICE_AQ_LP_AN_ABILITY\t\tBIT(1)\n+#define ICE_AQ_PD_FAULT\t\t\tBIT(2)\t/* Parallel Detection Fault */\n+#define ICE_AQ_FEC_EN\t\t\tBIT(3)\n+#define ICE_AQ_PHY_LOW_POWER\t\tBIT(4)\t/* Low Power State */\n+#define ICE_AQ_LINK_PAUSE_TX\t\tBIT(5)\n+#define ICE_AQ_LINK_PAUSE_RX\t\tBIT(6)\n+#define ICE_AQ_QUALIFIED_MODULE\t\tBIT(7)\n+\tu8 ext_info;\n+#define ICE_AQ_LINK_PHY_TEMP_ALARM\tBIT(0)\n+#define ICE_AQ_LINK_EXCESSIVE_ERRORS\tBIT(1)\t/* Excessive Link Errors */\n+\t/* Port TX Suspended */\n+#define ICE_AQ_LINK_TX_S\t\t2\n+#define ICE_AQ_LINK_TX_M\t\t(0x03 << ICE_AQ_LINK_TX_S)\n+#define ICE_AQ_LINK_TX_ACTIVE\t\t0\n+#define ICE_AQ_LINK_TX_DRAINED\t\t1\n+#define ICE_AQ_LINK_TX_FLUSHED\t\t3\n+\tu8 reserved2;\n+\t__le16 max_frame_size;\n+\tu8 cfg;\n+#define ICE_AQ_LINK_25G_KR_FEC_EN\tBIT(0)\n+#define ICE_AQ_LINK_25G_RS_528_FEC_EN\tBIT(1)\n+#define ICE_AQ_LINK_25G_RS_544_FEC_EN\tBIT(2)\n+#define ICE_AQ_FEC_MASK\t\t\tMAKEMASK(0x7, 0)\n+\t/* Pacing Config */\n+#define ICE_AQ_CFG_PACING_S\t\t3\n+#define ICE_AQ_CFG_PACING_M\t\t(0xF << ICE_AQ_CFG_PACING_S)\n+#define ICE_AQ_CFG_PACING_TYPE_M\tBIT(7)\n+#define ICE_AQ_CFG_PACING_TYPE_AVG\t0\n+#define ICE_AQ_CFG_PACING_TYPE_FIXED\tICE_AQ_CFG_PACING_TYPE_M\n+\t/* External Device Power Ability */\n+\tu8 power_desc;\n+#define ICE_AQ_PWR_CLASS_M\t\t0x3\n+#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH\t0\n+#define ICE_AQ_LINK_PWR_BASET_HIGH\t1\n+#define ICE_AQ_LINK_PWR_QSFP_CLASS_1\t0\n+#define ICE_AQ_LINK_PWR_QSFP_CLASS_2\t1\n+#define ICE_AQ_LINK_PWR_QSFP_CLASS_3\t2\n+#define ICE_AQ_LINK_PWR_QSFP_CLASS_4\t3\n+\t__le16 link_speed;\n+#define ICE_AQ_LINK_SPEED_10MB\t\tBIT(0)\n+#define ICE_AQ_LINK_SPEED_100MB\t\tBIT(1)\n+#define ICE_AQ_LINK_SPEED_1000MB\tBIT(2)\n+#define ICE_AQ_LINK_SPEED_2500MB\tBIT(3)\n+#define ICE_AQ_LINK_SPEED_5GB\t\tBIT(4)\n+#define ICE_AQ_LINK_SPEED_10GB\t\tBIT(5)\n+#define ICE_AQ_LINK_SPEED_20GB\t\tBIT(6)\n+#define ICE_AQ_LINK_SPEED_25GB\t\tBIT(7)\n+#define ICE_AQ_LINK_SPEED_40GB\t\tBIT(8)\n+#define ICE_AQ_LINK_SPEED_UNKNOWN\tBIT(15)\n+\t__le32 reserved3; /* Aligns next field to 8-byte boundary */\n+\t__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */\n+\t__le64 reserved4;\n+};\n+\n+\n+/* Set event mask command (direct 0x0613) */\n+struct ice_aqc_set_event_mask {\n+\tu8\tlport_num;\n+\tu8\treserved[7];\n+\t__le16\tevent_mask;\n+#define ICE_AQ_LINK_EVENT_UPDOWN\t\tBIT(1)\n+#define ICE_AQ_LINK_EVENT_MEDIA_NA\t\tBIT(2)\n+#define ICE_AQ_LINK_EVENT_LINK_FAULT\t\tBIT(3)\n+#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM\tBIT(4)\n+#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS\tBIT(5)\n+#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT\t\tBIT(6)\n+#define ICE_AQ_LINK_EVENT_AN_COMPLETED\t\tBIT(7)\n+#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL\tBIT(8)\n+#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED\tBIT(9)\n+\tu8\treserved1[6];\n+};\n+\n+\n+\n+/* Set MAC Loopback command (direct 0x0620) */\n+struct ice_aqc_set_mac_lb {\n+\tu8 lb_mode;\n+#define ICE_AQ_MAC_LB_EN\t\tBIT(0)\n+#define ICE_AQ_MAC_LB_OSC_CLK\t\tBIT(1)\n+\tu8 reserved[15];\n+};\n+\n+\n+\n+\n+\n+/* Set Port Identification LED (direct, 0x06E9) */\n+struct ice_aqc_set_port_id_led {\n+\tu8 lport_num;\n+\tu8 lport_num_valid;\n+#define ICE_AQC_PORT_ID_PORT_NUM_VALID\tBIT(0)\n+\tu8 ident_mode;\n+#define ICE_AQC_PORT_IDENT_LED_BLINK\tBIT(0)\n+#define ICE_AQC_PORT_IDENT_LED_ORIG\t0\n+\tu8 rsvd[13];\n+};\n+\n+\n+\n+/* NVM Read command (indirect 0x0701)\n+ * NVM Erase commands (direct 0x0702)\n+ * NVM Update commands (indirect 0x0703)\n+ */\n+struct ice_aqc_nvm {\n+\t__le16 offset_low;\n+\tu8 offset_high;\n+\tu8 cmd_flags;\n+#define ICE_AQC_NVM_LAST_CMD\t\tBIT(0)\n+#define ICE_AQC_NVM_PCIR_REQ\t\tBIT(0)\t/* Used by NVM Update reply */\n+#define ICE_AQC_NVM_PRESERVATION_S\t1\n+#define ICE_AQC_NVM_PRESERVATION_M\t(3 << ICE_AQC_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_NO_PRESERVATION\t(0 << ICE_AQC_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_PRESERVE_ALL\tBIT(1)\n+#define ICE_AQC_NVM_FACTORY_DEFAULT\t(2 << ICE_AQC_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_PRESERVE_SELECTED\t(3 << ICE_AQC_NVM_PRESERVATION_S)\n+#define ICE_AQC_NVM_FLASH_ONLY\t\tBIT(7)\n+\t__le16 module_typeid;\n+\t__le16 length;\n+#define ICE_AQC_NVM_ERASE_LEN\t0xFFFF\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* Used for 0x0704 as well as for 0x0705 commands */\n+struct ice_aqc_nvm_cfg {\n+\tu8\tcmd_flags;\n+#define ICE_AQC_ANVM_MULTIPLE_ELEMS\tBIT(0)\n+#define ICE_AQC_ANVM_IMMEDIATE_FIELD\tBIT(1)\n+#define ICE_AQC_ANVM_NEW_CFG\t\tBIT(2)\n+\tu8\treserved;\n+\t__le16 count;\n+\t__le16 id;\n+\tu8 reserved1[2];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+struct ice_aqc_nvm_cfg_data {\n+\t__le16 field_id;\n+\t__le16 field_options;\n+\t__le16 field_value;\n+};\n+\n+\n+/* NVM Checksum Command (direct, 0x0706) */\n+struct ice_aqc_nvm_checksum {\n+\tu8 flags;\n+#define ICE_AQC_NVM_CHECKSUM_VERIFY\tBIT(0)\n+#define ICE_AQC_NVM_CHECKSUM_RECALC\tBIT(1)\n+\tu8 rsvd;\n+\t__le16 checksum; /* Used only by response */\n+#define ICE_AQC_NVM_CHECKSUM_CORRECT\t0xBABA\n+\tu8 rsvd2[12];\n+};\n+\n+\n+/**\n+ * Send to PF command (indirect 0x0801) id is only used by PF\n+ *\n+ * Send to VF command (indirect 0x0802) id is only used by PF\n+ *\n+ */\n+struct ice_aqc_pf_vf_msg {\n+\t__le32 id;\n+\tu32 reserved;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+\n+\n+/* Get/Set RSS key (indirect 0x0B04/0x0B02) */\n+struct ice_aqc_get_set_rss_key {\n+#define ICE_AQC_GSET_RSS_KEY_VSI_VALID\tBIT(15)\n+#define ICE_AQC_GSET_RSS_KEY_VSI_ID_S\t0\n+#define ICE_AQC_GSET_RSS_KEY_VSI_ID_M\t(0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)\n+\t__le16 vsi_id;\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE\t0x28\n+#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE\t0xC\n+\n+struct ice_aqc_get_set_rss_keys {\n+\tu8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];\n+\tu8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];\n+};\n+\n+\n+/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */\n+struct ice_aqc_get_set_rss_lut {\n+#define ICE_AQC_GSET_RSS_LUT_VSI_VALID\tBIT(15)\n+#define ICE_AQC_GSET_RSS_LUT_VSI_ID_S\t0\n+#define ICE_AQC_GSET_RSS_LUT_VSI_ID_M\t(0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)\n+\t__le16 vsi_id;\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S\t0\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M\t\\\n+\t\t\t\t(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)\n+\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI\t 0\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF\t 1\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL\t 2\n+\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S\t 2\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M\t \\\n+\t\t\t\t(0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)\n+\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128\t 128\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512\t 512\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K\t 2048\n+#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG\t 2\n+\n+#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S\t 4\n+#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M\t \\\n+\t\t\t\t(0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)\n+\n+\t__le16 flags;\n+\t__le32 reserved;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+\n+\n+\n+/* Add TX LAN Queues (indirect 0x0C30) */\n+struct ice_aqc_add_txqs {\n+\tu8 num_qgrps;\n+\tu8 reserved[3];\n+\t__le32 reserved1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* This is the descriptor of each queue entry for the Add TX LAN Queues\n+ * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.\n+ */\n+struct ice_aqc_add_txqs_perq {\n+\t__le16 txq_id;\n+\tu8 rsvd[2];\n+\t__le32 q_teid;\n+\tu8 txq_ctx[22];\n+\tu8 rsvd2[2];\n+\tstruct ice_aqc_txsched_elem info;\n+};\n+\n+\n+/* The format of the command buffer for Add TX LAN Queues (0x0C30)\n+ * is an array of the following structs. Please note that the length of\n+ * each struct ice_aqc_add_tx_qgrp is variable due\n+ * to the variable number of queues in each group!\n+ */\n+struct ice_aqc_add_tx_qgrp {\n+\t__le32 parent_teid;\n+\tu8 num_txqs;\n+\tu8 rsvd[3];\n+\tstruct ice_aqc_add_txqs_perq txqs[1];\n+};\n+\n+\n+/* Disable TX LAN Queues (indirect 0x0C31) */\n+struct ice_aqc_dis_txqs {\n+\tu8 cmd_type;\n+#define ICE_AQC_Q_DIS_CMD_S\t\t0\n+#define ICE_AQC_Q_DIS_CMD_M\t\t(0x3 << ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET\t(0 << ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_VM_RESET\tBIT(ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_VF_RESET\t(2 << ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_PF_RESET\t(3 << ICE_AQC_Q_DIS_CMD_S)\n+#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL\tBIT(2)\n+#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE\tBIT(3)\n+\tu8 num_entries;\n+\t__le16 vmvf_and_timeout;\n+#define ICE_AQC_Q_DIS_VMVF_NUM_S\t0\n+#define ICE_AQC_Q_DIS_VMVF_NUM_M\t(0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)\n+#define ICE_AQC_Q_DIS_TIMEOUT_S\t\t10\n+#define ICE_AQC_Q_DIS_TIMEOUT_M\t\t(0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)\n+\t__le32 blocked_cgds;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/* The buffer for Disable TX LAN Queues (indirect 0x0C31)\n+ * contains the following structures, arrayed one after the\n+ * other.\n+ * Note: Since the q_id is 16 bits wide, if the\n+ * number of queues is even, then 2 bytes of alignment MUST be\n+ * added before the start of the next group, to allow correct\n+ * alignment of the parent_teid field.\n+ */\n+struct ice_aqc_dis_txq_item {\n+\t__le32 parent_teid;\n+\tu8 num_qs;\n+\tu8 rsvd;\n+\t/* The length of the q_id array varies according to num_qs */\n+\t__le16 q_id[1];\n+\t/* This only applies from F8 onward */\n+#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S\t\t15\n+#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q\t\\\n+\t\t\t(0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)\n+#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET\t\\\n+\t\t\t(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)\n+};\n+\n+\n+struct ice_aqc_dis_txq {\n+\tstruct ice_aqc_dis_txq_item qgrps[1];\n+};\n+\n+\n+\n+\n+\n+\n+\n+/* Lan Queue Overflow Event (direct, 0x1001) */\n+struct ice_aqc_event_lan_overflow {\n+\t__le32 prtdcb_ruptq;\n+\t__le32 qtx_ctl;\n+\tu8 reserved[8];\n+};\n+\n+\n+\n+/* Configure Firmware Logging Command (indirect 0xFF09)\n+ * Logging Information Read Response (indirect 0xFF10)\n+ * Note: The 0xFF10 command has no input parameters.\n+ */\n+struct ice_aqc_fw_logging {\n+\tu8 log_ctrl;\n+#define ICE_AQC_FW_LOG_AQ_EN\t\tBIT(0)\n+#define ICE_AQC_FW_LOG_UART_EN\t\tBIT(1)\n+\tu8 rsvd0;\n+\tu8 log_ctrl_valid; /* Not used by 0xFF10 Response */\n+#define ICE_AQC_FW_LOG_AQ_VALID\t\tBIT(0)\n+#define ICE_AQC_FW_LOG_UART_VALID\tBIT(1)\n+\tu8 rsvd1[5];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+enum ice_aqc_fw_logging_mod {\n+\tICE_AQC_FW_LOG_ID_GENERAL = 0,\n+\tICE_AQC_FW_LOG_ID_CTRL,\n+\tICE_AQC_FW_LOG_ID_LINK,\n+\tICE_AQC_FW_LOG_ID_LINK_TOPO,\n+\tICE_AQC_FW_LOG_ID_DNL,\n+\tICE_AQC_FW_LOG_ID_I2C,\n+\tICE_AQC_FW_LOG_ID_SDP,\n+\tICE_AQC_FW_LOG_ID_MDIO,\n+\tICE_AQC_FW_LOG_ID_ADMINQ,\n+\tICE_AQC_FW_LOG_ID_HDMA,\n+\tICE_AQC_FW_LOG_ID_LLDP,\n+\tICE_AQC_FW_LOG_ID_DCBX,\n+\tICE_AQC_FW_LOG_ID_DCB,\n+\tICE_AQC_FW_LOG_ID_NETPROXY,\n+\tICE_AQC_FW_LOG_ID_NVM,\n+\tICE_AQC_FW_LOG_ID_AUTH,\n+\tICE_AQC_FW_LOG_ID_VPD,\n+\tICE_AQC_FW_LOG_ID_IOSF,\n+\tICE_AQC_FW_LOG_ID_PARSER,\n+\tICE_AQC_FW_LOG_ID_SW,\n+\tICE_AQC_FW_LOG_ID_SCHEDULER,\n+\tICE_AQC_FW_LOG_ID_TXQ,\n+\tICE_AQC_FW_LOG_ID_RSVD,\n+\tICE_AQC_FW_LOG_ID_POST,\n+\tICE_AQC_FW_LOG_ID_WATCHDOG,\n+\tICE_AQC_FW_LOG_ID_TASK_DISPATCH,\n+\tICE_AQC_FW_LOG_ID_MNG,\n+\tICE_AQC_FW_LOG_ID_MAX,\n+};\n+\n+/* This is the buffer for both of the logging commands.\n+ * The entry array size depends on the datalen parameter in the descriptor.\n+ * There will be a total of datalen / 2 entries.\n+ */\n+struct ice_aqc_fw_logging_data {\n+\t__le16 entry[1];\n+#define ICE_AQC_FW_LOG_ID_S\t\t0\n+#define ICE_AQC_FW_LOG_ID_M\t\t(0xFFF << ICE_AQC_FW_LOG_ID_S)\n+\n+#define ICE_AQC_FW_LOG_CONF_SUCCESS\t0\t/* Used by response */\n+#define ICE_AQC_FW_LOG_CONF_BAD_INDX\tBIT(12)\t/* Used by response */\n+\n+#define ICE_AQC_FW_LOG_EN_S\t\t12\n+#define ICE_AQC_FW_LOG_EN_M\t\t(0xF << ICE_AQC_FW_LOG_EN_S)\n+#define ICE_AQC_FW_LOG_INFO_EN\t\tBIT(12)\t/* Used by command */\n+#define ICE_AQC_FW_LOG_INIT_EN\t\tBIT(13)\t/* Used by command */\n+#define ICE_AQC_FW_LOG_FLOW_EN\t\tBIT(14)\t/* Used by command */\n+#define ICE_AQC_FW_LOG_ERR_EN\t\tBIT(15)\t/* Used by command */\n+};\n+\n+\n+/* Get/Clear FW Log (indirect 0xFF11) */\n+struct ice_aqc_get_clear_fw_log {\n+\tu8 flags;\n+#define ICE_AQC_FW_LOG_CLEAR\t\tBIT(0)\n+#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL\tBIT(1)\n+\tu8 rsvd1[7];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+\n+/**\n+ * struct ice_aq_desc - Admin Queue (AQ) descriptor\n+ * @flags: ICE_AQ_FLAG_* flags\n+ * @opcode: AQ command opcode\n+ * @datalen: length in bytes of indirect/external data buffer\n+ * @retval: return value from firmware\n+ * @cookie_h: opaque data high-half\n+ * @cookie_l: opaque data low-half\n+ * @params: command-specific parameters\n+ *\n+ * Descriptor format for commands the driver posts on the Admin Transmit Queue\n+ * (ATQ). The firmware writes back onto the command descriptor and returns\n+ * the result of the command. Asynchronous events that are not an immediate\n+ * result of the command are written to the Admin Receive Queue (ARQ) using\n+ * the same descriptor format. Descriptors are in little-endian notation with\n+ * 32-bit words.\n+ */\n+struct ice_aq_desc {\n+\t__le16 flags;\n+\t__le16 opcode;\n+\t__le16 datalen;\n+\t__le16 retval;\n+\t__le32 cookie_high;\n+\t__le32 cookie_low;\n+\tunion {\n+\t\tu8 raw[16];\n+\t\tstruct ice_aqc_generic generic;\n+\t\tstruct ice_aqc_get_ver get_ver;\n+\t\tstruct ice_aqc_q_shutdown q_shutdown;\n+\t\tstruct ice_aqc_req_res res_owner;\n+\t\tstruct ice_aqc_manage_mac_read mac_read;\n+\t\tstruct ice_aqc_manage_mac_write mac_write;\n+\t\tstruct ice_aqc_clear_pxe clear_pxe;\n+\t\tstruct ice_aqc_list_caps get_cap;\n+\t\tstruct ice_aqc_get_phy_caps get_phy;\n+\t\tstruct ice_aqc_set_phy_cfg set_phy;\n+\t\tstruct ice_aqc_restart_an restart_an;\n+\t\tstruct ice_aqc_set_port_id_led set_port_id_led;\n+\t\tstruct ice_aqc_get_sw_cfg get_sw_conf;\n+\t\tstruct ice_aqc_sw_rules sw_rules;\n+\t\tstruct ice_aqc_get_topo get_topo;\n+\t\tstruct ice_aqc_sched_elem_cmd sched_elem_cmd;\n+\t\tstruct ice_aqc_query_txsched_res query_sched_res;\n+\t\tstruct ice_aqc_nvm nvm;\n+\t\tstruct ice_aqc_nvm_cfg nvm_cfg;\n+\t\tstruct ice_aqc_nvm_checksum nvm_checksum;\n+\t\tstruct ice_aqc_pf_vf_msg virt;\n+\t\tstruct ice_aqc_get_set_rss_lut get_set_rss_lut;\n+\t\tstruct ice_aqc_get_set_rss_key get_set_rss_key;\n+\t\tstruct ice_aqc_add_txqs add_txqs;\n+\t\tstruct ice_aqc_dis_txqs dis_txqs;\n+\t\tstruct ice_aqc_add_get_update_free_vsi vsi_cmd;\n+\t\tstruct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;\n+\t\tstruct ice_aqc_fw_logging fw_logging;\n+\t\tstruct ice_aqc_get_clear_fw_log get_clear_fw_log;\n+\t\tstruct ice_aqc_set_mac_lb set_mac_lb;\n+\t\tstruct ice_aqc_alloc_free_res_cmd sw_res_ctrl;\n+\t\tstruct ice_aqc_set_event_mask set_event_mask;\n+\t\tstruct ice_aqc_get_link_status get_link_status;\n+\t} params;\n+};\n+\n+\n+/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */\n+#define ICE_AQ_LG_BUF\t512\n+\n+/* Flags sub-structure\n+ * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |\n+ * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |\n+ */\n+\n+/* command flags and offsets */\n+#define ICE_AQ_FLAG_DD_S\t0\n+#define ICE_AQ_FLAG_CMP_S\t1\n+#define ICE_AQ_FLAG_ERR_S\t2\n+#define ICE_AQ_FLAG_VFE_S\t3\n+#define ICE_AQ_FLAG_LB_S\t9\n+#define ICE_AQ_FLAG_RD_S\t10\n+#define ICE_AQ_FLAG_VFC_S\t11\n+#define ICE_AQ_FLAG_BUF_S\t12\n+#define ICE_AQ_FLAG_SI_S\t13\n+#define ICE_AQ_FLAG_EI_S\t14\n+#define ICE_AQ_FLAG_FE_S\t15\n+\n+#define ICE_AQ_FLAG_DD\t\tBIT(ICE_AQ_FLAG_DD_S)  /* 0x1    */\n+#define ICE_AQ_FLAG_CMP\t\tBIT(ICE_AQ_FLAG_CMP_S) /* 0x2    */\n+#define ICE_AQ_FLAG_ERR\t\tBIT(ICE_AQ_FLAG_ERR_S) /* 0x4    */\n+#define ICE_AQ_FLAG_VFE\t\tBIT(ICE_AQ_FLAG_VFE_S) /* 0x8    */\n+#define ICE_AQ_FLAG_LB\t\tBIT(ICE_AQ_FLAG_LB_S)  /* 0x200  */\n+#define ICE_AQ_FLAG_RD\t\tBIT(ICE_AQ_FLAG_RD_S)  /* 0x400  */\n+#define ICE_AQ_FLAG_VFC\t\tBIT(ICE_AQ_FLAG_VFC_S) /* 0x800  */\n+#define ICE_AQ_FLAG_BUF\t\tBIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */\n+#define ICE_AQ_FLAG_SI\t\tBIT(ICE_AQ_FLAG_SI_S)  /* 0x2000 */\n+#define ICE_AQ_FLAG_EI\t\tBIT(ICE_AQ_FLAG_EI_S)  /* 0x4000 */\n+#define ICE_AQ_FLAG_FE\t\tBIT(ICE_AQ_FLAG_FE_S)  /* 0x8000 */\n+\n+/* error codes */\n+enum ice_aq_err {\n+\tICE_AQ_RC_OK\t\t= 0,  /* Success */\n+\tICE_AQ_RC_EPERM\t\t= 1,  /* Operation not permitted */\n+\tICE_AQ_RC_ENOENT\t= 2,  /* No such element */\n+\tICE_AQ_RC_ESRCH\t\t= 3,  /* Bad opcode */\n+\tICE_AQ_RC_EINTR\t\t= 4,  /* Operation interrupted */\n+\tICE_AQ_RC_EIO\t\t= 5,  /* I/O error */\n+\tICE_AQ_RC_ENXIO\t\t= 6,  /* No such resource */\n+\tICE_AQ_RC_E2BIG\t\t= 7,  /* Arg too long */\n+\tICE_AQ_RC_EAGAIN\t= 8,  /* Try again */\n+\tICE_AQ_RC_ENOMEM\t= 9,  /* Out of memory */\n+\tICE_AQ_RC_EACCES\t= 10, /* Permission denied */\n+\tICE_AQ_RC_EFAULT\t= 11, /* Bad address */\n+\tICE_AQ_RC_EBUSY\t\t= 12, /* Device or resource busy */\n+\tICE_AQ_RC_EEXIST\t= 13, /* object already exists */\n+\tICE_AQ_RC_EINVAL\t= 14, /* Invalid argument */\n+\tICE_AQ_RC_ENOTTY\t= 15, /* Not a typewriter */\n+\tICE_AQ_RC_ENOSPC\t= 16, /* No space left or allocation failure */\n+\tICE_AQ_RC_ENOSYS\t= 17, /* Function not implemented */\n+\tICE_AQ_RC_ERANGE\t= 18, /* Parameter out of range */\n+\tICE_AQ_RC_EFLUSHED\t= 19, /* Cmd flushed due to prev cmd error */\n+\tICE_AQ_RC_BAD_ADDR\t= 20, /* Descriptor contains a bad pointer */\n+\tICE_AQ_RC_EMODE\t\t= 21, /* Op not allowed in current dev mode */\n+\tICE_AQ_RC_EFBIG\t\t= 22, /* File too big */\n+\tICE_AQ_RC_ESBCOMP\t= 23, /* SB-IOSF completion unsuccessful */\n+\tICE_AQ_RC_ENOSEC\t= 24, /* Missing security manifest */\n+\tICE_AQ_RC_EBADSIG\t= 25, /* Bad RSA signature */\n+\tICE_AQ_RC_ESVN\t\t= 26, /* SVN number prohibits this package */\n+\tICE_AQ_RC_EBADMAN\t= 27, /* Manifest hash mismatch */\n+\tICE_AQ_RC_EBADBUF\t= 28, /* Buffer hash mismatches manifest */\n+};\n+\n+/* Admin Queue command opcodes */\n+enum ice_adminq_opc {\n+\t/* AQ commands */\n+\tice_aqc_opc_get_ver\t\t\t\t= 0x0001,\n+\tice_aqc_opc_driver_ver\t\t\t\t= 0x0002,\n+\tice_aqc_opc_q_shutdown\t\t\t\t= 0x0003,\n+\tice_aqc_opc_get_exp_err\t\t\t\t= 0x0005,\n+\n+\t/* resource ownership */\n+\tice_aqc_opc_req_res\t\t\t\t= 0x0008,\n+\tice_aqc_opc_release_res\t\t\t\t= 0x0009,\n+\n+\t/* device/function capabilities */\n+\tice_aqc_opc_list_func_caps\t\t\t= 0x000A,\n+\tice_aqc_opc_list_dev_caps\t\t\t= 0x000B,\n+\n+\t/* manage MAC address */\n+\tice_aqc_opc_manage_mac_read\t\t\t= 0x0107,\n+\tice_aqc_opc_manage_mac_write\t\t\t= 0x0108,\n+\n+\t/* PXE */\n+\tice_aqc_opc_clear_pxe_mode\t\t\t= 0x0110,\n+\n+\t/* internal switch commands */\n+\tice_aqc_opc_get_sw_cfg\t\t\t\t= 0x0200,\n+\n+\t/* Alloc/Free/Get Resources */\n+\tice_aqc_opc_get_res_alloc\t\t\t= 0x0204,\n+\tice_aqc_opc_alloc_res\t\t\t\t= 0x0208,\n+\tice_aqc_opc_free_res\t\t\t\t= 0x0209,\n+\tice_aqc_opc_get_allocd_res_desc\t\t\t= 0x020A,\n+\n+\t/* VSI commands */\n+\tice_aqc_opc_add_vsi\t\t\t\t= 0x0210,\n+\tice_aqc_opc_update_vsi\t\t\t\t= 0x0211,\n+\tice_aqc_opc_get_vsi_params\t\t\t= 0x0212,\n+\tice_aqc_opc_free_vsi\t\t\t\t= 0x0213,\n+\n+\n+\n+\t/* switch rules population commands */\n+\tice_aqc_opc_add_sw_rules\t\t\t= 0x02A0,\n+\tice_aqc_opc_update_sw_rules\t\t\t= 0x02A1,\n+\tice_aqc_opc_remove_sw_rules\t\t\t= 0x02A2,\n+\tice_aqc_opc_get_sw_rules\t\t\t= 0x02A3,\n+\tice_aqc_opc_clear_pf_cfg\t\t\t= 0x02A4,\n+\n+\n+\t/* transmit scheduler commands */\n+\tice_aqc_opc_get_dflt_topo\t\t\t= 0x0400,\n+\tice_aqc_opc_add_sched_elems\t\t\t= 0x0401,\n+\tice_aqc_opc_cfg_sched_elems\t\t\t= 0x0403,\n+\tice_aqc_opc_get_sched_elems\t\t\t= 0x0404,\n+\tice_aqc_opc_move_sched_elems\t\t\t= 0x0408,\n+\tice_aqc_opc_suspend_sched_elems\t\t\t= 0x0409,\n+\tice_aqc_opc_resume_sched_elems\t\t\t= 0x040A,\n+\tice_aqc_opc_suspend_sched_traffic\t\t= 0x040B,\n+\tice_aqc_opc_resume_sched_traffic\t\t= 0x040C,\n+\tice_aqc_opc_delete_sched_elems\t\t\t= 0x040F,\n+\tice_aqc_opc_query_sched_res\t\t\t= 0x0412,\n+\tice_aqc_opc_query_node_to_root\t\t\t= 0x0413,\n+\tice_aqc_opc_cfg_l2_node_cgd\t\t\t= 0x0414,\n+\n+\t/* PHY commands */\n+\tice_aqc_opc_get_phy_caps\t\t\t= 0x0600,\n+\tice_aqc_opc_set_phy_cfg\t\t\t\t= 0x0601,\n+\tice_aqc_opc_set_mac_cfg\t\t\t\t= 0x0603,\n+\tice_aqc_opc_restart_an\t\t\t\t= 0x0605,\n+\tice_aqc_opc_get_link_status\t\t\t= 0x0607,\n+\tice_aqc_opc_set_event_mask\t\t\t= 0x0613,\n+\tice_aqc_opc_set_mac_lb\t\t\t\t= 0x0620,\n+\tice_aqc_opc_set_port_id_led\t\t\t= 0x06E9,\n+\tice_aqc_opc_get_port_options\t\t\t= 0x06EA,\n+\tice_aqc_opc_set_port_option\t\t\t= 0x06EB,\n+\tice_aqc_opc_set_gpio\t\t\t\t= 0x06EC,\n+\tice_aqc_opc_get_gpio\t\t\t\t= 0x06ED,\n+\n+\t/* NVM commands */\n+\tice_aqc_opc_nvm_read\t\t\t\t= 0x0701,\n+\tice_aqc_opc_nvm_erase\t\t\t\t= 0x0702,\n+\tice_aqc_opc_nvm_update\t\t\t\t= 0x0703,\n+\tice_aqc_opc_nvm_cfg_read\t\t\t= 0x0704,\n+\tice_aqc_opc_nvm_cfg_write\t\t\t= 0x0705,\n+\tice_aqc_opc_nvm_checksum\t\t\t= 0x0706,\n+\n+\t/* PF/VF mailbox commands */\n+\tice_mbx_opc_send_msg_to_pf\t\t\t= 0x0801,\n+\tice_mbx_opc_send_msg_to_vf\t\t\t= 0x0802,\n+\n+\t/* RSS commands */\n+\tice_aqc_opc_set_rss_key\t\t\t\t= 0x0B02,\n+\tice_aqc_opc_set_rss_lut\t\t\t\t= 0x0B03,\n+\tice_aqc_opc_get_rss_key\t\t\t\t= 0x0B04,\n+\tice_aqc_opc_get_rss_lut\t\t\t\t= 0x0B05,\n+\n+\t/* TX queue handling commands/events */\n+\tice_aqc_opc_add_txqs\t\t\t\t= 0x0C30,\n+\tice_aqc_opc_dis_txqs\t\t\t\t= 0x0C31,\n+\tice_aqc_opc_txqs_cleanup\t\t\t= 0x0C31,\n+\tice_aqc_opc_move_recfg_txqs\t\t\t= 0x0C32,\n+\n+\n+\n+\n+\t/* Standalone Commands/Events */\n+\tice_aqc_opc_event_lan_overflow\t\t\t= 0x1001,\n+\n+\t/* debug commands */\n+\tice_aqc_opc_fw_logging\t\t\t\t= 0xFF09,\n+\tice_aqc_opc_fw_logging_info\t\t\t= 0xFF10,\n+\tice_aqc_opc_get_clear_fw_log\t\t\t= 0xFF11\n+};\n+\n+#endif /* _ICE_ADMINQ_CMD_H_ */\ndiff --git a/drivers/net/ice/base/ice_alloc.h b/drivers/net/ice/base/ice_alloc.h\nnew file mode 100644\nindex 0000000..7883104\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_alloc.h\n@@ -0,0 +1,22 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_ALLOC_H_\n+#define _ICE_ALLOC_H_\n+\n+/* Memory types */\n+enum ice_memset_type {\n+\tICE_NONDMA_MEM = 0,\n+\tICE_DMA_MEM\n+};\n+\n+/* Memcpy types */\n+enum ice_memcpy_type {\n+\tICE_NONDMA_TO_NONDMA = 0,\n+\tICE_NONDMA_TO_DMA,\n+\tICE_DMA_TO_DMA,\n+\tICE_DMA_TO_NONDMA\n+};\n+\n+#endif /* _ICE_ALLOC_H_ */\ndiff --git a/drivers/net/ice/base/ice_bitops.h b/drivers/net/ice/base/ice_bitops.h\nnew file mode 100644\nindex 0000000..ac6a51b\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_bitops.h\n@@ -0,0 +1,233 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_BITOPS_H_\n+#define _ICE_BITOPS_H_\n+\n+/* Define the size of the bitmap chunk */\n+typedef u32 ice_bitmap_t;\n+\n+\n+/* Number of bits per bitmap chunk */\n+#define BITS_PER_CHUNK\t\t(BITS_PER_BYTE * sizeof(ice_bitmap_t))\n+/* Determine which chunk a bit belongs in */\n+#define BIT_CHUNK(nr)\t\t((nr) / BITS_PER_CHUNK)\n+/* How many chunks are required to store this many bits */\n+#define BITS_TO_CHUNKS(sz)\tDIVIDE_AND_ROUND_UP((sz), BITS_PER_CHUNK)\n+/* Which bit inside a chunk this bit corresponds to */\n+#define BIT_IN_CHUNK(nr)\tBIT((nr) % BITS_PER_CHUNK)\n+/* How many bits are valid in the last chunk, assumes nr > 0 */\n+#define LAST_CHUNK_BITS(nr)\t((((nr) - 1) % BITS_PER_CHUNK) + 1)\n+/* Generate a bitmask of valid bits in the last chunk, assumes nr > 0 */\n+#define LAST_CHUNK_MASK(nr)\t(((ice_bitmap_t)~0) >> \\\n+\t\t\t\t (BITS_PER_CHUNK - LAST_CHUNK_BITS(nr)))\n+\n+#define ice_declare_bitmap(A, sz) \\\n+\tice_bitmap_t A[BITS_TO_CHUNKS(sz)]\n+\n+/**\n+ * ice_is_bit_set - Check state of a bit in a bitmap\n+ * @bitmap: the bitmap to check\n+ * @nr: the bit to check\n+ *\n+ * Returns true if bit nr of bitmap is set. False otherwise. Assumes that nr\n+ * is less than the size of the bitmap.\n+ */\n+static inline bool ice_is_bit_set(const ice_bitmap_t *bitmap, u16 nr)\n+{\n+\treturn !!(bitmap[BIT_CHUNK(nr)] & BIT_IN_CHUNK(nr));\n+}\n+\n+/**\n+ * ice_clear_bit - Clear a bit in a bitmap\n+ * @bitmap: the bitmap to change\n+ * @nr: the bit to change\n+ *\n+ * Clears the bit nr in bitmap. Assumes that nr is less than the size of the\n+ * bitmap.\n+ */\n+static inline void ice_clear_bit(u16 nr, ice_bitmap_t *bitmap)\n+{\n+\tbitmap[BIT_CHUNK(nr)] &= ~BIT_IN_CHUNK(nr);\n+}\n+\n+/**\n+ * ice_set_bit - Set a bit in a bitmap\n+ * @bitmap: the bitmap to change\n+ * @nr: the bit to change\n+ *\n+ * Sets the bit nr in bitmap. Assumes that nr is less than the size of the\n+ * bitmap.\n+ */\n+static inline void ice_set_bit(u16 nr, ice_bitmap_t *bitmap)\n+{\n+\tbitmap[BIT_CHUNK(nr)] |= BIT_IN_CHUNK(nr);\n+}\n+\n+/* ice_zero_bitmap - set bits of bitmap to zero.\n+ * @bmp: bitmap to set zeros\n+ * @size: Size of the bitmaps in bits\n+ *\n+ * This function sets bits of a bitmap to zero.\n+ */\n+static inline void ice_zero_bitmap(ice_bitmap_t *bmp, u16 size)\n+{\n+\tice_bitmap_t mask;\n+\tu16 i;\n+\n+\t/* Handle all but last chunk*/\n+\tfor (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)\n+\t\tbmp[i] = 0;\n+\t/* For the last chunk, we want to take care of not to modify bits\n+\t * outside the size boundary. ~mask take care of all the bits outside\n+\t * the boundary.\n+\t */\n+\tmask = LAST_CHUNK_MASK(size);\n+\tbmp[i] &= ~mask;\n+}\n+\n+/**\n+ * ice_and_bitmap - bitwise AND 2 bitmaps and store result in dst bitmap\n+ * @dst: Destination bitmap that receive the result of the operation\n+ * @bmp1: The first bitmap to intersect\n+ * @bmp2: The second bitmap to intersect wit the first\n+ * @size: Size of the bitmaps in bits\n+ *\n+ * This function performs a bitwise AND on two \"source\" bitmaps of the same size\n+ * and stores the result to \"dst\" bitmap. The \"dst\" bitmap must be of the same\n+ * size as the \"source\" bitmaps to avoid buffer overflows. This function returns\n+ * a non-zero value if at least one bit location from both \"source\" bitmaps is\n+ * non-zero.\n+ */\n+static inline int\n+ice_and_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,\n+\t       const ice_bitmap_t *bmp2, u16 size)\n+{\n+\tice_bitmap_t res = 0, mask;\n+\tu16 i;\n+\n+\t/* Handle all but the last chunk */\n+\tfor (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++) {\n+\t\tdst[i] = bmp1[i] & bmp2[i];\n+\t\tres |= dst[i];\n+\t}\n+\n+\t/* We want to take care not to modify any bits outside of the bitmap\n+\t * size, even in the destination bitmap. Thus, we won't directly\n+\t * assign the last bitmap, but instead use a bitmask to ensure we only\n+\t * modify bits which are within the size, and leave any bits above the\n+\t * size value alone.\n+\t */\n+\tmask = LAST_CHUNK_MASK(size);\n+\tdst[i] &= ~mask;\n+\tdst[i] |= (bmp1[i] & bmp2[i]) & mask;\n+\tres |= dst[i] & mask;\n+\n+\treturn res != 0;\n+}\n+\n+/**\n+ * ice_or_bitmap - bitwise OR 2 bitmaps and store result in dst bitmap\n+ * @dst: Destination bitmap that receive the result of the operation\n+ * @bmp1: The first bitmap to intersect\n+ * @bmp2: The second bitmap to intersect wit the first\n+ * @size: Size of the bitmaps in bits\n+ *\n+ * This function performs a bitwise OR on two \"source\" bitmaps of the same size\n+ * and stores the result to \"dst\" bitmap. The \"dst\" bitmap must be of the same\n+ * size as the \"source\" bitmaps to avoid buffer overflows.\n+ */\n+static inline void\n+ice_or_bitmap(ice_bitmap_t *dst, const ice_bitmap_t *bmp1,\n+\t      const ice_bitmap_t *bmp2, u16 size)\n+{\n+\tice_bitmap_t mask;\n+\tu16 i;\n+\n+\t/* Handle all but last chunk*/\n+\tfor (i = 0; i < BITS_TO_CHUNKS(size) - 1; i++)\n+\t\tdst[i] = bmp1[i] | bmp2[i];\n+\n+\t/* We want to only OR bits within the size. Furthermore, we also do\n+\t * not want to modify destination bits which are beyond the specified\n+\t * size. Use a bitmask to ensure that we only modify the bits that are\n+\t * within the specified size.\n+\t */\n+\tmask = LAST_CHUNK_MASK(size);\n+\tdst[i] &= ~mask;\n+\tdst[i] |= (bmp1[i] | bmp2[i]) & mask;\n+}\n+\n+/**\n+ * ice_find_next_bit - Find the index of the next set bit of a bitmap\n+ * @bitmap: the bitmap to scan\n+ * @size: the size in bits of the bitmap\n+ * @offset: the offset to start at\n+ *\n+ * Scans the bitmap and returns the index of the first set bit which is equal\n+ * to or after the specified offset. Will return size if no bits are set.\n+ */\n+static inline u16\n+ice_find_next_bit(const ice_bitmap_t *bitmap, u16 size, u16 offset)\n+{\n+\tu16 i, j;\n+\n+\tif (offset >= size)\n+\t\treturn size;\n+\n+\t/* Since the starting position may not be directly on a chunk\n+\t * boundary, we need to be careful to handle the first chunk specially\n+\t */\n+\ti = BIT_CHUNK(offset);\n+\tif (bitmap[i] != 0) {\n+\t\tu16 off = i * BITS_PER_CHUNK;\n+\n+\t\tfor (j = offset % BITS_PER_CHUNK; j < BITS_PER_CHUNK; j++) {\n+\t\t\tif (ice_is_bit_set(bitmap, off + j))\n+\t\t\t\treturn min(size, (u16)(off + j));\n+\t\t}\n+\t}\n+\n+\t/* Now we handle the remaining chunks, if any */\n+\tfor (i++; i < BITS_TO_CHUNKS(size); i++) {\n+\t\tif (bitmap[i] != 0) {\n+\t\t\tu16 off = i * BITS_PER_CHUNK;\n+\n+\t\t\tfor (j = 0; j < BITS_PER_CHUNK; j++) {\n+\t\t\t\tif (ice_is_bit_set(bitmap, off + j))\n+\t\t\t\t\treturn min(size, (u16)(off + j));\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn size;\n+}\n+\n+/**\n+ * ice_find_first_bit - Find the index of the first set bit of a bitmap\n+ * @bitmap: the bitmap to scan\n+ * @size: the size in bits of the bitmap\n+ *\n+ * Scans the bitmap and returns the index of the first set bit. Will return\n+ * size if no bits are set.\n+ */\n+static inline u16 ice_find_first_bit(const ice_bitmap_t *bitmap, u16 size)\n+{\n+\treturn ice_find_next_bit(bitmap, size, 0);\n+}\n+\n+/**\n+ * ice_is_any_bit_set - Return true of any bit in the bitmap is set\n+ * @bitmap: the bitmap to check\n+ * @size: the size of the bitmap\n+ *\n+ * Equivalent to checking if ice_find_first_bit returns a value less than the\n+ * bitmap size.\n+ */\n+static inline bool ice_is_any_bit_set(ice_bitmap_t *bitmap, u16 size)\n+{\n+\treturn ice_find_first_bit(bitmap, size) < size;\n+}\n+\n+\n+#endif /* _ICE_BITOPS_H_ */\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nnew file mode 100644\nindex 0000000..d2e294e\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -0,0 +1,3332 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_common.h\"\n+#include \"ice_sched.h\"\n+#include \"ice_adminq_cmd.h\"\n+\n+#include \"ice_flow.h\"\n+#include \"ice_switch.h\"\n+\n+#define ICE_PF_RESET_WAIT_COUNT\t200\n+\n+#define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \\\n+\twr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \\\n+\t     ((ICE_RX_OPC_MDID << \\\n+\t       GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \\\n+\t      GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \\\n+\t     (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \\\n+\t      GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))\n+\n+#define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \\\n+\twr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \\\n+\t     (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \\\n+\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \\\n+\t     (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \\\n+\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \\\n+\t     (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \\\n+\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \\\n+\t     (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \\\n+\t      GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))\n+\n+\n+/**\n+ * ice_set_mac_type - Sets MAC type\n+ * @hw: pointer to the HW structure\n+ *\n+ * This function sets the MAC type of the adapter based on the\n+ * vendor ID and device ID stored in the hw structure.\n+ */\n+static enum ice_status ice_set_mac_type(struct ice_hw *hw)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_set_mac_type\\n\");\n+\n+\tif (hw->vendor_id == ICE_INTEL_VENDOR_ID) {\n+\t\tswitch (hw->device_id) {\n+\t\tdefault:\n+\t\t\thw->mac_type = ICE_MAC_GENERIC;\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\tstatus = ICE_ERR_DEVICE_NOT_SUPPORTED;\n+\t}\n+\n+\tice_debug(hw, ICE_DBG_INIT, \"found mac_type: %d, status: %d\\n\",\n+\t\t  hw->mac_type, status);\n+\n+\treturn status;\n+}\n+\n+#if defined(FPGA_SUPPORT) || defined(CVL_A0_SUPPORT)\n+void ice_dev_onetime_setup(struct ice_hw *hw)\n+{\n+\n+\t/* configure Rx - set non pxe mode */\n+\twr32(hw, GLLAN_RCTL_0, 0x1);\n+\n+\n+#define MBX_PF_VT_PFALLOC\t0x00231E80 /* Reset Source: CORER */\n+\t/* set VFs per PF */\n+\twr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF));\n+}\n+#endif /* FPGA_SUPPORT || CVL_A0_SUPPORT */\n+\n+/**\n+ * ice_clear_pf_cfg - Clear PF configuration\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port\n+ * configuration, flow director filters, etc.).\n+ */\n+enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+}\n+\n+/**\n+ * ice_aq_manage_mac_read - manage MAC address read command\n+ * @hw: pointer to the hw struct\n+ * @buf: a virtual buffer to hold the manage MAC read response\n+ * @buf_size: Size of the virtual buffer\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function is used to return per PF station MAC address (0x0107).\n+ * NOTE: Upon successful completion of this command, MAC address information\n+ * is returned in user specified buffer. Please interpret user specified\n+ * buffer as \"manage_mac_read\" response.\n+ * Response such as various MAC addresses are stored in HW struct (port.mac)\n+ * ice_aq_discover_caps is expected to be called before this function is called.\n+ */\n+static enum ice_status\n+ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,\n+\t\t       struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_manage_mac_read_resp *resp;\n+\tstruct ice_aqc_manage_mac_read *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\tu16 flags;\n+\tu8 i;\n+\n+\tcmd = &desc.params.mac_read;\n+\n+\tif (buf_size < sizeof(*resp))\n+\t\treturn ICE_ERR_BUF_TOO_SHORT;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (status)\n+\t\treturn status;\n+\n+\tresp = (struct ice_aqc_manage_mac_read_resp *)buf;\n+\tflags = LE16_TO_CPU(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;\n+\n+\tif (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {\n+\t\tice_debug(hw, ICE_DBG_LAN, \"got invalid MAC address\\n\");\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+\t/* A single port can report up to two (LAN and WoL) addresses */\n+\tfor (i = 0; i < cmd->num_addr; i++)\n+\t\tif (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {\n+\t\t\tice_memcpy(hw->port_info->mac.lan_addr,\n+\t\t\t\t   resp[i].mac_addr, ETH_ALEN,\n+\t\t\t\t   ICE_DMA_TO_NONDMA);\n+\t\t\tice_memcpy(hw->port_info->mac.perm_addr,\n+\t\t\t\t   resp[i].mac_addr,\n+\t\t\t\t   ETH_ALEN, ICE_DMA_TO_NONDMA);\n+\t\t\tbreak;\n+\t\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_aq_get_phy_caps - returns PHY capabilities\n+ * @pi: port information structure\n+ * @qual_mods: report qualified modules\n+ * @report_mode: report mode capabilities\n+ * @pcaps: structure for PHY capabilities to be filled\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Returns the various PHY capabilities supported on the Port (0x0600)\n+ */\n+enum ice_status\n+ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n+\t\t    struct ice_aqc_get_phy_caps_data *pcaps,\n+\t\t    struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_get_phy_caps *cmd;\n+\tu16 pcaps_size = sizeof(*pcaps);\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.get_phy;\n+\n+\tif (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);\n+\n+\tif (qual_mods)\n+\t\tcmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);\n+\n+\tcmd->param0 |= CPU_TO_LE16(report_mode);\n+\tstatus = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);\n+\n+\tif (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP)\n+\t\tpi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_get_media_type - Gets media type\n+ * @pi: port information structure\n+ */\n+static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)\n+{\n+\tstruct ice_link_status *hw_link_info;\n+\n+\tif (!pi)\n+\t\treturn ICE_MEDIA_UNKNOWN;\n+\n+\thw_link_info = &pi->phy.link_info;\n+\n+\tif (hw_link_info->phy_type_low) {\n+\t\tswitch (hw_link_info->phy_type_low) {\n+\t\tcase ICE_PHY_TYPE_LOW_1000BASE_SX:\n+\t\tcase ICE_PHY_TYPE_LOW_1000BASE_LX:\n+\t\tcase ICE_PHY_TYPE_LOW_10GBASE_SR:\n+\t\tcase ICE_PHY_TYPE_LOW_10GBASE_LR:\n+\t\tcase ICE_PHY_TYPE_LOW_10G_SFI_C2C:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_SR:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_LR:\n+\t\tcase ICE_PHY_TYPE_LOW_25G_AUI_C2C:\n+\t\tcase ICE_PHY_TYPE_LOW_40GBASE_SR4:\n+\t\tcase ICE_PHY_TYPE_LOW_40GBASE_LR4:\n+\t\t\treturn ICE_MEDIA_FIBER;\n+\t\tcase ICE_PHY_TYPE_LOW_100BASE_TX:\n+\t\tcase ICE_PHY_TYPE_LOW_1000BASE_T:\n+\t\tcase ICE_PHY_TYPE_LOW_2500BASE_T:\n+\t\tcase ICE_PHY_TYPE_LOW_5GBASE_T:\n+\t\tcase ICE_PHY_TYPE_LOW_10GBASE_T:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_T:\n+\t\t\treturn ICE_MEDIA_BASET;\n+\t\tcase ICE_PHY_TYPE_LOW_10G_SFI_DA:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR_S:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_CR1:\n+\t\tcase ICE_PHY_TYPE_LOW_40GBASE_CR4:\n+\t\t\treturn ICE_MEDIA_DA;\n+\t\tcase ICE_PHY_TYPE_LOW_1000BASE_KX:\n+\t\tcase ICE_PHY_TYPE_LOW_2500BASE_KX:\n+\t\tcase ICE_PHY_TYPE_LOW_2500BASE_X:\n+\t\tcase ICE_PHY_TYPE_LOW_5GBASE_KR:\n+\t\tcase ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR1:\n+\t\tcase ICE_PHY_TYPE_LOW_25GBASE_KR_S:\n+\t\tcase ICE_PHY_TYPE_LOW_40GBASE_KR4:\n+\t\t\treturn ICE_MEDIA_BACKPLANE;\n+\t\t}\n+\t}\n+\treturn ICE_MEDIA_UNKNOWN;\n+}\n+\n+/**\n+ * ice_aq_get_link_info\n+ * @pi: port information structure\n+ * @ena_lse: enable/disable LinkStatusEvent reporting\n+ * @link: pointer to link status structure - optional\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get Link Status (0x607). Returns the link status of the adapter.\n+ */\n+enum ice_status\n+ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n+\t\t     struct ice_link_status *link, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_link_status *hw_link_info_old, *hw_link_info;\n+\tstruct ice_aqc_get_link_status_data link_data = { 0 };\n+\tstruct ice_aqc_get_link_status *resp;\n+\tenum ice_media_type *hw_media_type;\n+\tstruct ice_fc_info *hw_fc_info;\n+\tbool tx_pause, rx_pause;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\tu16 cmd_flags;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\thw_link_info_old = &pi->phy.link_info_old;\n+\thw_media_type = &pi->phy.media_type;\n+\thw_link_info = &pi->phy.link_info;\n+\thw_fc_info = &pi->fc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);\n+\tcmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;\n+\tresp = &desc.params.get_link_status;\n+\tresp->cmd_flags = CPU_TO_LE16(cmd_flags);\n+\tresp->lport_num = pi->lport;\n+\n+\tstatus = ice_aq_send_cmd(pi->hw, &desc, &link_data, sizeof(link_data),\n+\t\t\t\t cd);\n+\n+\tif (status != ICE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* save off old link status information */\n+\t*hw_link_info_old = *hw_link_info;\n+\n+\t/* update current link status information */\n+\thw_link_info->link_speed = LE16_TO_CPU(link_data.link_speed);\n+\thw_link_info->phy_type_low = LE64_TO_CPU(link_data.phy_type_low);\n+\t*hw_media_type = ice_get_media_type(pi);\n+\thw_link_info->link_info = link_data.link_info;\n+\thw_link_info->an_info = link_data.an_info;\n+\thw_link_info->ext_info = link_data.ext_info;\n+\thw_link_info->max_frame_size = LE16_TO_CPU(link_data.max_frame_size);\n+\thw_link_info->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;\n+\thw_link_info->topo_media_conflict = link_data.topo_media_conflict;\n+\thw_link_info->pacing = link_data.cfg & ICE_AQ_CFG_PACING_M;\n+\n+\t/* update fc info */\n+\ttx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);\n+\trx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);\n+\tif (tx_pause && rx_pause)\n+\t\thw_fc_info->current_mode = ICE_FC_FULL;\n+\telse if (tx_pause)\n+\t\thw_fc_info->current_mode = ICE_FC_TX_PAUSE;\n+\telse if (rx_pause)\n+\t\thw_fc_info->current_mode = ICE_FC_RX_PAUSE;\n+\telse\n+\t\thw_fc_info->current_mode = ICE_FC_NONE;\n+\n+\thw_link_info->lse_ena =\n+\t\t!!(resp->cmd_flags & CPU_TO_LE16(ICE_AQ_LSE_IS_ENABLED));\n+\n+\n+\t/* save link status information */\n+\tif (link)\n+\t\t*link = *hw_link_info;\n+\n+\t/* flag cleared so calling functions don't call AQ again */\n+\tpi->phy.get_link_info = false;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_init_flex_flags\n+ * @hw: pointer to the hardware structure\n+ * @prof_id: Rx Descriptor Builder profile ID\n+ *\n+ * Function to initialize Rx flex flags\n+ */\n+static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)\n+{\n+\tu8 idx = 0;\n+\n+\t/* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:\n+\t * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE\n+\t * flexiflags1[3:0] - Not used for flag programming\n+\t * flexiflags2[7:0] - Tunnel and VLAN types\n+\t * 2 invalid fields in last index\n+\t */\n+\tswitch (prof_id) {\n+\t/* Rx flex flags are currently programmed for the NIC profiles only.\n+\t * Different flag bit programming configurations can be added per\n+\t * profile as needed.\n+\t */\n+\tcase ICE_RXDID_FLEX_NIC:\n+\tcase ICE_RXDID_FLEX_NIC_2:\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_FRG,\n+\t\t\t\t   ICE_RXFLG_UDP_GRE, ICE_RXFLG_PKT_DSI,\n+\t\t\t\t   ICE_RXFLG_FIN, idx++);\n+\t\t/* flex flag 1 is not used for flexi-flag programming, skipping\n+\t\t * these four FLG64 bits.\n+\t\t */\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_SYN, ICE_RXFLG_RST,\n+\t\t\t\t   ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_DSI,\n+\t\t\t\t   ICE_RXFLG_PKT_DSI, ICE_RXFLG_EVLAN_x8100,\n+\t\t\t\t   ICE_RXFLG_EVLAN_x9100, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_VLAN_x8100,\n+\t\t\t\t   ICE_RXFLG_TNL_VLAN, ICE_RXFLG_TNL_MAC,\n+\t\t\t\t   ICE_RXFLG_TNL0, idx++);\n+\t\tICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2,\n+\t\t\t\t   ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Flag programming for profile ID %d not supported\\n\",\n+\t\t\t  prof_id);\n+\t}\n+}\n+\n+/**\n+ * ice_init_flex_flds\n+ * @hw: pointer to the hardware structure\n+ * @prof_id: Rx Descriptor Builder profile ID\n+ *\n+ * Function to initialize flex descriptors\n+ */\n+static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)\n+{\n+\tenum ice_flex_rx_mdid mdid;\n+\n+\tswitch (prof_id) {\n+\tcase ICE_RXDID_FLEX_NIC:\n+\tcase ICE_RXDID_FLEX_NIC_2:\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0);\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1);\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2);\n+\n+\t\tmdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?\n+\t\t\tICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH;\n+\n+\t\tICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);\n+\n+\t\tice_init_flex_flags(hw, prof_id);\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Field init for profile ID %d not supported\\n\",\n+\t\t\t  prof_id);\n+\t}\n+}\n+\n+\n+/**\n+ * ice_init_fltr_mgmt_struct - initializes filter management list and locks\n+ * @hw: pointer to the hw struct\n+ */\n+static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)\n+{\n+\tstruct ice_switch_info *sw;\n+\n+\thw->switch_info = (struct ice_switch_info *)\n+\t\t\t  ice_malloc(hw, sizeof(*hw->switch_info));\n+\tsw = hw->switch_info;\n+\n+\tif (!sw)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tINIT_LIST_HEAD(&sw->vsi_list_map_head);\n+\n+\treturn ice_init_def_sw_recp(hw);\n+}\n+\n+/**\n+ * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks\n+ * @hw: pointer to the hw struct\n+ */\n+static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct ice_vsi_list_map_info *v_pos_map;\n+\tstruct ice_vsi_list_map_info *v_tmp_map;\n+\tstruct ice_sw_recipe *recps;\n+\tu8 i;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,\n+\t\t\t\t ice_vsi_list_map_info, list_entry) {\n+\t\tLIST_DEL(&v_pos_map->list_entry);\n+\t\tice_free(hw, v_pos_map);\n+\t}\n+\trecps = hw->switch_info->recp_list;\n+\tfor (i = 0; i < ICE_SW_LKUP_LAST; i++) {\n+\t\trecps[i].root_rid = i;\n+\n+\t\tif (recps[i].adv_rule) {\n+\t\t\tstruct ice_adv_fltr_mgmt_list_entry *tmp_entry;\n+\t\t\tstruct ice_adv_fltr_mgmt_list_entry *lst_itr;\n+\n+\t\t\tice_destroy_lock(&recps[i].filt_rule_lock);\n+\t\t\tLIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,\n+\t\t\t\t\t\t &recps[i].filt_rules,\n+\t\t\t\t\t\t ice_adv_fltr_mgmt_list_entry,\n+\t\t\t\t\t\t list_entry) {\n+\t\t\t\tLIST_DEL(&lst_itr->list_entry);\n+\t\t\t\tice_free(hw, lst_itr->lkups);\n+\t\t\t\tice_free(hw, lst_itr);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tstruct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;\n+\n+\t\t\tice_destroy_lock(&recps[i].filt_rule_lock);\n+\t\t\tLIST_FOR_EACH_ENTRY_SAFE(lst_itr, tmp_entry,\n+\t\t\t\t\t\t &recps[i].filt_rules,\n+\t\t\t\t\t\t ice_fltr_mgmt_list_entry,\n+\t\t\t\t\t\t list_entry) {\n+\t\t\t\tLIST_DEL(&lst_itr->list_entry);\n+\t\t\t\tice_free(hw, lst_itr);\n+\t\t\t}\n+\t\t}\n+\t}\n+\tice_rm_all_sw_replay_rule_info(hw);\n+\tice_free(hw, sw->recp_list);\n+\tice_free(hw, sw);\n+}\n+\n+#define ICE_FW_LOG_DESC_SIZE(n)\t(sizeof(struct ice_aqc_fw_logging_data) + \\\n+\t(((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))\n+#define ICE_FW_LOG_DESC_SIZE_MAX\t\\\n+\tICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)\n+\n+/**\n+ * ice_cfg_fw_log - configure FW logging\n+ * @hw: pointer to the hw struct\n+ * @enable: enable certain FW logging events if true, disable all if false\n+ *\n+ * This function enables/disables the FW logging via Rx CQ events and a UART\n+ * port based on predetermined configurations. FW logging via the Rx CQ can be\n+ * enabled/disabled for individual PF's. However, FW logging via the UART can\n+ * only be enabled/disabled for all PFs on the same device.\n+ *\n+ * To enable overall FW logging, the \"cq_en\" and \"uart_en\" enable bits in\n+ * hw->fw_log need to be set accordingly, e.g. based on user-provided input,\n+ * before initializing the device.\n+ *\n+ * When re/configuring FW logging, callers need to update the \"cfg\" elements of\n+ * the hw->fw_log.evnts array with the desired logging event configurations for\n+ * modules of interest. When disabling FW logging completely, the callers can\n+ * just pass false in the \"enable\" parameter. On completion, the function will\n+ * update the \"cur\" element of the hw->fw_log.evnts array with the resulting\n+ * logging event configurations of the modules that are being re/configured. FW\n+ * logging modules that are not part of a reconfiguration operation retain their\n+ * previous states.\n+ *\n+ * Before resetting the device, it is recommended that the driver disables FW\n+ * logging before shutting down the control queue. When disabling FW logging\n+ * (\"enable\" = false), the latest configurations of FW logging events stored in\n+ * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after\n+ * a device reset.\n+ *\n+ * When enabling FW logging to emit log messages via the Rx CQ during the\n+ * device's initialization phase, a mechanism alternative to interrupt handlers\n+ * needs to be used to extract FW log messages from the Rx CQ periodically and\n+ * to prevent the Rx CQ from being full and stalling other types of control\n+ * messages from FW to SW. Interrupts are typically disabled during the device's\n+ * initialization phase.\n+ */\n+static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)\n+{\n+\tstruct ice_aqc_fw_logging_data *data = NULL;\n+\tstruct ice_aqc_fw_logging *cmd;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu16 i, chgs = 0, len = 0;\n+\tstruct ice_aq_desc desc;\n+\tu8 actv_evnts = 0;\n+\tvoid *buf = NULL;\n+\n+\tif (!hw->fw_log.cq_en && !hw->fw_log.uart_en)\n+\t\treturn ICE_SUCCESS;\n+\n+\t/* Disable FW logging only when the control queue is still responsive */\n+\tif (!enable &&\n+\t    (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))\n+\t\treturn ICE_SUCCESS;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);\n+\tcmd = &desc.params.fw_logging;\n+\n+\t/* Indicate which controls are valid */\n+\tif (hw->fw_log.cq_en)\n+\t\tcmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;\n+\n+\tif (hw->fw_log.uart_en)\n+\t\tcmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;\n+\n+\tif (enable) {\n+\t\t/* Fill in an array of entries with FW logging modules and\n+\t\t * logging events being reconfigured.\n+\t\t */\n+\t\tfor (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {\n+\t\t\tu16 val;\n+\n+\t\t\t/* Keep track of enabled event types */\n+\t\t\tactv_evnts |= hw->fw_log.evnts[i].cfg;\n+\n+\t\t\tif (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (!data) {\n+\t\t\t\tdata = (struct ice_aqc_fw_logging_data *)\n+\t\t\t\t\tice_malloc(hw,\n+\t\t\t\t\t\t   ICE_FW_LOG_DESC_SIZE_MAX);\n+\t\t\t\tif (!data)\n+\t\t\t\t\treturn ICE_ERR_NO_MEMORY;\n+\t\t\t}\n+\n+\t\t\tval = i << ICE_AQC_FW_LOG_ID_S;\n+\t\t\tval |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;\n+\t\t\tdata->entry[chgs++] = CPU_TO_LE16(val);\n+\t\t}\n+\n+\t\t/* Only enable FW logging if at least one module is specified.\n+\t\t * If FW logging is currently enabled but all modules are not\n+\t\t * enabled to emit log messages, disable FW logging altogether.\n+\t\t */\n+\t\tif (actv_evnts) {\n+\t\t\t/* Leave if there is effectively no change */\n+\t\t\tif (!chgs)\n+\t\t\t\tgoto out;\n+\n+\t\t\tif (hw->fw_log.cq_en)\n+\t\t\t\tcmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;\n+\n+\t\t\tif (hw->fw_log.uart_en)\n+\t\t\t\tcmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;\n+\n+\t\t\tbuf = data;\n+\t\t\tlen = ICE_FW_LOG_DESC_SIZE(chgs);\n+\t\t\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\t\t}\n+\t}\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, len, NULL);\n+\tif (!status) {\n+\t\t/* Update the current configuration to reflect events enabled.\n+\t\t * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW\n+\t\t * logging mode is enabled for the device. They do not reflect\n+\t\t * actual modules being enabled to emit log messages. So, their\n+\t\t * values remain unchanged even when all modules are disabled.\n+\t\t */\n+\t\tu16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;\n+\n+\t\thw->fw_log.actv_evnts = actv_evnts;\n+\t\tfor (i = 0; i < cnt; i++) {\n+\t\t\tu16 v, m;\n+\n+\t\t\tif (!enable) {\n+\t\t\t\t/* When disabling all FW logging events as part\n+\t\t\t\t * of device's de-initialization, the original\n+\t\t\t\t * configurations are retained, and can be used\n+\t\t\t\t * to reconfigure FW logging later if the device\n+\t\t\t\t * is re-initialized.\n+\t\t\t\t */\n+\t\t\t\thw->fw_log.evnts[i].cur = 0;\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tv = LE16_TO_CPU(data->entry[i]);\n+\t\t\tm = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;\n+\t\t\thw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;\n+\t\t}\n+\t}\n+\n+out:\n+\tif (data)\n+\t\tice_free(hw, data);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_output_fw_log\n+ * @hw: pointer to the hw struct\n+ * @desc: pointer to the AQ message descriptor\n+ * @buf: pointer to the buffer accompanying the AQ message\n+ *\n+ * Formats a FW Log message and outputs it via the standard driver logs.\n+ */\n+void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)\n+{\n+\tice_debug(hw, ICE_DBG_AQ_MSG, \"[ FW Log Msg Start ]\\n\");\n+\tice_debug_array(hw, ICE_DBG_AQ_MSG, 16, 1, (u8 *)buf,\n+\t\t\tLE16_TO_CPU(desc->datalen));\n+\tice_debug(hw, ICE_DBG_AQ_MSG, \"[ FW Log Msg End ]\\n\");\n+}\n+\n+/**\n+ * ice_get_itr_intrl_gran - determine int/intrl granularity\n+ * @hw: pointer to the hw struct\n+ *\n+ * Determines the itr/intrl granularities based on the maximum aggregate\n+ * bandwidth according to the device's configuration during power-on.\n+ */\n+static enum ice_status ice_get_itr_intrl_gran(struct ice_hw *hw)\n+{\n+\tu8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &\n+\t\t\t GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>\n+\t\t\tGL_PWR_MODE_CTL_CAR_MAX_BW_S;\n+\n+\tswitch (max_agg_bw) {\n+\tcase ICE_MAX_AGG_BW_200G:\n+\tcase ICE_MAX_AGG_BW_100G:\n+\tcase ICE_MAX_AGG_BW_50G:\n+\t\thw->itr_gran = ICE_ITR_GRAN_ABOVE_25;\n+\t\thw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;\n+\t\tbreak;\n+\tcase ICE_MAX_AGG_BW_25G:\n+\t\thw->itr_gran = ICE_ITR_GRAN_MAX_25;\n+\t\thw->intrl_gran = ICE_INTRL_GRAN_MAX_25;\n+\t\tbreak;\n+\tdefault:\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Failed to determine itr/intrl granularity\\n\");\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_init_hw - main hardware initialization routine\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_init_hw(struct ice_hw *hw)\n+{\n+\tstruct ice_aqc_get_phy_caps_data *pcaps;\n+\tenum ice_status status;\n+\tu16 mac_buf_len;\n+\tvoid *mac_buf;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_init_hw\");\n+\n+\n+\t/* Set MAC type based on DeviceID */\n+\tstatus = ice_set_mac_type(hw);\n+\tif (status)\n+\t\treturn status;\n+\n+\thw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &\n+\t\t\t PF_FUNC_RID_FUNCTION_NUMBER_M) >>\n+\t\tPF_FUNC_RID_FUNCTION_NUMBER_S;\n+\n+\n+\tstatus = ice_reset(hw, ICE_RESET_PFR);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_get_itr_intrl_gran(hw);\n+\tif (status)\n+\t\treturn status;\n+\n+\n+\tstatus = ice_init_all_ctrlq(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\t/* Enable FW logging. Not fatal if this fails. */\n+\tstatus = ice_cfg_fw_log(hw, true);\n+\tif (status)\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to enable FW logging.\\n\");\n+\n+\tstatus = ice_clear_pf_cfg(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\n+\tice_clear_pxe_mode(hw);\n+\n+\tstatus = ice_init_nvm(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\tstatus = ice_get_caps(hw);\n+\tif (status)\n+\t\tgoto err_unroll_cqinit;\n+\n+\thw->port_info = (struct ice_port_info *)\n+\t\t\tice_malloc(hw, sizeof(*hw->port_info));\n+\tif (!hw->port_info) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto err_unroll_cqinit;\n+\t}\n+\n+\t/* set the back pointer to hw */\n+\thw->port_info->hw = hw;\n+\n+\t/* Initialize port_info struct with switch configuration data */\n+\tstatus = ice_get_initial_sw_cfg(hw);\n+\tif (status)\n+\t\tgoto err_unroll_alloc;\n+\n+\thw->evb_veb = true;\n+\n+\t/* Query the allocated resources for Tx scheduler */\n+\tstatus = ice_sched_query_res_alloc(hw);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t  \"Failed to get scheduler allocated resources\\n\");\n+\t\tgoto err_unroll_alloc;\n+\t}\n+\n+\n+\t/* Initialize port_info struct with scheduler data */\n+\tstatus = ice_sched_init_port(hw->port_info);\n+\tif (status)\n+\t\tgoto err_unroll_sched;\n+\n+\tpcaps = (struct ice_aqc_get_phy_caps_data *)\n+\t\tice_malloc(hw, sizeof(*pcaps));\n+\tif (!pcaps) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto err_unroll_sched;\n+\t}\n+\n+\t/* Initialize port_info struct with PHY capabilities */\n+\tstatus = ice_aq_get_phy_caps(hw->port_info, false,\n+\t\t\t\t     ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);\n+\tice_free(hw, pcaps);\n+\tif (status)\n+\t\tgoto err_unroll_sched;\n+\n+\t/* Initialize port_info struct with link information */\n+\tstatus = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);\n+\tif (status)\n+\t\tgoto err_unroll_sched;\n+\t/* need a valid SW entry point to build a Tx tree */\n+\tif (!hw->sw_entry_point_layer) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"invalid sw entry point\\n\");\n+\t\tstatus = ICE_ERR_CFG;\n+\t\tgoto err_unroll_sched;\n+\t}\n+\tINIT_LIST_HEAD(&hw->agg_list);\n+\n+\tstatus = ice_init_fltr_mgmt_struct(hw);\n+\tif (status)\n+\t\tgoto err_unroll_sched;\n+\n+#if defined(FPGA_SUPPORT) || defined(CVL_A0_SUPPORT)\n+\t/* some of the register write workarounds to get Rx working */\n+\tice_dev_onetime_setup(hw);\n+#endif /* FPGA_SUPPORT || CVL_A0_SUPPORT */\n+\n+\t/* Get MAC information */\n+\t/* A single port can report up to two (LAN and WoL) addresses */\n+\tmac_buf = ice_calloc(hw, 2,\n+\t\t\t     sizeof(struct ice_aqc_manage_mac_read_resp));\n+\tmac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);\n+\n+\tif (!mac_buf) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto err_unroll_fltr_mgmt_struct;\n+\t}\n+\n+\tstatus = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);\n+\tice_free(hw, mac_buf);\n+\n+\tif (status)\n+\t\tgoto err_unroll_fltr_mgmt_struct;\n+\n+\tice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);\n+\tice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);\n+\n+\n+\treturn ICE_SUCCESS;\n+\n+err_unroll_fltr_mgmt_struct:\n+\tice_cleanup_fltr_mgmt_struct(hw);\n+err_unroll_sched:\n+\tice_sched_cleanup_all(hw);\n+err_unroll_alloc:\n+\tice_free(hw, hw->port_info);\n+\thw->port_info = NULL;\n+err_unroll_cqinit:\n+\tice_shutdown_all_ctrlq(hw);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_deinit_hw - unroll initialization operations done by ice_init_hw\n+ * @hw: pointer to the hardware structure\n+ *\n+ * This should be called only during nominal operation, not as a result of\n+ * ice_init_hw() failing since ice_init_hw() will take care of unrolling\n+ * applicable initializations if it fails for any reason.\n+ */\n+void ice_deinit_hw(struct ice_hw *hw)\n+{\n+\tice_cleanup_fltr_mgmt_struct(hw);\n+\n+\tice_sched_cleanup_all(hw);\n+\tice_sched_clear_agg(hw);\n+\n+\tif (hw->port_info) {\n+\t\tice_free(hw, hw->port_info);\n+\t\thw->port_info = NULL;\n+\t}\n+\n+\t/* Attempt to disable FW logging before shutting down control queues */\n+\tice_cfg_fw_log(hw, false);\n+\tice_shutdown_all_ctrlq(hw);\n+\n+\t/* Clear VSI contexts if not already cleared */\n+\tice_clear_all_vsi_ctx(hw);\n+}\n+\n+/**\n+ * ice_check_reset - Check to see if a global reset is complete\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_check_reset(struct ice_hw *hw)\n+{\n+\tu32 cnt, reg = 0, grst_delay;\n+\n+\t/* Poll for Device Active state in case a recent CORER, GLOBR,\n+\t * or EMPR has occurred. The grst delay value is in 100ms units.\n+\t * Add 1sec for outstanding AQ commands that can take a long time.\n+\t */\n+#define GLGEN_RSTCTL\t\t0x000B8180 /* Reset Source: POR */\n+#define GLGEN_RSTCTL_GRSTDEL_S\t0\n+#define GLGEN_RSTCTL_GRSTDEL_M\tMAKEMASK(0x3F, GLGEN_RSTCTL_GRSTDEL_S)\n+\tgrst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>\n+\t\t      GLGEN_RSTCTL_GRSTDEL_S) + 10;\n+\n+\tfor (cnt = 0; cnt < grst_delay; cnt++) {\n+\t\tice_msec_delay(100, true);\n+\t\treg = rd32(hw, GLGEN_RSTAT);\n+\t\tif (!(reg & GLGEN_RSTAT_DEVSTATE_M))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (cnt == grst_delay) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Global reset polling failed to complete.\\n\");\n+\t\treturn ICE_ERR_RESET_FAILED;\n+\t}\n+\n+#define ICE_RESET_DONE_MASK\t(GLNVM_ULD_CORER_DONE_M | \\\n+\t\t\t\t GLNVM_ULD_GLOBR_DONE_M)\n+\n+\t/* Device is Active; check Global Reset processes are done */\n+\tfor (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {\n+\t\treg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;\n+\t\tif (reg == ICE_RESET_DONE_MASK) {\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"Global reset processes done. %d\\n\", cnt);\n+\t\t\tbreak;\n+\t\t}\n+\t\tice_msec_delay(10, true);\n+\t}\n+\n+\tif (cnt == ICE_PF_RESET_WAIT_COUNT) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Wait for Reset Done timed out. GLNVM_ULD = 0x%x\\n\",\n+\t\t\t  reg);\n+\t\treturn ICE_ERR_RESET_FAILED;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_pf_reset - Reset the PF\n+ * @hw: pointer to the hardware structure\n+ *\n+ * If a global reset has been triggered, this function checks\n+ * for its completion and then issues the PF reset\n+ */\n+static enum ice_status ice_pf_reset(struct ice_hw *hw)\n+{\n+\tu32 cnt, reg;\n+\n+\t/* If at function entry a global reset was already in progress, i.e.\n+\t * state is not 'device active' or any of the reset done bits are not\n+\t * set in GLNVM_ULD, there is no need for a PF Reset; poll until the\n+\t * global reset is done.\n+\t */\n+\tif ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||\n+\t    (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {\n+\t\t/* poll on global reset currently in progress until done */\n+\t\tif (ice_check_reset(hw))\n+\t\t\treturn ICE_ERR_RESET_FAILED;\n+\n+\t\treturn ICE_SUCCESS;\n+\t}\n+\n+\t/* Reset the PF */\n+\treg = rd32(hw, PFGEN_CTRL);\n+\n+\twr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));\n+\n+\tfor (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {\n+\t\treg = rd32(hw, PFGEN_CTRL);\n+\t\tif (!(reg & PFGEN_CTRL_PFSWR_M))\n+\t\t\tbreak;\n+\n+\t\tice_msec_delay(1, true);\n+\t}\n+\n+\tif (cnt == ICE_PF_RESET_WAIT_COUNT) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"PF reset polling failed to complete.\\n\");\n+\t\treturn ICE_ERR_RESET_FAILED;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_reset - Perform different types of reset\n+ * @hw: pointer to the hardware structure\n+ * @req: reset request\n+ *\n+ * This function triggers a reset as specified by the req parameter.\n+ *\n+ * Note:\n+ * If anything other than a PF reset is triggered, PXE mode is restored.\n+ * This has to be cleared using ice_clear_pxe_mode again, once the AQ\n+ * interface has been restored in the rebuild flow.\n+ */\n+enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)\n+{\n+\tu32 val = 0;\n+\n+\tswitch (req) {\n+\tcase ICE_RESET_PFR:\n+\t\treturn ice_pf_reset(hw);\n+\tcase ICE_RESET_CORER:\n+\t\tice_debug(hw, ICE_DBG_INIT, \"CoreR requested\\n\");\n+\t\tval = GLGEN_RTRIG_CORER_M;\n+\t\tbreak;\n+\tcase ICE_RESET_GLOBR:\n+\t\tice_debug(hw, ICE_DBG_INIT, \"GlobalR requested\\n\");\n+\t\tval = GLGEN_RTRIG_GLOBR_M;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tval |= rd32(hw, GLGEN_RTRIG);\n+\twr32(hw, GLGEN_RTRIG, val);\n+\tice_flush(hw);\n+\n+\n+\t/* wait for the FW to be ready */\n+\treturn ice_check_reset(hw);\n+}\n+\n+\n+\n+/**\n+ * ice_copy_rxq_ctx_to_hw\n+ * @hw: pointer to the hardware structure\n+ * @ice_rxq_ctx: pointer to the rxq context\n+ * @rxq_index: the index of the Rx queue\n+ *\n+ * Copies rxq context from dense structure to hw register space\n+ */\n+static enum ice_status\n+ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)\n+{\n+\tu8 i;\n+\n+\tif (!ice_rxq_ctx)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tif (rxq_index > QRX_CTRL_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Copy each dword separately to hw */\n+\tfor (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {\n+\t\twr32(hw, QRX_CONTEXT(i, rxq_index),\n+\t\t     *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));\n+\n+\t\tice_debug(hw, ICE_DBG_QCTX, \"qrxdata[%d]: %08X\\n\", i,\n+\t\t\t  *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/* LAN Rx Queue Context */\n+static const struct ice_ctx_ele ice_rlan_ctx_info[] = {\n+\t/* Field\t\tWidth\tLSB */\n+\tICE_CTX_STORE(ice_rlan_ctx, head,\t\t13,\t0),\n+\tICE_CTX_STORE(ice_rlan_ctx, cpuid,\t\t8,\t13),\n+\tICE_CTX_STORE(ice_rlan_ctx, base,\t\t57,\t32),\n+\tICE_CTX_STORE(ice_rlan_ctx, qlen,\t\t13,\t89),\n+\tICE_CTX_STORE(ice_rlan_ctx, dbuf,\t\t7,\t102),\n+\tICE_CTX_STORE(ice_rlan_ctx, hbuf,\t\t5,\t109),\n+\tICE_CTX_STORE(ice_rlan_ctx, dtype,\t\t2,\t114),\n+\tICE_CTX_STORE(ice_rlan_ctx, dsize,\t\t1,\t116),\n+\tICE_CTX_STORE(ice_rlan_ctx, crcstrip,\t\t1,\t117),\n+\tICE_CTX_STORE(ice_rlan_ctx, l2tsel,\t\t1,\t119),\n+\tICE_CTX_STORE(ice_rlan_ctx, hsplit_0,\t\t4,\t120),\n+\tICE_CTX_STORE(ice_rlan_ctx, hsplit_1,\t\t2,\t124),\n+\tICE_CTX_STORE(ice_rlan_ctx, showiv,\t\t1,\t127),\n+\tICE_CTX_STORE(ice_rlan_ctx, rxmax,\t\t14,\t174),\n+\tICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena,\t1,\t193),\n+\tICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena,\t1,\t194),\n+\tICE_CTX_STORE(ice_rlan_ctx, tphdata_ena,\t1,\t195),\n+\tICE_CTX_STORE(ice_rlan_ctx, tphhead_ena,\t1,\t196),\n+\tICE_CTX_STORE(ice_rlan_ctx, lrxqthresh,\t\t3,\t198),\n+\t{ 0 }\n+};\n+\n+/**\n+ * ice_write_rxq_ctx\n+ * @hw: pointer to the hardware structure\n+ * @rlan_ctx: pointer to the rxq context\n+ * @rxq_index: the index of the Rx queue\n+ *\n+ * Converts rxq context from sparse to dense structure and then writes\n+ * it to hw register space\n+ */\n+enum ice_status\n+ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n+\t\t  u32 rxq_index)\n+{\n+\tu8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };\n+\n+\tice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);\n+\treturn ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);\n+}\n+\n+#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)\n+/**\n+ * ice_clear_rxq_ctx\n+ * @hw: pointer to the hardware structure\n+ * @rxq_index: the index of the Rx queue to clear\n+ *\n+ * Clears rxq context in hw register space\n+ */\n+enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index)\n+{\n+\tu8 i;\n+\n+\tif (rxq_index > QRX_CTRL_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Clear each dword register separately */\n+\tfor (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++)\n+\t\twr32(hw, QRX_CONTEXT(i, rxq_index), 0);\n+\n+\treturn ICE_SUCCESS;\n+}\n+#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */\n+\n+/* LAN Tx Queue Context */\n+const struct ice_ctx_ele ice_tlan_ctx_info[] = {\n+\t\t\t\t    /* Field\t\t\tWidth\tLSB */\n+\tICE_CTX_STORE(ice_tlan_ctx, base,\t\t\t57,\t0),\n+\tICE_CTX_STORE(ice_tlan_ctx, port_num,\t\t\t3,\t57),\n+\tICE_CTX_STORE(ice_tlan_ctx, cgd_num,\t\t\t5,\t60),\n+\tICE_CTX_STORE(ice_tlan_ctx, pf_num,\t\t\t3,\t65),\n+\tICE_CTX_STORE(ice_tlan_ctx, vmvf_num,\t\t\t10,\t68),\n+\tICE_CTX_STORE(ice_tlan_ctx, vmvf_type,\t\t\t2,\t78),\n+\tICE_CTX_STORE(ice_tlan_ctx, src_vsi,\t\t\t10,\t80),\n+\tICE_CTX_STORE(ice_tlan_ctx, tsyn_ena,\t\t\t1,\t90),\n+\tICE_CTX_STORE(ice_tlan_ctx, alt_vlan,\t\t\t1,\t92),\n+\tICE_CTX_STORE(ice_tlan_ctx, cpuid,\t\t\t8,\t93),\n+\tICE_CTX_STORE(ice_tlan_ctx, wb_mode,\t\t\t1,\t101),\n+\tICE_CTX_STORE(ice_tlan_ctx, tphrd_desc,\t\t\t1,\t102),\n+\tICE_CTX_STORE(ice_tlan_ctx, tphrd,\t\t\t1,\t103),\n+\tICE_CTX_STORE(ice_tlan_ctx, tphwr_desc,\t\t\t1,\t104),\n+\tICE_CTX_STORE(ice_tlan_ctx, cmpq_id,\t\t\t9,\t105),\n+\tICE_CTX_STORE(ice_tlan_ctx, qnum_in_func,\t\t14,\t114),\n+\tICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode,\t1,\t128),\n+\tICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id,\t\t6,\t129),\n+\tICE_CTX_STORE(ice_tlan_ctx, qlen,\t\t\t13,\t135),\n+\tICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx,\t\t4,\t148),\n+\tICE_CTX_STORE(ice_tlan_ctx, tso_ena,\t\t\t1,\t152),\n+\tICE_CTX_STORE(ice_tlan_ctx, tso_qnum,\t\t\t11,\t153),\n+\tICE_CTX_STORE(ice_tlan_ctx, legacy_int,\t\t\t1,\t164),\n+\tICE_CTX_STORE(ice_tlan_ctx, drop_ena,\t\t\t1,\t165),\n+\tICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx,\t\t2,\t166),\n+\tICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx,\t3,\t168),\n+\tICE_CTX_STORE(ice_tlan_ctx, int_q_state,\t\t110,\t171),\n+\t{ 0 }\n+};\n+\n+#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)\n+/**\n+ * ice_copy_tx_cmpltnq_ctx_to_hw\n+ * @hw: pointer to the hardware structure\n+ * @ice_tx_cmpltnq_ctx: pointer to the Tx completion queue context\n+ * @tx_cmpltnq_index: the index of the completion queue\n+ *\n+ * Copies Tx completion q context from dense structure to hw register space\n+ */\n+static enum ice_status\n+ice_copy_tx_cmpltnq_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_cmpltnq_ctx,\n+\t\t\t      u32 tx_cmpltnq_index)\n+{\n+\tu8 i;\n+\n+\tif (!ice_tx_cmpltnq_ctx)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tif (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Copy each dword separately to hw */\n+\tfor (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++) {\n+\t\twr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index),\n+\t\t     *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));\n+\n+\t\tice_debug(hw, ICE_DBG_QCTX, \"cmpltnqdata[%d]: %08X\\n\", i,\n+\t\t\t  *((u32 *)(ice_tx_cmpltnq_ctx + (i * sizeof(u32)))));\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/* LAN Tx Completion Queue Context */\n+static const struct ice_ctx_ele ice_tx_cmpltnq_ctx_info[] = {\n+\t\t\t\t       /* Field\t\t\tWidth   LSB */\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, base,\t\t\t57,\t0),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, q_len,\t\t18,\t64),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, generation,\t\t1,\t96),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, wrt_ptr,\t\t22,\t97),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, pf_num,\t\t3,\t128),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_num,\t\t10,\t131),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, vmvf_type,\t\t2,\t141),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, tph_desc_wr,\t\t1,\t160),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, cpuid,\t\t8,\t161),\n+\tICE_CTX_STORE(ice_tx_cmpltnq_ctx, cmpltn_cache,\t\t512,\t192),\n+\t{ 0 }\n+};\n+\n+/**\n+ * ice_write_tx_cmpltnq_ctx\n+ * @hw: pointer to the hardware structure\n+ * @tx_cmpltnq_ctx: pointer to the completion queue context\n+ * @tx_cmpltnq_index: the index of the completion queue\n+ *\n+ * Converts completion queue context from sparse to dense structure and then\n+ * writes it to hw register space\n+ */\n+enum ice_status\n+ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,\n+\t\t\t struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,\n+\t\t\t u32 tx_cmpltnq_index)\n+{\n+\tu8 ctx_buf[ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };\n+\n+\tice_set_ctx((u8 *)tx_cmpltnq_ctx, ctx_buf, ice_tx_cmpltnq_ctx_info);\n+\treturn ice_copy_tx_cmpltnq_ctx_to_hw(hw, ctx_buf, tx_cmpltnq_index);\n+}\n+\n+/**\n+ * ice_clear_tx_cmpltnq_ctx\n+ * @hw: pointer to the hardware structure\n+ * @tx_cmpltnq_index: the index of the completion queue to clear\n+ *\n+ * Clears Tx completion queue context in hw register space\n+ */\n+enum ice_status\n+ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index)\n+{\n+\tu8 i;\n+\n+\tif (tx_cmpltnq_index > GLTCLAN_CQ_CNTX0_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Clear each dword register separately */\n+\tfor (i = 0; i < ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS; i++)\n+\t\twr32(hw, GLTCLAN_CQ_CNTX(i, tx_cmpltnq_index), 0);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_copy_tx_drbell_q_ctx_to_hw\n+ * @hw: pointer to the hardware structure\n+ * @ice_tx_drbell_q_ctx: pointer to the doorbell queue context\n+ * @tx_drbell_q_index: the index of the doorbell queue\n+ *\n+ * Copies doorbell q context from dense structure to hw register space\n+ */\n+static enum ice_status\n+ice_copy_tx_drbell_q_ctx_to_hw(struct ice_hw *hw, u8 *ice_tx_drbell_q_ctx,\n+\t\t\t       u32 tx_drbell_q_index)\n+{\n+\tu8 i;\n+\n+\tif (!ice_tx_drbell_q_ctx)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tif (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Copy each dword separately to hw */\n+\tfor (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++) {\n+\t\twr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index),\n+\t\t     *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));\n+\n+\t\tice_debug(hw, ICE_DBG_QCTX, \"tx_drbell_qdata[%d]: %08X\\n\", i,\n+\t\t\t  *((u32 *)(ice_tx_drbell_q_ctx + (i * sizeof(u32)))));\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/* LAN Tx Doorbell Queue Context info */\n+static const struct ice_ctx_ele ice_tx_drbell_q_ctx_info[] = {\n+\t\t\t\t\t/* Field\t\tWidth   LSB */\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, base,\t\t57,\t0),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, ring_len,\t\t13,\t64),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, pf_num,\t\t3,\t80),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, vf_num,\t\t8,\t84),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, vmvf_type,\t\t2,\t94),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, cpuid,\t\t8,\t96),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_rd,\t\t1,\t104),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, tph_desc_wr,\t\t1,\t108),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, db_q_en,\t\t1,\t112),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_head,\t\t13,\t128),\n+\tICE_CTX_STORE(ice_tx_drbell_q_ctx, rd_tail,\t\t13,\t144),\n+\t{ 0 }\n+};\n+\n+/**\n+ * ice_write_tx_drbell_q_ctx\n+ * @hw: pointer to the hardware structure\n+ * @tx_drbell_q_ctx: pointer to the doorbell queue context\n+ * @tx_drbell_q_index: the index of the doorbell queue\n+ *\n+ * Converts doorbell queue context from sparse to dense structure and then\n+ * writes it to hw register space\n+ */\n+enum ice_status\n+ice_write_tx_drbell_q_ctx(struct ice_hw *hw,\n+\t\t\t  struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,\n+\t\t\t  u32 tx_drbell_q_index)\n+{\n+\tu8 ctx_buf[ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS * sizeof(u32)] = { 0 };\n+\n+\tice_set_ctx((u8 *)tx_drbell_q_ctx, ctx_buf, ice_tx_drbell_q_ctx_info);\n+\treturn ice_copy_tx_drbell_q_ctx_to_hw(hw, ctx_buf, tx_drbell_q_index);\n+}\n+\n+/**\n+ * ice_clear_tx_drbell_q_ctx\n+ * @hw: pointer to the hardware structure\n+ * @tx_drbell_q_index: the index of the doorbell queue to clear\n+ *\n+ * Clears doorbell queue context in hw register space\n+ */\n+enum ice_status\n+ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index)\n+{\n+\tu8 i;\n+\n+\tif (tx_drbell_q_index > QTX_COMM_DBLQ_DBELL_MAX_INDEX)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Clear each dword register separately */\n+\tfor (i = 0; i < ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS; i++)\n+\t\twr32(hw, QTX_COMM_DBLQ_CNTX(i, tx_drbell_q_index), 0);\n+\n+\treturn ICE_SUCCESS;\n+}\n+#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */\n+\n+/**\n+ * ice_debug_cq\n+ * @hw: pointer to the hardware structure\n+ * @mask: debug mask\n+ * @desc: pointer to control queue descriptor\n+ * @buf: pointer to command buffer\n+ * @buf_len: max length of buf\n+ *\n+ * Dumps debug log about control command with descriptor contents.\n+ */\n+void\n+ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, void *buf,\n+\t     u16 buf_len)\n+{\n+\tstruct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;\n+\tu16 len;\n+\n+\n+\tif (!desc)\n+\t\treturn;\n+\n+\tlen = LE16_TO_CPU(cq_desc->datalen);\n+\n+\tice_debug(hw, mask,\n+\t\t  \"CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\\n\",\n+\t\t  LE16_TO_CPU(cq_desc->opcode),\n+\t\t  LE16_TO_CPU(cq_desc->flags),\n+\t\t  LE16_TO_CPU(cq_desc->datalen), LE16_TO_CPU(cq_desc->retval));\n+\tice_debug(hw, mask, \"\\tcookie (h,l) 0x%08X 0x%08X\\n\",\n+\t\t  LE32_TO_CPU(cq_desc->cookie_high),\n+\t\t  LE32_TO_CPU(cq_desc->cookie_low));\n+\tice_debug(hw, mask, \"\\tparam (0,1)  0x%08X 0x%08X\\n\",\n+\t\t  LE32_TO_CPU(cq_desc->params.generic.param0),\n+\t\t  LE32_TO_CPU(cq_desc->params.generic.param1));\n+\tice_debug(hw, mask, \"\\taddr (h,l)   0x%08X 0x%08X\\n\",\n+\t\t  LE32_TO_CPU(cq_desc->params.generic.addr_high),\n+\t\t  LE32_TO_CPU(cq_desc->params.generic.addr_low));\n+\tif (buf && cq_desc->datalen != 0) {\n+\t\tice_debug(hw, mask, \"Buffer:\\n\");\n+\t\tif (buf_len < len)\n+\t\t\tlen = buf_len;\n+\n+\t\tice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);\n+\t}\n+}\n+\n+\n+/* FW Admin Queue command wrappers */\n+\n+/**\n+ * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue\n+ * @hw: pointer to the hw struct\n+ * @desc: descriptor describing the command\n+ * @buf: buffer to use for indirect commands (NULL for direct commands)\n+ * @buf_size: size of buffer for indirect commands (0 for direct commands)\n+ * @cd: pointer to command details structure\n+ *\n+ * Helper function to send FW Admin Queue commands to the FW Admin Queue.\n+ */\n+enum ice_status\n+ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,\n+\t\tu16 buf_size, struct ice_sq_cd *cd)\n+{\n+\treturn ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);\n+}\n+\n+/**\n+ * ice_aq_get_fw_ver\n+ * @hw: pointer to the hw struct\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get the firmware version (0x0001) from the admin queue commands\n+ */\n+enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_get_ver *resp;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tresp = &desc.params.get_ver;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+\n+\tif (!status) {\n+\t\thw->fw_branch = resp->fw_branch;\n+\t\thw->fw_maj_ver = resp->fw_major;\n+\t\thw->fw_min_ver = resp->fw_minor;\n+\t\thw->fw_patch = resp->fw_patch;\n+\t\thw->fw_build = LE32_TO_CPU(resp->fw_build);\n+\t\thw->api_branch = resp->api_branch;\n+\t\thw->api_maj_ver = resp->api_major;\n+\t\thw->api_min_ver = resp->api_minor;\n+\t\thw->api_patch = resp->api_patch;\n+\t}\n+\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_aq_q_shutdown\n+ * @hw: pointer to the hw struct\n+ * @unloading: is the driver unloading itself\n+ *\n+ * Tell the Firmware that we're shutting down the AdminQ and whether\n+ * or not the driver is unloading as well (0x0003).\n+ */\n+enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)\n+{\n+\tstruct ice_aqc_q_shutdown *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.q_shutdown;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);\n+\n+\tif (unloading)\n+\t\tcmd->driver_unloading = CPU_TO_LE32(ICE_AQC_DRIVER_UNLOADING);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+}\n+\n+/**\n+ * ice_aq_req_res\n+ * @hw: pointer to the hw struct\n+ * @res: resource id\n+ * @access: access type\n+ * @sdp_number: resource number\n+ * @timeout: the maximum time in ms that the driver may hold the resource\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Requests common resource using the admin queue commands (0x0008).\n+ * When attempting to acquire the Global Config Lock, the driver can\n+ * learn of three states:\n+ *  1) ICE_SUCCESS -        acquired lock, and can perform download package\n+ *  2) ICE_ERR_AQ_ERROR -   did not get lock, driver should fail to load\n+ *  3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has\n+ *                          successfully downloaded the package; the driver does\n+ *                          not have to download the package and can continue\n+ *                          loading\n+ *\n+ * Note that if the caller is in an acquire lock, perform action, release lock\n+ * phase of operation, it is possible that the FW may detect a timeout and issue\n+ * a CORER. In this case, the driver will receive a CORER interrupt and will\n+ * have to determine its cause. The calling thread that is handling this flow\n+ * will likely get an error propagated back to it indicating the Download\n+ * Package, Update Package or the Release Resource AQ commands timed out.\n+ */\n+static enum ice_status\n+ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,\n+\t       enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,\n+\t       struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_req_res *cmd_resp;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_req_res\");\n+\n+\tcmd_resp = &desc.params.res_owner;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);\n+\n+\tcmd_resp->res_id = CPU_TO_LE16(res);\n+\tcmd_resp->access_type = CPU_TO_LE16(access);\n+\tcmd_resp->res_number = CPU_TO_LE32(sdp_number);\n+\tcmd_resp->timeout = CPU_TO_LE32(*timeout);\n+\t*timeout = 0;\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+\n+\t/* The completion specifies the maximum time in ms that the driver\n+\t * may hold the resource in the Timeout field.\n+\t */\n+\n+\t/* Global config lock response utilizes an additional status field.\n+\t *\n+\t * If the Global config lock resource is held by some other driver, the\n+\t * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field\n+\t * and the timeout field indicates the maximum time the current owner\n+\t * of the resource has to free it.\n+\t */\n+\tif (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {\n+\t\tif (LE16_TO_CPU(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {\n+\t\t\t*timeout = LE32_TO_CPU(cmd_resp->timeout);\n+\t\t\treturn ICE_SUCCESS;\n+\t\t} else if (LE16_TO_CPU(cmd_resp->status) ==\n+\t\t\t   ICE_AQ_RES_GLBL_IN_PROG) {\n+\t\t\t*timeout = LE32_TO_CPU(cmd_resp->timeout);\n+\t\t\treturn ICE_ERR_AQ_ERROR;\n+\t\t} else if (LE16_TO_CPU(cmd_resp->status) ==\n+\t\t\t   ICE_AQ_RES_GLBL_DONE) {\n+\t\t\treturn ICE_ERR_AQ_NO_WORK;\n+\t\t}\n+\n+\t\t/* invalid FW response, force a timeout immediately */\n+\t\t*timeout = 0;\n+\t\treturn ICE_ERR_AQ_ERROR;\n+\t}\n+\n+\t/* If the resource is held by some other driver, the command completes\n+\t * with a busy return value and the timeout field indicates the maximum\n+\t * time the current owner of the resource has to free it.\n+\t */\n+\tif (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)\n+\t\t*timeout = LE32_TO_CPU(cmd_resp->timeout);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_release_res\n+ * @hw: pointer to the hw struct\n+ * @res: resource id\n+ * @sdp_number: resource number\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * release common resource using the admin queue commands (0x0009)\n+ */\n+static enum ice_status\n+ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,\n+\t\t   struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_req_res *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_release_res\");\n+\n+\tcmd = &desc.params.res_owner;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);\n+\n+\tcmd->res_id = CPU_TO_LE16(res);\n+\tcmd->res_number = CPU_TO_LE32(sdp_number);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * ice_acquire_res\n+ * @hw: pointer to the HW structure\n+ * @res: resource id\n+ * @access: access type (read or write)\n+ * @timeout: timeout in milliseconds\n+ *\n+ * This function will attempt to acquire the ownership of a resource.\n+ */\n+enum ice_status\n+ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,\n+\t\tenum ice_aq_res_access_type access, u32 timeout)\n+{\n+#define ICE_RES_POLLING_DELAY_MS\t10\n+\tu32 delay = ICE_RES_POLLING_DELAY_MS;\n+\tu32 time_left = timeout;\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_acquire_res\");\n+\n+\tstatus = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);\n+\n+\t/* A return code of ICE_ERR_AQ_NO_WORK means that another driver has\n+\t * previously acquired the resource and performed any necessary updates;\n+\t * in this case the caller does not obtain the resource and has no\n+\t * further work to do.\n+\t */\n+\tif (status == ICE_ERR_AQ_NO_WORK)\n+\t\tgoto ice_acquire_res_exit;\n+\n+\tif (status)\n+\t\tice_debug(hw, ICE_DBG_RES,\n+\t\t\t  \"resource %d acquire type %d failed.\\n\", res, access);\n+\n+\t/* If necessary, poll until the current lock owner timeouts */\n+\ttimeout = time_left;\n+\twhile (status && timeout && time_left) {\n+\t\tice_msec_delay(delay, true);\n+\t\ttimeout = (timeout > delay) ? timeout - delay : 0;\n+\t\tstatus = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);\n+\n+\t\tif (status == ICE_ERR_AQ_NO_WORK)\n+\t\t\t/* lock free, but no work to do */\n+\t\t\tbreak;\n+\n+\t\tif (!status)\n+\t\t\t/* lock acquired */\n+\t\t\tbreak;\n+\t}\n+\tif (status && status != ICE_ERR_AQ_NO_WORK)\n+\t\tice_debug(hw, ICE_DBG_RES, \"resource acquire timed out.\\n\");\n+\n+ice_acquire_res_exit:\n+\tif (status == ICE_ERR_AQ_NO_WORK) {\n+\t\tif (access == ICE_RES_WRITE)\n+\t\t\tice_debug(hw, ICE_DBG_RES,\n+\t\t\t\t  \"resource indicates no work to do.\\n\");\n+\t\telse\n+\t\t\tice_debug(hw, ICE_DBG_RES,\n+\t\t\t\t  \"Warning: ICE_ERR_AQ_NO_WORK not expected\\n\");\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_release_res\n+ * @hw: pointer to the HW structure\n+ * @res: resource id\n+ *\n+ * This function will release a resource using the proper Admin Command.\n+ */\n+void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)\n+{\n+\tenum ice_status status;\n+\tu32 total_delay = 0;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_release_res\");\n+\n+\tstatus = ice_aq_release_res(hw, res, 0, NULL);\n+\n+\t/* there are some rare cases when trying to release the resource\n+\t * results in an admin Q timeout, so handle them correctly\n+\t */\n+\twhile ((status == ICE_ERR_AQ_TIMEOUT) &&\n+\t       (total_delay < hw->adminq.sq_cmd_timeout)) {\n+\t\tice_msec_delay(1, true);\n+\t\tstatus = ice_aq_release_res(hw, res, 0, NULL);\n+\t\ttotal_delay++;\n+\t}\n+}\n+\n+/**\n+ * ice_aq_alloc_free_res - command to allocate/free resources\n+ * @hw: pointer to the hw struct\n+ * @num_entries: number of resource entries in buffer\n+ * @buf: Indirect buffer to hold data parameters and response\n+ * @buf_size: size of buffer for indirect commands\n+ * @opc: pass in the command opcode\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Helper function to allocate/free resources using the admin queue commands\n+ */\n+enum ice_status\n+ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,\n+\t\t      struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,\n+\t\t      enum ice_adminq_opc opc, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_alloc_free_res_cmd *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_alloc_free_res\");\n+\n+\tcmd = &desc.params.sw_res_ctrl;\n+\n+\tif (!buf)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (buf_size < (num_entries * sizeof(buf->elem[0])))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, opc);\n+\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tcmd->num_entries = CPU_TO_LE16(num_entries);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+}\n+\n+\n+/**\n+ * ice_get_guar_num_vsi - determine number of guar VSI for a PF\n+ * @hw: pointer to the hw structure\n+ *\n+ * Determine the number of valid functions by going through the bitmap returned\n+ * from parsing capabilities and use this to calculate the number of VSI per PF.\n+ */\n+static u32 ice_get_guar_num_vsi(struct ice_hw *hw)\n+{\n+\tu8 funcs;\n+\n+#define ICE_CAPS_VALID_FUNCS_M\t0xFF\n+\tfuncs = ice_hweight8(hw->dev_caps.common_cap.valid_functions &\n+\t\t\t     ICE_CAPS_VALID_FUNCS_M);\n+\n+\tif (!funcs)\n+\t\treturn 0;\n+\n+\treturn ICE_MAX_VSI / funcs;\n+}\n+\n+/**\n+ * ice_parse_caps - parse function/device capabilities\n+ * @hw: pointer to the hw struct\n+ * @buf: pointer to a buffer containing function/device capability records\n+ * @cap_count: number of capability records in the list\n+ * @opc: type of capabilities list to parse\n+ *\n+ * Helper function to parse function(0x000a)/device(0x000b) capabilities list.\n+ */\n+static void\n+ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n+\t       enum ice_adminq_opc opc)\n+{\n+\tstruct ice_aqc_list_caps_elem *cap_resp;\n+\tstruct ice_hw_func_caps *func_p = NULL;\n+\tstruct ice_hw_dev_caps *dev_p = NULL;\n+\tstruct ice_hw_common_caps *caps;\n+\tu32 i;\n+\n+\tif (!buf)\n+\t\treturn;\n+\n+\tcap_resp = (struct ice_aqc_list_caps_elem *)buf;\n+\n+\tif (opc == ice_aqc_opc_list_dev_caps) {\n+\t\tdev_p = &hw->dev_caps;\n+\t\tcaps = &dev_p->common_cap;\n+\t} else if (opc == ice_aqc_opc_list_func_caps) {\n+\t\tfunc_p = &hw->func_caps;\n+\t\tcaps = &func_p->common_cap;\n+\t} else {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"wrong opcode\\n\");\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; caps && i < cap_count; i++, cap_resp++) {\n+\t\tu32 logical_id = LE32_TO_CPU(cap_resp->logical_id);\n+\t\tu32 phys_id = LE32_TO_CPU(cap_resp->phys_id);\n+\t\tu32 number = LE32_TO_CPU(cap_resp->number);\n+\t\tu16 cap = LE16_TO_CPU(cap_resp->cap);\n+\n+\t\tswitch (cap) {\n+\t\tcase ICE_AQC_CAPS_VALID_FUNCTIONS:\n+\t\t\tcaps->valid_functions = number;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Valid Functions = %d\\n\",\n+\t\t\t\t  caps->valid_functions);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_SRIOV:\n+\t\t\tcaps->sr_iov_1_1 = (number == 1);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: SR-IOV = %d\\n\", caps->sr_iov_1_1);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_VF:\n+\t\t\tif (dev_p) {\n+\t\t\t\tdev_p->num_vfs_exposed = number;\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: VFs exposed = %d\\n\",\n+\t\t\t\t\t  dev_p->num_vfs_exposed);\n+\t\t\t} else if (func_p) {\n+\t\t\t\tfunc_p->num_allocd_vfs = number;\n+\t\t\t\tfunc_p->vf_base_id = logical_id;\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: VFs allocated = %d\\n\",\n+\t\t\t\t\t  func_p->num_allocd_vfs);\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: VF base_id = %d\\n\",\n+\t\t\t\t\t  func_p->vf_base_id);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_VSI:\n+\t\t\tif (dev_p) {\n+\t\t\t\tdev_p->num_vsi_allocd_to_host = number;\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: Dev.VSI cnt = %d\\n\",\n+\t\t\t\t\t  dev_p->num_vsi_allocd_to_host);\n+\t\t\t} else if (func_p) {\n+\t\t\t\tfunc_p->guar_num_vsi =\n+\t\t\t\t\tice_get_guar_num_vsi(hw);\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: Func.VSI cnt = %d\\n\",\n+\t\t\t\t\t  number);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_RSS:\n+\t\t\tcaps->rss_table_size = number;\n+\t\t\tcaps->rss_table_entry_width = logical_id;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: RSS table size = %d\\n\",\n+\t\t\t\t  caps->rss_table_size);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: RSS table width = %d\\n\",\n+\t\t\t\t  caps->rss_table_entry_width);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_RXQS:\n+\t\t\tcaps->num_rxq = number;\n+\t\t\tcaps->rxq_first_id = phys_id;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Num Rx Qs = %d\\n\", caps->num_rxq);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Rx first queue ID = %d\\n\",\n+\t\t\t\t  caps->rxq_first_id);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_TXQS:\n+\t\t\tcaps->num_txq = number;\n+\t\t\tcaps->txq_first_id = phys_id;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Num Tx Qs = %d\\n\", caps->num_txq);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Tx first queue ID = %d\\n\",\n+\t\t\t\t  caps->txq_first_id);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_MSIX:\n+\t\t\tcaps->num_msix_vectors = number;\n+\t\t\tcaps->msix_vector_first_id = phys_id;\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: MSIX vector count = %d\\n\",\n+\t\t\t\t  caps->num_msix_vectors);\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: MSIX first vector index = %d\\n\",\n+\t\t\t\t  caps->msix_vector_first_id);\n+\t\t\tbreak;\n+\t\tcase ICE_AQC_CAPS_MAX_MTU:\n+\t\t\tcaps->max_mtu = number;\n+\t\t\tif (dev_p)\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: Dev.MaxMTU = %d\\n\",\n+\t\t\t\t\t  caps->max_mtu);\n+\t\t\telse if (func_p)\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t  \"HW caps: func.MaxMTU = %d\\n\",\n+\t\t\t\t\t  caps->max_mtu);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t  \"HW caps: Unknown capability[%d]: 0x%x\\n\", i,\n+\t\t\t\t  cap);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * ice_aq_discover_caps - query function/device capabilities\n+ * @hw: pointer to the hw struct\n+ * @buf: a virtual buffer to hold the capabilities\n+ * @buf_size: Size of the virtual buffer\n+ * @cap_count: cap count needed if AQ err==ENOMEM\n+ * @opc: capabilities type to discover - pass in the command opcode\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get the function(0x000a)/device(0x000b) capabilities description from\n+ * the firmware.\n+ */\n+static enum ice_status\n+ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,\n+\t\t     enum ice_adminq_opc opc, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_list_caps *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.get_cap;\n+\n+\tif (opc != ice_aqc_opc_list_func_caps &&\n+\t    opc != ice_aqc_opc_list_dev_caps)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, opc);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (!status)\n+\t\tice_parse_caps(hw, buf, LE32_TO_CPU(cmd->count), opc);\n+\telse if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)\n+\t\t*cap_count = LE32_TO_CPU(cmd->count);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_discover_caps - get info about the HW\n+ * @hw: pointer to the hardware structure\n+ * @opc: capabilities type to discover - pass in the command opcode\n+ */\n+static enum ice_status\n+ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)\n+{\n+\tenum ice_status status;\n+\tu32 cap_count;\n+\tu16 cbuf_len;\n+\tu8 retries;\n+\n+\t/* The driver doesn't know how many capabilities the device will return\n+\t * so the buffer size required isn't known ahead of time. The driver\n+\t * starts with cbuf_len and if this turns out to be insufficient, the\n+\t * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.\n+\t * The driver then allocates the buffer based on the count and retries\n+\t * the operation. So it follows that the retry count is 2.\n+\t */\n+#define ICE_GET_CAP_BUF_COUNT\t40\n+#define ICE_GET_CAP_RETRY_COUNT\t2\n+\n+\tcap_count = ICE_GET_CAP_BUF_COUNT;\n+\tretries = ICE_GET_CAP_RETRY_COUNT;\n+\n+\tdo {\n+\t\tvoid *cbuf;\n+\n+\t\tcbuf_len = (u16)(cap_count *\n+\t\t\t\t sizeof(struct ice_aqc_list_caps_elem));\n+\t\tcbuf = ice_malloc(hw, cbuf_len);\n+\t\tif (!cbuf)\n+\t\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t\tstatus = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,\n+\t\t\t\t\t      opc, NULL);\n+\t\tice_free(hw, cbuf);\n+\n+\t\tif (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)\n+\t\t\tbreak;\n+\n+\t\t/* If ENOMEM is returned, try again with bigger buffer */\n+\t} while (--retries);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_get_caps - get info about the HW\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_get_caps(struct ice_hw *hw)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);\n+\tif (!status)\n+\t\tstatus = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_manage_mac_write - manage MAC address write command\n+ * @hw: pointer to the hw struct\n+ * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address\n+ * @flags: flags to control write behavior\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function is used to write MAC address to the NVM (0x0108).\n+ */\n+enum ice_status\n+ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,\n+\t\t\tstruct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_manage_mac_write *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.mac_write;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);\n+\n+\tcmd->flags = flags;\n+\n+\n+\t/* Prep values for flags, sah, sal */\n+\tcmd->sah = HTONS(*((const u16 *)mac_addr));\n+\tcmd->sal = HTONL(*((const u32 *)(mac_addr + 2)));\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * ice_aq_clear_pxe_mode\n+ * @hw: pointer to the hw struct\n+ *\n+ * Tell the firmware that the driver is taking over from PXE (0x0110).\n+ */\n+static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);\n+\tdesc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+}\n+\n+/**\n+ * ice_clear_pxe_mode - clear pxe operations mode\n+ * @hw: pointer to the hw struct\n+ *\n+ * Make sure all PXE mode settings are cleared, including things\n+ * like descriptor fetch/write-back mode.\n+ */\n+void ice_clear_pxe_mode(struct ice_hw *hw)\n+{\n+\tif (ice_check_sq_alive(hw, &hw->adminq))\n+\t\tice_aq_clear_pxe_mode(hw);\n+}\n+\n+\n+\n+/**\n+ * ice_get_link_speed_based_on_phy_type - returns link speed\n+ * @phy_type_low: lower part of phy_type\n+ *\n+ * This helper function will convert a phy_type_low to its corresponding link\n+ * speed.\n+ * Note: In the structure of phy_type_low, there should be one bit set, as\n+ * this function will convert one phy type to its speed.\n+ * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned\n+ * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned\n+ */\n+static u16 ice_get_link_speed_based_on_phy_type(u64 phy_type_low)\n+{\n+\tu16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\n+\tswitch (phy_type_low) {\n+\tcase ICE_PHY_TYPE_LOW_100BASE_TX:\n+\tcase ICE_PHY_TYPE_LOW_100M_SGMII:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_1000BASE_T:\n+\tcase ICE_PHY_TYPE_LOW_1000BASE_SX:\n+\tcase ICE_PHY_TYPE_LOW_1000BASE_LX:\n+\tcase ICE_PHY_TYPE_LOW_1000BASE_KX:\n+\tcase ICE_PHY_TYPE_LOW_1G_SGMII:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_2500BASE_T:\n+\tcase ICE_PHY_TYPE_LOW_2500BASE_X:\n+\tcase ICE_PHY_TYPE_LOW_2500BASE_KX:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_5GBASE_T:\n+\tcase ICE_PHY_TYPE_LOW_5GBASE_KR:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_10GBASE_T:\n+\tcase ICE_PHY_TYPE_LOW_10G_SFI_DA:\n+\tcase ICE_PHY_TYPE_LOW_10GBASE_SR:\n+\tcase ICE_PHY_TYPE_LOW_10GBASE_LR:\n+\tcase ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:\n+\tcase ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_10G_SFI_C2C:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_T:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_CR:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_CR_S:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_CR1:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_SR:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_LR:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_KR:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_KR_S:\n+\tcase ICE_PHY_TYPE_LOW_25GBASE_KR1:\n+\tcase ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_25G_AUI_C2C:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;\n+\t\tbreak;\n+\tcase ICE_PHY_TYPE_LOW_40GBASE_CR4:\n+\tcase ICE_PHY_TYPE_LOW_40GBASE_SR4:\n+\tcase ICE_PHY_TYPE_LOW_40GBASE_LR4:\n+\tcase ICE_PHY_TYPE_LOW_40GBASE_KR4:\n+\tcase ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:\n+\tcase ICE_PHY_TYPE_LOW_40G_XLAUI:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;\n+\t\tbreak;\n+\tdefault:\n+\t\tspeed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\t\tbreak;\n+\t}\n+\n+\treturn speed_phy_type_low;\n+}\n+\n+/**\n+ * ice_update_phy_type\n+ * @phy_type_low: pointer to the lower part of phy_type\n+ * @link_speeds_bitmap: targeted link speeds bitmap\n+ *\n+ * Note: For the link_speeds_bitmap structure, you can check it at\n+ * [ice_aqc_get_link_status->link_speed]. Caller can pass in\n+ * link_speeds_bitmap include multiple speeds.\n+ *\n+ * The value of phy_type_low will present a certain link speed. This helper\n+ * function will turn on bits in the phy_type_low based on the value of\n+ * link_speeds_bitmap input parameter.\n+ */\n+void ice_update_phy_type(u64 *phy_type_low, u16 link_speeds_bitmap)\n+{\n+\tu16 speed = ICE_AQ_LINK_SPEED_UNKNOWN;\n+\tu64 pt_low;\n+\tint index;\n+\n+\t/* We first check with low part of phy_type */\n+\tfor (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {\n+\t\tpt_low = BIT_ULL(index);\n+\t\tspeed = ice_get_link_speed_based_on_phy_type(pt_low);\n+\n+\t\tif (link_speeds_bitmap & speed)\n+\t\t\t*phy_type_low |= BIT_ULL(index);\n+\t}\n+}\n+\n+/**\n+ * ice_aq_set_phy_cfg\n+ * @hw: pointer to the hw struct\n+ * @lport: logical port number\n+ * @cfg: structure with PHY configuration data to be set\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Set the various PHY configuration parameters supported on the Port.\n+ * One or more of the Set PHY config parameters may be ignored in an MFP\n+ * mode as the PF may not have the privilege to set some of the PHY Config\n+ * parameters. This status will be indicated by the command response (0x0601).\n+ */\n+enum ice_status\n+ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,\n+\t\t   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tif (!cfg)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);\n+\tdesc.params.set_phy.lport_num = lport;\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);\n+}\n+\n+/**\n+ * ice_update_link_info - update status of the HW network link\n+ * @pi: port info structure of the interested logical port\n+ */\n+enum ice_status ice_update_link_info(struct ice_port_info *pi)\n+{\n+\tstruct ice_aqc_get_phy_caps_data *pcaps;\n+\tstruct ice_phy_info *phy_info;\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\thw = pi->hw;\n+\n+\tpcaps = (struct ice_aqc_get_phy_caps_data *)\n+\t\tice_malloc(hw, sizeof(*pcaps));\n+\tif (!pcaps)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tphy_info = &pi->phy;\n+\tstatus = ice_aq_get_link_info(pi, true, NULL, NULL);\n+\tif (status)\n+\t\tgoto out;\n+\n+\tif (phy_info->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {\n+\t\tstatus = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG,\n+\t\t\t\t\t     pcaps, NULL);\n+\t\tif (status)\n+\t\t\tgoto out;\n+\n+\t\tice_memcpy(phy_info->link_info.module_type, &pcaps->module_type,\n+\t\t\t   sizeof(phy_info->link_info.module_type),\n+\t\t\t   ICE_NONDMA_TO_NONDMA);\n+\t}\n+out:\n+\tice_free(hw, pcaps);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_set_fc\n+ * @pi: port information structure\n+ * @aq_failures: pointer to status code, specific to ice_set_fc routine\n+ * @ena_auto_link_update: enable automatic link update\n+ *\n+ * Set the requested flow control mode.\n+ */\n+enum ice_status\n+ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n+{\n+\tstruct ice_aqc_set_phy_cfg_data cfg = { 0 };\n+\tstruct ice_aqc_get_phy_caps_data *pcaps;\n+\tenum ice_status status;\n+\tu8 pause_mask = 0x0;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\thw = pi->hw;\n+\t*aq_failures = ICE_SET_FC_AQ_FAIL_NONE;\n+\n+\tswitch (pi->fc.req_mode) {\n+\tcase ICE_FC_FULL:\n+\t\tpause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;\n+\t\tpause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;\n+\t\tbreak;\n+\tcase ICE_FC_RX_PAUSE:\n+\t\tpause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;\n+\t\tbreak;\n+\tcase ICE_FC_TX_PAUSE:\n+\t\tpause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tpcaps = (struct ice_aqc_get_phy_caps_data *)\n+\t\tice_malloc(hw, sizeof(*pcaps));\n+\tif (!pcaps)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t/* Get the current phy config */\n+\tstatus = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,\n+\t\t\t\t     NULL);\n+\tif (status) {\n+\t\t*aq_failures = ICE_SET_FC_AQ_FAIL_GET;\n+\t\tgoto out;\n+\t}\n+\n+\t/* clear the old pause settings */\n+\tcfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |\n+\t\t\t\t   ICE_AQC_PHY_EN_RX_LINK_PAUSE);\n+\t/* set the new capabilities */\n+\tcfg.caps |= pause_mask;\n+\t/* If the capabilities have changed, then set the new config */\n+\tif (cfg.caps != pcaps->caps) {\n+\t\tint retry_count, retry_max = 10;\n+\n+\t\t/* Auto restart link so settings take effect */\n+\t\tif (ena_auto_link_update)\n+\t\t\tcfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;\n+\t\t/* Copy over all the old settings */\n+\t\tcfg.phy_type_low = pcaps->phy_type_low;\n+\t\tcfg.low_power_ctrl = pcaps->low_power_ctrl;\n+\t\tcfg.eee_cap = pcaps->eee_cap;\n+\t\tcfg.eeer_value = pcaps->eeer_value;\n+\t\tcfg.link_fec_opt = pcaps->link_fec_options;\n+\n+\t\tstatus = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);\n+\t\tif (status) {\n+\t\t\t*aq_failures = ICE_SET_FC_AQ_FAIL_SET;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\t/* Update the link info\n+\t\t * It sometimes takes a really long time for link to\n+\t\t * come back from the atomic reset. Thus, we wait a\n+\t\t * little bit.\n+\t\t */\n+\t\tfor (retry_count = 0; retry_count < retry_max; retry_count++) {\n+\t\t\tstatus = ice_update_link_info(pi);\n+\n+\t\t\tif (status == ICE_SUCCESS)\n+\t\t\t\tbreak;\n+\n+\t\t\tice_msec_delay(100, true);\n+\t\t}\n+\n+\t\tif (status)\n+\t\t\t*aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;\n+\t}\n+\n+out:\n+\tice_free(hw, pcaps);\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_get_link_status - get status of the HW network link\n+ * @pi: port information structure\n+ * @link_up: pointer to bool (true/false = linkup/linkdown)\n+ *\n+ * Variable link_up is true if link is up, false if link is down.\n+ * The variable link_up is invalid if status is non zero. As a\n+ * result of this call, link status reporting becomes enabled\n+ */\n+enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)\n+{\n+\tstruct ice_phy_info *phy_info;\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\tif (!pi || !link_up)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tphy_info = &pi->phy;\n+\n+\tif (phy_info->get_link_info) {\n+\t\tstatus = ice_update_link_info(pi);\n+\n+\t\tif (status)\n+\t\t\tice_debug(pi->hw, ICE_DBG_LINK,\n+\t\t\t\t  \"get link status error, status = %d\\n\",\n+\t\t\t\t  status);\n+\t}\n+\n+\t*link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_set_link_restart_an\n+ * @pi: pointer to the port information structure\n+ * @ena_link: if true: enable link, if false: disable link\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Sets up the link and restarts the Auto-Negotiation over the link.\n+ */\n+enum ice_status\n+ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,\n+\t\t\t   struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_restart_an *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.restart_an;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);\n+\n+\tcmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;\n+\tcmd->lport_num = pi->lport;\n+\tif (ena_link)\n+\t\tcmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;\n+\telse\n+\t\tcmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;\n+\n+\treturn ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * ice_aq_set_event_mask\n+ * @hw: pointer to the hw struct\n+ * @port_num: port number of the physical function\n+ * @mask: event mask to be set\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Set event mask (0x0613)\n+ */\n+enum ice_status\n+ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,\n+\t\t      struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_set_event_mask *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.set_event_mask;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);\n+\n+\tcmd->lport_num = port_num;\n+\n+\tcmd->event_mask = CPU_TO_LE16(mask);\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+/**\n+ * ice_aq_set_mac_loopback\n+ * @hw: pointer to the hw struct\n+ * @ena_lpbk: Enable or Disable loopback\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Enable/disable loopback on a given port\n+ */\n+enum ice_status\n+ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_set_mac_lb *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.set_mac_lb;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);\n+\tif (ena_lpbk)\n+\t\tcmd->lb_mode = ICE_AQ_MAC_LB_EN;\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+\n+/**\n+ * ice_aq_set_port_id_led\n+ * @pi: pointer to the port information\n+ * @is_orig_mode: is this LED set to original mode (by the net-list)\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Set LED value for the given port (0x06e9)\n+ */\n+enum ice_status\n+ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,\n+\t\t       struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_set_port_id_led *cmd;\n+\tstruct ice_hw *hw = pi->hw;\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd = &desc.params.set_port_id_led;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);\n+\n+\n+\tif (is_orig_mode)\n+\t\tcmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;\n+\telse\n+\t\tcmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;\n+\n+\treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+}\n+\n+\n+/**\n+ * __ice_aq_get_set_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_id: VSI FW index\n+ * @lut_type: LUT table type\n+ * @lut: pointer to the LUT buffer provided by the caller\n+ * @lut_size: size of the LUT buffer\n+ * @glob_lut_idx: global LUT index\n+ * @set: set true to set the table, false to get the table\n+ *\n+ * Internal function to get (0x0B05) or set (0x0B03) RSS look up table\n+ */\n+static enum ice_status\n+__ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,\n+\t\t\t u16 lut_size, u8 glob_lut_idx, bool set)\n+{\n+\tstruct ice_aqc_get_set_rss_lut *cmd_resp;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\tu16 flags = 0;\n+\n+\tcmd_resp = &desc.params.get_set_rss_lut;\n+\n+\tif (set) {\n+\t\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);\n+\t\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\t} else {\n+\t\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);\n+\t}\n+\n+\tcmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<\n+\t\t\t\t\t ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &\n+\t\t\t\t\tICE_AQC_GSET_RSS_LUT_VSI_ID_M) |\n+\t\t\t\t       ICE_AQC_GSET_RSS_LUT_VSI_VALID);\n+\n+\tswitch (lut_type) {\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:\n+\t\tflags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &\n+\t\t\t  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);\n+\t\tbreak;\n+\tdefault:\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto ice_aq_get_set_rss_lut_exit;\n+\t}\n+\n+\tif (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {\n+\t\tflags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &\n+\t\t\t  ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);\n+\n+\t\tif (!set)\n+\t\t\tgoto ice_aq_get_set_rss_lut_send;\n+\t} else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {\n+\t\tif (!set)\n+\t\t\tgoto ice_aq_get_set_rss_lut_send;\n+\t} else {\n+\t\tgoto ice_aq_get_set_rss_lut_send;\n+\t}\n+\n+\t/* LUT size is only valid for Global and PF table types */\n+\tswitch (lut_size) {\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:\n+\t\tbreak;\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:\n+\t\tflags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<\n+\t\t\t  ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &\n+\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;\n+\t\tbreak;\n+\tcase ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:\n+\t\tif (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {\n+\t\t\tflags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<\n+\t\t\t\t  ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &\n+\t\t\t\t ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* fall-through */\n+\tdefault:\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto ice_aq_get_set_rss_lut_exit;\n+\t}\n+\n+ice_aq_get_set_rss_lut_send:\n+\tcmd_resp->flags = CPU_TO_LE16(flags);\n+\tstatus = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);\n+\n+ice_aq_get_set_rss_lut_exit:\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_get_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: software VSI handle\n+ * @lut_type: LUT table type\n+ * @lut: pointer to the LUT buffer provided by the caller\n+ * @lut_size: size of the LUT buffer\n+ *\n+ * get the RSS lookup table, PF or VSI type\n+ */\n+enum ice_status\n+ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,\n+\t\t   u8 *lut, u16 lut_size)\n+{\n+\tif (!ice_is_vsi_valid(hw, vsi_handle) || !lut)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),\n+\t\t\t\t\tlut_type, lut, lut_size, 0, false);\n+}\n+\n+/**\n+ * ice_aq_set_rss_lut\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: software VSI handle\n+ * @lut_type: LUT table type\n+ * @lut: pointer to the LUT buffer provided by the caller\n+ * @lut_size: size of the LUT buffer\n+ *\n+ * set the RSS lookup table, PF or VSI type\n+ */\n+enum ice_status\n+ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,\n+\t\t   u8 *lut, u16 lut_size)\n+{\n+\tif (!ice_is_vsi_valid(hw, vsi_handle) || !lut)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),\n+\t\t\t\t\tlut_type, lut, lut_size, 0, true);\n+}\n+\n+/**\n+ * __ice_aq_get_set_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_id: VSI FW index\n+ * @key: pointer to key info struct\n+ * @set: set true to set the key, false to get the key\n+ *\n+ * get (0x0B04) or set (0x0B02) the RSS key per VSI\n+ */\n+static enum\n+ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,\n+\t\t\t\t    struct ice_aqc_get_set_rss_keys *key,\n+\t\t\t\t    bool set)\n+{\n+\tstruct ice_aqc_get_set_rss_key *cmd_resp;\n+\tu16 key_size = sizeof(*key);\n+\tstruct ice_aq_desc desc;\n+\n+\tcmd_resp = &desc.params.get_set_rss_key;\n+\n+\tif (set) {\n+\t\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);\n+\t\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\t} else {\n+\t\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);\n+\t}\n+\n+\tcmd_resp->vsi_id = CPU_TO_LE16(((vsi_id <<\n+\t\t\t\t\t ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &\n+\t\t\t\t\tICE_AQC_GSET_RSS_KEY_VSI_ID_M) |\n+\t\t\t\t       ICE_AQC_GSET_RSS_KEY_VSI_VALID);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, key, key_size, NULL);\n+}\n+\n+/**\n+ * ice_aq_get_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: software VSI handle\n+ * @key: pointer to key info struct\n+ *\n+ * get the RSS key per VSI\n+ */\n+enum ice_status\n+ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,\n+\t\t   struct ice_aqc_get_set_rss_keys *key)\n+{\n+\tif (!ice_is_vsi_valid(hw, vsi_handle) || !key)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),\n+\t\t\t\t\tkey, false);\n+}\n+\n+/**\n+ * ice_aq_set_rss_key\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: software VSI handle\n+ * @keys: pointer to key info struct\n+ *\n+ * set the RSS key per VSI\n+ */\n+enum ice_status\n+ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,\n+\t\t   struct ice_aqc_get_set_rss_keys *keys)\n+{\n+\tif (!ice_is_vsi_valid(hw, vsi_handle) || !keys)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\treturn __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),\n+\t\t\t\t\tkeys, true);\n+}\n+\n+/**\n+ * ice_aq_add_lan_txq\n+ * @hw: pointer to the hardware structure\n+ * @num_qgrps: Number of added queue groups\n+ * @qg_list: list of queue groups to be added\n+ * @buf_size: size of buffer for indirect command\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Add Tx LAN queue (0x0C30)\n+ *\n+ * NOTE:\n+ * Prior to calling add Tx LAN queue:\n+ * Initialize the following as part of the Tx queue context:\n+ * Completion queue ID if the queue uses Completion queue, Quanta profile,\n+ * Cache profile and Packet shaper profile.\n+ *\n+ * After add Tx LAN queue AQ command is completed:\n+ * Interrupts should be associated with specific queues,\n+ * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue\n+ * flow.\n+ */\n+static enum ice_status\n+ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,\n+\t\t   struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,\n+\t\t   struct ice_sq_cd *cd)\n+{\n+\tu16 i, sum_header_size, sum_q_size = 0;\n+\tstruct ice_aqc_add_tx_qgrp *list;\n+\tstruct ice_aqc_add_txqs *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_add_lan_txq\");\n+\n+\tcmd = &desc.params.add_txqs;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);\n+\n+\tif (!qg_list)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tsum_header_size = num_qgrps *\n+\t\t(sizeof(*qg_list) - sizeof(*qg_list->txqs));\n+\n+\tlist = qg_list;\n+\tfor (i = 0; i < num_qgrps; i++) {\n+\t\tstruct ice_aqc_add_txqs_perq *q = list->txqs;\n+\n+\t\tsum_q_size += list->num_txqs * sizeof(*q);\n+\t\tlist = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);\n+\t}\n+\n+\tif (buf_size != (sum_header_size + sum_q_size))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tcmd->num_qgrps = num_qgrps;\n+\n+\treturn ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);\n+}\n+\n+/**\n+ * ice_aq_dis_lan_txq\n+ * @hw: pointer to the hardware structure\n+ * @num_qgrps: number of groups in the list\n+ * @qg_list: the list of groups to disable\n+ * @buf_size: the total size of the qg_list buffer in bytes\n+ * @rst_src: if called due to reset, specifies the rst source\n+ * @vmvf_num: the relative vm or vf number that is undergoing the reset\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Disable LAN Tx queue (0x0C31)\n+ */\n+static enum ice_status\n+ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,\n+\t\t   struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,\n+\t\t   enum ice_disq_rst_src rst_src, u16 vmvf_num,\n+\t\t   struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_dis_txqs *cmd;\n+\tstruct ice_aq_desc desc;\n+\tu16 i, sz = 0;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_dis_lan_txq\");\n+\tcmd = &desc.params.dis_txqs;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);\n+\n+\t/* qg_list can be NULL only in VM/VF reset flow */\n+\tif (!qg_list && !rst_src)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tcmd->num_entries = num_qgrps;\n+\n+\tcmd->vmvf_and_timeout = CPU_TO_LE16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &\n+\t\t\t\t\t    ICE_AQC_Q_DIS_TIMEOUT_M);\n+\n+\tswitch (rst_src) {\n+\tcase ICE_VM_RESET:\n+\t\tcmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;\n+\t\tcmd->vmvf_and_timeout |=\n+\t\t\tCPU_TO_LE16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);\n+\t\tbreak;\n+\tcase ICE_VF_RESET:\n+\t\tcmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;\n+\t\t/* In this case, FW expects vmvf_num to be absolute VF id */\n+\t\tcmd->vmvf_and_timeout |=\n+\t\t\tCPU_TO_LE16((vmvf_num + hw->func_caps.vf_base_id) &\n+\t\t\t\t    ICE_AQC_Q_DIS_VMVF_NUM_M);\n+\t\tbreak;\n+\tcase ICE_NO_RESET:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/* If no queue group info, we are in a reset flow. Issue the AQ */\n+\tif (!qg_list)\n+\t\tgoto do_aq;\n+\n+\t/* set RD bit to indicate that command buffer is provided by the driver\n+\t * and it needs to be read by the firmware\n+\t */\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tfor (i = 0; i < num_qgrps; ++i) {\n+\t\t/* Calculate the size taken up by the queue IDs in this group */\n+\t\tsz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);\n+\n+\t\t/* Add the size of the group header */\n+\t\tsz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);\n+\n+\t\t/* If the num of queues is even, add 2 bytes of padding */\n+\t\tif ((qg_list[i].num_qs % 2) == 0)\n+\t\t\tsz += 2;\n+\t}\n+\n+\tif (buf_size != sz)\n+\t\treturn ICE_ERR_PARAM;\n+\n+do_aq:\n+\treturn ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);\n+}\n+\n+\n+/* End of FW Admin Queue command wrappers */\n+\n+/**\n+ * ice_write_byte - write a byte to a packed context structure\n+ * @src_ctx:  the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info:  a description of the struct to be filled\n+ */\n+static void\n+ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tu8 src_byte, dest_byte, mask;\n+\tu8 *from, *dest;\n+\tu16 shift_width;\n+\n+\t/* copy from the next struct field */\n+\tfrom = src_ctx + ce_info->offset;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\tmask = (u8)(BIT(ce_info->width) - 1);\n+\n+\tsrc_byte = *from;\n+\tsrc_byte &= mask;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\tsrc_byte <<= shift_width;\n+\n+\t/* get the current bits from the target bit string */\n+\tdest = dest_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&dest_byte, dest, sizeof(dest_byte), ICE_DMA_TO_NONDMA);\n+\n+\tdest_byte &= ~mask;\t/* get the bits not changing */\n+\tdest_byte |= src_byte;\t/* add in the new bits */\n+\n+\t/* put it all back */\n+\tice_memcpy(dest, &dest_byte, sizeof(dest_byte), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_write_word - write a word to a packed context structure\n+ * @src_ctx:  the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info:  a description of the struct to be filled\n+ */\n+static void\n+ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tu16 src_word, mask;\n+\t__le16 dest_word;\n+\tu8 *from, *dest;\n+\tu16 shift_width;\n+\n+\t/* copy from the next struct field */\n+\tfrom = src_ctx + ce_info->offset;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\tmask = BIT(ce_info->width) - 1;\n+\n+\t/* don't swizzle the bits until after the mask because the mask bits\n+\t * will be in a different bit position on big endian machines\n+\t */\n+\tsrc_word = *(u16 *)from;\n+\tsrc_word &= mask;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\tsrc_word <<= shift_width;\n+\n+\t/* get the current bits from the target bit string */\n+\tdest = dest_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&dest_word, dest, sizeof(dest_word), ICE_DMA_TO_NONDMA);\n+\n+\tdest_word &= ~(CPU_TO_LE16(mask));\t/* get the bits not changing */\n+\tdest_word |= CPU_TO_LE16(src_word);\t/* add in the new bits */\n+\n+\t/* put it all back */\n+\tice_memcpy(dest, &dest_word, sizeof(dest_word), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_write_dword - write a dword to a packed context structure\n+ * @src_ctx:  the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info:  a description of the struct to be filled\n+ */\n+static void\n+ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tu32 src_dword, mask;\n+\t__le32 dest_dword;\n+\tu8 *from, *dest;\n+\tu16 shift_width;\n+\n+\t/* copy from the next struct field */\n+\tfrom = src_ctx + ce_info->offset;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\n+\t/* if the field width is exactly 32 on an x86 machine, then the shift\n+\t * operation will not work because the SHL instructions count is masked\n+\t * to 5 bits so the shift will do nothing\n+\t */\n+\tif (ce_info->width < 32)\n+\t\tmask = BIT(ce_info->width) - 1;\n+\telse\n+\t\tmask = (u32)~0;\n+\n+\t/* don't swizzle the bits until after the mask because the mask bits\n+\t * will be in a different bit position on big endian machines\n+\t */\n+\tsrc_dword = *(u32 *)from;\n+\tsrc_dword &= mask;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\tsrc_dword <<= shift_width;\n+\n+\t/* get the current bits from the target bit string */\n+\tdest = dest_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&dest_dword, dest, sizeof(dest_dword), ICE_DMA_TO_NONDMA);\n+\n+\tdest_dword &= ~(CPU_TO_LE32(mask));\t/* get the bits not changing */\n+\tdest_dword |= CPU_TO_LE32(src_dword);\t/* add in the new bits */\n+\n+\t/* put it all back */\n+\tice_memcpy(dest, &dest_dword, sizeof(dest_dword), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_write_qword - write a qword to a packed context structure\n+ * @src_ctx:  the context structure to read from\n+ * @dest_ctx: the context to be written to\n+ * @ce_info:  a description of the struct to be filled\n+ */\n+static void\n+ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tu64 src_qword, mask;\n+\t__le64 dest_qword;\n+\tu8 *from, *dest;\n+\tu16 shift_width;\n+\n+\t/* copy from the next struct field */\n+\tfrom = src_ctx + ce_info->offset;\n+\n+\t/* prepare the bits and mask */\n+\tshift_width = ce_info->lsb % 8;\n+\n+\t/* if the field width is exactly 64 on an x86 machine, then the shift\n+\t * operation will not work because the SHL instructions count is masked\n+\t * to 6 bits so the shift will do nothing\n+\t */\n+\tif (ce_info->width < 64)\n+\t\tmask = BIT_ULL(ce_info->width) - 1;\n+\telse\n+\t\tmask = (u64)~0;\n+\n+\t/* don't swizzle the bits until after the mask because the mask bits\n+\t * will be in a different bit position on big endian machines\n+\t */\n+\tsrc_qword = *(u64 *)from;\n+\tsrc_qword &= mask;\n+\n+\t/* shift to correct alignment */\n+\tmask <<= shift_width;\n+\tsrc_qword <<= shift_width;\n+\n+\t/* get the current bits from the target bit string */\n+\tdest = dest_ctx + (ce_info->lsb / 8);\n+\n+\tice_memcpy(&dest_qword, dest, sizeof(dest_qword), ICE_DMA_TO_NONDMA);\n+\n+\tdest_qword &= ~(CPU_TO_LE64(mask));\t/* get the bits not changing */\n+\tdest_qword |= CPU_TO_LE64(src_qword);\t/* add in the new bits */\n+\n+\t/* put it all back */\n+\tice_memcpy(dest, &dest_qword, sizeof(dest_qword), ICE_NONDMA_TO_DMA);\n+}\n+\n+/**\n+ * ice_set_ctx - set context bits in packed structure\n+ * @src_ctx:  pointer to a generic non-packed context structure\n+ * @dest_ctx: pointer to memory for the packed structure\n+ * @ce_info:  a description of the structure to be transformed\n+ */\n+enum ice_status\n+ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)\n+{\n+\tint f;\n+\n+\tfor (f = 0; ce_info[f].width; f++) {\n+\t\t/* We have to deal with each element of the FW response\n+\t\t * using the correct size so that we are correct regardless\n+\t\t * of the endianness of the machine.\n+\t\t */\n+\t\tswitch (ce_info[f].size_of) {\n+\t\tcase sizeof(u8):\n+\t\t\tice_write_byte(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tcase sizeof(u16):\n+\t\t\tice_write_word(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tcase sizeof(u32):\n+\t\t\tice_write_dword(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tcase sizeof(u64):\n+\t\t\tice_write_qword(src_ctx, dest_ctx, &ce_info[f]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\treturn ICE_ERR_INVAL_SIZE;\n+\t\t}\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+\n+\n+\n+\n+/**\n+ * ice_ena_vsi_txq\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: tc number\n+ * @num_qgrps: Number of added queue groups\n+ * @buf: list of queue groups to be added\n+ * @buf_size: size of buffer for indirect command\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function adds one lan q\n+ */\n+enum ice_status\n+ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_qgrps,\n+\t\tstruct ice_aqc_add_tx_qgrp *buf, u16 buf_size,\n+\t\tstruct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_txsched_elem_data node = { 0 };\n+\tstruct ice_sched_node *parent;\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tif (num_qgrps > 1 || buf->num_txqs > 1)\n+\t\treturn ICE_ERR_MAX_LIMIT;\n+\n+\thw = pi->hw;\n+\n+\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\t/* find a parent node */\n+\tparent = ice_sched_get_free_qparent(pi, vsi_handle, tc,\n+\t\t\t\t\t    ICE_SCHED_NODE_OWNER_LAN);\n+\tif (!parent) {\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto ena_txq_exit;\n+\t}\n+\n+\tbuf->parent_teid = parent->info.node_teid;\n+\tnode.parent_teid = parent->info.node_teid;\n+\t/* Mark that the values in the \"generic\" section as valid. The default\n+\t * value in the \"generic\" section is zero. This means that :\n+\t * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.\n+\t * - 0 priority among siblings, indicated by Bit 1-3.\n+\t * - WFQ, indicated by Bit 4.\n+\t * - 0 Adjustment value is used in PSM credit update flow, indicated by\n+\t * Bit 5-6.\n+\t * - Bit 7 is reserved.\n+\t * Without setting the generic section as valid in valid_sections, the\n+\t * Admin Q command will fail with error code ICE_AQ_RC_EINVAL.\n+\t */\n+\tbuf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;\n+\n+\t/* add the lan q */\n+\tstatus = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);\n+\tif (status != ICE_SUCCESS)\n+\t\tgoto ena_txq_exit;\n+\n+\tnode.node_teid = buf->txqs[0].q_teid;\n+\tnode.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;\n+\n+\t/* add a leaf node into schduler tree q layer */\n+\tstatus = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);\n+\n+ena_txq_exit:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_dis_vsi_txq\n+ * @pi: port information structure\n+ * @num_queues: number of queues\n+ * @q_ids: pointer to the q_id array\n+ * @q_teids: pointer to queue node teids\n+ * @rst_src: if called due to reset, specifies the rst source\n+ * @vmvf_num: the relative vm or vf number that is undergoing the reset\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function removes queues and their corresponding nodes in SW DB\n+ */\n+enum ice_status\n+ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,\n+\t\tu32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,\n+\t\tstruct ice_sq_cd *cd)\n+{\n+\tenum ice_status status = ICE_ERR_DOES_NOT_EXIST;\n+\tstruct ice_aqc_dis_txq_item qg_list;\n+\tu16 i;\n+\n+\tif (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)\n+\t\treturn ICE_ERR_CFG;\n+\n+\t/* if queue is disabled already yet the disable queue command has to be\n+\t * sent to complete the VF reset, then call ice_aq_dis_lan_txq without\n+\t * any queue information\n+\t */\n+\n+\tif (!num_queues && rst_src)\n+\t\treturn ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src, vmvf_num,\n+\t\t\t\t\t  NULL);\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\tfor (i = 0; i < num_queues; i++) {\n+\t\tstruct ice_sched_node *node;\n+\n+\t\tnode = ice_sched_find_node_by_teid(pi->root, q_teids[i]);\n+\t\tif (!node)\n+\t\t\tcontinue;\n+\t\tqg_list.parent_teid = node->info.parent_teid;\n+\t\tqg_list.num_qs = 1;\n+\t\tqg_list.q_id[0] = CPU_TO_LE16(q_ids[i]);\n+\t\tstatus = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,\n+\t\t\t\t\t    sizeof(qg_list), rst_src, vmvf_num,\n+\t\t\t\t\t    cd);\n+\n+\t\tif (status != ICE_SUCCESS)\n+\t\t\tbreak;\n+\t\tice_free_sched_node(pi, node);\n+\t}\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_vsi_qs - configure the new/exisiting VSI queues\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc_bitmap: TC bitmap\n+ * @maxqs: max queues array per TC\n+ * @owner: lan or rdma\n+ *\n+ * This function adds/updates the VSI queues per TC.\n+ */\n+static enum ice_status\n+ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n+\t       u16 *maxqs, u8 owner)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 i;\n+\n+\tif (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_acquire_lock(&pi->sched_lock);\n+\n+\tfor (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) {\n+\t\t/* configuration is possible only if TC node is present */\n+\t\tif (!ice_sched_get_tc_node(pi, i))\n+\t\t\tcontinue;\n+\n+\t\tstatus = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,\n+\t\t\t\t\t   ice_is_tc_ena(tc_bitmap, i));\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_cfg_vsi_lan - configure VSI lan queues\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc_bitmap: TC bitmap\n+ * @max_lanqs: max lan queues array per TC\n+ *\n+ * This function adds/updates the VSI lan queues per TC.\n+ */\n+enum ice_status\n+ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n+\t\tu16 *max_lanqs)\n+{\n+\treturn ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,\n+\t\t\t      ICE_SCHED_NODE_OWNER_LAN);\n+}\n+\n+\n+\n+\n+\n+/**\n+ * ice_replay_pre_init - replay pre initialization\n+ * @hw: pointer to the hw struct\n+ *\n+ * Initializes required config data for VSI, FD, ACL, and RSS before replay.\n+ */\n+static enum ice_status ice_replay_pre_init(struct ice_hw *hw)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tu8 i;\n+\n+\t/* Delete old entries from replay filter list head if there is any */\n+\tice_rm_all_sw_replay_rule_info(hw);\n+\t/* In start of replay, move entries into replay_rules list, it\n+\t * will allow adding rules entries back to filt_rules list,\n+\t * which is operational list.\n+\t */\n+\tfor (i = 0; i < ICE_SW_LKUP_LAST; i++)\n+\t\tLIST_REPLACE_INIT(&sw->recp_list[i].filt_rules,\n+\t\t\t\t  &sw->recp_list[i].filt_replay_rules);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_replay_vsi - replay vsi configuration\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: driver vsi handle\n+ *\n+ * Restore all VSI configuration after reset. It is required to call this\n+ * function with main VSI first.\n+ */\n+enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\tenum ice_status status;\n+\n+\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Replay pre-initialization if there is any */\n+\tif (vsi_handle == ICE_MAIN_VSI_HANDLE) {\n+\t\tstatus = ice_replay_pre_init(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\t/* Replay per VSI all filters */\n+\tstatus = ice_replay_vsi_all_fltr(hw, vsi_handle);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_replay_post - post replay configuration cleanup\n+ * @hw: pointer to the hw struct\n+ *\n+ * Post replay cleanup.\n+ */\n+void ice_replay_post(struct ice_hw *hw)\n+{\n+\t/* Delete old entries from replay filter list head */\n+\tice_rm_all_sw_replay_rule_info(hw);\n+}\n+\n+/**\n+ * ice_stat_update40 - read 40 bit stat from the chip and update stat values\n+ * @hw: ptr to the hardware info\n+ * @hireg: high 32 bit HW register to read from\n+ * @loreg: low 32 bit HW register to read from\n+ * @prev_stat_loaded: bool to specify if previous stats are loaded\n+ * @prev_stat: ptr to previous loaded stat value\n+ * @cur_stat: ptr to current stat value\n+ */\n+void\n+ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,\n+\t\t  bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat)\n+{\n+\tu64 new_data;\n+\n+\tnew_data = rd32(hw, loreg);\n+\tnew_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;\n+\n+\t/* device stats are not reset at PFR, they likely will not be zeroed\n+\t * when the driver starts. So save the first values read and use them as\n+\t * offsets to be subtracted from the raw values in order to report stats\n+\t * that count from zero.\n+\t */\n+\tif (!prev_stat_loaded)\n+\t\t*prev_stat = new_data;\n+\tif (new_data >= *prev_stat)\n+\t\t*cur_stat = new_data - *prev_stat;\n+\telse\n+\t\t/* to manage the potential roll-over */\n+\t\t*cur_stat = (new_data + BIT_ULL(40)) - *prev_stat;\n+\t*cur_stat &= 0xFFFFFFFFFFULL;\n+}\n+\n+/**\n+ * ice_stat_update32 - read 32 bit stat from the chip and update stat values\n+ * @hw: ptr to the hardware info\n+ * @reg: HW register to read from\n+ * @prev_stat_loaded: bool to specify if previous stats are loaded\n+ * @prev_stat: ptr to previous loaded stat value\n+ * @cur_stat: ptr to current stat value\n+ */\n+void\n+ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,\n+\t\t  u64 *prev_stat, u64 *cur_stat)\n+{\n+\tu32 new_data;\n+\n+\tnew_data = rd32(hw, reg);\n+\n+\t/* device stats are not reset at PFR, they likely will not be zeroed\n+\t * when the driver starts. So save the first values read and use them as\n+\t * offsets to be subtracted from the raw values in order to report stats\n+\t * that count from zero.\n+\t */\n+\tif (!prev_stat_loaded)\n+\t\t*prev_stat = new_data;\n+\tif (new_data >= *prev_stat)\n+\t\t*cur_stat = new_data - *prev_stat;\n+\telse\n+\t\t/* to manage the potential roll-over */\n+\t\t*cur_stat = (new_data + BIT_ULL(32)) - *prev_stat;\n+}\n+\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nnew file mode 100644\nindex 0000000..fc2870c\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -0,0 +1,159 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_COMMON_H_\n+#define _ICE_COMMON_H_\n+\n+#include \"ice_type.h\"\n+\n+#include \"virtchnl.h\"\n+#include \"ice_switch.h\"\n+\n+enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);\n+\n+void\n+ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len);\n+enum ice_status ice_init_hw(struct ice_hw *hw);\n+void ice_deinit_hw(struct ice_hw *hw);\n+enum ice_status ice_check_reset(struct ice_hw *hw);\n+enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);\n+\n+enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);\n+void ice_shutdown_all_ctrlq(struct ice_hw *hw);\n+enum ice_status\n+ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n+\t\t  struct ice_rq_event_info *e, u16 *pending);\n+enum ice_status\n+ice_get_link_status(struct ice_port_info *pi, bool *link_up);\n+enum ice_status\n+ice_update_link_info(struct ice_port_info *pi);\n+enum ice_status\n+ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,\n+\t\tenum ice_aq_res_access_type access, u32 timeout);\n+void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);\n+enum ice_status\n+ice_aq_alloc_free_res(struct ice_hw *hw, u16 num_entries,\n+\t\t      struct ice_aqc_alloc_free_res_elem *buf, u16 buf_size,\n+\t\t      enum ice_adminq_opc opc, struct ice_sq_cd *cd);\n+enum ice_status ice_init_nvm(struct ice_hw *hw);\n+enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);\n+enum ice_status\n+ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);\n+enum ice_status\n+ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n+\t\tstruct ice_aq_desc *desc, void *buf, u16 buf_size,\n+\t\tstruct ice_sq_cd *cd);\n+void ice_clear_pxe_mode(struct ice_hw *hw);\n+\n+enum ice_status ice_get_caps(struct ice_hw *hw);\n+\n+\n+\n+#if defined(FPGA_SUPPORT) || defined(CVL_A0_SUPPORT)\n+void ice_dev_onetime_setup(struct ice_hw *hw);\n+#endif /* FPGA_SUPPORT || CVL_A0_SUPPORT */\n+\n+\n+enum ice_status\n+ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,\n+\t\t  u32 rxq_index);\n+#if !defined(NO_UNUSED_CTX_CODE) || defined(AE_DRIVER)\n+enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index);\n+enum ice_status\n+ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index);\n+enum ice_status\n+ice_write_tx_cmpltnq_ctx(struct ice_hw *hw,\n+\t\t\t struct ice_tx_cmpltnq_ctx *tx_cmpltnq_ctx,\n+\t\t\t u32 tx_cmpltnq_index);\n+enum ice_status\n+ice_clear_tx_drbell_q_ctx(struct ice_hw *hw, u32 tx_drbell_q_index);\n+enum ice_status\n+ice_write_tx_drbell_q_ctx(struct ice_hw *hw,\n+\t\t\t  struct ice_tx_drbell_q_ctx *tx_drbell_q_ctx,\n+\t\t\t  u32 tx_drbell_q_index);\n+#endif /* !NO_UNUSED_CTX_CODE || AE_DRIVER */\n+\n+enum ice_status\n+ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,\n+\t\t   u16 lut_size);\n+enum ice_status\n+ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,\n+\t\t   u16 lut_size);\n+enum ice_status\n+ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,\n+\t\t   struct ice_aqc_get_set_rss_keys *keys);\n+enum ice_status\n+ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,\n+\t\t   struct ice_aqc_get_set_rss_keys *keys);\n+\n+bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);\n+enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);\n+void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);\n+extern const struct ice_ctx_ele ice_tlan_ctx_info[];\n+enum ice_status\n+ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);\n+enum ice_status\n+ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,\n+\t\tvoid *buf, u16 buf_size, struct ice_sq_cd *cd);\n+enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);\n+\n+enum ice_status\n+ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n+\t\t    struct ice_aqc_get_phy_caps_data *caps,\n+\t\t    struct ice_sq_cd *cd);\n+void\n+ice_update_phy_type(u64 *phy_type_low, u16 link_speeds_bitmap);\n+enum ice_status\n+ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,\n+\t\t\tstruct ice_sq_cd *cd);\n+\n+enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);\n+enum ice_status\n+ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,\n+\t\t   struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);\n+enum ice_status\n+ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,\n+\t   bool ena_auto_link_update);\n+\n+enum ice_status\n+ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,\n+\t\t\t   struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,\n+\t\t     struct ice_link_status *link, struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,\n+\t\t      struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd);\n+\n+\n+enum ice_status\n+ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,\n+\t\t       struct ice_sq_cd *cd);\n+\n+\n+\n+\n+enum ice_status\n+ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,\n+\t\tu32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,\n+\t\tstruct ice_sq_cd *cmd_details);\n+enum ice_status\n+ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,\n+\t\tu16 *max_lanqs);\n+enum ice_status\n+ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_qgrps,\n+\t\tstruct ice_aqc_add_tx_qgrp *buf, u16 buf_size,\n+\t\tstruct ice_sq_cd *cd);\n+enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);\n+void ice_replay_post(struct ice_hw *hw);\n+void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf);\n+void\n+ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,\n+\t\t  bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat);\n+void\n+ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,\n+\t\t  u64 *prev_stat, u64 *cur_stat);\n+#endif /* _ICE_COMMON_H_ */\ndiff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c\nnew file mode 100644\nindex 0000000..cbc4cb4\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_controlq.c\n@@ -0,0 +1,1098 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_common.h\"\n+\n+\n+#define ICE_CQ_INIT_REGS(qinfo, prefix)\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\\\n+\t(qinfo)->sq.head = prefix##_ATQH;\t\t\t\\\n+\t(qinfo)->sq.tail = prefix##_ATQT;\t\t\t\\\n+\t(qinfo)->sq.len = prefix##_ATQLEN;\t\t\t\\\n+\t(qinfo)->sq.bah = prefix##_ATQBAH;\t\t\t\\\n+\t(qinfo)->sq.bal = prefix##_ATQBAL;\t\t\t\\\n+\t(qinfo)->sq.len_mask = prefix##_ATQLEN_ATQLEN_M;\t\\\n+\t(qinfo)->sq.len_ena_mask = prefix##_ATQLEN_ATQENABLE_M;\t\\\n+\t(qinfo)->sq.head_mask = prefix##_ATQH_ATQH_M;\t\t\\\n+\t(qinfo)->rq.head = prefix##_ARQH;\t\t\t\\\n+\t(qinfo)->rq.tail = prefix##_ARQT;\t\t\t\\\n+\t(qinfo)->rq.len = prefix##_ARQLEN;\t\t\t\\\n+\t(qinfo)->rq.bah = prefix##_ARQBAH;\t\t\t\\\n+\t(qinfo)->rq.bal = prefix##_ARQBAL;\t\t\t\\\n+\t(qinfo)->rq.len_mask = prefix##_ARQLEN_ARQLEN_M;\t\\\n+\t(qinfo)->rq.len_ena_mask = prefix##_ARQLEN_ARQENABLE_M;\t\\\n+\t(qinfo)->rq.head_mask = prefix##_ARQH_ARQH_M;\t\t\\\n+} while (0)\n+\n+/**\n+ * ice_adminq_init_regs - Initialize AdminQ registers\n+ * @hw: pointer to the hardware structure\n+ *\n+ * This assumes the alloc_sq and alloc_rq functions have already been called\n+ */\n+static void ice_adminq_init_regs(struct ice_hw *hw)\n+{\n+\tstruct ice_ctl_q_info *cq = &hw->adminq;\n+\n+\tICE_CQ_INIT_REGS(cq, PF_FW);\n+}\n+\n+/**\n+ * ice_mailbox_init_regs - Initialize Mailbox registers\n+ * @hw: pointer to the hardware structure\n+ *\n+ * This assumes the alloc_sq and alloc_rq functions have already been called\n+ */\n+static void ice_mailbox_init_regs(struct ice_hw *hw)\n+{\n+\tstruct ice_ctl_q_info *cq = &hw->mailboxq;\n+\n+\tICE_CQ_INIT_REGS(cq, PF_MBX);\n+}\n+\n+\n+/**\n+ * ice_check_sq_alive\n+ * @hw: pointer to the hw struct\n+ * @cq: pointer to the specific Control queue\n+ *\n+ * Returns true if Queue is enabled else false.\n+ */\n+bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\t/* check both queue-length and queue-enable fields */\n+\tif (cq->sq.len && cq->sq.len_mask && cq->sq.len_ena_mask)\n+\t\treturn (rd32(hw, cq->sq.len) & (cq->sq.len_mask |\n+\t\t\t\t\t\tcq->sq.len_ena_mask)) ==\n+\t\t\t(cq->num_sq_entries | cq->sq.len_ena_mask);\n+\n+\treturn false;\n+}\n+\n+/**\n+ * ice_alloc_ctrlq_sq_ring - Allocate Control Transmit Queue (ATQ) rings\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ */\n+static enum ice_status\n+ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tsize_t size = cq->num_sq_entries * sizeof(struct ice_aq_desc);\n+\n+\tcq->sq.desc_buf.va = ice_alloc_dma_mem(hw, &cq->sq.desc_buf, size);\n+\tif (!cq->sq.desc_buf.va)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tcq->sq.cmd_buf = ice_calloc(hw, cq->num_sq_entries,\n+\t\t\t\t    sizeof(struct ice_sq_cd));\n+\tif (!cq->sq.cmd_buf) {\n+\t\tice_free_dma_mem(hw, &cq->sq.desc_buf);\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_alloc_ctrlq_rq_ring - Allocate Control Receive Queue (ARQ) rings\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ */\n+static enum ice_status\n+ice_alloc_ctrlq_rq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tsize_t size = cq->num_rq_entries * sizeof(struct ice_aq_desc);\n+\n+\tcq->rq.desc_buf.va = ice_alloc_dma_mem(hw, &cq->rq.desc_buf, size);\n+\tif (!cq->rq.desc_buf.va)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_free_cq_ring - Free control queue ring\n+ * @hw: pointer to the hardware structure\n+ * @ring: pointer to the specific control queue ring\n+ *\n+ * This assumes the posted buffers have already been cleaned\n+ * and de-allocated\n+ */\n+static void ice_free_cq_ring(struct ice_hw *hw, struct ice_ctl_q_ring *ring)\n+{\n+\tice_free_dma_mem(hw, &ring->desc_buf);\n+}\n+\n+/**\n+ * ice_alloc_rq_bufs - Allocate pre-posted buffers for the ARQ\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ */\n+static enum ice_status\n+ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tint i;\n+\n+\t/* We'll be allocating the buffer info memory first, then we can\n+\t * allocate the mapped buffers for the event processing\n+\t */\n+\tcq->rq.dma_head = ice_calloc(hw, cq->num_rq_entries,\n+\t\t\t\t     sizeof(cq->rq.desc_buf));\n+\tif (!cq->rq.dma_head)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\tcq->rq.r.rq_bi = (struct ice_dma_mem *)cq->rq.dma_head;\n+\n+\t/* allocate the mapped buffers */\n+\tfor (i = 0; i < cq->num_rq_entries; i++) {\n+\t\tstruct ice_aq_desc *desc;\n+\t\tstruct ice_dma_mem *bi;\n+\n+\t\tbi = &cq->rq.r.rq_bi[i];\n+\t\tbi->va = ice_alloc_dma_mem(hw, bi, cq->rq_buf_size);\n+\t\tif (!bi->va)\n+\t\t\tgoto unwind_alloc_rq_bufs;\n+\n+\t\t/* now configure the descriptors for use */\n+\t\tdesc = ICE_CTL_Q_DESC(cq->rq, i);\n+\n+\t\tdesc->flags = CPU_TO_LE16(ICE_AQ_FLAG_BUF);\n+\t\tif (cq->rq_buf_size > ICE_AQ_LG_BUF)\n+\t\t\tdesc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);\n+\t\tdesc->opcode = 0;\n+\t\t/* This is in accordance with Admin queue design, there is no\n+\t\t * register for buffer size configuration\n+\t\t */\n+\t\tdesc->datalen = CPU_TO_LE16(bi->size);\n+\t\tdesc->retval = 0;\n+\t\tdesc->cookie_high = 0;\n+\t\tdesc->cookie_low = 0;\n+\t\tdesc->params.generic.addr_high =\n+\t\t\tCPU_TO_LE32(ICE_HI_DWORD(bi->pa));\n+\t\tdesc->params.generic.addr_low =\n+\t\t\tCPU_TO_LE32(ICE_LO_DWORD(bi->pa));\n+\t\tdesc->params.generic.param0 = 0;\n+\t\tdesc->params.generic.param1 = 0;\n+\t}\n+\treturn ICE_SUCCESS;\n+\n+unwind_alloc_rq_bufs:\n+\t/* don't try to free the one that failed... */\n+\ti--;\n+\tfor (; i >= 0; i--)\n+\t\tice_free_dma_mem(hw, &cq->rq.r.rq_bi[i]);\n+\tice_free(hw, cq->rq.dma_head);\n+\n+\treturn ICE_ERR_NO_MEMORY;\n+}\n+\n+/**\n+ * ice_alloc_sq_bufs - Allocate empty buffer structs for the ATQ\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ */\n+static enum ice_status\n+ice_alloc_sq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tint i;\n+\n+\t/* No mapped memory needed yet, just the buffer info structures */\n+\tcq->sq.dma_head = ice_calloc(hw, cq->num_sq_entries,\n+\t\t\t\t     sizeof(cq->sq.desc_buf));\n+\tif (!cq->sq.dma_head)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\tcq->sq.r.sq_bi = (struct ice_dma_mem *)cq->sq.dma_head;\n+\n+\t/* allocate the mapped buffers */\n+\tfor (i = 0; i < cq->num_sq_entries; i++) {\n+\t\tstruct ice_dma_mem *bi;\n+\n+\t\tbi = &cq->sq.r.sq_bi[i];\n+\t\tbi->va = ice_alloc_dma_mem(hw, bi, cq->sq_buf_size);\n+\t\tif (!bi->va)\n+\t\t\tgoto unwind_alloc_sq_bufs;\n+\t}\n+\treturn ICE_SUCCESS;\n+\n+unwind_alloc_sq_bufs:\n+\t/* don't try to free the one that failed... */\n+\ti--;\n+\tfor (; i >= 0; i--)\n+\t\tice_free_dma_mem(hw, &cq->sq.r.sq_bi[i]);\n+\tice_free(hw, cq->sq.dma_head);\n+\n+\treturn ICE_ERR_NO_MEMORY;\n+}\n+\n+static enum ice_status\n+ice_cfg_cq_regs(struct ice_hw *hw, struct ice_ctl_q_ring *ring, u16 num_entries)\n+{\n+\t/* Clear Head and Tail */\n+\twr32(hw, ring->head, 0);\n+\twr32(hw, ring->tail, 0);\n+\n+\t/* set starting point */\n+\twr32(hw, ring->len, (num_entries | ring->len_ena_mask));\n+\twr32(hw, ring->bal, ICE_LO_DWORD(ring->desc_buf.pa));\n+\twr32(hw, ring->bah, ICE_HI_DWORD(ring->desc_buf.pa));\n+\n+\t/* Check one register to verify that config was applied */\n+\tif (rd32(hw, ring->bal) != ICE_LO_DWORD(ring->desc_buf.pa))\n+\t\treturn ICE_ERR_AQ_ERROR;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_cfg_sq_regs - configure Control ATQ registers\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ *\n+ * Configure base address and length registers for the transmit queue\n+ */\n+static enum ice_status\n+ice_cfg_sq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\treturn ice_cfg_cq_regs(hw, &cq->sq, cq->num_sq_entries);\n+}\n+\n+/**\n+ * ice_cfg_rq_regs - configure Control ARQ register\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ *\n+ * Configure base address and length registers for the receive (event q)\n+ */\n+static enum ice_status\n+ice_cfg_rq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_cfg_cq_regs(hw, &cq->rq, cq->num_rq_entries);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Update tail in the HW to post pre-allocated buffers */\n+\twr32(hw, cq->rq.tail, (u32)(cq->num_rq_entries - 1));\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_init_sq - main initialization routine for Control ATQ\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ *\n+ * This is the main initialization routine for the Control Send Queue\n+ * Prior to calling this function, drivers *MUST* set the following fields\n+ * in the cq->structure:\n+ *     - cq->num_sq_entries\n+ *     - cq->sq_buf_size\n+ *\n+ * Do *NOT* hold the lock when calling this as the memory allocation routines\n+ * called are not going to be atomic context safe\n+ */\n+static enum ice_status ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tenum ice_status ret_code;\n+\n+\tif (cq->sq.count > 0) {\n+\t\t/* queue already initialized */\n+\t\tret_code = ICE_ERR_NOT_READY;\n+\t\tgoto init_ctrlq_exit;\n+\t}\n+\n+\t/* verify input for valid configuration */\n+\tif (!cq->num_sq_entries || !cq->sq_buf_size) {\n+\t\tret_code = ICE_ERR_CFG;\n+\t\tgoto init_ctrlq_exit;\n+\t}\n+\n+\tcq->sq.next_to_use = 0;\n+\tcq->sq.next_to_clean = 0;\n+\n+\t/* allocate the ring memory */\n+\tret_code = ice_alloc_ctrlq_sq_ring(hw, cq);\n+\tif (ret_code)\n+\t\tgoto init_ctrlq_exit;\n+\n+\t/* allocate buffers in the rings */\n+\tret_code = ice_alloc_sq_bufs(hw, cq);\n+\tif (ret_code)\n+\t\tgoto init_ctrlq_free_rings;\n+\n+\t/* initialize base registers */\n+\tret_code = ice_cfg_sq_regs(hw, cq);\n+\tif (ret_code)\n+\t\tgoto init_ctrlq_free_rings;\n+\n+\t/* success! */\n+\tcq->sq.count = cq->num_sq_entries;\n+\tgoto init_ctrlq_exit;\n+\n+init_ctrlq_free_rings:\n+\tice_free_cq_ring(hw, &cq->sq);\n+\n+init_ctrlq_exit:\n+\treturn ret_code;\n+}\n+\n+/**\n+ * ice_init_rq - initialize ARQ\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ *\n+ * The main initialization routine for the Admin Receive (Event) Queue.\n+ * Prior to calling this function, drivers *MUST* set the following fields\n+ * in the cq->structure:\n+ *     - cq->num_rq_entries\n+ *     - cq->rq_buf_size\n+ *\n+ * Do *NOT* hold the lock when calling this as the memory allocation routines\n+ * called are not going to be atomic context safe\n+ */\n+static enum ice_status ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tenum ice_status ret_code;\n+\n+\tif (cq->rq.count > 0) {\n+\t\t/* queue already initialized */\n+\t\tret_code = ICE_ERR_NOT_READY;\n+\t\tgoto init_ctrlq_exit;\n+\t}\n+\n+\t/* verify input for valid configuration */\n+\tif (!cq->num_rq_entries || !cq->rq_buf_size) {\n+\t\tret_code = ICE_ERR_CFG;\n+\t\tgoto init_ctrlq_exit;\n+\t}\n+\n+\tcq->rq.next_to_use = 0;\n+\tcq->rq.next_to_clean = 0;\n+\n+\t/* allocate the ring memory */\n+\tret_code = ice_alloc_ctrlq_rq_ring(hw, cq);\n+\tif (ret_code)\n+\t\tgoto init_ctrlq_exit;\n+\n+\t/* allocate buffers in the rings */\n+\tret_code = ice_alloc_rq_bufs(hw, cq);\n+\tif (ret_code)\n+\t\tgoto init_ctrlq_free_rings;\n+\n+\t/* initialize base registers */\n+\tret_code = ice_cfg_rq_regs(hw, cq);\n+\tif (ret_code)\n+\t\tgoto init_ctrlq_free_rings;\n+\n+\t/* success! */\n+\tcq->rq.count = cq->num_rq_entries;\n+\tgoto init_ctrlq_exit;\n+\n+init_ctrlq_free_rings:\n+\tice_free_cq_ring(hw, &cq->rq);\n+\n+init_ctrlq_exit:\n+\treturn ret_code;\n+}\n+\n+#define ICE_FREE_CQ_BUFS(hw, qi, ring)\t\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\t\\\n+\tint i;\t\t\t\t\t\t\t\t\\\n+\t/* free descriptors */\t\t\t\t\t\t\\\n+\tfor (i = 0; i < (qi)->num_##ring##_entries; i++)\t\t\\\n+\t\tif ((qi)->ring.r.ring##_bi[i].pa)\t\t\t\\\n+\t\t\tice_free_dma_mem((hw),\t\t\t\t\\\n+\t\t\t\t\t &(qi)->ring.r.ring##_bi[i]);\t\\\n+\t/* free the buffer info list */\t\t\t\t\t\\\n+\tif ((qi)->ring.cmd_buf)\t\t\t\t\t\t\\\n+\t\tice_free(hw, (qi)->ring.cmd_buf);\t\t\t\\\n+\t/* free dma head */\t\t\t\t\t\t\\\n+\tice_free(hw, (qi)->ring.dma_head);\t\t\t\t\\\n+} while (0)\n+\n+/**\n+ * ice_shutdown_sq - shutdown the Control ATQ\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ *\n+ * The main shutdown routine for the Control Transmit Queue\n+ */\n+static enum ice_status\n+ice_shutdown_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tenum ice_status ret_code = ICE_SUCCESS;\n+\n+\tice_acquire_lock(&cq->sq_lock);\n+\n+\tif (!cq->sq.count) {\n+\t\tret_code = ICE_ERR_NOT_READY;\n+\t\tgoto shutdown_sq_out;\n+\t}\n+\n+\t/* Stop firmware AdminQ processing */\n+\twr32(hw, cq->sq.head, 0);\n+\twr32(hw, cq->sq.tail, 0);\n+\twr32(hw, cq->sq.len, 0);\n+\twr32(hw, cq->sq.bal, 0);\n+\twr32(hw, cq->sq.bah, 0);\n+\n+\tcq->sq.count = 0;\t/* to indicate uninitialized queue */\n+\n+\t/* free ring buffers and the ring itself */\n+\tICE_FREE_CQ_BUFS(hw, cq, sq);\n+\tice_free_cq_ring(hw, &cq->sq);\n+\n+shutdown_sq_out:\n+\tice_release_lock(&cq->sq_lock);\n+\treturn ret_code;\n+}\n+\n+/**\n+ * ice_aq_ver_check - Check the reported AQ API version.\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Checks if the driver should load on a given AQ API version.\n+ *\n+ * Return: 'true' iff the driver should attempt to load. 'false' otherwise.\n+ */\n+static bool ice_aq_ver_check(struct ice_hw *hw)\n+{\n+\tif (hw->api_maj_ver > EXP_FW_API_VER_MAJOR) {\n+\t\t/* Major API version is newer than expected, don't load */\n+\t\tice_warn(hw, \"The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\\n\");\n+\t\treturn false;\n+\t} else if (hw->api_maj_ver == EXP_FW_API_VER_MAJOR) {\n+\t\tif (hw->api_min_ver > (EXP_FW_API_VER_MINOR + 2))\n+\t\t\tice_info(hw, \"The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\\n\");\n+\t\telse if ((hw->api_min_ver + 2) < EXP_FW_API_VER_MINOR)\n+\t\t\tice_info(hw, \"The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\\n\");\n+\t} else {\n+\t\t/* Major API version is older than expected, log a warning */\n+\t\tice_info(hw, \"The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\\n\");\n+\t}\n+\treturn true;\n+}\n+\n+/**\n+ * ice_shutdown_rq - shutdown Control ARQ\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ *\n+ * The main shutdown routine for the Control Receive Queue\n+ */\n+static enum ice_status\n+ice_shutdown_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tenum ice_status ret_code = ICE_SUCCESS;\n+\n+\tice_acquire_lock(&cq->rq_lock);\n+\n+\tif (!cq->rq.count) {\n+\t\tret_code = ICE_ERR_NOT_READY;\n+\t\tgoto shutdown_rq_out;\n+\t}\n+\n+\t/* Stop Control Queue processing */\n+\twr32(hw, cq->rq.head, 0);\n+\twr32(hw, cq->rq.tail, 0);\n+\twr32(hw, cq->rq.len, 0);\n+\twr32(hw, cq->rq.bal, 0);\n+\twr32(hw, cq->rq.bah, 0);\n+\n+\t/* set rq.count to 0 to indicate uninitialized queue */\n+\tcq->rq.count = 0;\n+\n+\t/* free ring buffers and the ring itself */\n+\tICE_FREE_CQ_BUFS(hw, cq, rq);\n+\tice_free_cq_ring(hw, &cq->rq);\n+\n+shutdown_rq_out:\n+\tice_release_lock(&cq->rq_lock);\n+\treturn ret_code;\n+}\n+\n+\n+/**\n+ * ice_init_check_adminq - Check version for Admin Queue to know if its alive\n+ * @hw: pointer to the hardware structure\n+ */\n+static enum ice_status ice_init_check_adminq(struct ice_hw *hw)\n+{\n+\tstruct ice_ctl_q_info *cq = &hw->adminq;\n+\tenum ice_status status;\n+\n+\n+\tstatus = ice_aq_get_fw_ver(hw, NULL);\n+\tif (status)\n+\t\tgoto init_ctrlq_free_rq;\n+\n+\n+\tif (!ice_aq_ver_check(hw)) {\n+\t\tstatus = ICE_ERR_FW_API_VER;\n+\t\tgoto init_ctrlq_free_rq;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+\n+init_ctrlq_free_rq:\n+\tif (cq->rq.count) {\n+\t\tice_shutdown_rq(hw, cq);\n+\t\tice_destroy_lock(&cq->rq_lock);\n+\t}\n+\tif (cq->sq.count) {\n+\t\tice_shutdown_sq(hw, cq);\n+\t\tice_destroy_lock(&cq->sq_lock);\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_init_ctrlq - main initialization routine for any control Queue\n+ * @hw: pointer to the hardware structure\n+ * @q_type: specific Control queue type\n+ *\n+ * Prior to calling this function, drivers *MUST* set the following fields\n+ * in the cq->structure:\n+ *     - cq->num_sq_entries\n+ *     - cq->num_rq_entries\n+ *     - cq->rq_buf_size\n+ *     - cq->sq_buf_size\n+ */\n+static enum ice_status ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)\n+{\n+\tstruct ice_ctl_q_info *cq;\n+\tenum ice_status ret_code;\n+\n+\tswitch (q_type) {\n+\tcase ICE_CTL_Q_ADMIN:\n+\t\tice_adminq_init_regs(hw);\n+\t\tcq = &hw->adminq;\n+\t\tbreak;\n+\tcase ICE_CTL_Q_MAILBOX:\n+\t\tice_mailbox_init_regs(hw);\n+\t\tcq = &hw->mailboxq;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\tcq->qtype = q_type;\n+\n+\t/* verify input for valid configuration */\n+\tif (!cq->num_rq_entries || !cq->num_sq_entries ||\n+\t    !cq->rq_buf_size || !cq->sq_buf_size) {\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\tice_init_lock(&cq->sq_lock);\n+\tice_init_lock(&cq->rq_lock);\n+\n+\t/* setup SQ command write back timeout */\n+\tcq->sq_cmd_timeout = ICE_CTL_Q_SQ_CMD_TIMEOUT;\n+\n+\t/* allocate the ATQ */\n+\tret_code = ice_init_sq(hw, cq);\n+\tif (ret_code)\n+\t\tgoto init_ctrlq_destroy_locks;\n+\n+\t/* allocate the ARQ */\n+\tret_code = ice_init_rq(hw, cq);\n+\tif (ret_code)\n+\t\tgoto init_ctrlq_free_sq;\n+\n+\t/* success! */\n+\treturn ICE_SUCCESS;\n+\n+init_ctrlq_free_sq:\n+\tice_shutdown_sq(hw, cq);\n+init_ctrlq_destroy_locks:\n+\tice_destroy_lock(&cq->sq_lock);\n+\tice_destroy_lock(&cq->rq_lock);\n+\treturn ret_code;\n+}\n+\n+/**\n+ * ice_init_all_ctrlq - main initialization routine for all control queues\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Prior to calling this function, drivers *MUST* set the following fields\n+ * in the cq->structure for all control queues:\n+ *     - cq->num_sq_entries\n+ *     - cq->num_rq_entries\n+ *     - cq->rq_buf_size\n+ *     - cq->sq_buf_size\n+ */\n+enum ice_status ice_init_all_ctrlq(struct ice_hw *hw)\n+{\n+\tenum ice_status ret_code;\n+\n+\n+\t/* Init FW admin queue */\n+\tret_code = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN);\n+\tif (ret_code)\n+\t\treturn ret_code;\n+\n+\tret_code = ice_init_check_adminq(hw);\n+\tif (ret_code)\n+\t\treturn ret_code;\n+\t/* Init Mailbox queue */\n+\treturn ice_init_ctrlq(hw, ICE_CTL_Q_MAILBOX);\n+}\n+\n+/**\n+ * ice_shutdown_ctrlq - shutdown routine for any control queue\n+ * @hw: pointer to the hardware structure\n+ * @q_type: specific Control queue type\n+ */\n+static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)\n+{\n+\tstruct ice_ctl_q_info *cq;\n+\n+\tswitch (q_type) {\n+\tcase ICE_CTL_Q_ADMIN:\n+\t\tcq = &hw->adminq;\n+\t\tif (ice_check_sq_alive(hw, cq))\n+\t\t\tice_aq_q_shutdown(hw, true);\n+\t\tbreak;\n+\tcase ICE_CTL_Q_MAILBOX:\n+\t\tcq = &hw->mailboxq;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tif (cq->sq.count) {\n+\t\tice_shutdown_sq(hw, cq);\n+\t\tice_destroy_lock(&cq->sq_lock);\n+\t}\n+\tif (cq->rq.count) {\n+\t\tice_shutdown_rq(hw, cq);\n+\t\tice_destroy_lock(&cq->rq_lock);\n+\t}\n+}\n+\n+/**\n+ * ice_shutdown_all_ctrlq - shutdown routine for all control queues\n+ * @hw: pointer to the hardware structure\n+ */\n+void ice_shutdown_all_ctrlq(struct ice_hw *hw)\n+{\n+\t/* Shutdown FW admin queue */\n+\tice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);\n+\t/* Shutdown PF-VF Mailbox */\n+\tice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX);\n+}\n+\n+/**\n+ * ice_clean_sq - cleans Admin send queue (ATQ)\n+ * @hw: pointer to the hardware structure\n+ * @cq: pointer to the specific Control queue\n+ *\n+ * returns the number of free desc\n+ */\n+static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\tstruct ice_ctl_q_ring *sq = &cq->sq;\n+\tu16 ntc = sq->next_to_clean;\n+\tstruct ice_sq_cd *details;\n+#if 0\n+\tstruct ice_aq_desc desc_cb;\n+#endif\n+\tstruct ice_aq_desc *desc;\n+\n+\tdesc = ICE_CTL_Q_DESC(*sq, ntc);\n+\tdetails = ICE_CTL_Q_DETAILS(*sq, ntc);\n+\n+\twhile (rd32(hw, cq->sq.head) != ntc) {\n+\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t  \"ntc %d head %d.\\n\", ntc, rd32(hw, cq->sq.head));\n+#if 0\n+\t\tif (details->callback) {\n+\t\t\tICE_CTL_Q_CALLBACK cb_func =\n+\t\t\t\t(ICE_CTL_Q_CALLBACK)details->callback;\n+\t\t\tice_memcpy(&desc_cb, desc, sizeof(desc_cb),\n+\t\t\t\t   ICE_DMA_TO_DMA);\n+\t\t\tcb_func(hw, &desc_cb);\n+\t\t}\n+#endif\n+\t\tice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);\n+\t\tice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);\n+\t\tntc++;\n+\t\tif (ntc == sq->count)\n+\t\t\tntc = 0;\n+\t\tdesc = ICE_CTL_Q_DESC(*sq, ntc);\n+\t\tdetails = ICE_CTL_Q_DETAILS(*sq, ntc);\n+\t}\n+\n+\tsq->next_to_clean = ntc;\n+\n+\treturn ICE_CTL_Q_DESC_UNUSED(sq);\n+}\n+\n+/**\n+ * ice_sq_done - check if FW has processed the Admin Send Queue (ATQ)\n+ * @hw: pointer to the hw struct\n+ * @cq: pointer to the specific Control queue\n+ *\n+ * Returns true if the firmware has processed all descriptors on the\n+ * admin send queue. Returns false if there are still requests pending.\n+ */\n+static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)\n+{\n+\t/* AQ designers suggest use of head for better\n+\t * timing reliability than DD bit\n+\t */\n+\treturn rd32(hw, cq->sq.head) == cq->sq.next_to_use;\n+}\n+\n+/**\n+ * ice_sq_send_cmd - send command to Control Queue (ATQ)\n+ * @hw: pointer to the hw struct\n+ * @cq: pointer to the specific Control queue\n+ * @desc: prefilled descriptor describing the command (non DMA mem)\n+ * @buf: buffer to use for indirect commands (or NULL for direct commands)\n+ * @buf_size: size of buffer for indirect commands (or 0 for direct commands)\n+ * @cd: pointer to command details structure\n+ *\n+ * This is the main send command routine for the ATQ. It runs the queue,\n+ * cleans the queue, etc.\n+ */\n+enum ice_status\n+ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n+\t\tstruct ice_aq_desc *desc, void *buf, u16 buf_size,\n+\t\tstruct ice_sq_cd *cd)\n+{\n+\tstruct ice_dma_mem *dma_buf = NULL;\n+\tstruct ice_aq_desc *desc_on_ring;\n+\tbool cmd_completed = false;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_sq_cd *details;\n+\tu32 total_delay = 0;\n+\tu16 retval = 0;\n+\tu32 val = 0;\n+\n+\t/* if reset is in progress return a soft error */\n+\tif (hw->reset_ongoing)\n+\t\treturn ICE_ERR_RESET_ONGOING;\n+\tice_acquire_lock(&cq->sq_lock);\n+\n+\tcq->sq_last_status = ICE_AQ_RC_OK;\n+\n+\tif (!cq->sq.count) {\n+\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t  \"Control Send queue not initialized.\\n\");\n+\t\tstatus = ICE_ERR_AQ_EMPTY;\n+\t\tgoto sq_send_command_error;\n+\t}\n+\n+\tif ((buf && !buf_size) || (!buf && buf_size)) {\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto sq_send_command_error;\n+\t}\n+\n+\tif (buf) {\n+\t\tif (buf_size > cq->sq_buf_size) {\n+\t\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t\t  \"Invalid buffer size for Control Send queue: %d.\\n\",\n+\t\t\t\t  buf_size);\n+\t\t\tstatus = ICE_ERR_INVAL_SIZE;\n+\t\t\tgoto sq_send_command_error;\n+\t\t}\n+\n+\t\tdesc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_BUF);\n+\t\tif (buf_size > ICE_AQ_LG_BUF)\n+\t\t\tdesc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);\n+\t}\n+\n+\tval = rd32(hw, cq->sq.head);\n+\tif (val >= cq->num_sq_entries) {\n+\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t  \"head overrun at %d in the Control Send Queue ring\\n\",\n+\t\t\t  val);\n+\t\tstatus = ICE_ERR_AQ_EMPTY;\n+\t\tgoto sq_send_command_error;\n+\t}\n+\n+\tdetails = ICE_CTL_Q_DETAILS(cq->sq, cq->sq.next_to_use);\n+\tif (cd)\n+\t\t*details = *cd;\n+#if 0\n+\t\t/* FIXME: if/when this block gets enabled (when the #if 0\n+\t\t * is removed), add braces to both branches of the surrounding\n+\t\t * conditional expression. The braces have been removed to\n+\t\t * prevent checkpatch complaining.\n+\t\t */\n+\n+\t\t/* If the command details are defined copy the cookie. The\n+\t\t * CPU_TO_LE32 is not needed here because the data is ignored\n+\t\t * by the FW, only used by the driver\n+\t\t */\n+\t\tif (details->cookie) {\n+\t\t\tdesc->cookie_high =\n+\t\t\t\tCPU_TO_LE32(ICE_HI_DWORD(details->cookie));\n+\t\t\tdesc->cookie_low =\n+\t\t\t\tCPU_TO_LE32(ICE_LO_DWORD(details->cookie));\n+\t\t}\n+#endif\n+\telse\n+\t\tice_memset(details, 0, sizeof(*details), ICE_NONDMA_MEM);\n+#if 0\n+\t/* clear requested flags and then set additional flags if defined */\n+\tdesc->flags &= ~CPU_TO_LE16(details->flags_dis);\n+\tdesc->flags |= CPU_TO_LE16(details->flags_ena);\n+\n+\tif (details->postpone && !details->async) {\n+\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t  \"Async flag not set along with postpone flag\\n\");\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto sq_send_command_error;\n+\t}\n+#endif\n+\n+\t/* Call clean and check queue available function to reclaim the\n+\t * descriptors that were processed by FW/MBX; the function returns the\n+\t * number of desc available. The clean function called here could be\n+\t * called in a separate thread in case of asynchronous completions.\n+\t */\n+\tif (ice_clean_sq(hw, cq) == 0) {\n+\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t  \"Error: Control Send Queue is full.\\n\");\n+\t\tstatus = ICE_ERR_AQ_FULL;\n+\t\tgoto sq_send_command_error;\n+\t}\n+\n+\t/* initialize the temp desc pointer with the right desc */\n+\tdesc_on_ring = ICE_CTL_Q_DESC(cq->sq, cq->sq.next_to_use);\n+\n+\t/* if the desc is available copy the temp desc to the right place */\n+\tice_memcpy(desc_on_ring, desc, sizeof(*desc_on_ring),\n+\t\t   ICE_NONDMA_TO_DMA);\n+\n+\t/* if buf is not NULL assume indirect command */\n+\tif (buf) {\n+\t\tdma_buf = &cq->sq.r.sq_bi[cq->sq.next_to_use];\n+\t\t/* copy the user buf into the respective DMA buf */\n+\t\tice_memcpy(dma_buf->va, buf, buf_size, ICE_NONDMA_TO_DMA);\n+\t\tdesc_on_ring->datalen = CPU_TO_LE16(buf_size);\n+\n+\t\t/* Update the address values in the desc with the pa value\n+\t\t * for respective buffer\n+\t\t */\n+\t\tdesc_on_ring->params.generic.addr_high =\n+\t\t\tCPU_TO_LE32(ICE_HI_DWORD(dma_buf->pa));\n+\t\tdesc_on_ring->params.generic.addr_low =\n+\t\t\tCPU_TO_LE32(ICE_LO_DWORD(dma_buf->pa));\n+\t}\n+\n+\t/* Debug desc and buffer */\n+\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t  \"ATQ: Control Send queue desc and buffer:\\n\");\n+\n+\tice_debug_cq(hw, ICE_DBG_AQ_CMD, (void *)desc_on_ring, buf, buf_size);\n+\n+\n+\t(cq->sq.next_to_use)++;\n+\tif (cq->sq.next_to_use == cq->sq.count)\n+\t\tcq->sq.next_to_use = 0;\n+#if 0\n+\t/* FIXME - handle this case? */\n+\tif (!details->postpone)\n+#endif\n+\twr32(hw, cq->sq.tail, cq->sq.next_to_use);\n+\n+#if 0\n+\t/* if command details are not defined or async flag is not set,\n+\t * we need to wait for desc write back\n+\t */\n+\tif (!details->async && !details->postpone) {\n+\t\t/* FIXME - handle this case? */\n+\t}\n+#endif\n+\tdo {\n+\t\tif (ice_sq_done(hw, cq))\n+\t\t\tbreak;\n+\n+\t\tice_msec_delay(1, false);\n+\t\ttotal_delay++;\n+\t} while (total_delay < cq->sq_cmd_timeout);\n+\n+\t/* if ready, copy the desc back to temp */\n+\tif (ice_sq_done(hw, cq)) {\n+\t\tice_memcpy(desc, desc_on_ring, sizeof(*desc),\n+\t\t\t   ICE_DMA_TO_NONDMA);\n+\t\tif (buf) {\n+\t\t\t/* get returned length to copy */\n+\t\t\tu16 copy_size = LE16_TO_CPU(desc->datalen);\n+\n+\t\t\tif (copy_size > buf_size) {\n+\t\t\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t\t\t  \"Return len %d > than buf len %d\\n\",\n+\t\t\t\t\t  copy_size, buf_size);\n+\t\t\t\tstatus = ICE_ERR_AQ_ERROR;\n+\t\t\t} else {\n+\t\t\t\tice_memcpy(buf, dma_buf->va, copy_size,\n+\t\t\t\t\t   ICE_DMA_TO_NONDMA);\n+\t\t\t}\n+\t\t}\n+\t\tretval = LE16_TO_CPU(desc->retval);\n+\t\tif (retval) {\n+\t\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t\t  \"Control Send Queue command completed with error 0x%x\\n\",\n+\t\t\t\t  retval);\n+\n+\t\t\t/* strip off FW internal code */\n+\t\t\tretval &= 0xff;\n+\t\t}\n+\t\tcmd_completed = true;\n+\t\tif (!status && retval != ICE_AQ_RC_OK)\n+\t\t\tstatus = ICE_ERR_AQ_ERROR;\n+\t\tcq->sq_last_status = (enum ice_aq_err)retval;\n+\t}\n+\n+\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t  \"ATQ: desc and buffer writeback:\\n\");\n+\n+\tice_debug_cq(hw, ICE_DBG_AQ_CMD, (void *)desc, buf, buf_size);\n+\n+\n+\t/* save writeback AQ if requested */\n+\tif (details->wb_desc)\n+\t\tice_memcpy(details->wb_desc, desc_on_ring,\n+\t\t\t   sizeof(*details->wb_desc), ICE_DMA_TO_NONDMA);\n+\n+\t/* update the error if time out occurred */\n+\tif (!cmd_completed) {\n+#if 0\n+\t    (!details->async && !details->postpone)) {\n+#endif\n+\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t  \"Control Send Queue Writeback timeout.\\n\");\n+\t\tstatus = ICE_ERR_AQ_TIMEOUT;\n+\t}\n+\n+sq_send_command_error:\n+\tice_release_lock(&cq->sq_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_fill_dflt_direct_cmd_desc - AQ descriptor helper function\n+ * @desc: pointer to the temp descriptor (non DMA mem)\n+ * @opcode: the opcode can be used to decide which flags to turn off or on\n+ *\n+ * Fill the desc with default values\n+ */\n+void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode)\n+{\n+\t/* zero out the desc */\n+\tice_memset(desc, 0, sizeof(*desc), ICE_NONDMA_MEM);\n+\tdesc->opcode = CPU_TO_LE16(opcode);\n+\tdesc->flags = CPU_TO_LE16(ICE_AQ_FLAG_SI);\n+}\n+\n+/**\n+ * ice_clean_rq_elem\n+ * @hw: pointer to the hw struct\n+ * @cq: pointer to the specific Control queue\n+ * @e: event info from the receive descriptor, includes any buffers\n+ * @pending: number of events that could be left to process\n+ *\n+ * This function cleans one Admin Receive Queue element and returns\n+ * the contents through e. It can also return how many events are\n+ * left to process through 'pending'.\n+ */\n+enum ice_status\n+ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n+\t\t  struct ice_rq_event_info *e, u16 *pending)\n+{\n+\tu16 ntc = cq->rq.next_to_clean;\n+\tenum ice_status ret_code = ICE_SUCCESS;\n+\tstruct ice_aq_desc *desc;\n+\tstruct ice_dma_mem *bi;\n+\tu16 desc_idx;\n+\tu16 datalen;\n+\tu16 flags;\n+\tu16 ntu;\n+\n+\t/* pre-clean the event info */\n+\tice_memset(&e->desc, 0, sizeof(e->desc), ICE_NONDMA_MEM);\n+\n+\t/* take the lock before we start messing with the ring */\n+\tice_acquire_lock(&cq->rq_lock);\n+\n+\tif (!cq->rq.count) {\n+\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t  \"Control Receive queue not initialized.\\n\");\n+\t\tret_code = ICE_ERR_AQ_EMPTY;\n+\t\tgoto clean_rq_elem_err;\n+\t}\n+\n+\t/* set next_to_use to head */\n+\tntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);\n+\n+\tif (ntu == ntc) {\n+\t\t/* nothing to do - shouldn't need to update ring's values */\n+\t\tret_code = ICE_ERR_AQ_NO_WORK;\n+\t\tgoto clean_rq_elem_out;\n+\t}\n+\n+\t/* now clean the next descriptor */\n+\tdesc = ICE_CTL_Q_DESC(cq->rq, ntc);\n+\tdesc_idx = ntc;\n+\n+\tcq->rq_last_status = (enum ice_aq_err)LE16_TO_CPU(desc->retval);\n+\tflags = LE16_TO_CPU(desc->flags);\n+\tif (flags & ICE_AQ_FLAG_ERR) {\n+\t\tret_code = ICE_ERR_AQ_ERROR;\n+\t\tice_debug(hw, ICE_DBG_AQ_MSG,\n+\t\t\t  \"Control Receive Queue Event received with error 0x%x\\n\",\n+\t\t\t  cq->rq_last_status);\n+\t}\n+\tice_memcpy(&e->desc, desc, sizeof(e->desc), ICE_DMA_TO_NONDMA);\n+\tdatalen = LE16_TO_CPU(desc->datalen);\n+\te->msg_len = min(datalen, e->buf_len);\n+\tif (e->msg_buf && e->msg_len)\n+\t\tice_memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va,\n+\t\t\t   e->msg_len, ICE_DMA_TO_NONDMA);\n+\n+\tice_debug(hw, ICE_DBG_AQ_MSG, \"ARQ: desc and buffer:\\n\");\n+\n+\tice_debug_cq(hw, ICE_DBG_AQ_CMD, (void *)desc, e->msg_buf,\n+\t\t     cq->rq_buf_size);\n+\n+\n+\t/* Restore the original datalen and buffer address in the desc,\n+\t * FW updates datalen to indicate the event message size\n+\t */\n+\tbi = &cq->rq.r.rq_bi[ntc];\n+\tice_memset(desc, 0, sizeof(*desc), ICE_DMA_MEM);\n+\n+\tdesc->flags = CPU_TO_LE16(ICE_AQ_FLAG_BUF);\n+\tif (cq->rq_buf_size > ICE_AQ_LG_BUF)\n+\t\tdesc->flags |= CPU_TO_LE16(ICE_AQ_FLAG_LB);\n+\tdesc->datalen = CPU_TO_LE16(bi->size);\n+\tdesc->params.generic.addr_high = CPU_TO_LE32(ICE_HI_DWORD(bi->pa));\n+\tdesc->params.generic.addr_low = CPU_TO_LE32(ICE_LO_DWORD(bi->pa));\n+\n+\t/* set tail = the last cleaned desc index. */\n+\twr32(hw, cq->rq.tail, ntc);\n+\t/* ntc is updated to tail + 1 */\n+\tntc++;\n+\tif (ntc == cq->num_rq_entries)\n+\t\tntc = 0;\n+\tcq->rq.next_to_clean = ntc;\n+\tcq->rq.next_to_use = ntu;\n+\n+#if 0\n+\tice_nvmupd_check_wait_event(hw, LE16_TO_CPU(e->desc.opcode));\n+#endif\n+clean_rq_elem_out:\n+\t/* Set pending if needed, unlock and return */\n+\tif (pending) {\n+\t\t/* re-read HW head to calculate actual pending messages */\n+\t\tntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);\n+\t\t*pending = (u16)((ntc > ntu ? cq->rq.count : 0) + (ntu - ntc));\n+\t}\n+clean_rq_elem_err:\n+\tice_release_lock(&cq->rq_lock);\n+\n+\treturn ret_code;\n+}\ndiff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h\nnew file mode 100644\nindex 0000000..db2db93\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_controlq.h\n@@ -0,0 +1,97 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_CONTROLQ_H_\n+#define _ICE_CONTROLQ_H_\n+\n+#include \"ice_adminq_cmd.h\"\n+\n+\n+/* Maximum buffer lengths for all control queue types */\n+#define ICE_AQ_MAX_BUF_LEN 4096\n+#define ICE_MBXQ_MAX_BUF_LEN 4096\n+\n+#define ICE_CTL_Q_DESC(R, i) \\\n+\t(&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))\n+\n+#define ICE_CTL_Q_DESC_UNUSED(R) \\\n+\t(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \\\n+\t      (R)->next_to_clean - (R)->next_to_use - 1)\n+\n+/* Defines that help manage the driver vs FW API checks.\n+ * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.\n+ */\n+#define EXP_FW_API_VER_BRANCH\t\t0x00\n+#define EXP_FW_API_VER_MAJOR\t\t0x01\n+#define EXP_FW_API_VER_MINOR\t\t0x03\n+\n+/* Different control queue types: These are mainly for SW consumption. */\n+enum ice_ctl_q {\n+\tICE_CTL_Q_UNKNOWN = 0,\n+\tICE_CTL_Q_ADMIN,\n+\tICE_CTL_Q_MAILBOX,\n+};\n+\n+/* Control Queue default settings */\n+#define ICE_CTL_Q_SQ_CMD_TIMEOUT\t250  /* msecs */\n+\n+struct ice_ctl_q_ring {\n+\tvoid *dma_head;\t\t\t/* Virtual address to dma head */\n+\tstruct ice_dma_mem desc_buf;\t/* descriptor ring memory */\n+\tvoid *cmd_buf;\t\t\t/* command buffer memory */\n+\n+\tunion {\n+\t\tstruct ice_dma_mem *sq_bi;\n+\t\tstruct ice_dma_mem *rq_bi;\n+\t} r;\n+\n+\tu16 count;\t\t/* Number of descriptors */\n+\n+\t/* used for interrupt processing */\n+\tu16 next_to_use;\n+\tu16 next_to_clean;\n+\n+\t/* used for queue tracking */\n+\tu32 head;\n+\tu32 tail;\n+\tu32 len;\n+\tu32 bah;\n+\tu32 bal;\n+\tu32 len_mask;\n+\tu32 len_ena_mask;\n+\tu32 head_mask;\n+};\n+\n+/* sq transaction details */\n+struct ice_sq_cd {\n+\tstruct ice_aq_desc *wb_desc;\n+};\n+\n+#define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))\n+\n+/* rq event information */\n+struct ice_rq_event_info {\n+\tstruct ice_aq_desc desc;\n+\tu16 msg_len;\n+\tu16 buf_len;\n+\tu8 *msg_buf;\n+};\n+\n+/* Control Queue information */\n+struct ice_ctl_q_info {\n+\tenum ice_ctl_q qtype;\n+\tstruct ice_ctl_q_ring rq;\t/* receive queue */\n+\tstruct ice_ctl_q_ring sq;\t/* send queue */\n+\tu32 sq_cmd_timeout;\t\t/* send queue cmd write back timeout */\n+\tu16 num_rq_entries;\t\t/* receive queue depth */\n+\tu16 num_sq_entries;\t\t/* send queue depth */\n+\tu16 rq_buf_size;\t\t/* receive queue buffer size */\n+\tu16 sq_buf_size;\t\t/* send queue buffer size */\n+\tstruct ice_lock sq_lock;\t\t/* Send queue lock */\n+\tstruct ice_lock rq_lock;\t\t/* Receive queue lock */\n+\tenum ice_aq_err sq_last_status;\t/* last status on send queue */\n+\tenum ice_aq_err rq_last_status;\t/* last status on receive queue */\n+};\n+\n+#endif /* _ICE_CONTROLQ_H_ */\ndiff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h\nnew file mode 100644\nindex 0000000..87f17ab\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_devids.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_DEVIDS_H_\n+#define _ICE_DEVIDS_H_\n+\n+\n+/* Device IDs */\n+/* Intel(R) Ethernet Controller E810-C for backplane */\n+#define ICE_DEV_ID_E810C_BACKPLANE\t0x1591\n+/* Intel(R) Ethernet Controller E810-C for QSFP */\n+#define ICE_DEV_ID_E810C_QSFP\t\t0x1592\n+/* Intel(R) Ethernet Controller E810-C for SFP */\n+#define ICE_DEV_ID_E810C_SFP\t\t0x1593\n+\n+#endif /* _ICE_DEVIDS_H_ */\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nnew file mode 100644\nindex 0000000..934cb26\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -0,0 +1,5 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_common.h\"\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h\nnew file mode 100644\nindex 0000000..f52f7a4\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_flex_pipe.h\n@@ -0,0 +1,83 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_FLEX_PIPE_H_\n+#define _ICE_FLEX_PIPE_H_\n+\n+#include \"ice_type.h\"\n+\n+/* Package format version */\n+#define ICE_PKG_FMT_VER_MAJ\t1\n+#define ICE_PKG_FMT_VER_MNR\t0\n+#define ICE_PKG_FMT_VER_UPD\t0\n+#define ICE_PKG_FMT_VER_DFT\t0\n+\n+enum ice_status\n+ice_update_pkg(struct ice_hw *hw, struct ice_buf *bufs, u32 count);\n+\n+\n+/* package buffer building routines */\n+\n+struct ice_buf_build *ice_pkg_buf_alloc(struct ice_hw *hw);\n+enum ice_status\n+ice_pkg_buf_reserve_section(struct ice_buf_build *bld, u16 count);\n+void *ice_pkg_buf_alloc_section(struct ice_buf_build *bld, u32 type, u16 size);\n+struct ice_buf *ice_pkg_buf(struct ice_buf_build *bld);\n+void ice_pkg_buf_free(struct ice_hw *hw, struct ice_buf_build *bld);\n+\n+/* XLT1/PType group functions */\n+enum ice_status ice_ptg_update_xlt1(struct ice_hw *hw, enum ice_block blk);\n+enum ice_status\n+ice_ptg_find_ptype(struct ice_hw *hw, enum ice_block blk, u16 ptype, u8 *ptg);\n+u8 ice_ptg_alloc(struct ice_hw *hw, enum ice_block blk);\n+void ice_ptg_free(struct ice_hw *hw, enum ice_block blk, u8 ptg);\n+enum ice_status\n+ice_ptg_add_mv_ptype(struct ice_hw *hw, enum ice_block blk, u16 ptype, u8 ptg);\n+\n+/* XLT2/Vsi group functions */\n+enum ice_status ice_vsig_update_xlt2(struct ice_hw *hw, enum ice_block blk);\n+enum ice_status\n+ice_vsig_find_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 *vsig);\n+enum ice_status\n+ice_find_dup_props_vsig(struct ice_hw *hw, enum ice_block blk,\n+\t\t\tstruct LIST_HEAD_TYPE *chs, u16 *vsig);\n+\n+enum ice_status\n+ice_vsig_add_mv_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig);\n+enum ice_status ice_vsig_free(struct ice_hw *hw, enum ice_block blk, u16 vsig);\n+enum ice_status\n+ice_vsig_add_mv_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig);\n+enum ice_status\n+ice_vsig_remove_vsi(struct ice_hw *hw, enum ice_block blk, u16 vsi, u16 vsig);\n+enum ice_status\n+ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n+\t     struct ice_fv_word *es);\n+struct ice_prof_map *\n+ice_search_prof_id(struct ice_hw *hw, enum ice_block blk, u64 id);\n+enum ice_status\n+ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);\n+enum ice_status\n+ice_rem_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl);\n+struct ice_prof_map *\n+ice_set_prof_context(struct ice_hw *hw, enum ice_block blk, u64 id, u64 cntxt);\n+struct ice_prof_map *\n+ice_get_prof_context(struct ice_hw *hw, enum ice_block blk, u64 id, u64 *cntxt);\n+enum ice_status\n+ice_copy_and_init_pkg(struct ice_hw *hw, const u8 *buf, u32 len);\n+enum ice_status ice_init_hw_tbls(struct ice_hw *hw);\n+void ice_free_seg(struct ice_hw *hw);\n+void ice_free_hw_tbls(struct ice_hw *hw);\n+enum ice_status\n+ice_add_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi[], u8 count,\n+\t     u64 id);\n+enum ice_status\n+ice_rem_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi[], u8 count,\n+\t     u64 id);\n+enum ice_status\n+ice_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 id);\n+\n+enum ice_status\n+ice_set_key(u8 *key, u16 size, u8 *val, u8 *upd, u8 *dc, u8 *nm, u16 off,\n+\t    u16 len);\n+#endif /* _ICE_FLEX_PIPE_H_ */\ndiff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h\nnew file mode 100644\nindex 0000000..84a38cb\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_flex_type.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_FLEX_TYPE_H_\n+#define _ICE_FLEX_TYPE_H_\n+\n+/* Extraction Sequence (Field Vector) Table */\n+struct ice_fv_word {\n+\tu8 prot_id;\n+\tu8 off;\t\t/* Offset within the protocol header */\n+};\n+\n+#define ICE_MAX_FV_WORDS 48\n+struct ice_fv {\n+\tstruct ice_fv_word ew[ICE_MAX_FV_WORDS];\n+};\n+\n+#endif /* _ICE_FLEX_TYPE_H_ */\ndiff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nnew file mode 100644\nindex 0000000..49b22bc\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -0,0 +1,4 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\ndiff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h\nnew file mode 100644\nindex 0000000..228a2c0\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_flow.h\n@@ -0,0 +1,8 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_FLOW_H_\n+#define _ICE_FLOW_H_\n+\n+#endif /* _ICE_FLOW_H_ */\ndiff --git a/drivers/net/ice/base/ice_hw_autogen.h b/drivers/net/ice/base/ice_hw_autogen.h\nnew file mode 100644\nindex 0000000..8c79891\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_hw_autogen.h\n@@ -0,0 +1,9815 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+/* Machine-generated file; do not edit */\n+#ifndef _ICE_HW_AUTOGEN_H_\n+#define _ICE_HW_AUTOGEN_H_\n+\n+\n+\n+#define GL_RDPU_CNTRL\t\t\t\t0x00052054 /* Reset Source: CORER */\n+#define GL_RDPU_CNTRL_RX_PAD_EN_S\t\t0\n+#define GL_RDPU_CNTRL_RX_PAD_EN_M\t\tBIT(0)\n+#define GL_RDPU_CNTRL_UDP_ZERO_EN_S\t\t1\n+#define GL_RDPU_CNTRL_UDP_ZERO_EN_M\t\tBIT(1)\n+#define GL_RDPU_CNTRL_BLNC_EN_S\t\t\t2\n+#define GL_RDPU_CNTRL_BLNC_EN_M\t\t\tBIT(2)\n+#define GL_RDPU_CNTRL_RECIPE_BYPASS_S\t\t3\n+#define GL_RDPU_CNTRL_RECIPE_BYPASS_M\t\tBIT(3)\n+#define GL_RDPU_CNTRL_RLAN_ACK_REQ_PM_TH_S\t4\n+#define GL_RDPU_CNTRL_RLAN_ACK_REQ_PM_TH_M\tMAKEMASK(0x3F, 4)\n+#define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_S\t10\n+#define GL_RDPU_CNTRL_PE_ACK_REQ_PM_TH_M\tMAKEMASK(0x3F, 10)\n+#define GL_RDPU_CNTRL_REQ_WB_PM_TH_S\t\t16\n+#define GL_RDPU_CNTRL_REQ_WB_PM_TH_M\t\tMAKEMASK(0x1F, 16)\n+#define GL_RDPU_CNTRL_ECO_S\t\t\t21\n+#define GL_RDPU_CNTRL_ECO_M\t\t\tMAKEMASK(0x7FF, 21)\n+#define MSIX_PBA(_i)\t\t\t\t(0x00008000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: FLR */\n+#define MSIX_PBA_MAX_INDEX\t\t\t2\n+#define MSIX_PBA_PENBIT_S\t\t\t0\n+#define MSIX_PBA_PENBIT_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define MSIX_TADD(_i)\t\t\t\t(0x00000000 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */\n+#define MSIX_TADD_MAX_INDEX\t\t\t64\n+#define MSIX_TADD_MSIXTADD10_S\t\t\t0\n+#define MSIX_TADD_MSIXTADD10_M\t\t\tMAKEMASK(0x3, 0)\n+#define MSIX_TADD_MSIXTADD_S\t\t\t2\n+#define MSIX_TADD_MSIXTADD_M\t\t\tMAKEMASK(0x3FFFFFFF, 2)\n+#define MSIX_TUADD(_i)\t\t\t\t(0x00000004 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */\n+#define MSIX_TUADD_MAX_INDEX\t\t\t64\n+#define MSIX_TUADD_MSIXTUADD_S\t\t\t0\n+#define MSIX_TUADD_MSIXTUADD_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define MSIX_TVCTRL(_i)\t\t\t\t(0x0000000C + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */\n+#define MSIX_TVCTRL_MAX_INDEX\t\t\t64\n+#define MSIX_TVCTRL_MASK_S\t\t\t0\n+#define MSIX_TVCTRL_MASK_M\t\t\tBIT(0)\n+#define PF0_FW_HLP_ARQBAH_PAGE\t\t\t0x02D00180 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_S\t\t0\n+#define PF0_FW_HLP_ARQBAH_PAGE_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_FW_HLP_ARQBAL_PAGE\t\t\t0x02D00080 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_S\t0\n+#define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_LSB_M\tMAKEMASK(0x3F, 0)\n+#define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_S\t\t6\n+#define PF0_FW_HLP_ARQBAL_PAGE_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_FW_HLP_ARQH_PAGE\t\t\t0x02D00380 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQH_PAGE_ARQH_S\t\t0\n+#define PF0_FW_HLP_ARQH_PAGE_ARQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ARQLEN_PAGE\t\t\t0x02D00280 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_S\t\t0\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQVFE_S\t\t28\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQVFE_M\t\tBIT(28)\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQOVFL_S\t29\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQOVFL_M\tBIT(29)\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQCRIT_S\t30\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQCRIT_M\tBIT(30)\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQENABLE_S\t31\n+#define PF0_FW_HLP_ARQLEN_PAGE_ARQENABLE_M\tBIT(31)\n+#define PF0_FW_HLP_ARQT_PAGE\t\t\t0x02D00480 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQT_PAGE_ARQT_S\t\t0\n+#define PF0_FW_HLP_ARQT_PAGE_ARQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ATQBAH_PAGE\t\t\t0x02D00100 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_S\t\t0\n+#define PF0_FW_HLP_ATQBAH_PAGE_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_FW_HLP_ATQBAL_PAGE\t\t\t0x02D00000 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_S\t0\n+#define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_LSB_M\tMAKEMASK(0x3F, 0)\n+#define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_S\t\t6\n+#define PF0_FW_HLP_ATQBAL_PAGE_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_FW_HLP_ATQH_PAGE\t\t\t0x02D00300 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQH_PAGE_ATQH_S\t\t0\n+#define PF0_FW_HLP_ATQH_PAGE_ATQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ATQLEN_PAGE\t\t\t0x02D00200 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_S\t\t0\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQVFE_S\t\t28\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQVFE_M\t\tBIT(28)\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQOVFL_S\t29\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQOVFL_M\tBIT(29)\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQCRIT_S\t30\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQCRIT_M\tBIT(30)\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQENABLE_S\t31\n+#define PF0_FW_HLP_ATQLEN_PAGE_ATQENABLE_M\tBIT(31)\n+#define PF0_FW_HLP_ATQT_PAGE\t\t\t0x02D00400 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQT_PAGE_ATQT_S\t\t0\n+#define PF0_FW_HLP_ATQT_PAGE_ATQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ARQBAH_PAGE\t\t\t0x02D40180 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_S\t\t0\n+#define PF0_FW_PSM_ARQBAH_PAGE_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_FW_PSM_ARQBAL_PAGE\t\t\t0x02D40080 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_S\t0\n+#define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_LSB_M\tMAKEMASK(0x3F, 0)\n+#define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_S\t\t6\n+#define PF0_FW_PSM_ARQBAL_PAGE_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_FW_PSM_ARQH_PAGE\t\t\t0x02D40380 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQH_PAGE_ARQH_S\t\t0\n+#define PF0_FW_PSM_ARQH_PAGE_ARQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ARQLEN_PAGE\t\t\t0x02D40280 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_S\t\t0\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQVFE_S\t\t28\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQVFE_M\t\tBIT(28)\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQOVFL_S\t29\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQOVFL_M\tBIT(29)\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQCRIT_S\t30\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQCRIT_M\tBIT(30)\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQENABLE_S\t31\n+#define PF0_FW_PSM_ARQLEN_PAGE_ARQENABLE_M\tBIT(31)\n+#define PF0_FW_PSM_ARQT_PAGE\t\t\t0x02D40480 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQT_PAGE_ARQT_S\t\t0\n+#define PF0_FW_PSM_ARQT_PAGE_ARQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ATQBAH_PAGE\t\t\t0x02D40100 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_S\t\t0\n+#define PF0_FW_PSM_ATQBAH_PAGE_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_FW_PSM_ATQBAL_PAGE\t\t\t0x02D40000 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_S\t0\n+#define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_LSB_M\tMAKEMASK(0x3F, 0)\n+#define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_S\t\t6\n+#define PF0_FW_PSM_ATQBAL_PAGE_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_FW_PSM_ATQH_PAGE\t\t\t0x02D40300 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQH_PAGE_ATQH_S\t\t0\n+#define PF0_FW_PSM_ATQH_PAGE_ATQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ATQLEN_PAGE\t\t\t0x02D40200 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_S\t\t0\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQVFE_S\t\t28\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQVFE_M\t\tBIT(28)\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQOVFL_S\t29\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQOVFL_M\tBIT(29)\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQCRIT_S\t30\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQCRIT_M\tBIT(30)\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQENABLE_S\t31\n+#define PF0_FW_PSM_ATQLEN_PAGE_ATQENABLE_M\tBIT(31)\n+#define PF0_FW_PSM_ATQT_PAGE\t\t\t0x02D40400 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQT_PAGE_ATQT_S\t\t0\n+#define PF0_FW_PSM_ATQT_PAGE_ATQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ARQBAH_PAGE\t\t\t0x02D80190 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_S\t0\n+#define PF0_MBX_CPM_ARQBAH_PAGE_ARQBAH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_CPM_ARQBAL_PAGE\t\t\t0x02D80090 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_S\t0\n+#define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_LSB_M\tMAKEMASK(0x3F, 0)\n+#define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_S\t6\n+#define PF0_MBX_CPM_ARQBAL_PAGE_ARQBAL_M\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_CPM_ARQH_PAGE\t\t\t0x02D80390 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQH_PAGE_ARQH_S\t\t0\n+#define PF0_MBX_CPM_ARQH_PAGE_ARQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ARQLEN_PAGE\t\t\t0x02D80290 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_S\t0\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQLEN_M\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_S\t28\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQVFE_M\tBIT(28)\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQOVFL_S\t29\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQOVFL_M\tBIT(29)\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQCRIT_S\t30\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQCRIT_M\tBIT(30)\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQENABLE_S\t31\n+#define PF0_MBX_CPM_ARQLEN_PAGE_ARQENABLE_M\tBIT(31)\n+#define PF0_MBX_CPM_ARQT_PAGE\t\t\t0x02D80490 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQT_PAGE_ARQT_S\t\t0\n+#define PF0_MBX_CPM_ARQT_PAGE_ARQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ATQBAH_PAGE\t\t\t0x02D80110 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_S\t0\n+#define PF0_MBX_CPM_ATQBAH_PAGE_ATQBAH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_CPM_ATQBAL_PAGE\t\t\t0x02D80010 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQBAL_PAGE_ATQBAL_S\t6\n+#define PF0_MBX_CPM_ATQBAL_PAGE_ATQBAL_M\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_CPM_ATQH_PAGE\t\t\t0x02D80310 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQH_PAGE_ATQH_S\t\t0\n+#define PF0_MBX_CPM_ATQH_PAGE_ATQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ATQLEN_PAGE\t\t\t0x02D80210 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_S\t0\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQLEN_M\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_S\t28\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQVFE_M\tBIT(28)\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQOVFL_S\t29\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQOVFL_M\tBIT(29)\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQCRIT_S\t30\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQCRIT_M\tBIT(30)\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQENABLE_S\t31\n+#define PF0_MBX_CPM_ATQLEN_PAGE_ATQENABLE_M\tBIT(31)\n+#define PF0_MBX_CPM_ATQT_PAGE\t\t\t0x02D80410 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQT_PAGE_ATQT_S\t\t0\n+#define PF0_MBX_CPM_ATQT_PAGE_ATQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ARQBAH_PAGE\t\t\t0x02D00190 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_S\t0\n+#define PF0_MBX_HLP_ARQBAH_PAGE_ARQBAH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_HLP_ARQBAL_PAGE\t\t\t0x02D00090 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_S\t0\n+#define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_LSB_M\tMAKEMASK(0x3F, 0)\n+#define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_S\t6\n+#define PF0_MBX_HLP_ARQBAL_PAGE_ARQBAL_M\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_HLP_ARQH_PAGE\t\t\t0x02D00390 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQH_PAGE_ARQH_S\t\t0\n+#define PF0_MBX_HLP_ARQH_PAGE_ARQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ARQLEN_PAGE\t\t\t0x02D00290 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_S\t0\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQLEN_M\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_S\t28\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQVFE_M\tBIT(28)\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQOVFL_S\t29\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQOVFL_M\tBIT(29)\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQCRIT_S\t30\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQCRIT_M\tBIT(30)\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQENABLE_S\t31\n+#define PF0_MBX_HLP_ARQLEN_PAGE_ARQENABLE_M\tBIT(31)\n+#define PF0_MBX_HLP_ARQT_PAGE\t\t\t0x02D00490 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQT_PAGE_ARQT_S\t\t0\n+#define PF0_MBX_HLP_ARQT_PAGE_ARQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ATQBAH_PAGE\t\t\t0x02D00110 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_S\t0\n+#define PF0_MBX_HLP_ATQBAH_PAGE_ATQBAH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_HLP_ATQBAL_PAGE\t\t\t0x02D00010 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQBAL_PAGE_ATQBAL_S\t6\n+#define PF0_MBX_HLP_ATQBAL_PAGE_ATQBAL_M\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_HLP_ATQH_PAGE\t\t\t0x02D00310 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQH_PAGE_ATQH_S\t\t0\n+#define PF0_MBX_HLP_ATQH_PAGE_ATQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ATQLEN_PAGE\t\t\t0x02D00210 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_S\t0\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQLEN_M\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_S\t28\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQVFE_M\tBIT(28)\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQOVFL_S\t29\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQOVFL_M\tBIT(29)\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQCRIT_S\t30\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQCRIT_M\tBIT(30)\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQENABLE_S\t31\n+#define PF0_MBX_HLP_ATQLEN_PAGE_ATQENABLE_M\tBIT(31)\n+#define PF0_MBX_HLP_ATQT_PAGE\t\t\t0x02D00410 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQT_PAGE_ATQT_S\t\t0\n+#define PF0_MBX_HLP_ATQT_PAGE_ATQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ARQBAH_PAGE\t\t\t0x02D40190 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_S\t0\n+#define PF0_MBX_PSM_ARQBAH_PAGE_ARQBAH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_PSM_ARQBAL_PAGE\t\t\t0x02D40090 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_S\t0\n+#define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_LSB_M\tMAKEMASK(0x3F, 0)\n+#define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_S\t6\n+#define PF0_MBX_PSM_ARQBAL_PAGE_ARQBAL_M\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_PSM_ARQH_PAGE\t\t\t0x02D40390 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQH_PAGE_ARQH_S\t\t0\n+#define PF0_MBX_PSM_ARQH_PAGE_ARQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ARQLEN_PAGE\t\t\t0x02D40290 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_S\t0\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQLEN_M\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_S\t28\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQVFE_M\tBIT(28)\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQOVFL_S\t29\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQOVFL_M\tBIT(29)\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQCRIT_S\t30\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQCRIT_M\tBIT(30)\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQENABLE_S\t31\n+#define PF0_MBX_PSM_ARQLEN_PAGE_ARQENABLE_M\tBIT(31)\n+#define PF0_MBX_PSM_ARQT_PAGE\t\t\t0x02D40490 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQT_PAGE_ARQT_S\t\t0\n+#define PF0_MBX_PSM_ARQT_PAGE_ARQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ATQBAH_PAGE\t\t\t0x02D40110 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_S\t0\n+#define PF0_MBX_PSM_ATQBAH_PAGE_ATQBAH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_PSM_ATQBAL_PAGE\t\t\t0x02D40010 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQBAL_PAGE_ATQBAL_S\t6\n+#define PF0_MBX_PSM_ATQBAL_PAGE_ATQBAL_M\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_PSM_ATQH_PAGE\t\t\t0x02D40310 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQH_PAGE_ATQH_S\t\t0\n+#define PF0_MBX_PSM_ATQH_PAGE_ATQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ATQLEN_PAGE\t\t\t0x02D40210 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_S\t0\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQLEN_M\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_S\t28\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQVFE_M\tBIT(28)\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQOVFL_S\t29\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQOVFL_M\tBIT(29)\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQCRIT_S\t30\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQCRIT_M\tBIT(30)\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQENABLE_S\t31\n+#define PF0_MBX_PSM_ATQLEN_PAGE_ATQENABLE_M\tBIT(31)\n+#define PF0_MBX_PSM_ATQT_PAGE\t\t\t0x02D40410 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQT_PAGE_ATQT_S\t\t0\n+#define PF0_MBX_PSM_ATQT_PAGE_ATQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ARQBAH_PAGE\t\t\t0x02D801A0 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_S\t\t0\n+#define PF0_SB_CPM_ARQBAH_PAGE_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_SB_CPM_ARQBAL_PAGE\t\t\t0x02D800A0 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_S\t0\n+#define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_LSB_M\tMAKEMASK(0x3F, 0)\n+#define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_S\t\t6\n+#define PF0_SB_CPM_ARQBAL_PAGE_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_SB_CPM_ARQH_PAGE\t\t\t0x02D803A0 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQH_PAGE_ARQH_S\t\t0\n+#define PF0_SB_CPM_ARQH_PAGE_ARQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ARQLEN_PAGE\t\t\t0x02D802A0 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_S\t\t0\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_S\t\t28\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQVFE_M\t\tBIT(28)\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQOVFL_S\t29\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQOVFL_M\tBIT(29)\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQCRIT_S\t30\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQCRIT_M\tBIT(30)\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQENABLE_S\t31\n+#define PF0_SB_CPM_ARQLEN_PAGE_ARQENABLE_M\tBIT(31)\n+#define PF0_SB_CPM_ARQT_PAGE\t\t\t0x02D804A0 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQT_PAGE_ARQT_S\t\t0\n+#define PF0_SB_CPM_ARQT_PAGE_ARQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ATQBAH_PAGE\t\t\t0x02D80120 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_S\t\t0\n+#define PF0_SB_CPM_ATQBAH_PAGE_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_SB_CPM_ATQBAL_PAGE\t\t\t0x02D80020 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQBAL_PAGE_ATQBAL_S\t\t6\n+#define PF0_SB_CPM_ATQBAL_PAGE_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_SB_CPM_ATQH_PAGE\t\t\t0x02D80320 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQH_PAGE_ATQH_S\t\t0\n+#define PF0_SB_CPM_ATQH_PAGE_ATQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ATQLEN_PAGE\t\t\t0x02D80220 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_S\t\t0\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_S\t\t28\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQVFE_M\t\tBIT(28)\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQOVFL_S\t29\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQOVFL_M\tBIT(29)\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQCRIT_S\t30\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQCRIT_M\tBIT(30)\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQENABLE_S\t31\n+#define PF0_SB_CPM_ATQLEN_PAGE_ATQENABLE_M\tBIT(31)\n+#define PF0_SB_CPM_ATQT_PAGE\t\t\t0x02D80420 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQT_PAGE_ATQT_S\t\t0\n+#define PF0_SB_CPM_ATQT_PAGE_ATQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ARQBAH_PAGE\t\t\t0x02D001A0 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_S\t\t0\n+#define PF0_SB_HLP_ARQBAH_PAGE_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_SB_HLP_ARQBAL_PAGE\t\t\t0x02D000A0 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_S\t0\n+#define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_LSB_M\tMAKEMASK(0x3F, 0)\n+#define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_S\t\t6\n+#define PF0_SB_HLP_ARQBAL_PAGE_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_SB_HLP_ARQH_PAGE\t\t\t0x02D003A0 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQH_PAGE_ARQH_S\t\t0\n+#define PF0_SB_HLP_ARQH_PAGE_ARQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ARQLEN_PAGE\t\t\t0x02D002A0 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_S\t\t0\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_S\t\t28\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQVFE_M\t\tBIT(28)\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQOVFL_S\t29\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQOVFL_M\tBIT(29)\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQCRIT_S\t30\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQCRIT_M\tBIT(30)\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQENABLE_S\t31\n+#define PF0_SB_HLP_ARQLEN_PAGE_ARQENABLE_M\tBIT(31)\n+#define PF0_SB_HLP_ARQT_PAGE\t\t\t0x02D004A0 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQT_PAGE_ARQT_S\t\t0\n+#define PF0_SB_HLP_ARQT_PAGE_ARQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ATQBAH_PAGE\t\t\t0x02D00120 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_S\t\t0\n+#define PF0_SB_HLP_ATQBAH_PAGE_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_SB_HLP_ATQBAL_PAGE\t\t\t0x02D00020 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQBAL_PAGE_ATQBAL_S\t\t6\n+#define PF0_SB_HLP_ATQBAL_PAGE_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_SB_HLP_ATQH_PAGE\t\t\t0x02D00320 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQH_PAGE_ATQH_S\t\t0\n+#define PF0_SB_HLP_ATQH_PAGE_ATQH_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ATQLEN_PAGE\t\t\t0x02D00220 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_S\t\t0\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_S\t\t28\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQVFE_M\t\tBIT(28)\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQOVFL_S\t29\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQOVFL_M\tBIT(29)\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQCRIT_S\t30\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQCRIT_M\tBIT(30)\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQENABLE_S\t31\n+#define PF0_SB_HLP_ATQLEN_PAGE_ATQENABLE_M\tBIT(31)\n+#define PF0_SB_HLP_ATQT_PAGE\t\t\t0x02D00420 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQT_PAGE_ATQT_S\t\t0\n+#define PF0_SB_HLP_ATQT_PAGE_ATQT_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0INT_DYN_CTL(_i)\t\t\t(0x03000000 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: PFR */\n+#define PF0INT_DYN_CTL_MAX_INDEX\t\t2047\n+#define PF0INT_DYN_CTL_INTENA_S\t\t\t0\n+#define PF0INT_DYN_CTL_INTENA_M\t\t\tBIT(0)\n+#define PF0INT_DYN_CTL_CLEARPBA_S\t\t1\n+#define PF0INT_DYN_CTL_CLEARPBA_M\t\tBIT(1)\n+#define PF0INT_DYN_CTL_SWINT_TRIG_S\t\t2\n+#define PF0INT_DYN_CTL_SWINT_TRIG_M\t\tBIT(2)\n+#define PF0INT_DYN_CTL_ITR_INDX_S\t\t3\n+#define PF0INT_DYN_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 3)\n+#define PF0INT_DYN_CTL_INTERVAL_S\t\t5\n+#define PF0INT_DYN_CTL_INTERVAL_M\t\tMAKEMASK(0xFFF, 5)\n+#define PF0INT_DYN_CTL_SW_ITR_INDX_ENA_S\t24\n+#define PF0INT_DYN_CTL_SW_ITR_INDX_ENA_M\tBIT(24)\n+#define PF0INT_DYN_CTL_SW_ITR_INDX_S\t\t25\n+#define PF0INT_DYN_CTL_SW_ITR_INDX_M\t\tMAKEMASK(0x3, 25)\n+#define PF0INT_DYN_CTL_WB_ON_ITR_S\t\t30\n+#define PF0INT_DYN_CTL_WB_ON_ITR_M\t\tBIT(30)\n+#define PF0INT_DYN_CTL_INTENA_MSK_S\t\t31\n+#define PF0INT_DYN_CTL_INTENA_MSK_M\t\tBIT(31)\n+#define PF0INT_ITR_0(_i)\t\t\t(0x03000004 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: PFR */\n+#define PF0INT_ITR_0_MAX_INDEX\t\t\t2047\n+#define PF0INT_ITR_0_INTERVAL_S\t\t\t0\n+#define PF0INT_ITR_0_INTERVAL_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define PF0INT_ITR_1(_i)\t\t\t(0x03000008 + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: PFR */\n+#define PF0INT_ITR_1_MAX_INDEX\t\t\t2047\n+#define PF0INT_ITR_1_INTERVAL_S\t\t\t0\n+#define PF0INT_ITR_1_INTERVAL_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define PF0INT_ITR_2(_i)\t\t\t(0x0300000C + ((_i) * 4096)) /* _i=0...2047 */ /* Reset Source: PFR */\n+#define PF0INT_ITR_2_MAX_INDEX\t\t\t2047\n+#define PF0INT_ITR_2_INTERVAL_S\t\t\t0\n+#define PF0INT_ITR_2_INTERVAL_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define PF0INT_OICR_CPM_PAGE\t\t\t0x02D03000 /* Reset Source: CORER */\n+#define PF0INT_OICR_CPM_PAGE_INTEVENT_S\t\t0\n+#define PF0INT_OICR_CPM_PAGE_INTEVENT_M\t\tBIT(0)\n+#define PF0INT_OICR_CPM_PAGE_QUEUE_S\t\t1\n+#define PF0INT_OICR_CPM_PAGE_QUEUE_M\t\tBIT(1)\n+#define PF0INT_OICR_CPM_PAGE_RSV1_S\t\t2\n+#define PF0INT_OICR_CPM_PAGE_RSV1_M\t\tMAKEMASK(0xFF, 2)\n+#define PF0INT_OICR_CPM_PAGE_HH_COMP_S\t\t10\n+#define PF0INT_OICR_CPM_PAGE_HH_COMP_M\t\tBIT(10)\n+#define PF0INT_OICR_CPM_PAGE_TSYN_TX_S\t\t11\n+#define PF0INT_OICR_CPM_PAGE_TSYN_TX_M\t\tBIT(11)\n+#define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_S\t12\n+#define PF0INT_OICR_CPM_PAGE_TSYN_EVNT_M\tBIT(12)\n+#define PF0INT_OICR_CPM_PAGE_TSYN_TGT_S\t\t13\n+#define PF0INT_OICR_CPM_PAGE_TSYN_TGT_M\t\tBIT(13)\n+#define PF0INT_OICR_CPM_PAGE_HLP_RDY_S\t\t14\n+#define PF0INT_OICR_CPM_PAGE_HLP_RDY_M\t\tBIT(14)\n+#define PF0INT_OICR_CPM_PAGE_CPM_RDY_S\t\t15\n+#define PF0INT_OICR_CPM_PAGE_CPM_RDY_M\t\tBIT(15)\n+#define PF0INT_OICR_CPM_PAGE_ECC_ERR_S\t\t16\n+#define PF0INT_OICR_CPM_PAGE_ECC_ERR_M\t\tBIT(16)\n+#define PF0INT_OICR_CPM_PAGE_RSV2_S\t\t17\n+#define PF0INT_OICR_CPM_PAGE_RSV2_M\t\tMAKEMASK(0x3, 17)\n+#define PF0INT_OICR_CPM_PAGE_MAL_DETECT_S\t19\n+#define PF0INT_OICR_CPM_PAGE_MAL_DETECT_M\tBIT(19)\n+#define PF0INT_OICR_CPM_PAGE_GRST_S\t\t20\n+#define PF0INT_OICR_CPM_PAGE_GRST_M\t\tBIT(20)\n+#define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_S\t21\n+#define PF0INT_OICR_CPM_PAGE_PCI_EXCEPTION_M\tBIT(21)\n+#define PF0INT_OICR_CPM_PAGE_GPIO_S\t\t22\n+#define PF0INT_OICR_CPM_PAGE_GPIO_M\t\tBIT(22)\n+#define PF0INT_OICR_CPM_PAGE_RSV3_S\t\t23\n+#define PF0INT_OICR_CPM_PAGE_RSV3_M\t\tBIT(23)\n+#define PF0INT_OICR_CPM_PAGE_STORM_DETECT_S\t24\n+#define PF0INT_OICR_CPM_PAGE_STORM_DETECT_M\tBIT(24)\n+#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_S 25\n+#define PF0INT_OICR_CPM_PAGE_LINK_STAT_CHANGE_M BIT(25)\n+#define PF0INT_OICR_CPM_PAGE_HMC_ERR_S\t\t26\n+#define PF0INT_OICR_CPM_PAGE_HMC_ERR_M\t\tBIT(26)\n+#define PF0INT_OICR_CPM_PAGE_PE_PUSH_S\t\t27\n+#define PF0INT_OICR_CPM_PAGE_PE_PUSH_M\t\tBIT(27)\n+#define PF0INT_OICR_CPM_PAGE_PE_CRITERR_S\t28\n+#define PF0INT_OICR_CPM_PAGE_PE_CRITERR_M\tBIT(28)\n+#define PF0INT_OICR_CPM_PAGE_VFLR_S\t\t29\n+#define PF0INT_OICR_CPM_PAGE_VFLR_M\t\tBIT(29)\n+#define PF0INT_OICR_CPM_PAGE_XLR_HW_DONE_S\t30\n+#define PF0INT_OICR_CPM_PAGE_XLR_HW_DONE_M\tBIT(30)\n+#define PF0INT_OICR_CPM_PAGE_SWINT_S\t\t31\n+#define PF0INT_OICR_CPM_PAGE_SWINT_M\t\tBIT(31)\n+#define PF0INT_OICR_ENA_CPM_PAGE\t\t0x02D03100 /* Reset Source: CORER */\n+#define PF0INT_OICR_ENA_CPM_PAGE_RSV0_S\t\t0\n+#define PF0INT_OICR_ENA_CPM_PAGE_RSV0_M\t\tBIT(0)\n+#define PF0INT_OICR_ENA_CPM_PAGE_INT_ENA_S\t1\n+#define PF0INT_OICR_ENA_CPM_PAGE_INT_ENA_M\tMAKEMASK(0x7FFFFFFF, 1)\n+#define PF0INT_OICR_ENA_HLP_PAGE\t\t0x02D01100 /* Reset Source: CORER */\n+#define PF0INT_OICR_ENA_HLP_PAGE_RSV0_S\t\t0\n+#define PF0INT_OICR_ENA_HLP_PAGE_RSV0_M\t\tBIT(0)\n+#define PF0INT_OICR_ENA_HLP_PAGE_INT_ENA_S\t1\n+#define PF0INT_OICR_ENA_HLP_PAGE_INT_ENA_M\tMAKEMASK(0x7FFFFFFF, 1)\n+#define PF0INT_OICR_ENA_PSM_PAGE\t\t0x02D02100 /* Reset Source: CORER */\n+#define PF0INT_OICR_ENA_PSM_PAGE_RSV0_S\t\t0\n+#define PF0INT_OICR_ENA_PSM_PAGE_RSV0_M\t\tBIT(0)\n+#define PF0INT_OICR_ENA_PSM_PAGE_INT_ENA_S\t1\n+#define PF0INT_OICR_ENA_PSM_PAGE_INT_ENA_M\tMAKEMASK(0x7FFFFFFF, 1)\n+#define PF0INT_OICR_HLP_PAGE\t\t\t0x02D01000 /* Reset Source: CORER */\n+#define PF0INT_OICR_HLP_PAGE_INTEVENT_S\t\t0\n+#define PF0INT_OICR_HLP_PAGE_INTEVENT_M\t\tBIT(0)\n+#define PF0INT_OICR_HLP_PAGE_QUEUE_S\t\t1\n+#define PF0INT_OICR_HLP_PAGE_QUEUE_M\t\tBIT(1)\n+#define PF0INT_OICR_HLP_PAGE_RSV1_S\t\t2\n+#define PF0INT_OICR_HLP_PAGE_RSV1_M\t\tMAKEMASK(0xFF, 2)\n+#define PF0INT_OICR_HLP_PAGE_HH_COMP_S\t\t10\n+#define PF0INT_OICR_HLP_PAGE_HH_COMP_M\t\tBIT(10)\n+#define PF0INT_OICR_HLP_PAGE_TSYN_TX_S\t\t11\n+#define PF0INT_OICR_HLP_PAGE_TSYN_TX_M\t\tBIT(11)\n+#define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_S\t12\n+#define PF0INT_OICR_HLP_PAGE_TSYN_EVNT_M\tBIT(12)\n+#define PF0INT_OICR_HLP_PAGE_TSYN_TGT_S\t\t13\n+#define PF0INT_OICR_HLP_PAGE_TSYN_TGT_M\t\tBIT(13)\n+#define PF0INT_OICR_HLP_PAGE_HLP_RDY_S\t\t14\n+#define PF0INT_OICR_HLP_PAGE_HLP_RDY_M\t\tBIT(14)\n+#define PF0INT_OICR_HLP_PAGE_CPM_RDY_S\t\t15\n+#define PF0INT_OICR_HLP_PAGE_CPM_RDY_M\t\tBIT(15)\n+#define PF0INT_OICR_HLP_PAGE_ECC_ERR_S\t\t16\n+#define PF0INT_OICR_HLP_PAGE_ECC_ERR_M\t\tBIT(16)\n+#define PF0INT_OICR_HLP_PAGE_RSV2_S\t\t17\n+#define PF0INT_OICR_HLP_PAGE_RSV2_M\t\tMAKEMASK(0x3, 17)\n+#define PF0INT_OICR_HLP_PAGE_MAL_DETECT_S\t19\n+#define PF0INT_OICR_HLP_PAGE_MAL_DETECT_M\tBIT(19)\n+#define PF0INT_OICR_HLP_PAGE_GRST_S\t\t20\n+#define PF0INT_OICR_HLP_PAGE_GRST_M\t\tBIT(20)\n+#define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_S\t21\n+#define PF0INT_OICR_HLP_PAGE_PCI_EXCEPTION_M\tBIT(21)\n+#define PF0INT_OICR_HLP_PAGE_GPIO_S\t\t22\n+#define PF0INT_OICR_HLP_PAGE_GPIO_M\t\tBIT(22)\n+#define PF0INT_OICR_HLP_PAGE_RSV3_S\t\t23\n+#define PF0INT_OICR_HLP_PAGE_RSV3_M\t\tBIT(23)\n+#define PF0INT_OICR_HLP_PAGE_STORM_DETECT_S\t24\n+#define PF0INT_OICR_HLP_PAGE_STORM_DETECT_M\tBIT(24)\n+#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_S 25\n+#define PF0INT_OICR_HLP_PAGE_LINK_STAT_CHANGE_M BIT(25)\n+#define PF0INT_OICR_HLP_PAGE_HMC_ERR_S\t\t26\n+#define PF0INT_OICR_HLP_PAGE_HMC_ERR_M\t\tBIT(26)\n+#define PF0INT_OICR_HLP_PAGE_PE_PUSH_S\t\t27\n+#define PF0INT_OICR_HLP_PAGE_PE_PUSH_M\t\tBIT(27)\n+#define PF0INT_OICR_HLP_PAGE_PE_CRITERR_S\t28\n+#define PF0INT_OICR_HLP_PAGE_PE_CRITERR_M\tBIT(28)\n+#define PF0INT_OICR_HLP_PAGE_VFLR_S\t\t29\n+#define PF0INT_OICR_HLP_PAGE_VFLR_M\t\tBIT(29)\n+#define PF0INT_OICR_HLP_PAGE_XLR_HW_DONE_S\t30\n+#define PF0INT_OICR_HLP_PAGE_XLR_HW_DONE_M\tBIT(30)\n+#define PF0INT_OICR_HLP_PAGE_SWINT_S\t\t31\n+#define PF0INT_OICR_HLP_PAGE_SWINT_M\t\tBIT(31)\n+#define PF0INT_OICR_PSM_PAGE\t\t\t0x02D02000 /* Reset Source: CORER */\n+#define PF0INT_OICR_PSM_PAGE_INTEVENT_S\t\t0\n+#define PF0INT_OICR_PSM_PAGE_INTEVENT_M\t\tBIT(0)\n+#define PF0INT_OICR_PSM_PAGE_QUEUE_S\t\t1\n+#define PF0INT_OICR_PSM_PAGE_QUEUE_M\t\tBIT(1)\n+#define PF0INT_OICR_PSM_PAGE_RSV1_S\t\t2\n+#define PF0INT_OICR_PSM_PAGE_RSV1_M\t\tMAKEMASK(0xFF, 2)\n+#define PF0INT_OICR_PSM_PAGE_HH_COMP_S\t\t10\n+#define PF0INT_OICR_PSM_PAGE_HH_COMP_M\t\tBIT(10)\n+#define PF0INT_OICR_PSM_PAGE_TSYN_TX_S\t\t11\n+#define PF0INT_OICR_PSM_PAGE_TSYN_TX_M\t\tBIT(11)\n+#define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_S\t12\n+#define PF0INT_OICR_PSM_PAGE_TSYN_EVNT_M\tBIT(12)\n+#define PF0INT_OICR_PSM_PAGE_TSYN_TGT_S\t\t13\n+#define PF0INT_OICR_PSM_PAGE_TSYN_TGT_M\t\tBIT(13)\n+#define PF0INT_OICR_PSM_PAGE_HLP_RDY_S\t\t14\n+#define PF0INT_OICR_PSM_PAGE_HLP_RDY_M\t\tBIT(14)\n+#define PF0INT_OICR_PSM_PAGE_CPM_RDY_S\t\t15\n+#define PF0INT_OICR_PSM_PAGE_CPM_RDY_M\t\tBIT(15)\n+#define PF0INT_OICR_PSM_PAGE_ECC_ERR_S\t\t16\n+#define PF0INT_OICR_PSM_PAGE_ECC_ERR_M\t\tBIT(16)\n+#define PF0INT_OICR_PSM_PAGE_RSV2_S\t\t17\n+#define PF0INT_OICR_PSM_PAGE_RSV2_M\t\tMAKEMASK(0x3, 17)\n+#define PF0INT_OICR_PSM_PAGE_MAL_DETECT_S\t19\n+#define PF0INT_OICR_PSM_PAGE_MAL_DETECT_M\tBIT(19)\n+#define PF0INT_OICR_PSM_PAGE_GRST_S\t\t20\n+#define PF0INT_OICR_PSM_PAGE_GRST_M\t\tBIT(20)\n+#define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_S\t21\n+#define PF0INT_OICR_PSM_PAGE_PCI_EXCEPTION_M\tBIT(21)\n+#define PF0INT_OICR_PSM_PAGE_GPIO_S\t\t22\n+#define PF0INT_OICR_PSM_PAGE_GPIO_M\t\tBIT(22)\n+#define PF0INT_OICR_PSM_PAGE_RSV3_S\t\t23\n+#define PF0INT_OICR_PSM_PAGE_RSV3_M\t\tBIT(23)\n+#define PF0INT_OICR_PSM_PAGE_STORM_DETECT_S\t24\n+#define PF0INT_OICR_PSM_PAGE_STORM_DETECT_M\tBIT(24)\n+#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_S 25\n+#define PF0INT_OICR_PSM_PAGE_LINK_STAT_CHANGE_M BIT(25)\n+#define PF0INT_OICR_PSM_PAGE_HMC_ERR_S\t\t26\n+#define PF0INT_OICR_PSM_PAGE_HMC_ERR_M\t\tBIT(26)\n+#define PF0INT_OICR_PSM_PAGE_PE_PUSH_S\t\t27\n+#define PF0INT_OICR_PSM_PAGE_PE_PUSH_M\t\tBIT(27)\n+#define PF0INT_OICR_PSM_PAGE_PE_CRITERR_S\t28\n+#define PF0INT_OICR_PSM_PAGE_PE_CRITERR_M\tBIT(28)\n+#define PF0INT_OICR_PSM_PAGE_VFLR_S\t\t29\n+#define PF0INT_OICR_PSM_PAGE_VFLR_M\t\tBIT(29)\n+#define PF0INT_OICR_PSM_PAGE_XLR_HW_DONE_S\t30\n+#define PF0INT_OICR_PSM_PAGE_XLR_HW_DONE_M\tBIT(30)\n+#define PF0INT_OICR_PSM_PAGE_SWINT_S\t\t31\n+#define PF0INT_OICR_PSM_PAGE_SWINT_M\t\tBIT(31)\n+#define QRX_TAIL_PAGE(_QRX)\t\t\t(0x03800000 + ((_QRX) * 4096)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define QRX_TAIL_PAGE_MAX_INDEX\t\t\t2047\n+#define QRX_TAIL_PAGE_TAIL_S\t\t\t0\n+#define QRX_TAIL_PAGE_TAIL_M\t\t\tMAKEMASK(0x1FFF, 0)\n+#define QTX_COMM_DBELL_PAGE(_DBQM)\t\t(0x04000000 + ((_DBQM) * 4096)) /* _i=0...16383 */ /* Reset Source: CORER */\n+#define QTX_COMM_DBELL_PAGE_MAX_INDEX\t\t16383\n+#define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_S\t0\n+#define QTX_COMM_DBELL_PAGE_QTX_COMM_DBELL_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define QTX_COMM_DBLQ_DBELL_PAGE(_DBLQ)\t\t(0x02F00000 + ((_DBLQ) * 8)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define QTX_COMM_DBLQ_DBELL_PAGE_MAX_INDEX\t255\n+#define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_S\t\t0\n+#define QTX_COMM_DBLQ_DBELL_PAGE_TAIL_M\t\tMAKEMASK(0x1FFF, 0)\n+#define VSI_MBX_ARQBAH(_VSI)\t\t\t(0x02000018 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ARQBAH_MAX_INDEX\t\t767\n+#define VSI_MBX_ARQBAH_ARQBAH_S\t\t\t0\n+#define VSI_MBX_ARQBAH_ARQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VSI_MBX_ARQBAL(_VSI)\t\t\t(0x02000014 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ARQBAL_MAX_INDEX\t\t767\n+#define VSI_MBX_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define VSI_MBX_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VSI_MBX_ARQBAL_ARQBAL_S\t\t\t6\n+#define VSI_MBX_ARQBAL_ARQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VSI_MBX_ARQH(_VSI)\t\t\t(0x02000020 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ARQH_MAX_INDEX\t\t\t767\n+#define VSI_MBX_ARQH_ARQH_S\t\t\t0\n+#define VSI_MBX_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VSI_MBX_ARQLEN(_VSI)\t\t\t(0x0200001C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ARQLEN_MAX_INDEX\t\t767\n+#define VSI_MBX_ARQLEN_ARQLEN_S\t\t\t0\n+#define VSI_MBX_ARQLEN_ARQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VSI_MBX_ARQLEN_ARQVFE_S\t\t\t28\n+#define VSI_MBX_ARQLEN_ARQVFE_M\t\t\tBIT(28)\n+#define VSI_MBX_ARQLEN_ARQOVFL_S\t\t29\n+#define VSI_MBX_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define VSI_MBX_ARQLEN_ARQCRIT_S\t\t30\n+#define VSI_MBX_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define VSI_MBX_ARQLEN_ARQENABLE_S\t\t31\n+#define VSI_MBX_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define VSI_MBX_ARQT(_VSI)\t\t\t(0x02000024 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ARQT_MAX_INDEX\t\t\t767\n+#define VSI_MBX_ARQT_ARQT_S\t\t\t0\n+#define VSI_MBX_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VSI_MBX_ATQBAH(_VSI)\t\t\t(0x02000004 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ATQBAH_MAX_INDEX\t\t767\n+#define VSI_MBX_ATQBAH_ATQBAH_S\t\t\t0\n+#define VSI_MBX_ATQBAH_ATQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VSI_MBX_ATQBAL(_VSI)\t\t\t(0x02000000 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ATQBAL_MAX_INDEX\t\t767\n+#define VSI_MBX_ATQBAL_ATQBAL_S\t\t\t6\n+#define VSI_MBX_ATQBAL_ATQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VSI_MBX_ATQH(_VSI)\t\t\t(0x0200000C + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ATQH_MAX_INDEX\t\t\t767\n+#define VSI_MBX_ATQH_ATQH_S\t\t\t0\n+#define VSI_MBX_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VSI_MBX_ATQLEN(_VSI)\t\t\t(0x02000008 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ATQLEN_MAX_INDEX\t\t767\n+#define VSI_MBX_ATQLEN_ATQLEN_S\t\t\t0\n+#define VSI_MBX_ATQLEN_ATQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VSI_MBX_ATQLEN_ATQVFE_S\t\t\t28\n+#define VSI_MBX_ATQLEN_ATQVFE_M\t\t\tBIT(28)\n+#define VSI_MBX_ATQLEN_ATQOVFL_S\t\t29\n+#define VSI_MBX_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define VSI_MBX_ATQLEN_ATQCRIT_S\t\t30\n+#define VSI_MBX_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define VSI_MBX_ATQLEN_ATQENABLE_S\t\t31\n+#define VSI_MBX_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define VSI_MBX_ATQT(_VSI)\t\t\t(0x02000010 + ((_VSI) * 4096)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_MBX_ATQT_MAX_INDEX\t\t\t767\n+#define VSI_MBX_ATQT_ATQT_S\t\t\t0\n+#define VSI_MBX_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define GL_ACL_ACCESS_CMD\t\t\t0x00391000 /* Reset Source: CORER */\n+#define GL_ACL_ACCESS_CMD_TABLE_ID_S\t\t0\n+#define GL_ACL_ACCESS_CMD_TABLE_ID_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_ACL_ACCESS_CMD_ENTRY_INDEX_S\t\t8\n+#define GL_ACL_ACCESS_CMD_ENTRY_INDEX_M\t\tMAKEMASK(0xFFF, 8)\n+#define GL_ACL_ACCESS_CMD_OPERATION_S\t\t20\n+#define GL_ACL_ACCESS_CMD_OPERATION_M\t\tBIT(20)\n+#define GL_ACL_ACCESS_CMD_OBJ_TYPE_S\t\t24\n+#define GL_ACL_ACCESS_CMD_OBJ_TYPE_M\t\tMAKEMASK(0xF, 24)\n+#define GL_ACL_ACCESS_CMD_EXECUTE_S\t\t31\n+#define GL_ACL_ACCESS_CMD_EXECUTE_M\t\tBIT(31)\n+#define GL_ACL_ACCESS_STATUS\t\t\t0x00391004 /* Reset Source: CORER */\n+#define GL_ACL_ACCESS_STATUS_BUSY_S\t\t0\n+#define GL_ACL_ACCESS_STATUS_BUSY_M\t\tBIT(0)\n+#define GL_ACL_ACCESS_STATUS_DONE_S\t\t1\n+#define GL_ACL_ACCESS_STATUS_DONE_M\t\tBIT(1)\n+#define GL_ACL_ACCESS_STATUS_ERROR_S\t\t2\n+#define GL_ACL_ACCESS_STATUS_ERROR_M\t\tBIT(2)\n+#define GL_ACL_ACCESS_STATUS_OPERATION_S\t3\n+#define GL_ACL_ACCESS_STATUS_OPERATION_M\tBIT(3)\n+#define GL_ACL_ACCESS_STATUS_ERROR_CODE_S\t4\n+#define GL_ACL_ACCESS_STATUS_ERROR_CODE_M\tMAKEMASK(0xF, 4)\n+#define GL_ACL_ACCESS_STATUS_TABLE_ID_S\t\t8\n+#define GL_ACL_ACCESS_STATUS_TABLE_ID_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_ACL_ACCESS_STATUS_ENTRY_INDEX_S\t16\n+#define GL_ACL_ACCESS_STATUS_ENTRY_INDEX_M\tMAKEMASK(0xFFF, 16)\n+#define GL_ACL_ACCESS_STATUS_OBJ_TYPE_S\t\t28\n+#define GL_ACL_ACCESS_STATUS_OBJ_TYPE_M\t\tMAKEMASK(0xF, 28)\n+#define GL_ACL_ACTMEM_ACT(_i)\t\t\t(0x00393824 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GL_ACL_ACTMEM_ACT_MAX_INDEX\t\t1\n+#define GL_ACL_ACTMEM_ACT_VALUE_S\t\t0\n+#define GL_ACL_ACTMEM_ACT_VALUE_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_ACL_ACTMEM_ACT_MDID_S\t\t20\n+#define GL_ACL_ACTMEM_ACT_MDID_M\t\tMAKEMASK(0x3F, 20)\n+#define GL_ACL_ACTMEM_ACT_PRIORITY_S\t\t28\n+#define GL_ACL_ACTMEM_ACT_PRIORITY_M\t\tMAKEMASK(0x7, 28)\n+#define GL_ACL_CHICKEN_REGISTER\t\t\t0x00393810 /* Reset Source: CORER */\n+#define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_S 0\n+#define GL_ACL_CHICKEN_REGISTER_TCAM_DATA_POL_CH_M BIT(0)\n+#define GL_ACL_CHICKEN_REGISTER_TCAM_ADDR_POL_CH_S 1\n+#define GL_ACL_CHICKEN_REGISTER_TCAM_ADDR_POL_CH_M BIT(1)\n+#define GL_ACL_DEFAULT_ACT(_i)\t\t\t(0x00391168 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GL_ACL_DEFAULT_ACT_MAX_INDEX\t\t15\n+#define GL_ACL_DEFAULT_ACT_VALUE_S\t\t0\n+#define GL_ACL_DEFAULT_ACT_VALUE_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_ACL_DEFAULT_ACT_MDID_S\t\t20\n+#define GL_ACL_DEFAULT_ACT_MDID_M\t\tMAKEMASK(0x3F, 20)\n+#define GL_ACL_DEFAULT_ACT_PRIORITY_S\t\t28\n+#define GL_ACL_DEFAULT_ACT_PRIORITY_M\t\tMAKEMASK(0x7, 28)\n+#define GL_ACL_PROFILE_BWSB_SEL(_i)\t\t(0x00391008 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GL_ACL_PROFILE_BWSB_SEL_MAX_INDEX\t31\n+#define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_S\t0\n+#define GL_ACL_PROFILE_BWSB_SEL_BSB_SRC_OFF_M\tMAKEMASK(0x3F, 0)\n+#define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_S\t8\n+#define GL_ACL_PROFILE_BWSB_SEL_WSB_SRC_OFF_M\tMAKEMASK(0x1F, 8)\n+#define GL_ACL_PROFILE_DWSB_SEL(_i)\t\t(0x00391088 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GL_ACL_PROFILE_DWSB_SEL_MAX_INDEX\t15\n+#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_S 0\n+#define GL_ACL_PROFILE_DWSB_SEL_DWORD_SEL_OFF_M MAKEMASK(0xF, 0)\n+#define GL_ACL_PROFILE_PF_CFG(_i)\t\t(0x003910C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GL_ACL_PROFILE_PF_CFG_MAX_INDEX\t\t7\n+#define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_S\t0\n+#define GL_ACL_PROFILE_PF_CFG_SCEN_SEL_M\tMAKEMASK(0x3F, 0)\n+#define GL_ACL_PROFILE_RC_CFG(_i)\t\t(0x003910E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GL_ACL_PROFILE_RC_CFG_MAX_INDEX\t\t7\n+#define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_S\t0\n+#define GL_ACL_PROFILE_RC_CFG_LOW_BOUND_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_ACL_PROFILE_RC_CFG_HIGH_BOUND_S\t16\n+#define GL_ACL_PROFILE_RC_CFG_HIGH_BOUND_M\tMAKEMASK(0xFFFF, 16)\n+#define GL_ACL_PROFILE_RCF_MASK(_i)\t\t(0x00391108 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GL_ACL_PROFILE_RCF_MASK_MAX_INDEX\t7\n+#define GL_ACL_PROFILE_RCF_MASK_MASK_S\t\t0\n+#define GL_ACL_PROFILE_RCF_MASK_MASK_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_ACL_SCENARIO_ACT_CFG(_i)\t\t(0x003938AC + ((_i) * 4)) /* _i=0...19 */ /* Reset Source: CORER */\n+#define GL_ACL_SCENARIO_ACT_CFG_MAX_INDEX\t19\n+#define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_S\t0\n+#define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_SEL_M\tMAKEMASK(0xF, 0)\n+#define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_EN_S\t8\n+#define GL_ACL_SCENARIO_ACT_CFG_ACTMEM_EN_M\tBIT(8)\n+#define GL_ACL_SCENARIO_CFG_H(_i)\t\t(0x0039386C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GL_ACL_SCENARIO_CFG_H_MAX_INDEX\t\t15\n+#define GL_ACL_SCENARIO_CFG_H_SELECT4_S\t\t0\n+#define GL_ACL_SCENARIO_CFG_H_SELECT4_M\t\tMAKEMASK(0x1F, 0)\n+#define GL_ACL_SCENARIO_CFG_H_CHUNKMASK_S\t8\n+#define GL_ACL_SCENARIO_CFG_H_CHUNKMASK_M\tMAKEMASK(0xFF, 8)\n+#define GL_ACL_SCENARIO_CFG_H_START_COMPARE_S\t24\n+#define GL_ACL_SCENARIO_CFG_H_START_COMPARE_M\tBIT(24)\n+#define GL_ACL_SCENARIO_CFG_H_START_SET_S\t28\n+#define GL_ACL_SCENARIO_CFG_H_START_SET_M\tBIT(28)\n+#define GL_ACL_SCENARIO_CFG_L(_i)\t\t(0x0039382C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GL_ACL_SCENARIO_CFG_L_MAX_INDEX\t\t15\n+#define GL_ACL_SCENARIO_CFG_L_SELECT0_S\t\t0\n+#define GL_ACL_SCENARIO_CFG_L_SELECT0_M\t\tMAKEMASK(0x7F, 0)\n+#define GL_ACL_SCENARIO_CFG_L_SELECT1_S\t\t8\n+#define GL_ACL_SCENARIO_CFG_L_SELECT1_M\t\tMAKEMASK(0x7F, 8)\n+#define GL_ACL_SCENARIO_CFG_L_SELECT2_S\t\t16\n+#define GL_ACL_SCENARIO_CFG_L_SELECT2_M\t\tMAKEMASK(0x7F, 16)\n+#define GL_ACL_SCENARIO_CFG_L_SELECT3_S\t\t24\n+#define GL_ACL_SCENARIO_CFG_L_SELECT3_M\t\tMAKEMASK(0x7F, 24)\n+#define GL_ACL_TCAM_KEY_H\t\t\t0x00393818 /* Reset Source: CORER */\n+#define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_S 0\n+#define GL_ACL_TCAM_KEY_H_GL_ACL_FFU_TCAM_KEY_H_M MAKEMASK(0xFF, 0)\n+#define GL_ACL_TCAM_KEY_INV_H\t\t\t0x00393820 /* Reset Source: CORER */\n+#define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_S 0\n+#define GL_ACL_TCAM_KEY_INV_H_GL_ACL_FFU_TCAM_KEY_INV_H_M MAKEMASK(0xFF, 0)\n+#define GL_ACL_TCAM_KEY_INV_L\t\t\t0x0039381C /* Reset Source: CORER */\n+#define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_S 0\n+#define GL_ACL_TCAM_KEY_INV_L_GL_ACL_FFU_TCAM_KEY_INV_L_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GL_ACL_TCAM_KEY_L\t\t\t0x00393814 /* Reset Source: CORER */\n+#define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_S 0\n+#define GL_ACL_TCAM_KEY_L_GL_ACL_FFU_TCAM_KEY_L_M MAKEMASK(0xFFFFFFFF, 0)\n+#define VSI_ACL_DEF_SEL(_VSI)\t\t\t(0x00391800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_ACL_DEF_SEL_MAX_INDEX\t\t767\n+#define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_S\t0\n+#define VSI_ACL_DEF_SEL_RX_PROFILE_MISS_SEL_M\tMAKEMASK(0x3, 0)\n+#define VSI_ACL_DEF_SEL_RX_TABLES_MISS_SEL_S\t4\n+#define VSI_ACL_DEF_SEL_RX_TABLES_MISS_SEL_M\tMAKEMASK(0x3, 4)\n+#define VSI_ACL_DEF_SEL_TX_PROFILE_MISS_SEL_S\t8\n+#define VSI_ACL_DEF_SEL_TX_PROFILE_MISS_SEL_M\tMAKEMASK(0x3, 8)\n+#define VSI_ACL_DEF_SEL_TX_TABLES_MISS_SEL_S\t12\n+#define VSI_ACL_DEF_SEL_TX_TABLES_MISS_SEL_M\tMAKEMASK(0x3, 12)\n+#define GL_SWT_L2TAG0(_i)\t\t\t(0x000492A8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GL_SWT_L2TAG0_MAX_INDEX\t\t\t7\n+#define GL_SWT_L2TAG0_DATA_S\t\t\t0\n+#define GL_SWT_L2TAG0_DATA_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_SWT_L2TAG1(_i)\t\t\t(0x000492C8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GL_SWT_L2TAG1_MAX_INDEX\t\t\t7\n+#define GL_SWT_L2TAG1_DATA_S\t\t\t0\n+#define GL_SWT_L2TAG1_DATA_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_SWT_L2TAGCTRL(_i)\t\t\t(0x001D2660 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GL_SWT_L2TAGCTRL_MAX_INDEX\t\t7\n+#define GL_SWT_L2TAGCTRL_LENGTH_S\t\t0\n+#define GL_SWT_L2TAGCTRL_LENGTH_M\t\tMAKEMASK(0x7F, 0)\n+#define GL_SWT_L2TAGCTRL_HAS_UP_S\t\t7\n+#define GL_SWT_L2TAGCTRL_HAS_UP_M\t\tBIT(7)\n+#define GL_SWT_L2TAGCTRL_ISVLAN_S\t\t9\n+#define GL_SWT_L2TAGCTRL_ISVLAN_M\t\tBIT(9)\n+#define GL_SWT_L2TAGCTRL_INNERUP_S\t\t10\n+#define GL_SWT_L2TAGCTRL_INNERUP_M\t\tBIT(10)\n+#define GL_SWT_L2TAGCTRL_OUTERUP_S\t\t11\n+#define GL_SWT_L2TAGCTRL_OUTERUP_M\t\tBIT(11)\n+#define GL_SWT_L2TAGCTRL_LONG_S\t\t\t12\n+#define GL_SWT_L2TAGCTRL_LONG_M\t\t\tBIT(12)\n+#define GL_SWT_L2TAGCTRL_ISMPLS_S\t\t13\n+#define GL_SWT_L2TAGCTRL_ISMPLS_M\t\tBIT(13)\n+#define GL_SWT_L2TAGCTRL_ISNSH_S\t\t14\n+#define GL_SWT_L2TAGCTRL_ISNSH_M\t\tBIT(14)\n+#define GL_SWT_L2TAGCTRL_ETHERTYPE_S\t\t16\n+#define GL_SWT_L2TAGCTRL_ETHERTYPE_M\t\tMAKEMASK(0xFFFF, 16)\n+#define GL_SWT_L2TAGRXEB(_i)\t\t\t(0x00052000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GL_SWT_L2TAGRXEB_MAX_INDEX\t\t7\n+#define GL_SWT_L2TAGRXEB_OFFSET_S\t\t0\n+#define GL_SWT_L2TAGRXEB_OFFSET_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_SWT_L2TAGRXEB_LENGTH_S\t\t8\n+#define GL_SWT_L2TAGRXEB_LENGTH_M\t\tMAKEMASK(0x3, 8)\n+#define GL_SWT_L2TAGTXIB(_i)\t\t\t(0x000492E8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GL_SWT_L2TAGTXIB_MAX_INDEX\t\t7\n+#define GL_SWT_L2TAGTXIB_OFFSET_S\t\t0\n+#define GL_SWT_L2TAGTXIB_OFFSET_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_SWT_L2TAGTXIB_LENGTH_S\t\t8\n+#define GL_SWT_L2TAGTXIB_LENGTH_M\t\tMAKEMASK(0x3, 8)\n+#define PRT_TDPUL2TAGSEN\t\t\t0x00040BA0 /* Reset Source: CORER */\n+#define PRT_TDPUL2TAGSEN_ENABLE_S\t\t0\n+#define PRT_TDPUL2TAGSEN_ENABLE_M\t\tMAKEMASK(0xFF, 0)\n+#define PRT_TDPUL2TAGSEN_NONLAST_TAG_S\t\t8\n+#define PRT_TDPUL2TAGSEN_NONLAST_TAG_M\t\tMAKEMASK(0xFF, 8)\n+#define GLCM_PE_CACHESIZE\t\t\t0x005046B4 /* Reset Source: CORER */\n+#define GLCM_PE_CACHESIZE_WORD_SIZE_S\t\t0\n+#define GLCM_PE_CACHESIZE_WORD_SIZE_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLCM_PE_CACHESIZE_SETS_S\t\t12\n+#define GLCM_PE_CACHESIZE_SETS_M\t\tMAKEMASK(0xF, 12)\n+#define GLCM_PE_CACHESIZE_WAYS_S\t\t16\n+#define GLCM_PE_CACHESIZE_WAYS_M\t\tMAKEMASK(0x1FF, 16)\n+#define GLCOMM_CQ_CTL(_CQ)\t\t\t(0x000F0000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLCOMM_CQ_CTL_MAX_INDEX\t\t\t511\n+#define GLCOMM_CQ_CTL_COMP_TYPE_S\t\t0\n+#define GLCOMM_CQ_CTL_COMP_TYPE_M\t\tMAKEMASK(0x7, 0)\n+#define GLCOMM_CQ_CTL_CMD_S\t\t\t4\n+#define GLCOMM_CQ_CTL_CMD_M\t\t\tMAKEMASK(0x7, 4)\n+#define GLCOMM_CQ_CTL_ID_S\t\t\t16\n+#define GLCOMM_CQ_CTL_ID_M\t\t\tMAKEMASK(0x3FFF, 16)\n+#define GLCOMM_MIN_MAX_PKT\t\t\t0x000FC064 /* Reset Source: CORER */\n+#define GLCOMM_MIN_MAX_PKT_MAHDL_S\t\t0\n+#define GLCOMM_MIN_MAX_PKT_MAHDL_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLCOMM_MIN_MAX_PKT_MIHDL_S\t\t16\n+#define GLCOMM_MIN_MAX_PKT_MIHDL_M\t\tMAKEMASK(0x3F, 16)\n+#define GLCOMM_MIN_MAX_PKT_LSO_COMS_MIHDL_S\t22\n+#define GLCOMM_MIN_MAX_PKT_LSO_COMS_MIHDL_M\tMAKEMASK(0x3FF, 22)\n+#define GLCOMM_PKT_SHAPER_PROF(_i)\t\t(0x002D2DA8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLCOMM_PKT_SHAPER_PROF_MAX_INDEX\t7\n+#define GLCOMM_PKT_SHAPER_PROF_PKTCNT_S\t\t0\n+#define GLCOMM_PKT_SHAPER_PROF_PKTCNT_M\t\tMAKEMASK(0x3F, 0)\n+#define GLCOMM_QTX_CNTX_CTL\t\t\t0x002D2DC8 /* Reset Source: CORER */\n+#define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_S\t\t0\n+#define GLCOMM_QTX_CNTX_CTL_QUEUE_ID_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLCOMM_QTX_CNTX_CTL_CMD_S\t\t16\n+#define GLCOMM_QTX_CNTX_CTL_CMD_M\t\tMAKEMASK(0x7, 16)\n+#define GLCOMM_QTX_CNTX_CTL_CMD_EXEC_S\t\t19\n+#define GLCOMM_QTX_CNTX_CTL_CMD_EXEC_M\t\tBIT(19)\n+#define GLCOMM_QTX_CNTX_DATA(_i)\t\t(0x002D2D40 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: CORER */\n+#define GLCOMM_QTX_CNTX_DATA_MAX_INDEX\t\t9\n+#define GLCOMM_QTX_CNTX_DATA_DATA_S\t\t0\n+#define GLCOMM_QTX_CNTX_DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLCOMM_QTX_CNTX_STAT\t\t\t0x002D2DCC /* Reset Source: CORER */\n+#define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_S\t0\n+#define GLCOMM_QTX_CNTX_STAT_CMD_IN_PROG_M\tBIT(0)\n+#define GLCOMM_QUANTA_PROF(_i)\t\t\t(0x002D2D68 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLCOMM_QUANTA_PROF_MAX_INDEX\t\t15\n+#define GLCOMM_QUANTA_PROF_QUANTA_SIZE_S\t0\n+#define GLCOMM_QUANTA_PROF_QUANTA_SIZE_M\tMAKEMASK(0x3FFF, 0)\n+#define GLCOMM_QUANTA_PROF_MAX_CMD_S\t\t16\n+#define GLCOMM_QUANTA_PROF_MAX_CMD_M\t\tMAKEMASK(0xFF, 16)\n+#define GLCOMM_QUANTA_PROF_MAX_DESC_S\t\t24\n+#define GLCOMM_QUANTA_PROF_MAX_DESC_M\t\tMAKEMASK(0x3F, 24)\n+#define GLLAN_TCLAN_CACHE_CTL\t\t\t0x000FC0B8 /* Reset Source: CORER */\n+#define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_S 0\n+#define GLLAN_TCLAN_CACHE_CTL_MIN_FETCH_THRESH_M MAKEMASK(0x3F, 0)\n+#define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_S\t6\n+#define GLLAN_TCLAN_CACHE_CTL_FETCH_CL_ALIGN_M\tBIT(6)\n+#define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_S 7\n+#define GLLAN_TCLAN_CACHE_CTL_MIN_ALLOC_THRESH_M MAKEMASK(0x7F, 7)\n+#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_S 14\n+#define GLLAN_TCLAN_CACHE_CTL_CACHE_ENTRY_CNT_M MAKEMASK(0xFF, 14)\n+#define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_S\t22\n+#define GLLAN_TCLAN_CACHE_CTL_CACHE_DESC_LIM_M\tMAKEMASK(0x3FF, 22)\n+#define GLTCLAN_CQ_CNTX0(_CQ)\t\t\t(0x000F0800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX0_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_S\t0\n+#define GLTCLAN_CQ_CNTX0_RING_ADDR_LSB_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX1(_CQ)\t\t\t(0x000F1000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX1_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_S\t0\n+#define GLTCLAN_CQ_CNTX1_RING_ADDR_MSB_M\tMAKEMASK(0x1FFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX10(_CQ)\t\t\t(0x000F5800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX10_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX10_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX11(_CQ)\t\t\t(0x000F6000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX11_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX11_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX12(_CQ)\t\t\t(0x000F6800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX12_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX12_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX13(_CQ)\t\t\t(0x000F7000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX13_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX13_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX14(_CQ)\t\t\t(0x000F7800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX14_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX14_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX15(_CQ)\t\t\t(0x000F8000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX15_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX15_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX16(_CQ)\t\t\t(0x000F8800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX16_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX16_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX17(_CQ)\t\t\t(0x000F9000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX17_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX17_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX18(_CQ)\t\t\t(0x000F9800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX18_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX18_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX19(_CQ)\t\t\t(0x000FA000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX19_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX19_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX2(_CQ)\t\t\t(0x000F1800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX2_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX2_RING_LEN_S\t\t0\n+#define GLTCLAN_CQ_CNTX2_RING_LEN_M\t\tMAKEMASK(0x3FFFF, 0)\n+#define GLTCLAN_CQ_CNTX20(_CQ)\t\t\t(0x000FA800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX20_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX20_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX21(_CQ)\t\t\t(0x000FB000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX21_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX21_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX3(_CQ)\t\t\t(0x000F2000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX3_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX3_GENERATION_S\t\t0\n+#define GLTCLAN_CQ_CNTX3_GENERATION_M\t\tBIT(0)\n+#define GLTCLAN_CQ_CNTX3_CQ_WR_PTR_S\t\t1\n+#define GLTCLAN_CQ_CNTX3_CQ_WR_PTR_M\t\tMAKEMASK(0x3FFFFF, 1)\n+#define GLTCLAN_CQ_CNTX4(_CQ)\t\t\t(0x000F2800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX4_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX4_PF_NUM_S\t\t0\n+#define GLTCLAN_CQ_CNTX4_PF_NUM_M\t\tMAKEMASK(0x7, 0)\n+#define GLTCLAN_CQ_CNTX4_VMVF_NUM_S\t\t3\n+#define GLTCLAN_CQ_CNTX4_VMVF_NUM_M\t\tMAKEMASK(0x3FF, 3)\n+#define GLTCLAN_CQ_CNTX4_VMVF_TYPE_S\t\t13\n+#define GLTCLAN_CQ_CNTX4_VMVF_TYPE_M\t\tMAKEMASK(0x3, 13)\n+#define GLTCLAN_CQ_CNTX5(_CQ)\t\t\t(0x000F3000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX5_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX5_TPH_EN_S\t\t0\n+#define GLTCLAN_CQ_CNTX5_TPH_EN_M\t\tBIT(0)\n+#define GLTCLAN_CQ_CNTX5_CPU_ID_S\t\t1\n+#define GLTCLAN_CQ_CNTX5_CPU_ID_M\t\tMAKEMASK(0xFF, 1)\n+#define GLTCLAN_CQ_CNTX5_FLUSH_ON_ITR_DIS_S\t9\n+#define GLTCLAN_CQ_CNTX5_FLUSH_ON_ITR_DIS_M\tBIT(9)\n+#define GLTCLAN_CQ_CNTX6(_CQ)\t\t\t(0x000F3800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX6_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX6_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX7(_CQ)\t\t\t(0x000F4000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX7_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX7_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX8(_CQ)\t\t\t(0x000F4800 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX8_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX8_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCLAN_CQ_CNTX9(_CQ)\t\t\t(0x000F5000 + ((_CQ) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLTCLAN_CQ_CNTX9_MAX_INDEX\t\t511\n+#define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_S\t\t0\n+#define GLTCLAN_CQ_CNTX9_CQ_CACHLINE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define QTX_COMM_DBELL(_DBQM)\t\t\t(0x002C0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */\n+#define QTX_COMM_DBELL_MAX_INDEX\t\t16383\n+#define QTX_COMM_DBELL_QTX_COMM_DBELL_S\t\t0\n+#define QTX_COMM_DBELL_QTX_COMM_DBELL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define QTX_COMM_DBLQ_CNTX(_i, _DBLQ)\t\t(0x002D0000 + ((_i) * 1024 + (_DBLQ) * 4)) /* _i=0...4, _DBLQ=0...255 */ /* Reset Source: CORER */\n+#define QTX_COMM_DBLQ_CNTX_MAX_INDEX\t\t4\n+#define QTX_COMM_DBLQ_CNTX_DATA_S\t\t0\n+#define QTX_COMM_DBLQ_CNTX_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define QTX_COMM_DBLQ_DBELL(_DBLQ)\t\t(0x002D1400 + ((_DBLQ) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define QTX_COMM_DBLQ_DBELL_MAX_INDEX\t\t255\n+#define QTX_COMM_DBLQ_DBELL_TAIL_S\t\t0\n+#define QTX_COMM_DBLQ_DBELL_TAIL_M\t\tMAKEMASK(0x1FFF, 0)\n+#define QTX_COMM_HEAD(_DBQM)\t\t\t(0x000E0000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */\n+#define QTX_COMM_HEAD_MAX_INDEX\t\t\t16383\n+#define QTX_COMM_HEAD_HEAD_S\t\t\t0\n+#define QTX_COMM_HEAD_HEAD_M\t\t\tMAKEMASK(0x1FFF, 0)\n+#define QTX_COMM_HEAD_RS_PENDING_S\t\t16\n+#define QTX_COMM_HEAD_RS_PENDING_M\t\tBIT(16)\n+#define GL_FW_TOOL_ARQBAH\t\t\t0x000801C0 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ARQBAH_ARQBAH_S\t\t0\n+#define GL_FW_TOOL_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_FW_TOOL_ARQBAL\t\t\t0x000800C0 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define GL_FW_TOOL_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define GL_FW_TOOL_ARQBAL_ARQBAL_S\t\t6\n+#define GL_FW_TOOL_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define GL_FW_TOOL_ARQH\t\t\t\t0x000803C0 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ARQH_ARQH_S\t\t\t0\n+#define GL_FW_TOOL_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define GL_FW_TOOL_ARQLEN\t\t\t0x000802C0 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ARQLEN_ARQLEN_S\t\t0\n+#define GL_FW_TOOL_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define GL_FW_TOOL_ARQLEN_ARQVFE_S\t\t28\n+#define GL_FW_TOOL_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define GL_FW_TOOL_ARQLEN_ARQOVFL_S\t\t29\n+#define GL_FW_TOOL_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define GL_FW_TOOL_ARQLEN_ARQCRIT_S\t\t30\n+#define GL_FW_TOOL_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define GL_FW_TOOL_ARQLEN_ARQENABLE_S\t\t31\n+#define GL_FW_TOOL_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define GL_FW_TOOL_ARQT\t\t\t\t0x000804C0 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ARQT_ARQT_S\t\t\t0\n+#define GL_FW_TOOL_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define GL_FW_TOOL_ATQBAH\t\t\t0x00080140 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ATQBAH_ATQBAH_S\t\t0\n+#define GL_FW_TOOL_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_FW_TOOL_ATQBAL\t\t\t0x00080040 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_S\t\t0\n+#define GL_FW_TOOL_ATQBAL_ATQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define GL_FW_TOOL_ATQBAL_ATQBAL_S\t\t6\n+#define GL_FW_TOOL_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define GL_FW_TOOL_ATQH\t\t\t\t0x00080340 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ATQH_ATQH_S\t\t\t0\n+#define GL_FW_TOOL_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define GL_FW_TOOL_ATQLEN\t\t\t0x00080240 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ATQLEN_ATQLEN_S\t\t0\n+#define GL_FW_TOOL_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define GL_FW_TOOL_ATQLEN_ATQVFE_S\t\t28\n+#define GL_FW_TOOL_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define GL_FW_TOOL_ATQLEN_ATQOVFL_S\t\t29\n+#define GL_FW_TOOL_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define GL_FW_TOOL_ATQLEN_ATQCRIT_S\t\t30\n+#define GL_FW_TOOL_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define GL_FW_TOOL_ATQLEN_ATQENABLE_S\t\t31\n+#define GL_FW_TOOL_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define GL_FW_TOOL_ATQT\t\t\t\t0x00080440 /* Reset Source: EMPR */\n+#define GL_FW_TOOL_ATQT_ATQT_S\t\t\t0\n+#define GL_FW_TOOL_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define GL_MBX_PASID\t\t\t\t0x00231EC0 /* Reset Source: CORER */\n+#define GL_MBX_PASID_PASID_MODE_S\t\t0\n+#define GL_MBX_PASID_PASID_MODE_M\t\tBIT(0)\n+#define GL_MBX_PASID_PASID_MODE_VALID_S\t\t1\n+#define GL_MBX_PASID_PASID_MODE_VALID_M\t\tBIT(1)\n+#define PF_FW_ARQBAH\t\t\t\t0x00080180 /* Reset Source: EMPR */\n+#define PF_FW_ARQBAH_ARQBAH_S\t\t\t0\n+#define PF_FW_ARQBAH_ARQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF_FW_ARQBAL\t\t\t\t0x00080080 /* Reset Source: EMPR */\n+#define PF_FW_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF_FW_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF_FW_ARQBAL_ARQBAL_S\t\t\t6\n+#define PF_FW_ARQBAL_ARQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF_FW_ARQH\t\t\t\t0x00080380 /* Reset Source: EMPR */\n+#define PF_FW_ARQH_ARQH_S\t\t\t0\n+#define PF_FW_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_FW_ARQLEN\t\t\t\t0x00080280 /* Reset Source: EMPR */\n+#define PF_FW_ARQLEN_ARQLEN_S\t\t\t0\n+#define PF_FW_ARQLEN_ARQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_FW_ARQLEN_ARQVFE_S\t\t\t28\n+#define PF_FW_ARQLEN_ARQVFE_M\t\t\tBIT(28)\n+#define PF_FW_ARQLEN_ARQOVFL_S\t\t\t29\n+#define PF_FW_ARQLEN_ARQOVFL_M\t\t\tBIT(29)\n+#define PF_FW_ARQLEN_ARQCRIT_S\t\t\t30\n+#define PF_FW_ARQLEN_ARQCRIT_M\t\t\tBIT(30)\n+#define PF_FW_ARQLEN_ARQENABLE_S\t\t31\n+#define PF_FW_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF_FW_ARQT\t\t\t\t0x00080480 /* Reset Source: EMPR */\n+#define PF_FW_ARQT_ARQT_S\t\t\t0\n+#define PF_FW_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_FW_ATQBAH\t\t\t\t0x00080100 /* Reset Source: EMPR */\n+#define PF_FW_ATQBAH_ATQBAH_S\t\t\t0\n+#define PF_FW_ATQBAH_ATQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF_FW_ATQBAL\t\t\t\t0x00080000 /* Reset Source: EMPR */\n+#define PF_FW_ATQBAL_ATQBAL_LSB_S\t\t0\n+#define PF_FW_ATQBAL_ATQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF_FW_ATQBAL_ATQBAL_S\t\t\t6\n+#define PF_FW_ATQBAL_ATQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF_FW_ATQH\t\t\t\t0x00080300 /* Reset Source: EMPR */\n+#define PF_FW_ATQH_ATQH_S\t\t\t0\n+#define PF_FW_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_FW_ATQLEN\t\t\t\t0x00080200 /* Reset Source: EMPR */\n+#define PF_FW_ATQLEN_ATQLEN_S\t\t\t0\n+#define PF_FW_ATQLEN_ATQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_FW_ATQLEN_ATQVFE_S\t\t\t28\n+#define PF_FW_ATQLEN_ATQVFE_M\t\t\tBIT(28)\n+#define PF_FW_ATQLEN_ATQOVFL_S\t\t\t29\n+#define PF_FW_ATQLEN_ATQOVFL_M\t\t\tBIT(29)\n+#define PF_FW_ATQLEN_ATQCRIT_S\t\t\t30\n+#define PF_FW_ATQLEN_ATQCRIT_M\t\t\tBIT(30)\n+#define PF_FW_ATQLEN_ATQENABLE_S\t\t31\n+#define PF_FW_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF_FW_ATQT\t\t\t\t0x00080400 /* Reset Source: EMPR */\n+#define PF_FW_ATQT_ATQT_S\t\t\t0\n+#define PF_FW_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_MBX_ARQBAH\t\t\t\t0x0022E400 /* Reset Source: CORER */\n+#define PF_MBX_ARQBAH_ARQBAH_S\t\t\t0\n+#define PF_MBX_ARQBAH_ARQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF_MBX_ARQBAL\t\t\t\t0x0022E380 /* Reset Source: CORER */\n+#define PF_MBX_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF_MBX_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF_MBX_ARQBAL_ARQBAL_S\t\t\t6\n+#define PF_MBX_ARQBAL_ARQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF_MBX_ARQH\t\t\t\t0x0022E500 /* Reset Source: CORER */\n+#define PF_MBX_ARQH_ARQH_S\t\t\t0\n+#define PF_MBX_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_MBX_ARQLEN\t\t\t\t0x0022E480 /* Reset Source: CORER */\n+#define PF_MBX_ARQLEN_ARQLEN_S\t\t\t0\n+#define PF_MBX_ARQLEN_ARQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_MBX_ARQLEN_ARQVFE_S\t\t\t28\n+#define PF_MBX_ARQLEN_ARQVFE_M\t\t\tBIT(28)\n+#define PF_MBX_ARQLEN_ARQOVFL_S\t\t\t29\n+#define PF_MBX_ARQLEN_ARQOVFL_M\t\t\tBIT(29)\n+#define PF_MBX_ARQLEN_ARQCRIT_S\t\t\t30\n+#define PF_MBX_ARQLEN_ARQCRIT_M\t\t\tBIT(30)\n+#define PF_MBX_ARQLEN_ARQENABLE_S\t\t31\n+#define PF_MBX_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF_MBX_ARQT\t\t\t\t0x0022E580 /* Reset Source: CORER */\n+#define PF_MBX_ARQT_ARQT_S\t\t\t0\n+#define PF_MBX_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_MBX_ATQBAH\t\t\t\t0x0022E180 /* Reset Source: CORER */\n+#define PF_MBX_ATQBAH_ATQBAH_S\t\t\t0\n+#define PF_MBX_ATQBAH_ATQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF_MBX_ATQBAL\t\t\t\t0x0022E100 /* Reset Source: CORER */\n+#define PF_MBX_ATQBAL_ATQBAL_S\t\t\t6\n+#define PF_MBX_ATQBAL_ATQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF_MBX_ATQH\t\t\t\t0x0022E280 /* Reset Source: CORER */\n+#define PF_MBX_ATQH_ATQH_S\t\t\t0\n+#define PF_MBX_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_MBX_ATQLEN\t\t\t\t0x0022E200 /* Reset Source: CORER */\n+#define PF_MBX_ATQLEN_ATQLEN_S\t\t\t0\n+#define PF_MBX_ATQLEN_ATQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_MBX_ATQLEN_ATQVFE_S\t\t\t28\n+#define PF_MBX_ATQLEN_ATQVFE_M\t\t\tBIT(28)\n+#define PF_MBX_ATQLEN_ATQOVFL_S\t\t\t29\n+#define PF_MBX_ATQLEN_ATQOVFL_M\t\t\tBIT(29)\n+#define PF_MBX_ATQLEN_ATQCRIT_S\t\t\t30\n+#define PF_MBX_ATQLEN_ATQCRIT_M\t\t\tBIT(30)\n+#define PF_MBX_ATQLEN_ATQENABLE_S\t\t31\n+#define PF_MBX_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF_MBX_ATQT\t\t\t\t0x0022E300 /* Reset Source: CORER */\n+#define PF_MBX_ATQT_ATQT_S\t\t\t0\n+#define PF_MBX_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_SB_ARQBAH\t\t\t\t0x0022FF00 /* Reset Source: CORER */\n+#define PF_SB_ARQBAH_ARQBAH_S\t\t\t0\n+#define PF_SB_ARQBAH_ARQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF_SB_ARQBAL\t\t\t\t0x0022FE80 /* Reset Source: CORER */\n+#define PF_SB_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF_SB_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF_SB_ARQBAL_ARQBAL_S\t\t\t6\n+#define PF_SB_ARQBAL_ARQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF_SB_ARQH\t\t\t\t0x00230000 /* Reset Source: CORER */\n+#define PF_SB_ARQH_ARQH_S\t\t\t0\n+#define PF_SB_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_SB_ARQLEN\t\t\t\t0x0022FF80 /* Reset Source: CORER */\n+#define PF_SB_ARQLEN_ARQLEN_S\t\t\t0\n+#define PF_SB_ARQLEN_ARQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_SB_ARQLEN_ARQVFE_S\t\t\t28\n+#define PF_SB_ARQLEN_ARQVFE_M\t\t\tBIT(28)\n+#define PF_SB_ARQLEN_ARQOVFL_S\t\t\t29\n+#define PF_SB_ARQLEN_ARQOVFL_M\t\t\tBIT(29)\n+#define PF_SB_ARQLEN_ARQCRIT_S\t\t\t30\n+#define PF_SB_ARQLEN_ARQCRIT_M\t\t\tBIT(30)\n+#define PF_SB_ARQLEN_ARQENABLE_S\t\t31\n+#define PF_SB_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF_SB_ARQT\t\t\t\t0x00230080 /* Reset Source: CORER */\n+#define PF_SB_ARQT_ARQT_S\t\t\t0\n+#define PF_SB_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_SB_ATQBAH\t\t\t\t0x0022FC80 /* Reset Source: CORER */\n+#define PF_SB_ATQBAH_ATQBAH_S\t\t\t0\n+#define PF_SB_ATQBAH_ATQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF_SB_ATQBAL\t\t\t\t0x0022FC00 /* Reset Source: CORER */\n+#define PF_SB_ATQBAL_ATQBAL_S\t\t\t6\n+#define PF_SB_ATQBAL_ATQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF_SB_ATQH\t\t\t\t0x0022FD80 /* Reset Source: CORER */\n+#define PF_SB_ATQH_ATQH_S\t\t\t0\n+#define PF_SB_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_SB_ATQLEN\t\t\t\t0x0022FD00 /* Reset Source: CORER */\n+#define PF_SB_ATQLEN_ATQLEN_S\t\t\t0\n+#define PF_SB_ATQLEN_ATQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_SB_ATQLEN_ATQVFE_S\t\t\t28\n+#define PF_SB_ATQLEN_ATQVFE_M\t\t\tBIT(28)\n+#define PF_SB_ATQLEN_ATQOVFL_S\t\t\t29\n+#define PF_SB_ATQLEN_ATQOVFL_M\t\t\tBIT(29)\n+#define PF_SB_ATQLEN_ATQCRIT_S\t\t\t30\n+#define PF_SB_ATQLEN_ATQCRIT_M\t\t\tBIT(30)\n+#define PF_SB_ATQLEN_ATQENABLE_S\t\t31\n+#define PF_SB_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF_SB_ATQT\t\t\t\t0x0022FE00 /* Reset Source: CORER */\n+#define PF_SB_ATQT_ATQT_S\t\t\t0\n+#define PF_SB_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF_SB_REM_DEV_CTL\t\t\t0x002300F0 /* Reset Source: CORER */\n+#define PF_SB_REM_DEV_CTL_DEST_EN_S\t\t0\n+#define PF_SB_REM_DEV_CTL_DEST_EN_M\t\tMAKEMASK(0xFFFF, 0)\n+#define PF0_FW_HLP_ARQBAH\t\t\t0x000801C8 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQBAH_ARQBAH_S\t\t0\n+#define PF0_FW_HLP_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_FW_HLP_ARQBAL\t\t\t0x000800C8 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF0_FW_HLP_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF0_FW_HLP_ARQBAL_ARQBAL_S\t\t6\n+#define PF0_FW_HLP_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_FW_HLP_ARQH\t\t\t\t0x000803C8 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQH_ARQH_S\t\t\t0\n+#define PF0_FW_HLP_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ARQLEN\t\t\t0x000802C8 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQLEN_ARQLEN_S\t\t0\n+#define PF0_FW_HLP_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ARQLEN_ARQVFE_S\t\t28\n+#define PF0_FW_HLP_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define PF0_FW_HLP_ARQLEN_ARQOVFL_S\t\t29\n+#define PF0_FW_HLP_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define PF0_FW_HLP_ARQLEN_ARQCRIT_S\t\t30\n+#define PF0_FW_HLP_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define PF0_FW_HLP_ARQLEN_ARQENABLE_S\t\t31\n+#define PF0_FW_HLP_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF0_FW_HLP_ARQT\t\t\t\t0x000804C8 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ARQT_ARQT_S\t\t\t0\n+#define PF0_FW_HLP_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ATQBAH\t\t\t0x00080148 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQBAH_ATQBAH_S\t\t0\n+#define PF0_FW_HLP_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_FW_HLP_ATQBAL\t\t\t0x00080048 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_S\t\t0\n+#define PF0_FW_HLP_ATQBAL_ATQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF0_FW_HLP_ATQBAL_ATQBAL_S\t\t6\n+#define PF0_FW_HLP_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_FW_HLP_ATQH\t\t\t\t0x00080348 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQH_ATQH_S\t\t\t0\n+#define PF0_FW_HLP_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ATQLEN\t\t\t0x00080248 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQLEN_ATQLEN_S\t\t0\n+#define PF0_FW_HLP_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_HLP_ATQLEN_ATQVFE_S\t\t28\n+#define PF0_FW_HLP_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define PF0_FW_HLP_ATQLEN_ATQOVFL_S\t\t29\n+#define PF0_FW_HLP_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define PF0_FW_HLP_ATQLEN_ATQCRIT_S\t\t30\n+#define PF0_FW_HLP_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define PF0_FW_HLP_ATQLEN_ATQENABLE_S\t\t31\n+#define PF0_FW_HLP_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF0_FW_HLP_ATQT\t\t\t\t0x00080448 /* Reset Source: EMPR */\n+#define PF0_FW_HLP_ATQT_ATQT_S\t\t\t0\n+#define PF0_FW_HLP_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ARQBAH\t\t\t0x000801C4 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQBAH_ARQBAH_S\t\t0\n+#define PF0_FW_PSM_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_FW_PSM_ARQBAL\t\t\t0x000800C4 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF0_FW_PSM_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF0_FW_PSM_ARQBAL_ARQBAL_S\t\t6\n+#define PF0_FW_PSM_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_FW_PSM_ARQH\t\t\t\t0x000803C4 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQH_ARQH_S\t\t\t0\n+#define PF0_FW_PSM_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ARQLEN\t\t\t0x000802C4 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQLEN_ARQLEN_S\t\t0\n+#define PF0_FW_PSM_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ARQLEN_ARQVFE_S\t\t28\n+#define PF0_FW_PSM_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define PF0_FW_PSM_ARQLEN_ARQOVFL_S\t\t29\n+#define PF0_FW_PSM_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define PF0_FW_PSM_ARQLEN_ARQCRIT_S\t\t30\n+#define PF0_FW_PSM_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define PF0_FW_PSM_ARQLEN_ARQENABLE_S\t\t31\n+#define PF0_FW_PSM_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF0_FW_PSM_ARQT\t\t\t\t0x000804C4 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ARQT_ARQT_S\t\t\t0\n+#define PF0_FW_PSM_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ATQBAH\t\t\t0x00080144 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQBAH_ATQBAH_S\t\t0\n+#define PF0_FW_PSM_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_FW_PSM_ATQBAL\t\t\t0x00080044 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_S\t\t0\n+#define PF0_FW_PSM_ATQBAL_ATQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF0_FW_PSM_ATQBAL_ATQBAL_S\t\t6\n+#define PF0_FW_PSM_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_FW_PSM_ATQH\t\t\t\t0x00080344 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQH_ATQH_S\t\t\t0\n+#define PF0_FW_PSM_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ATQLEN\t\t\t0x00080244 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQLEN_ATQLEN_S\t\t0\n+#define PF0_FW_PSM_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_FW_PSM_ATQLEN_ATQVFE_S\t\t28\n+#define PF0_FW_PSM_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define PF0_FW_PSM_ATQLEN_ATQOVFL_S\t\t29\n+#define PF0_FW_PSM_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define PF0_FW_PSM_ATQLEN_ATQCRIT_S\t\t30\n+#define PF0_FW_PSM_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define PF0_FW_PSM_ATQLEN_ATQENABLE_S\t\t31\n+#define PF0_FW_PSM_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF0_FW_PSM_ATQT\t\t\t\t0x00080444 /* Reset Source: EMPR */\n+#define PF0_FW_PSM_ATQT_ATQT_S\t\t\t0\n+#define PF0_FW_PSM_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ARQBAH\t\t\t0x0022E5D8 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQBAH_ARQBAH_S\t\t0\n+#define PF0_MBX_CPM_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_CPM_ARQBAL\t\t\t0x0022E5D4 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF0_MBX_CPM_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF0_MBX_CPM_ARQBAL_ARQBAL_S\t\t6\n+#define PF0_MBX_CPM_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_CPM_ARQH\t\t\t0x0022E5E0 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQH_ARQH_S\t\t\t0\n+#define PF0_MBX_CPM_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ARQLEN\t\t\t0x0022E5DC /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQLEN_ARQLEN_S\t\t0\n+#define PF0_MBX_CPM_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ARQLEN_ARQVFE_S\t\t28\n+#define PF0_MBX_CPM_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define PF0_MBX_CPM_ARQLEN_ARQOVFL_S\t\t29\n+#define PF0_MBX_CPM_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define PF0_MBX_CPM_ARQLEN_ARQCRIT_S\t\t30\n+#define PF0_MBX_CPM_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define PF0_MBX_CPM_ARQLEN_ARQENABLE_S\t\t31\n+#define PF0_MBX_CPM_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF0_MBX_CPM_ARQT\t\t\t0x0022E5E4 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ARQT_ARQT_S\t\t\t0\n+#define PF0_MBX_CPM_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ATQBAH\t\t\t0x0022E5C4 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQBAH_ATQBAH_S\t\t0\n+#define PF0_MBX_CPM_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_CPM_ATQBAL\t\t\t0x0022E5C0 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQBAL_ATQBAL_S\t\t6\n+#define PF0_MBX_CPM_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_CPM_ATQH\t\t\t0x0022E5CC /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQH_ATQH_S\t\t\t0\n+#define PF0_MBX_CPM_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ATQLEN\t\t\t0x0022E5C8 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQLEN_ATQLEN_S\t\t0\n+#define PF0_MBX_CPM_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_CPM_ATQLEN_ATQVFE_S\t\t28\n+#define PF0_MBX_CPM_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define PF0_MBX_CPM_ATQLEN_ATQOVFL_S\t\t29\n+#define PF0_MBX_CPM_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define PF0_MBX_CPM_ATQLEN_ATQCRIT_S\t\t30\n+#define PF0_MBX_CPM_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define PF0_MBX_CPM_ATQLEN_ATQENABLE_S\t\t31\n+#define PF0_MBX_CPM_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF0_MBX_CPM_ATQT\t\t\t0x0022E5D0 /* Reset Source: CORER */\n+#define PF0_MBX_CPM_ATQT_ATQT_S\t\t\t0\n+#define PF0_MBX_CPM_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ARQBAH\t\t\t0x0022E600 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQBAH_ARQBAH_S\t\t0\n+#define PF0_MBX_HLP_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_HLP_ARQBAL\t\t\t0x0022E5FC /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF0_MBX_HLP_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF0_MBX_HLP_ARQBAL_ARQBAL_S\t\t6\n+#define PF0_MBX_HLP_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_HLP_ARQH\t\t\t0x0022E608 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQH_ARQH_S\t\t\t0\n+#define PF0_MBX_HLP_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ARQLEN\t\t\t0x0022E604 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQLEN_ARQLEN_S\t\t0\n+#define PF0_MBX_HLP_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ARQLEN_ARQVFE_S\t\t28\n+#define PF0_MBX_HLP_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define PF0_MBX_HLP_ARQLEN_ARQOVFL_S\t\t29\n+#define PF0_MBX_HLP_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define PF0_MBX_HLP_ARQLEN_ARQCRIT_S\t\t30\n+#define PF0_MBX_HLP_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define PF0_MBX_HLP_ARQLEN_ARQENABLE_S\t\t31\n+#define PF0_MBX_HLP_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF0_MBX_HLP_ARQT\t\t\t0x0022E60C /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ARQT_ARQT_S\t\t\t0\n+#define PF0_MBX_HLP_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ATQBAH\t\t\t0x0022E5EC /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQBAH_ATQBAH_S\t\t0\n+#define PF0_MBX_HLP_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_HLP_ATQBAL\t\t\t0x0022E5E8 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQBAL_ATQBAL_S\t\t6\n+#define PF0_MBX_HLP_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_HLP_ATQH\t\t\t0x0022E5F4 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQH_ATQH_S\t\t\t0\n+#define PF0_MBX_HLP_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ATQLEN\t\t\t0x0022E5F0 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQLEN_ATQLEN_S\t\t0\n+#define PF0_MBX_HLP_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_HLP_ATQLEN_ATQVFE_S\t\t28\n+#define PF0_MBX_HLP_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define PF0_MBX_HLP_ATQLEN_ATQOVFL_S\t\t29\n+#define PF0_MBX_HLP_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define PF0_MBX_HLP_ATQLEN_ATQCRIT_S\t\t30\n+#define PF0_MBX_HLP_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define PF0_MBX_HLP_ATQLEN_ATQENABLE_S\t\t31\n+#define PF0_MBX_HLP_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF0_MBX_HLP_ATQT\t\t\t0x0022E5F8 /* Reset Source: CORER */\n+#define PF0_MBX_HLP_ATQT_ATQT_S\t\t\t0\n+#define PF0_MBX_HLP_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ARQBAH\t\t\t0x0022E628 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQBAH_ARQBAH_S\t\t0\n+#define PF0_MBX_PSM_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_PSM_ARQBAL\t\t\t0x0022E624 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF0_MBX_PSM_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF0_MBX_PSM_ARQBAL_ARQBAL_S\t\t6\n+#define PF0_MBX_PSM_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_PSM_ARQH\t\t\t0x0022E630 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQH_ARQH_S\t\t\t0\n+#define PF0_MBX_PSM_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ARQLEN\t\t\t0x0022E62C /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQLEN_ARQLEN_S\t\t0\n+#define PF0_MBX_PSM_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ARQLEN_ARQVFE_S\t\t28\n+#define PF0_MBX_PSM_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define PF0_MBX_PSM_ARQLEN_ARQOVFL_S\t\t29\n+#define PF0_MBX_PSM_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define PF0_MBX_PSM_ARQLEN_ARQCRIT_S\t\t30\n+#define PF0_MBX_PSM_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define PF0_MBX_PSM_ARQLEN_ARQENABLE_S\t\t31\n+#define PF0_MBX_PSM_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF0_MBX_PSM_ARQT\t\t\t0x0022E634 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ARQT_ARQT_S\t\t\t0\n+#define PF0_MBX_PSM_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ATQBAH\t\t\t0x0022E614 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQBAH_ATQBAH_S\t\t0\n+#define PF0_MBX_PSM_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_MBX_PSM_ATQBAL\t\t\t0x0022E610 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQBAL_ATQBAL_S\t\t6\n+#define PF0_MBX_PSM_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_MBX_PSM_ATQH\t\t\t0x0022E61C /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQH_ATQH_S\t\t\t0\n+#define PF0_MBX_PSM_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ATQLEN\t\t\t0x0022E618 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQLEN_ATQLEN_S\t\t0\n+#define PF0_MBX_PSM_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_MBX_PSM_ATQLEN_ATQVFE_S\t\t28\n+#define PF0_MBX_PSM_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define PF0_MBX_PSM_ATQLEN_ATQOVFL_S\t\t29\n+#define PF0_MBX_PSM_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define PF0_MBX_PSM_ATQLEN_ATQCRIT_S\t\t30\n+#define PF0_MBX_PSM_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define PF0_MBX_PSM_ATQLEN_ATQENABLE_S\t\t31\n+#define PF0_MBX_PSM_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF0_MBX_PSM_ATQT\t\t\t0x0022E620 /* Reset Source: CORER */\n+#define PF0_MBX_PSM_ATQT_ATQT_S\t\t\t0\n+#define PF0_MBX_PSM_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ARQBAH\t\t\t0x0022E650 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQBAH_ARQBAH_S\t\t0\n+#define PF0_SB_CPM_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_SB_CPM_ARQBAL\t\t\t0x0022E64C /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF0_SB_CPM_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF0_SB_CPM_ARQBAL_ARQBAL_S\t\t6\n+#define PF0_SB_CPM_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_SB_CPM_ARQH\t\t\t\t0x0022E658 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQH_ARQH_S\t\t\t0\n+#define PF0_SB_CPM_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ARQLEN\t\t\t0x0022E654 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQLEN_ARQLEN_S\t\t0\n+#define PF0_SB_CPM_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ARQLEN_ARQVFE_S\t\t28\n+#define PF0_SB_CPM_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define PF0_SB_CPM_ARQLEN_ARQOVFL_S\t\t29\n+#define PF0_SB_CPM_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define PF0_SB_CPM_ARQLEN_ARQCRIT_S\t\t30\n+#define PF0_SB_CPM_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define PF0_SB_CPM_ARQLEN_ARQENABLE_S\t\t31\n+#define PF0_SB_CPM_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF0_SB_CPM_ARQT\t\t\t\t0x0022E65C /* Reset Source: CORER */\n+#define PF0_SB_CPM_ARQT_ARQT_S\t\t\t0\n+#define PF0_SB_CPM_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ATQBAH\t\t\t0x0022E63C /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQBAH_ATQBAH_S\t\t0\n+#define PF0_SB_CPM_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_SB_CPM_ATQBAL\t\t\t0x0022E638 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQBAL_ATQBAL_S\t\t6\n+#define PF0_SB_CPM_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_SB_CPM_ATQH\t\t\t\t0x0022E644 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQH_ATQH_S\t\t\t0\n+#define PF0_SB_CPM_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ATQLEN\t\t\t0x0022E640 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQLEN_ATQLEN_S\t\t0\n+#define PF0_SB_CPM_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_ATQLEN_ATQVFE_S\t\t28\n+#define PF0_SB_CPM_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define PF0_SB_CPM_ATQLEN_ATQOVFL_S\t\t29\n+#define PF0_SB_CPM_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define PF0_SB_CPM_ATQLEN_ATQCRIT_S\t\t30\n+#define PF0_SB_CPM_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define PF0_SB_CPM_ATQLEN_ATQENABLE_S\t\t31\n+#define PF0_SB_CPM_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF0_SB_CPM_ATQT\t\t\t\t0x0022E648 /* Reset Source: CORER */\n+#define PF0_SB_CPM_ATQT_ATQT_S\t\t\t0\n+#define PF0_SB_CPM_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_CPM_REM_DEV_CTL\t\t\t0x002300F4 /* Reset Source: CORER */\n+#define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_S\t0\n+#define PF0_SB_CPM_REM_DEV_CTL_DEST_EN_M\tMAKEMASK(0xFFFF, 0)\n+#define PF0_SB_HLP_ARQBAH\t\t\t0x002300D8 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQBAH_ARQBAH_S\t\t0\n+#define PF0_SB_HLP_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_SB_HLP_ARQBAL\t\t\t0x002300D4 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define PF0_SB_HLP_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define PF0_SB_HLP_ARQBAL_ARQBAL_S\t\t6\n+#define PF0_SB_HLP_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_SB_HLP_ARQH\t\t\t\t0x002300E0 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQH_ARQH_S\t\t\t0\n+#define PF0_SB_HLP_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ARQLEN\t\t\t0x002300DC /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQLEN_ARQLEN_S\t\t0\n+#define PF0_SB_HLP_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ARQLEN_ARQVFE_S\t\t28\n+#define PF0_SB_HLP_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define PF0_SB_HLP_ARQLEN_ARQOVFL_S\t\t29\n+#define PF0_SB_HLP_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define PF0_SB_HLP_ARQLEN_ARQCRIT_S\t\t30\n+#define PF0_SB_HLP_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define PF0_SB_HLP_ARQLEN_ARQENABLE_S\t\t31\n+#define PF0_SB_HLP_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define PF0_SB_HLP_ARQT\t\t\t\t0x002300E4 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ARQT_ARQT_S\t\t\t0\n+#define PF0_SB_HLP_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ATQBAH\t\t\t0x002300C4 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQBAH_ATQBAH_S\t\t0\n+#define PF0_SB_HLP_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PF0_SB_HLP_ATQBAL\t\t\t0x002300C0 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQBAL_ATQBAL_S\t\t6\n+#define PF0_SB_HLP_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define PF0_SB_HLP_ATQH\t\t\t\t0x002300CC /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQH_ATQH_S\t\t\t0\n+#define PF0_SB_HLP_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ATQLEN\t\t\t0x002300C8 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQLEN_ATQLEN_S\t\t0\n+#define PF0_SB_HLP_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_ATQLEN_ATQVFE_S\t\t28\n+#define PF0_SB_HLP_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define PF0_SB_HLP_ATQLEN_ATQOVFL_S\t\t29\n+#define PF0_SB_HLP_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define PF0_SB_HLP_ATQLEN_ATQCRIT_S\t\t30\n+#define PF0_SB_HLP_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define PF0_SB_HLP_ATQLEN_ATQENABLE_S\t\t31\n+#define PF0_SB_HLP_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define PF0_SB_HLP_ATQT\t\t\t\t0x002300D0 /* Reset Source: CORER */\n+#define PF0_SB_HLP_ATQT_ATQT_S\t\t\t0\n+#define PF0_SB_HLP_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PF0_SB_HLP_REM_DEV_CTL\t\t\t0x002300E8 /* Reset Source: CORER */\n+#define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_S\t0\n+#define PF0_SB_HLP_REM_DEV_CTL_DEST_EN_M\tMAKEMASK(0xFFFF, 0)\n+#define SB_REM_DEV_DEST(_i)\t\t\t(0x002300F8 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define SB_REM_DEV_DEST_MAX_INDEX\t\t7\n+#define SB_REM_DEV_DEST_DEST_S\t\t\t0\n+#define SB_REM_DEV_DEST_DEST_M\t\t\tMAKEMASK(0xF, 0)\n+#define SB_REM_DEV_DEST_DEST_VALID_S\t\t31\n+#define SB_REM_DEV_DEST_DEST_VALID_M\t\tBIT(31)\n+#define VF_MBX_ARQBAH(_VF)\t\t\t(0x0022B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ARQBAH_MAX_INDEX\t\t\t255\n+#define VF_MBX_ARQBAH_ARQBAH_S\t\t\t0\n+#define VF_MBX_ARQBAH_ARQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_ARQBAL(_VF)\t\t\t(0x0022B400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ARQBAL_MAX_INDEX\t\t\t255\n+#define VF_MBX_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define VF_MBX_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_MBX_ARQBAL_ARQBAL_S\t\t\t6\n+#define VF_MBX_ARQBAL_ARQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_ARQH(_VF)\t\t\t(0x0022C000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ARQH_MAX_INDEX\t\t\t255\n+#define VF_MBX_ARQH_ARQH_S\t\t\t0\n+#define VF_MBX_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ARQLEN(_VF)\t\t\t(0x0022BC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ARQLEN_MAX_INDEX\t\t\t255\n+#define VF_MBX_ARQLEN_ARQLEN_S\t\t\t0\n+#define VF_MBX_ARQLEN_ARQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ARQLEN_ARQVFE_S\t\t\t28\n+#define VF_MBX_ARQLEN_ARQVFE_M\t\t\tBIT(28)\n+#define VF_MBX_ARQLEN_ARQOVFL_S\t\t\t29\n+#define VF_MBX_ARQLEN_ARQOVFL_M\t\t\tBIT(29)\n+#define VF_MBX_ARQLEN_ARQCRIT_S\t\t\t30\n+#define VF_MBX_ARQLEN_ARQCRIT_M\t\t\tBIT(30)\n+#define VF_MBX_ARQLEN_ARQENABLE_S\t\t31\n+#define VF_MBX_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define VF_MBX_ARQT(_VF)\t\t\t(0x0022C400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ARQT_MAX_INDEX\t\t\t255\n+#define VF_MBX_ARQT_ARQT_S\t\t\t0\n+#define VF_MBX_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ATQBAH(_VF)\t\t\t(0x0022A400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ATQBAH_MAX_INDEX\t\t\t255\n+#define VF_MBX_ATQBAH_ATQBAH_S\t\t\t0\n+#define VF_MBX_ATQBAH_ATQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_ATQBAL(_VF)\t\t\t(0x0022A000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ATQBAL_MAX_INDEX\t\t\t255\n+#define VF_MBX_ATQBAL_ATQBAL_S\t\t\t6\n+#define VF_MBX_ATQBAL_ATQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_ATQH(_VF)\t\t\t(0x0022AC00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ATQH_MAX_INDEX\t\t\t255\n+#define VF_MBX_ATQH_ATQH_S\t\t\t0\n+#define VF_MBX_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ATQLEN(_VF)\t\t\t(0x0022A800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ATQLEN_MAX_INDEX\t\t\t255\n+#define VF_MBX_ATQLEN_ATQLEN_S\t\t\t0\n+#define VF_MBX_ATQLEN_ATQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ATQLEN_ATQVFE_S\t\t\t28\n+#define VF_MBX_ATQLEN_ATQVFE_M\t\t\tBIT(28)\n+#define VF_MBX_ATQLEN_ATQOVFL_S\t\t\t29\n+#define VF_MBX_ATQLEN_ATQOVFL_M\t\t\tBIT(29)\n+#define VF_MBX_ATQLEN_ATQCRIT_S\t\t\t30\n+#define VF_MBX_ATQLEN_ATQCRIT_M\t\t\tBIT(30)\n+#define VF_MBX_ATQLEN_ATQENABLE_S\t\t31\n+#define VF_MBX_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define VF_MBX_ATQT(_VF)\t\t\t(0x0022B000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VF_MBX_ATQT_MAX_INDEX\t\t\t255\n+#define VF_MBX_ATQT_ATQT_S\t\t\t0\n+#define VF_MBX_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ARQBAH(_VF128)\t\t(0x0022D400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQBAH_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ARQBAH_ARQBAH_S\t\t0\n+#define VF_MBX_CPM_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_CPM_ARQBAL(_VF128)\t\t(0x0022D200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQBAL_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define VF_MBX_CPM_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_MBX_CPM_ARQBAL_ARQBAL_S\t\t6\n+#define VF_MBX_CPM_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_CPM_ARQH(_VF128)\t\t\t(0x0022D800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQH_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ARQH_ARQH_S\t\t\t0\n+#define VF_MBX_CPM_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ARQLEN(_VF128)\t\t(0x0022D600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQLEN_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ARQLEN_ARQLEN_S\t\t0\n+#define VF_MBX_CPM_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ARQLEN_ARQVFE_S\t\t28\n+#define VF_MBX_CPM_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define VF_MBX_CPM_ARQLEN_ARQOVFL_S\t\t29\n+#define VF_MBX_CPM_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define VF_MBX_CPM_ARQLEN_ARQCRIT_S\t\t30\n+#define VF_MBX_CPM_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define VF_MBX_CPM_ARQLEN_ARQENABLE_S\t\t31\n+#define VF_MBX_CPM_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define VF_MBX_CPM_ARQT(_VF128)\t\t\t(0x0022DA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQT_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ARQT_ARQT_S\t\t\t0\n+#define VF_MBX_CPM_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ATQBAH(_VF128)\t\t(0x0022CA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQBAH_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ATQBAH_ATQBAH_S\t\t0\n+#define VF_MBX_CPM_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_CPM_ATQBAL(_VF128)\t\t(0x0022C800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQBAL_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ATQBAL_ATQBAL_S\t\t6\n+#define VF_MBX_CPM_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_CPM_ATQH(_VF128)\t\t\t(0x0022CE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQH_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ATQH_ATQH_S\t\t\t0\n+#define VF_MBX_CPM_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ATQLEN(_VF128)\t\t(0x0022CC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQLEN_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ATQLEN_ATQLEN_S\t\t0\n+#define VF_MBX_CPM_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ATQLEN_ATQVFE_S\t\t28\n+#define VF_MBX_CPM_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define VF_MBX_CPM_ATQLEN_ATQOVFL_S\t\t29\n+#define VF_MBX_CPM_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define VF_MBX_CPM_ATQLEN_ATQCRIT_S\t\t30\n+#define VF_MBX_CPM_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define VF_MBX_CPM_ATQLEN_ATQENABLE_S\t\t31\n+#define VF_MBX_CPM_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define VF_MBX_CPM_ATQT(_VF128)\t\t\t(0x0022D000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQT_MAX_INDEX\t\t127\n+#define VF_MBX_CPM_ATQT_ATQT_S\t\t\t0\n+#define VF_MBX_CPM_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ARQBAH(_VF16)\t\t(0x0022DD80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQBAH_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ARQBAH_ARQBAH_S\t\t0\n+#define VF_MBX_HLP_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_HLP_ARQBAL(_VF16)\t\t(0x0022DD40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQBAL_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define VF_MBX_HLP_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_MBX_HLP_ARQBAL_ARQBAL_S\t\t6\n+#define VF_MBX_HLP_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_HLP_ARQH(_VF16)\t\t\t(0x0022DE00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQH_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ARQH_ARQH_S\t\t\t0\n+#define VF_MBX_HLP_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ARQLEN(_VF16)\t\t(0x0022DDC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQLEN_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ARQLEN_ARQLEN_S\t\t0\n+#define VF_MBX_HLP_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ARQLEN_ARQVFE_S\t\t28\n+#define VF_MBX_HLP_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define VF_MBX_HLP_ARQLEN_ARQOVFL_S\t\t29\n+#define VF_MBX_HLP_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define VF_MBX_HLP_ARQLEN_ARQCRIT_S\t\t30\n+#define VF_MBX_HLP_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define VF_MBX_HLP_ARQLEN_ARQENABLE_S\t\t31\n+#define VF_MBX_HLP_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define VF_MBX_HLP_ARQT(_VF16)\t\t\t(0x0022DE40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQT_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ARQT_ARQT_S\t\t\t0\n+#define VF_MBX_HLP_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ATQBAH(_VF16)\t\t(0x0022DC40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQBAH_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ATQBAH_ATQBAH_S\t\t0\n+#define VF_MBX_HLP_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_HLP_ATQBAL(_VF16)\t\t(0x0022DC00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQBAL_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ATQBAL_ATQBAL_S\t\t6\n+#define VF_MBX_HLP_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_HLP_ATQH(_VF16)\t\t\t(0x0022DCC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQH_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ATQH_ATQH_S\t\t\t0\n+#define VF_MBX_HLP_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ATQLEN(_VF16)\t\t(0x0022DC80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQLEN_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ATQLEN_ATQLEN_S\t\t0\n+#define VF_MBX_HLP_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ATQLEN_ATQVFE_S\t\t28\n+#define VF_MBX_HLP_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define VF_MBX_HLP_ATQLEN_ATQOVFL_S\t\t29\n+#define VF_MBX_HLP_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define VF_MBX_HLP_ATQLEN_ATQCRIT_S\t\t30\n+#define VF_MBX_HLP_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define VF_MBX_HLP_ATQLEN_ATQENABLE_S\t\t31\n+#define VF_MBX_HLP_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define VF_MBX_HLP_ATQT(_VF16)\t\t\t(0x0022DD00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQT_MAX_INDEX\t\t15\n+#define VF_MBX_HLP_ATQT_ATQT_S\t\t\t0\n+#define VF_MBX_HLP_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ARQBAH(_VF16)\t\t(0x0022E000 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQBAH_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ARQBAH_ARQBAH_S\t\t0\n+#define VF_MBX_PSM_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_PSM_ARQBAL(_VF16)\t\t(0x0022DFC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQBAL_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define VF_MBX_PSM_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_MBX_PSM_ARQBAL_ARQBAL_S\t\t6\n+#define VF_MBX_PSM_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_PSM_ARQH(_VF16)\t\t\t(0x0022E080 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQH_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ARQH_ARQH_S\t\t\t0\n+#define VF_MBX_PSM_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ARQLEN(_VF16)\t\t(0x0022E040 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQLEN_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ARQLEN_ARQLEN_S\t\t0\n+#define VF_MBX_PSM_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ARQLEN_ARQVFE_S\t\t28\n+#define VF_MBX_PSM_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define VF_MBX_PSM_ARQLEN_ARQOVFL_S\t\t29\n+#define VF_MBX_PSM_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define VF_MBX_PSM_ARQLEN_ARQCRIT_S\t\t30\n+#define VF_MBX_PSM_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define VF_MBX_PSM_ARQLEN_ARQENABLE_S\t\t31\n+#define VF_MBX_PSM_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define VF_MBX_PSM_ARQT(_VF16)\t\t\t(0x0022E0C0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQT_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ARQT_ARQT_S\t\t\t0\n+#define VF_MBX_PSM_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ATQBAH(_VF16)\t\t(0x0022DEC0 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQBAH_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ATQBAH_ATQBAH_S\t\t0\n+#define VF_MBX_PSM_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_PSM_ATQBAL(_VF16)\t\t(0x0022DE80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQBAL_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ATQBAL_ATQBAL_S\t\t6\n+#define VF_MBX_PSM_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_PSM_ATQH(_VF16)\t\t\t(0x0022DF40 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQH_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ATQH_ATQH_S\t\t\t0\n+#define VF_MBX_PSM_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ATQLEN(_VF16)\t\t(0x0022DF00 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQLEN_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ATQLEN_ATQLEN_S\t\t0\n+#define VF_MBX_PSM_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ATQLEN_ATQVFE_S\t\t28\n+#define VF_MBX_PSM_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define VF_MBX_PSM_ATQLEN_ATQOVFL_S\t\t29\n+#define VF_MBX_PSM_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define VF_MBX_PSM_ATQLEN_ATQCRIT_S\t\t30\n+#define VF_MBX_PSM_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define VF_MBX_PSM_ATQLEN_ATQENABLE_S\t\t31\n+#define VF_MBX_PSM_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define VF_MBX_PSM_ATQT(_VF16)\t\t\t(0x0022DF80 + ((_VF16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQT_MAX_INDEX\t\t15\n+#define VF_MBX_PSM_ATQT_ATQT_S\t\t\t0\n+#define VF_MBX_PSM_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ARQBAH(_VF128)\t\t(0x0022F400 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQBAH_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ARQBAH_ARQBAH_S\t\t0\n+#define VF_SB_CPM_ARQBAH_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_SB_CPM_ARQBAL(_VF128)\t\t(0x0022F200 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQBAL_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ARQBAL_ARQBAL_LSB_S\t\t0\n+#define VF_SB_CPM_ARQBAL_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_SB_CPM_ARQBAL_ARQBAL_S\t\t6\n+#define VF_SB_CPM_ARQBAL_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_SB_CPM_ARQH(_VF128)\t\t\t(0x0022F800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQH_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ARQH_ARQH_S\t\t\t0\n+#define VF_SB_CPM_ARQH_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ARQLEN(_VF128)\t\t(0x0022F600 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQLEN_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ARQLEN_ARQLEN_S\t\t0\n+#define VF_SB_CPM_ARQLEN_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ARQLEN_ARQVFE_S\t\t28\n+#define VF_SB_CPM_ARQLEN_ARQVFE_M\t\tBIT(28)\n+#define VF_SB_CPM_ARQLEN_ARQOVFL_S\t\t29\n+#define VF_SB_CPM_ARQLEN_ARQOVFL_M\t\tBIT(29)\n+#define VF_SB_CPM_ARQLEN_ARQCRIT_S\t\t30\n+#define VF_SB_CPM_ARQLEN_ARQCRIT_M\t\tBIT(30)\n+#define VF_SB_CPM_ARQLEN_ARQENABLE_S\t\t31\n+#define VF_SB_CPM_ARQLEN_ARQENABLE_M\t\tBIT(31)\n+#define VF_SB_CPM_ARQT(_VF128)\t\t\t(0x0022FA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQT_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ARQT_ARQT_S\t\t\t0\n+#define VF_SB_CPM_ARQT_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ATQBAH(_VF128)\t\t(0x0022EA00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQBAH_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ATQBAH_ATQBAH_S\t\t0\n+#define VF_SB_CPM_ATQBAH_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_SB_CPM_ATQBAL(_VF128)\t\t(0x0022E800 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQBAL_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ATQBAL_ATQBAL_S\t\t6\n+#define VF_SB_CPM_ATQBAL_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_SB_CPM_ATQH(_VF128)\t\t\t(0x0022EE00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQH_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ATQH_ATQH_S\t\t\t0\n+#define VF_SB_CPM_ATQH_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ATQLEN(_VF128)\t\t(0x0022EC00 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQLEN_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ATQLEN_ATQLEN_S\t\t0\n+#define VF_SB_CPM_ATQLEN_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ATQLEN_ATQVFE_S\t\t28\n+#define VF_SB_CPM_ATQLEN_ATQVFE_M\t\tBIT(28)\n+#define VF_SB_CPM_ATQLEN_ATQOVFL_S\t\t29\n+#define VF_SB_CPM_ATQLEN_ATQOVFL_M\t\tBIT(29)\n+#define VF_SB_CPM_ATQLEN_ATQCRIT_S\t\t30\n+#define VF_SB_CPM_ATQLEN_ATQCRIT_M\t\tBIT(30)\n+#define VF_SB_CPM_ATQLEN_ATQENABLE_S\t\t31\n+#define VF_SB_CPM_ATQLEN_ATQENABLE_M\t\tBIT(31)\n+#define VF_SB_CPM_ATQT(_VF128)\t\t\t(0x0022F000 + ((_VF128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQT_MAX_INDEX\t\t127\n+#define VF_SB_CPM_ATQT_ATQT_S\t\t\t0\n+#define VF_SB_CPM_ATQT_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_REM_DEV_CTL\t\t\t0x002300EC /* Reset Source: CORER */\n+#define VF_SB_CPM_REM_DEV_CTL_DEST_EN_S\t\t0\n+#define VF_SB_CPM_REM_DEV_CTL_DEST_EN_M\t\tMAKEMASK(0xFFFF, 0)\n+#define VP_MBX_CPM_PF_VF_CTRL(_VP128)\t\t(0x00231800 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VP_MBX_CPM_PF_VF_CTRL_MAX_INDEX\t\t127\n+#define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_S\t0\n+#define VP_MBX_CPM_PF_VF_CTRL_QUEUE_EN_M\tBIT(0)\n+#define VP_MBX_HLP_PF_VF_CTRL(_VP16)\t\t(0x00231A00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VP_MBX_HLP_PF_VF_CTRL_MAX_INDEX\t\t15\n+#define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_S\t0\n+#define VP_MBX_HLP_PF_VF_CTRL_QUEUE_EN_M\tBIT(0)\n+#define VP_MBX_PF_VF_CTRL(_VSI)\t\t\t(0x00230800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VP_MBX_PF_VF_CTRL_MAX_INDEX\t\t767\n+#define VP_MBX_PF_VF_CTRL_QUEUE_EN_S\t\t0\n+#define VP_MBX_PF_VF_CTRL_QUEUE_EN_M\t\tBIT(0)\n+#define VP_MBX_PSM_PF_VF_CTRL(_VP16)\t\t(0x00231A40 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VP_MBX_PSM_PF_VF_CTRL_MAX_INDEX\t\t15\n+#define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_S\t0\n+#define VP_MBX_PSM_PF_VF_CTRL_QUEUE_EN_M\tBIT(0)\n+#define VP_SB_CPM_PF_VF_CTRL(_VP128)\t\t(0x00231C00 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VP_SB_CPM_PF_VF_CTRL_MAX_INDEX\t\t127\n+#define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_S\t\t0\n+#define VP_SB_CPM_PF_VF_CTRL_QUEUE_EN_M\t\tBIT(0)\n+#define GL_DCB_TDSCP2TC_BLOCK_DIS\t\t0x00049218 /* Reset Source: CORER */\n+#define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_S 0\n+#define GL_DCB_TDSCP2TC_BLOCK_DIS_DSCP2TC_BLOCK_DIS_M BIT(0)\n+#define GL_DCB_TDSCP2TC_BLOCK_IPV4(_i)\t\t(0x00049018 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GL_DCB_TDSCP2TC_BLOCK_IPV4_MAX_INDEX\t63\n+#define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_S 0\n+#define GL_DCB_TDSCP2TC_BLOCK_IPV4_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GL_DCB_TDSCP2TC_BLOCK_IPV6(_i)\t\t(0x00049118 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GL_DCB_TDSCP2TC_BLOCK_IPV6_MAX_INDEX\t63\n+#define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_S 0\n+#define GL_DCB_TDSCP2TC_BLOCK_IPV6_TC_BLOCK_LUT_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_GENC\t\t\t\t0x00083044 /* Reset Source: CORER */\n+#define GLDCB_GENC_PCIRTT_S\t\t\t0\n+#define GLDCB_GENC_PCIRTT_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define GLDCB_PRS_RETSTCC(_i)\t\t\t(0x002000B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLDCB_PRS_RETSTCC_MAX_INDEX\t\t31\n+#define GLDCB_PRS_RETSTCC_BWSHARE_S\t\t0\n+#define GLDCB_PRS_RETSTCC_BWSHARE_M\t\tMAKEMASK(0x7F, 0)\n+#define GLDCB_PRS_RETSTCC_ETSTC_S\t\t31\n+#define GLDCB_PRS_RETSTCC_ETSTC_M\t\tBIT(31)\n+#define GLDCB_PRS_RSPMC\t\t\t\t0x00200160 /* Reset Source: CORER */\n+#define GLDCB_PRS_RSPMC_RSPM_S\t\t\t0\n+#define GLDCB_PRS_RSPMC_RSPM_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLDCB_PRS_RSPMC_RPM_MODE_S\t\t8\n+#define GLDCB_PRS_RSPMC_RPM_MODE_M\t\tMAKEMASK(0x3, 8)\n+#define GLDCB_PRS_RSPMC_PRR_MAX_EXP_S\t\t10\n+#define GLDCB_PRS_RSPMC_PRR_MAX_EXP_M\t\tMAKEMASK(0xF, 10)\n+#define GLDCB_PRS_RSPMC_PFCTIMER_S\t\t14\n+#define GLDCB_PRS_RSPMC_PFCTIMER_M\t\tMAKEMASK(0x3FFF, 14)\n+#define GLDCB_PRS_RSPMC_RPM_DIS_S\t\t31\n+#define GLDCB_PRS_RSPMC_RPM_DIS_M\t\tBIT(31)\n+#define GLDCB_RETSTCC(_i)\t\t\t(0x00122140 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLDCB_RETSTCC_MAX_INDEX\t\t\t31\n+#define GLDCB_RETSTCC_BWSHARE_S\t\t\t0\n+#define GLDCB_RETSTCC_BWSHARE_M\t\t\tMAKEMASK(0x7F, 0)\n+#define GLDCB_RETSTCC_ETSTC_S\t\t\t31\n+#define GLDCB_RETSTCC_ETSTC_M\t\t\tBIT(31)\n+#define GLDCB_RETSTCS(_i)\t\t\t(0x001221C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLDCB_RETSTCS_MAX_INDEX\t\t\t31\n+#define GLDCB_RETSTCS_CREDITS_S\t\t\t0\n+#define GLDCB_RETSTCS_CREDITS_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_RTC2PFC_RCB\t\t\t0x00122100 /* Reset Source: CORER */\n+#define GLDCB_RTC2PFC_RCB_TC2PFC_S\t\t0\n+#define GLDCB_RTC2PFC_RCB_TC2PFC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_SWT_RETSTCC(_i)\t\t\t(0x0020A040 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLDCB_SWT_RETSTCC_MAX_INDEX\t\t31\n+#define GLDCB_SWT_RETSTCC_BWSHARE_S\t\t0\n+#define GLDCB_SWT_RETSTCC_BWSHARE_M\t\tMAKEMASK(0x7F, 0)\n+#define GLDCB_SWT_RETSTCC_ETSTC_S\t\t31\n+#define GLDCB_SWT_RETSTCC_ETSTC_M\t\tBIT(31)\n+#define GLDCB_TC2PFC\t\t\t\t0x001D2694 /* Reset Source: CORER */\n+#define GLDCB_TC2PFC_TC2PFC_S\t\t\t0\n+#define GLDCB_TC2PFC_TC2PFC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_TCB_MNG_SP\t\t\t0x000AE12C /* Reset Source: CORER */\n+#define GLDCB_TCB_MNG_SP_MNG_SP_S\t\t0\n+#define GLDCB_TCB_MNG_SP_MNG_SP_M\t\tBIT(0)\n+#define GLDCB_TCB_TCLL_CFG\t\t\t0x000AE134 /* Reset Source: CORER */\n+#define GLDCB_TCB_TCLL_CFG_LLTC_S\t\t0\n+#define GLDCB_TCB_TCLL_CFG_LLTC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_TCB_WB_SP\t\t\t\t0x000AE310 /* Reset Source: CORER */\n+#define GLDCB_TCB_WB_SP_WB_SP_S\t\t\t0\n+#define GLDCB_TCB_WB_SP_WB_SP_M\t\t\tBIT(0)\n+#define GLDCB_TCUPM_IMM_EN\t\t\t0x000BC824 /* Reset Source: CORER */\n+#define GLDCB_TCUPM_IMM_EN_IMM_EN_S\t\t0\n+#define GLDCB_TCUPM_IMM_EN_IMM_EN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_TCUPM_LEGACY_TC\t\t\t0x000BC828 /* Reset Source: CORER */\n+#define GLDCB_TCUPM_LEGACY_TC_LEGTC_S\t\t0\n+#define GLDCB_TCUPM_LEGACY_TC_LEGTC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_TCUPM_NO_EXCEED_DIS\t\t0x000BC830 /* Reset Source: CORER */\n+#define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_S 0\n+#define GLDCB_TCUPM_NO_EXCEED_DIS_NON_EXCEED_DIS_M BIT(0)\n+#define GLDCB_TCUPM_WB_DIS\t\t\t0x000BC834 /* Reset Source: CORER */\n+#define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_S\t0\n+#define GLDCB_TCUPM_WB_DIS_PORT_DISABLE_M\tBIT(0)\n+#define GLDCB_TCUPM_WB_DIS_TC_DISABLE_S\t\t1\n+#define GLDCB_TCUPM_WB_DIS_TC_DISABLE_M\t\tBIT(1)\n+#define GLDCB_TFPFCI\t\t\t\t0x0009949C /* Reset Source: CORER */\n+#define GLDCB_TFPFCI_GLDCB_TFPFCI_S\t\t0\n+#define GLDCB_TFPFCI_GLDCB_TFPFCI_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_TLPM_IMM_TCB\t\t\t0x000A0190 /* Reset Source: CORER */\n+#define GLDCB_TLPM_IMM_TCB_IMM_EN_S\t\t0\n+#define GLDCB_TLPM_IMM_TCB_IMM_EN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_TLPM_IMM_TCUPM\t\t\t0x000A018C /* Reset Source: CORER */\n+#define GLDCB_TLPM_IMM_TCUPM_IMM_EN_S\t\t0\n+#define GLDCB_TLPM_IMM_TCUPM_IMM_EN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_TLPM_PCI_DM\t\t\t0x000A0180 /* Reset Source: CORER */\n+#define GLDCB_TLPM_PCI_DM_MONITOR_S\t\t0\n+#define GLDCB_TLPM_PCI_DM_MONITOR_M\t\tMAKEMASK(0x7FFFF, 0)\n+#define GLDCB_TLPM_PCI_DTHR\t\t\t0x000A0184 /* Reset Source: CORER */\n+#define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_S\t\t0\n+#define GLDCB_TLPM_PCI_DTHR_PCI_TDATA_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLDCB_TPB_IMM_TLPM\t\t\t0x00099468 /* Reset Source: CORER */\n+#define GLDCB_TPB_IMM_TLPM_IMM_EN_S\t\t0\n+#define GLDCB_TPB_IMM_TLPM_IMM_EN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_TPB_IMM_TPB\t\t\t0x0009946C /* Reset Source: CORER */\n+#define GLDCB_TPB_IMM_TPB_IMM_EN_S\t\t0\n+#define GLDCB_TPB_IMM_TPB_IMM_EN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_TPB_TCLL_CFG\t\t\t0x00099464 /* Reset Source: CORER */\n+#define GLDCB_TPB_TCLL_CFG_LLTC_S\t\t0\n+#define GLDCB_TPB_TCLL_CFG_LLTC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTCB_BULK_DWRR_REG_QUANTA\t\t0x000AE0E0 /* Reset Source: CORER */\n+#define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_S\t0\n+#define GLTCB_BULK_DWRR_REG_QUANTA_QUANTA_M\tMAKEMASK(0x7FF, 0)\n+#define GLTCB_BULK_DWRR_REG_SAT\t\t\t0x000AE0F0 /* Reset Source: CORER */\n+#define GLTCB_BULK_DWRR_REG_SAT_SATURATION_S\t0\n+#define GLTCB_BULK_DWRR_REG_SAT_SATURATION_M\tMAKEMASK(0x1FFFF, 0)\n+#define GLTCB_BULK_DWRR_WB_QUANTA\t\t0x000AE0E4 /* Reset Source: CORER */\n+#define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_S\t0\n+#define GLTCB_BULK_DWRR_WB_QUANTA_QUANTA_M\tMAKEMASK(0x7FF, 0)\n+#define GLTCB_BULK_DWRR_WB_SAT\t\t\t0x000AE0F4 /* Reset Source: CORER */\n+#define GLTCB_BULK_DWRR_WB_SAT_SATURATION_S\t0\n+#define GLTCB_BULK_DWRR_WB_SAT_SATURATION_M\tMAKEMASK(0x1FFFF, 0)\n+#define GLTCB_CREDIT_EXP_CTL\t\t\t0x000AE120 /* Reset Source: CORER */\n+#define GLTCB_CREDIT_EXP_CTL_EN_S\t\t0\n+#define GLTCB_CREDIT_EXP_CTL_EN_M\t\tBIT(0)\n+#define GLTCB_CREDIT_EXP_CTL_MIN_PKT_S\t\t1\n+#define GLTCB_CREDIT_EXP_CTL_MIN_PKT_M\t\tMAKEMASK(0x1FF, 1)\n+#define GLTCB_LL_DWRR_REG_QUANTA\t\t0x000AE0E8 /* Reset Source: CORER */\n+#define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_S\t0\n+#define GLTCB_LL_DWRR_REG_QUANTA_QUANTA_M\tMAKEMASK(0x7FF, 0)\n+#define GLTCB_LL_DWRR_REG_SAT\t\t\t0x000AE0F8 /* Reset Source: CORER */\n+#define GLTCB_LL_DWRR_REG_SAT_SATURATION_S\t0\n+#define GLTCB_LL_DWRR_REG_SAT_SATURATION_M\tMAKEMASK(0x1FFFF, 0)\n+#define GLTCB_LL_DWRR_WB_QUANTA\t\t\t0x000AE0EC /* Reset Source: CORER */\n+#define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_S\t0\n+#define GLTCB_LL_DWRR_WB_QUANTA_QUANTA_M\tMAKEMASK(0x7FF, 0)\n+#define GLTCB_LL_DWRR_WB_SAT\t\t\t0x000AE0FC /* Reset Source: CORER */\n+#define GLTCB_LL_DWRR_WB_SAT_SATURATION_S\t0\n+#define GLTCB_LL_DWRR_WB_SAT_SATURATION_M\tMAKEMASK(0x1FFFF, 0)\n+#define GLTCB_WB_RL\t\t\t\t0x000AE238 /* Reset Source: CORER */\n+#define GLTCB_WB_RL_PERIOD_S\t\t\t0\n+#define GLTCB_WB_RL_PERIOD_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define GLTCB_WB_RL_EN_S\t\t\t16\n+#define GLTCB_WB_RL_EN_M\t\t\tBIT(16)\n+#define GLTPB_WB_RL\t\t\t\t0x00099460 /* Reset Source: CORER */\n+#define GLTPB_WB_RL_PERIOD_S\t\t\t0\n+#define GLTPB_WB_RL_PERIOD_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define GLTPB_WB_RL_EN_S\t\t\t16\n+#define GLTPB_WB_RL_EN_M\t\t\tBIT(16)\n+#define PRTDCB_FCCFG\t\t\t\t0x001E4640 /* Reset Source: GLOBR */\n+#define PRTDCB_FCCFG_TFCE_S\t\t\t3\n+#define PRTDCB_FCCFG_TFCE_M\t\t\tMAKEMASK(0x3, 3)\n+#define PRTDCB_FCRTV\t\t\t\t0x001E4600 /* Reset Source: GLOBR */\n+#define PRTDCB_FCRTV_FC_REFRESH_TH_S\t\t0\n+#define PRTDCB_FCRTV_FC_REFRESH_TH_M\t\tMAKEMASK(0xFFFF, 0)\n+#define PRTDCB_FCTTVN(_i)\t\t\t(0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: GLOBR */\n+#define PRTDCB_FCTTVN_MAX_INDEX\t\t\t3\n+#define PRTDCB_FCTTVN_TTV_2N_S\t\t\t0\n+#define PRTDCB_FCTTVN_TTV_2N_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define PRTDCB_FCTTVN_TTV_2N_P1_S\t\t16\n+#define PRTDCB_FCTTVN_TTV_2N_P1_M\t\tMAKEMASK(0xFFFF, 16)\n+#define PRTDCB_GENC\t\t\t\t0x00083000 /* Reset Source: CORER */\n+#define PRTDCB_GENC_NUMTC_S\t\t\t2\n+#define PRTDCB_GENC_NUMTC_M\t\t\tMAKEMASK(0xF, 2)\n+#define PRTDCB_GENC_FCOEUP_S\t\t\t6\n+#define PRTDCB_GENC_FCOEUP_M\t\t\tMAKEMASK(0x7, 6)\n+#define PRTDCB_GENC_FCOEUP_VALID_S\t\t9\n+#define PRTDCB_GENC_FCOEUP_VALID_M\t\tBIT(9)\n+#define PRTDCB_GENC_PFCLDA_S\t\t\t16\n+#define PRTDCB_GENC_PFCLDA_M\t\t\tMAKEMASK(0xFFFF, 16)\n+#define PRTDCB_GENS\t\t\t\t0x00083020 /* Reset Source: CORER */\n+#define PRTDCB_GENS_DCBX_STATUS_S\t\t0\n+#define PRTDCB_GENS_DCBX_STATUS_M\t\tMAKEMASK(0x7, 0)\n+#define PRTDCB_PRS_RETSC\t\t\t0x002001A0 /* Reset Source: CORER */\n+#define PRTDCB_PRS_RETSC_ETS_MODE_S\t\t0\n+#define PRTDCB_PRS_RETSC_ETS_MODE_M\t\tBIT(0)\n+#define PRTDCB_PRS_RETSC_NON_ETS_MODE_S\t\t1\n+#define PRTDCB_PRS_RETSC_NON_ETS_MODE_M\t\tBIT(1)\n+#define PRTDCB_PRS_RETSC_ETS_MAX_EXP_S\t\t2\n+#define PRTDCB_PRS_RETSC_ETS_MAX_EXP_M\t\tMAKEMASK(0xF, 2)\n+#define PRTDCB_PRS_RPRRC\t\t\t0x00200180 /* Reset Source: CORER */\n+#define PRTDCB_PRS_RPRRC_BWSHARE_S\t\t0\n+#define PRTDCB_PRS_RPRRC_BWSHARE_M\t\tMAKEMASK(0x3FF, 0)\n+#define PRTDCB_PRS_RPRRC_BWSHARE_DIS_S\t\t31\n+#define PRTDCB_PRS_RPRRC_BWSHARE_DIS_M\t\tBIT(31)\n+#define PRTDCB_RETSC\t\t\t\t0x001222A0 /* Reset Source: CORER */\n+#define PRTDCB_RETSC_ETS_MODE_S\t\t\t0\n+#define PRTDCB_RETSC_ETS_MODE_M\t\t\tBIT(0)\n+#define PRTDCB_RETSC_NON_ETS_MODE_S\t\t1\n+#define PRTDCB_RETSC_NON_ETS_MODE_M\t\tBIT(1)\n+#define PRTDCB_RETSC_ETS_MAX_EXP_S\t\t2\n+#define PRTDCB_RETSC_ETS_MAX_EXP_M\t\tMAKEMASK(0xF, 2)\n+#define PRTDCB_RPRRC\t\t\t\t0x001220C0 /* Reset Source: CORER */\n+#define PRTDCB_RPRRC_BWSHARE_S\t\t\t0\n+#define PRTDCB_RPRRC_BWSHARE_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PRTDCB_RPRRC_BWSHARE_DIS_S\t\t31\n+#define PRTDCB_RPRRC_BWSHARE_DIS_M\t\tBIT(31)\n+#define PRTDCB_RPRRS\t\t\t\t0x001220E0 /* Reset Source: CORER */\n+#define PRTDCB_RPRRS_CREDITS_S\t\t\t0\n+#define PRTDCB_RPRRS_CREDITS_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PRTDCB_RUP_TDPU\t\t\t\t0x00040960 /* Reset Source: CORER */\n+#define PRTDCB_RUP_TDPU_NOVLANUP_S\t\t0\n+#define PRTDCB_RUP_TDPU_NOVLANUP_M\t\tMAKEMASK(0x7, 0)\n+#define PRTDCB_RUP2TC\t\t\t\t0x001D2640 /* Reset Source: CORER */\n+#define PRTDCB_RUP2TC_UP0TC_S\t\t\t0\n+#define PRTDCB_RUP2TC_UP0TC_M\t\t\tMAKEMASK(0x7, 0)\n+#define PRTDCB_RUP2TC_UP1TC_S\t\t\t3\n+#define PRTDCB_RUP2TC_UP1TC_M\t\t\tMAKEMASK(0x7, 3)\n+#define PRTDCB_RUP2TC_UP2TC_S\t\t\t6\n+#define PRTDCB_RUP2TC_UP2TC_M\t\t\tMAKEMASK(0x7, 6)\n+#define PRTDCB_RUP2TC_UP3TC_S\t\t\t9\n+#define PRTDCB_RUP2TC_UP3TC_M\t\t\tMAKEMASK(0x7, 9)\n+#define PRTDCB_RUP2TC_UP4TC_S\t\t\t12\n+#define PRTDCB_RUP2TC_UP4TC_M\t\t\tMAKEMASK(0x7, 12)\n+#define PRTDCB_RUP2TC_UP5TC_S\t\t\t15\n+#define PRTDCB_RUP2TC_UP5TC_M\t\t\tMAKEMASK(0x7, 15)\n+#define PRTDCB_RUP2TC_UP6TC_S\t\t\t18\n+#define PRTDCB_RUP2TC_UP6TC_M\t\t\tMAKEMASK(0x7, 18)\n+#define PRTDCB_RUP2TC_UP7TC_S\t\t\t21\n+#define PRTDCB_RUP2TC_UP7TC_M\t\t\tMAKEMASK(0x7, 21)\n+#define PRTDCB_SWT_RETSC\t\t\t0x0020A140 /* Reset Source: CORER */\n+#define PRTDCB_SWT_RETSC_ETS_MODE_S\t\t0\n+#define PRTDCB_SWT_RETSC_ETS_MODE_M\t\tBIT(0)\n+#define PRTDCB_SWT_RETSC_NON_ETS_MODE_S\t\t1\n+#define PRTDCB_SWT_RETSC_NON_ETS_MODE_M\t\tBIT(1)\n+#define PRTDCB_SWT_RETSC_ETS_MAX_EXP_S\t\t2\n+#define PRTDCB_SWT_RETSC_ETS_MAX_EXP_M\t\tMAKEMASK(0xF, 2)\n+#define PRTDCB_TCB_DWRR_CREDITS\t\t\t0x000AE000 /* Reset Source: CORER */\n+#define PRTDCB_TCB_DWRR_CREDITS_CREDITS_S\t0\n+#define PRTDCB_TCB_DWRR_CREDITS_CREDITS_M\tMAKEMASK(0x3FFFF, 0)\n+#define PRTDCB_TCB_DWRR_QUANTA\t\t\t0x000AE020 /* Reset Source: CORER */\n+#define PRTDCB_TCB_DWRR_QUANTA_QUANTA_S\t\t0\n+#define PRTDCB_TCB_DWRR_QUANTA_QUANTA_M\t\tMAKEMASK(0x7FF, 0)\n+#define PRTDCB_TCB_DWRR_SAT\t\t\t0x000AE040 /* Reset Source: CORER */\n+#define PRTDCB_TCB_DWRR_SAT_SATURATION_S\t0\n+#define PRTDCB_TCB_DWRR_SAT_SATURATION_M\tMAKEMASK(0x1FFFF, 0)\n+#define PRTDCB_TCUPM_NO_EXCEED_DM\t\t0x000BC3C0 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_S\t0\n+#define PRTDCB_TCUPM_NO_EXCEED_DM_MONITOR_M\tMAKEMASK(0x7FFFF, 0)\n+#define PRTDCB_TCUPM_REG_CM\t\t\t0x000BC360 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_REG_CM_MONITOR_S\t\t0\n+#define PRTDCB_TCUPM_REG_CM_MONITOR_M\t\tMAKEMASK(0x7FFF, 0)\n+#define PRTDCB_TCUPM_REG_CTHR\t\t\t0x000BC380 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_S\t0\n+#define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_H_M\tMAKEMASK(0x7FFF, 0)\n+#define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_L_S\t15\n+#define PRTDCB_TCUPM_REG_CTHR_PORTOFFTH_L_M\tMAKEMASK(0x7FFF, 15)\n+#define PRTDCB_TCUPM_REG_DM\t\t\t0x000BC3A0 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_REG_DM_MONITOR_S\t\t0\n+#define PRTDCB_TCUPM_REG_DM_MONITOR_M\t\tMAKEMASK(0x7FFFF, 0)\n+#define PRTDCB_TCUPM_REG_DTHR\t\t\t0x000BC3E0 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_S\t0\n+#define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_H_M\tMAKEMASK(0xFFF, 0)\n+#define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_L_S\t12\n+#define PRTDCB_TCUPM_REG_DTHR_PORTOFFTH_L_M\tMAKEMASK(0xFFF, 12)\n+#define PRTDCB_TCUPM_REG_PE_HB_DM\t\t0x000BC400 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_S\t0\n+#define PRTDCB_TCUPM_REG_PE_HB_DM_MONITOR_M\tMAKEMASK(0xFFF, 0)\n+#define PRTDCB_TCUPM_REG_PE_HB_DTHR\t\t0x000BC420 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_S 0\n+#define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_H_M MAKEMASK(0xFFF, 0)\n+#define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_L_S 12\n+#define PRTDCB_TCUPM_REG_PE_HB_DTHR_PORTOFFTH_L_M MAKEMASK(0xFFF, 12)\n+#define PRTDCB_TCUPM_WAIT_PFC_CM\t\t0x000BC440 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_S\t0\n+#define PRTDCB_TCUPM_WAIT_PFC_CM_MONITOR_M\tMAKEMASK(0x7FFF, 0)\n+#define PRTDCB_TCUPM_WAIT_PFC_CTHR\t\t0x000BC460 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_S\t0\n+#define PRTDCB_TCUPM_WAIT_PFC_CTHR_PORTOFFTH_M\tMAKEMASK(0x7FFF, 0)\n+#define PRTDCB_TCUPM_WAIT_PFC_DM\t\t0x000BC480 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_S\t0\n+#define PRTDCB_TCUPM_WAIT_PFC_DM_MONITOR_M\tMAKEMASK(0x7FFFF, 0)\n+#define PRTDCB_TCUPM_WAIT_PFC_DTHR\t\t0x000BC4A0 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_S\t0\n+#define PRTDCB_TCUPM_WAIT_PFC_DTHR_PORTOFFTH_M\tMAKEMASK(0xFFF, 0)\n+#define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM\t\t0x000BC4C0 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_S 0\n+#define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DM_MONITOR_M MAKEMASK(0xFFF, 0)\n+#define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR\t0x000BC4E0 /* Reset Source: CORER */\n+#define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_S 0\n+#define PRTDCB_TCUPM_WAIT_PFC_PE_HB_DTHR_PORTOFFTH_M MAKEMASK(0xFFF, 0)\n+#define PRTDCB_TDPUC\t\t\t\t0x00040940 /* Reset Source: CORER */\n+#define PRTDCB_TDPUC_MAX_TXFRAME_S\t\t0\n+#define PRTDCB_TDPUC_MAX_TXFRAME_M\t\tMAKEMASK(0xFFFF, 0)\n+#define PRTDCB_TDPUC_MAL_LENGTH_S\t\t16\n+#define PRTDCB_TDPUC_MAL_LENGTH_M\t\tBIT(16)\n+#define PRTDCB_TDPUC_MAL_CMD_S\t\t\t17\n+#define PRTDCB_TDPUC_MAL_CMD_M\t\t\tBIT(17)\n+#define PRTDCB_TDPUC_TTL_DROP_S\t\t\t18\n+#define PRTDCB_TDPUC_TTL_DROP_M\t\t\tBIT(18)\n+#define PRTDCB_TDPUC_UR_DROP_S\t\t\t19\n+#define PRTDCB_TDPUC_UR_DROP_M\t\t\tBIT(19)\n+#define PRTDCB_TDPUC_DUMMY_S\t\t\t20\n+#define PRTDCB_TDPUC_DUMMY_M\t\t\tBIT(20)\n+#define PRTDCB_TDPUC_BIG_PKT_SIZE_S\t\t21\n+#define PRTDCB_TDPUC_BIG_PKT_SIZE_M\t\tBIT(21)\n+#define PRTDCB_TDPUC_L2_ACCEPT_FAIL_S\t\t22\n+#define PRTDCB_TDPUC_L2_ACCEPT_FAIL_M\t\tBIT(22)\n+#define PRTDCB_TDPUC_DSCP_CHECK_FAIL_S\t\t23\n+#define PRTDCB_TDPUC_DSCP_CHECK_FAIL_M\t\tBIT(23)\n+#define PRTDCB_TDPUC_RCU_ANTISPOOF_S\t\t24\n+#define PRTDCB_TDPUC_RCU_ANTISPOOF_M\t\tBIT(24)\n+#define PRTDCB_TDPUC_NIC_DSI_S\t\t\t25\n+#define PRTDCB_TDPUC_NIC_DSI_M\t\t\tBIT(25)\n+#define PRTDCB_TDPUC_NIC_IPSEC_S\t\t26\n+#define PRTDCB_TDPUC_NIC_IPSEC_M\t\tBIT(26)\n+#define PRTDCB_TDPUC_CLEAR_DROP_S\t\t31\n+#define PRTDCB_TDPUC_CLEAR_DROP_M\t\tBIT(31)\n+#define PRTDCB_TFCS\t\t\t\t0x001E4560 /* Reset Source: GLOBR */\n+#define PRTDCB_TFCS_TXOFF_S\t\t\t0\n+#define PRTDCB_TFCS_TXOFF_M\t\t\tBIT(0)\n+#define PRTDCB_TFCS_TXOFF0_S\t\t\t8\n+#define PRTDCB_TFCS_TXOFF0_M\t\t\tBIT(8)\n+#define PRTDCB_TFCS_TXOFF1_S\t\t\t9\n+#define PRTDCB_TFCS_TXOFF1_M\t\t\tBIT(9)\n+#define PRTDCB_TFCS_TXOFF2_S\t\t\t10\n+#define PRTDCB_TFCS_TXOFF2_M\t\t\tBIT(10)\n+#define PRTDCB_TFCS_TXOFF3_S\t\t\t11\n+#define PRTDCB_TFCS_TXOFF3_M\t\t\tBIT(11)\n+#define PRTDCB_TFCS_TXOFF4_S\t\t\t12\n+#define PRTDCB_TFCS_TXOFF4_M\t\t\tBIT(12)\n+#define PRTDCB_TFCS_TXOFF5_S\t\t\t13\n+#define PRTDCB_TFCS_TXOFF5_M\t\t\tBIT(13)\n+#define PRTDCB_TFCS_TXOFF6_S\t\t\t14\n+#define PRTDCB_TFCS_TXOFF6_M\t\t\tBIT(14)\n+#define PRTDCB_TFCS_TXOFF7_S\t\t\t15\n+#define PRTDCB_TFCS_TXOFF7_M\t\t\tBIT(15)\n+#define PRTDCB_TLPM_REG_DM\t\t\t0x000A0000 /* Reset Source: CORER */\n+#define PRTDCB_TLPM_REG_DM_MONITOR_S\t\t0\n+#define PRTDCB_TLPM_REG_DM_MONITOR_M\t\tMAKEMASK(0x7FFFF, 0)\n+#define PRTDCB_TLPM_REG_DTHR\t\t\t0x000A0020 /* Reset Source: CORER */\n+#define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_S\t0\n+#define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_H_M\tMAKEMASK(0xFFF, 0)\n+#define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_L_S\t12\n+#define PRTDCB_TLPM_REG_DTHR_PORTOFFTH_L_M\tMAKEMASK(0xFFF, 12)\n+#define PRTDCB_TLPM_WAIT_PFC_DM\t\t\t0x000A0040 /* Reset Source: CORER */\n+#define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_S\t0\n+#define PRTDCB_TLPM_WAIT_PFC_DM_MONITOR_M\tMAKEMASK(0x7FFFF, 0)\n+#define PRTDCB_TLPM_WAIT_PFC_DTHR\t\t0x000A0060 /* Reset Source: CORER */\n+#define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_S\t0\n+#define PRTDCB_TLPM_WAIT_PFC_DTHR_PORTOFFTH_M\tMAKEMASK(0xFFF, 0)\n+#define PRTDCB_TPFCTS(_i)\t\t\t(0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */\n+#define PRTDCB_TPFCTS_MAX_INDEX\t\t\t7\n+#define PRTDCB_TPFCTS_PFCTIMER_S\t\t0\n+#define PRTDCB_TPFCTS_PFCTIMER_M\t\tMAKEMASK(0x3FFF, 0)\n+#define PRTDCB_TUP2TC\t\t\t\t0x001D26C0 /* Reset Source: CORER */\n+#define PRTDCB_TUP2TC_UP0TC_S\t\t\t0\n+#define PRTDCB_TUP2TC_UP0TC_M\t\t\tMAKEMASK(0x7, 0)\n+#define PRTDCB_TUP2TC_UP1TC_S\t\t\t3\n+#define PRTDCB_TUP2TC_UP1TC_M\t\t\tMAKEMASK(0x7, 3)\n+#define PRTDCB_TUP2TC_UP2TC_S\t\t\t6\n+#define PRTDCB_TUP2TC_UP2TC_M\t\t\tMAKEMASK(0x7, 6)\n+#define PRTDCB_TUP2TC_UP3TC_S\t\t\t9\n+#define PRTDCB_TUP2TC_UP3TC_M\t\t\tMAKEMASK(0x7, 9)\n+#define PRTDCB_TUP2TC_UP4TC_S\t\t\t12\n+#define PRTDCB_TUP2TC_UP4TC_M\t\t\tMAKEMASK(0x7, 12)\n+#define PRTDCB_TUP2TC_UP5TC_S\t\t\t15\n+#define PRTDCB_TUP2TC_UP5TC_M\t\t\tMAKEMASK(0x7, 15)\n+#define PRTDCB_TUP2TC_UP6TC_S\t\t\t18\n+#define PRTDCB_TUP2TC_UP6TC_M\t\t\tMAKEMASK(0x7, 18)\n+#define PRTDCB_TUP2TC_UP7TC_S\t\t\t21\n+#define PRTDCB_TUP2TC_UP7TC_M\t\t\tMAKEMASK(0x7, 21)\n+#define PRTDCB_TX_DSCP2UP_CTL\t\t\t0x00040980 /* Reset Source: CORER */\n+#define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_S\t0\n+#define PRTDCB_TX_DSCP2UP_CTL_DSCP2UP_ENA_M\tBIT(0)\n+#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_S 1\n+#define PRTDCB_TX_DSCP2UP_CTL_DSCP_DEFAULT_UP_M MAKEMASK(0x7, 1)\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT(_i)\t\t(0x000409A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_MAX_INDEX\t7\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_S 0\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_S 4\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_S 8\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_3_S 12\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12)\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_4_S 16\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16)\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_5_S 20\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20)\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_6_S 24\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24)\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_7_S 28\n+#define PRTDCB_TX_DSCP2UP_IPV4_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28)\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT(_i)\t\t(0x00040AA0 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_MAX_INDEX\t7\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_S 0\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_0_M MAKEMASK(0x7, 0)\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_1_S 4\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_1_M MAKEMASK(0x7, 4)\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_2_S 8\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_2_M MAKEMASK(0x7, 8)\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_3_S 12\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_3_M MAKEMASK(0x7, 12)\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_4_S 16\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_4_M MAKEMASK(0x7, 16)\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_5_S 20\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_5_M MAKEMASK(0x7, 20)\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_6_S 24\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_6_M MAKEMASK(0x7, 24)\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_7_S 28\n+#define PRTDCB_TX_DSCP2UP_IPV6_LUT_DSCP2UP_LUT_7_M MAKEMASK(0x7, 28)\n+#define PRTTCB_BULK_DWRR_REG_CREDITS\t\t0x000AE060 /* Reset Source: CORER */\n+#define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S\t0\n+#define PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M\tMAKEMASK(0x3FFFF, 0)\n+#define PRTTCB_BULK_DWRR_WB_CREDITS\t\t0x000AE080 /* Reset Source: CORER */\n+#define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S\t0\n+#define PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M\tMAKEMASK(0x3FFFF, 0)\n+#define PRTTCB_CREDIT_EXP\t\t\t0x000AE100 /* Reset Source: CORER */\n+#define PRTTCB_CREDIT_EXP_EXPANSION_S\t\t0\n+#define PRTTCB_CREDIT_EXP_EXPANSION_M\t\tMAKEMASK(0xFF, 0)\n+#define PRTTCB_LL_DWRR_REG_CREDITS\t\t0x000AE0A0 /* Reset Source: CORER */\n+#define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S\t0\n+#define PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M\tMAKEMASK(0x3FFFF, 0)\n+#define PRTTCB_LL_DWRR_WB_CREDITS\t\t0x000AE0C0 /* Reset Source: CORER */\n+#define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S\t0\n+#define PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M\tMAKEMASK(0x3FFFF, 0)\n+#define TCDCB_TCUPM_WAIT_CM(_i)\t\t\t(0x000BC520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCDCB_TCUPM_WAIT_CM_MAX_INDEX\t\t31\n+#define TCDCB_TCUPM_WAIT_CM_MONITOR_S\t\t0\n+#define TCDCB_TCUPM_WAIT_CM_MONITOR_M\t\tMAKEMASK(0x7FFF, 0)\n+#define TCDCB_TCUPM_WAIT_CTHR(_i)\t\t(0x000BC5A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCDCB_TCUPM_WAIT_CTHR_MAX_INDEX\t\t31\n+#define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_S\t\t0\n+#define TCDCB_TCUPM_WAIT_CTHR_TCOFFTH_M\t\tMAKEMASK(0x7FFF, 0)\n+#define TCDCB_TCUPM_WAIT_DM(_i)\t\t\t(0x000BC620 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCDCB_TCUPM_WAIT_DM_MAX_INDEX\t\t31\n+#define TCDCB_TCUPM_WAIT_DM_MONITOR_S\t\t0\n+#define TCDCB_TCUPM_WAIT_DM_MONITOR_M\t\tMAKEMASK(0x7FFFF, 0)\n+#define TCDCB_TCUPM_WAIT_DTHR(_i)\t\t(0x000BC6A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCDCB_TCUPM_WAIT_DTHR_MAX_INDEX\t\t31\n+#define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_S\t\t0\n+#define TCDCB_TCUPM_WAIT_DTHR_TCOFFTH_M\t\tMAKEMASK(0xFFF, 0)\n+#define TCDCB_TCUPM_WAIT_PE_HB_DM(_i)\t\t(0x000BC720 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCDCB_TCUPM_WAIT_PE_HB_DM_MAX_INDEX\t31\n+#define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_S\t0\n+#define TCDCB_TCUPM_WAIT_PE_HB_DM_MONITOR_M\tMAKEMASK(0xFFF, 0)\n+#define TCDCB_TCUPM_WAIT_PE_HB_DTHR(_i)\t\t(0x000BC7A0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCDCB_TCUPM_WAIT_PE_HB_DTHR_MAX_INDEX\t31\n+#define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_S\t0\n+#define TCDCB_TCUPM_WAIT_PE_HB_DTHR_TCOFFTH_M\tMAKEMASK(0xFFF, 0)\n+#define TCDCB_TLPM_WAIT_DM(_i)\t\t\t(0x000A0080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCDCB_TLPM_WAIT_DM_MAX_INDEX\t\t31\n+#define TCDCB_TLPM_WAIT_DM_MONITOR_S\t\t0\n+#define TCDCB_TLPM_WAIT_DM_MONITOR_M\t\tMAKEMASK(0x7FFFF, 0)\n+#define TCDCB_TLPM_WAIT_DTHR(_i)\t\t(0x000A0100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCDCB_TLPM_WAIT_DTHR_MAX_INDEX\t\t31\n+#define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_S\t\t0\n+#define TCDCB_TLPM_WAIT_DTHR_TCOFFTH_M\t\tMAKEMASK(0xFFF, 0)\n+#define TCTCB_WB_RL_TC_CFG(_i)\t\t\t(0x000AE138 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCTCB_WB_RL_TC_CFG_MAX_INDEX\t\t31\n+#define TCTCB_WB_RL_TC_CFG_TOKENS_S\t\t0\n+#define TCTCB_WB_RL_TC_CFG_TOKENS_M\t\tMAKEMASK(0xFFF, 0)\n+#define TCTCB_WB_RL_TC_CFG_BURST_SIZE_S\t\t12\n+#define TCTCB_WB_RL_TC_CFG_BURST_SIZE_M\t\tMAKEMASK(0x3FF, 12)\n+#define TCTCB_WB_RL_TC_STAT(_i)\t\t\t(0x000AE1B8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TCTCB_WB_RL_TC_STAT_MAX_INDEX\t\t31\n+#define TCTCB_WB_RL_TC_STAT_BUCKET_S\t\t0\n+#define TCTCB_WB_RL_TC_STAT_BUCKET_M\t\tMAKEMASK(0x1FFFF, 0)\n+#define TPB_BULK_DWRR_REG_QUANTA\t\t0x00099340 /* Reset Source: CORER */\n+#define TPB_BULK_DWRR_REG_QUANTA_QUANTA_S\t0\n+#define TPB_BULK_DWRR_REG_QUANTA_QUANTA_M\tMAKEMASK(0x7FF, 0)\n+#define TPB_BULK_DWRR_REG_SAT\t\t\t0x00099350 /* Reset Source: CORER */\n+#define TPB_BULK_DWRR_REG_SAT_SATURATION_S\t0\n+#define TPB_BULK_DWRR_REG_SAT_SATURATION_M\tMAKEMASK(0x1FFFF, 0)\n+#define TPB_BULK_DWRR_WB_QUANTA\t\t\t0x00099344 /* Reset Source: CORER */\n+#define TPB_BULK_DWRR_WB_QUANTA_QUANTA_S\t0\n+#define TPB_BULK_DWRR_WB_QUANTA_QUANTA_M\tMAKEMASK(0x7FF, 0)\n+#define TPB_BULK_DWRR_WB_SAT\t\t\t0x00099354 /* Reset Source: CORER */\n+#define TPB_BULK_DWRR_WB_SAT_SATURATION_S\t0\n+#define TPB_BULK_DWRR_WB_SAT_SATURATION_M\tMAKEMASK(0x1FFFF, 0)\n+#define TPB_GLDCB_TCB_WB_SP\t\t\t0x0009966C /* Reset Source: CORER */\n+#define TPB_GLDCB_TCB_WB_SP_WB_SP_S\t\t0\n+#define TPB_GLDCB_TCB_WB_SP_WB_SP_M\t\tBIT(0)\n+#define TPB_GLTCB_CREDIT_EXP_CTL\t\t0x00099664 /* Reset Source: CORER */\n+#define TPB_GLTCB_CREDIT_EXP_CTL_EN_S\t\t0\n+#define TPB_GLTCB_CREDIT_EXP_CTL_EN_M\t\tBIT(0)\n+#define TPB_GLTCB_CREDIT_EXP_CTL_MIN_PKT_S\t1\n+#define TPB_GLTCB_CREDIT_EXP_CTL_MIN_PKT_M\tMAKEMASK(0x1FF, 1)\n+#define TPB_LL_DWRR_REG_QUANTA\t\t\t0x00099348 /* Reset Source: CORER */\n+#define TPB_LL_DWRR_REG_QUANTA_QUANTA_S\t\t0\n+#define TPB_LL_DWRR_REG_QUANTA_QUANTA_M\t\tMAKEMASK(0x7FF, 0)\n+#define TPB_LL_DWRR_REG_SAT\t\t\t0x00099358 /* Reset Source: CORER */\n+#define TPB_LL_DWRR_REG_SAT_SATURATION_S\t0\n+#define TPB_LL_DWRR_REG_SAT_SATURATION_M\tMAKEMASK(0x1FFFF, 0)\n+#define TPB_LL_DWRR_WB_QUANTA\t\t\t0x0009934C /* Reset Source: CORER */\n+#define TPB_LL_DWRR_WB_QUANTA_QUANTA_S\t\t0\n+#define TPB_LL_DWRR_WB_QUANTA_QUANTA_M\t\tMAKEMASK(0x7FF, 0)\n+#define TPB_LL_DWRR_WB_SAT\t\t\t0x0009935C /* Reset Source: CORER */\n+#define TPB_LL_DWRR_WB_SAT_SATURATION_S\t\t0\n+#define TPB_LL_DWRR_WB_SAT_SATURATION_M\t\tMAKEMASK(0x1FFFF, 0)\n+#define TPB_PRTDCB_TCB_DWRR_CREDITS\t\t0x000991C0 /* Reset Source: CORER */\n+#define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_S\t0\n+#define TPB_PRTDCB_TCB_DWRR_CREDITS_CREDITS_M\tMAKEMASK(0x3FFFF, 0)\n+#define TPB_PRTDCB_TCB_DWRR_QUANTA\t\t0x00099220 /* Reset Source: CORER */\n+#define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_S\t0\n+#define TPB_PRTDCB_TCB_DWRR_QUANTA_QUANTA_M\tMAKEMASK(0x7FF, 0)\n+#define TPB_PRTDCB_TCB_DWRR_SAT\t\t\t0x00099260 /* Reset Source: CORER */\n+#define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_S\t0\n+#define TPB_PRTDCB_TCB_DWRR_SAT_SATURATION_M\tMAKEMASK(0x1FFFF, 0)\n+#define TPB_PRTTCB_BULK_DWRR_REG_CREDITS\t0x000992A0 /* Reset Source: CORER */\n+#define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_S 0\n+#define TPB_PRTTCB_BULK_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)\n+#define TPB_PRTTCB_BULK_DWRR_WB_CREDITS\t\t0x000992C0 /* Reset Source: CORER */\n+#define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_S 0\n+#define TPB_PRTTCB_BULK_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)\n+#define TPB_PRTTCB_CREDIT_EXP\t\t\t0x00099644 /* Reset Source: CORER */\n+#define TPB_PRTTCB_CREDIT_EXP_EXPANSION_S\t0\n+#define TPB_PRTTCB_CREDIT_EXP_EXPANSION_M\tMAKEMASK(0xFF, 0)\n+#define TPB_PRTTCB_LL_DWRR_REG_CREDITS\t\t0x00099300 /* Reset Source: CORER */\n+#define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_S 0\n+#define TPB_PRTTCB_LL_DWRR_REG_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)\n+#define TPB_PRTTCB_LL_DWRR_WB_CREDITS\t\t0x00099320 /* Reset Source: CORER */\n+#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_S 0\n+#define TPB_PRTTCB_LL_DWRR_WB_CREDITS_CREDITS_M MAKEMASK(0x3FFFF, 0)\n+#define TPB_WB_RL_TC_CFG(_i)\t\t\t(0x00099360 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TPB_WB_RL_TC_CFG_MAX_INDEX\t\t31\n+#define TPB_WB_RL_TC_CFG_TOKENS_S\t\t0\n+#define TPB_WB_RL_TC_CFG_TOKENS_M\t\tMAKEMASK(0xFFF, 0)\n+#define TPB_WB_RL_TC_CFG_BURST_SIZE_S\t\t12\n+#define TPB_WB_RL_TC_CFG_BURST_SIZE_M\t\tMAKEMASK(0x3FF, 12)\n+#define TPB_WB_RL_TC_STAT(_i)\t\t\t(0x000993E0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define TPB_WB_RL_TC_STAT_MAX_INDEX\t\t31\n+#define TPB_WB_RL_TC_STAT_BUCKET_S\t\t0\n+#define TPB_WB_RL_TC_STAT_BUCKET_M\t\tMAKEMASK(0x1FFFF, 0)\n+#define GL_ACLEXT_CDMD_L1SEL(_i)\t\t(0x00210054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_CDMD_L1SEL_MAX_INDEX\t\t2\n+#define GL_ACLEXT_CDMD_L1SEL_RX_SEL_S\t\t0\n+#define GL_ACLEXT_CDMD_L1SEL_RX_SEL_M\t\tMAKEMASK(0x1F, 0)\n+#define GL_ACLEXT_CDMD_L1SEL_TX_SEL_S\t\t8\n+#define GL_ACLEXT_CDMD_L1SEL_TX_SEL_M\t\tMAKEMASK(0x1F, 8)\n+#define GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_S\t\t16\n+#define GL_ACLEXT_CDMD_L1SEL_AUX0_SEL_M\t\tMAKEMASK(0x1F, 16)\n+#define GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_S\t\t24\n+#define GL_ACLEXT_CDMD_L1SEL_AUX1_SEL_M\t\tMAKEMASK(0x1F, 24)\n+#define GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_S\t30\n+#define GL_ACLEXT_CDMD_L1SEL_BIDIR_ENA_M\tMAKEMASK(0x3, 30)\n+#define GL_ACLEXT_CTLTBL_L2ADDR(_i)\t\t(0x00210084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_CTLTBL_L2ADDR_MAX_INDEX\t2\n+#define GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_S\t0\n+#define GL_ACLEXT_CTLTBL_L2ADDR_LINE_OFF_M\tMAKEMASK(0x7, 0)\n+#define GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_S\t8\n+#define GL_ACLEXT_CTLTBL_L2ADDR_LINE_IDX_M\tMAKEMASK(0x7, 8)\n+#define GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_S\t31\n+#define GL_ACLEXT_CTLTBL_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_ACLEXT_CTLTBL_L2DATA(_i)\t\t(0x00210090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_CTLTBL_L2DATA_MAX_INDEX\t2\n+#define GL_ACLEXT_CTLTBL_L2DATA_DATA_S\t\t0\n+#define GL_ACLEXT_CTLTBL_L2DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_ACLEXT_DFLT_L2PRFL(_i)\t\t(0x00210138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_DFLT_L2PRFL_MAX_INDEX\t\t2\n+#define GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_S\t0\n+#define GL_ACLEXT_DFLT_L2PRFL_DFLT_PRFL_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_ACLEXT_DFLT_L2PRFL_ACL(_i)\t\t(0x00393800 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_DFLT_L2PRFL_ACL_MAX_INDEX\t2\n+#define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_S\t0\n+#define GL_ACLEXT_DFLT_L2PRFL_ACL_DFLT_PRFL_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_ACLEXT_FLGS_L1SEL0_1(_i)\t\t(0x0021006C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_FLGS_L1SEL0_1_MAX_INDEX\t2\n+#define GL_ACLEXT_FLGS_L1SEL0_1_FLS0_S\t\t0\n+#define GL_ACLEXT_FLGS_L1SEL0_1_FLS0_M\t\tMAKEMASK(0x1FF, 0)\n+#define GL_ACLEXT_FLGS_L1SEL0_1_FLS1_S\t\t16\n+#define GL_ACLEXT_FLGS_L1SEL0_1_FLS1_M\t\tMAKEMASK(0x1FF, 16)\n+#define GL_ACLEXT_FLGS_L1SEL2_3(_i)\t\t(0x00210078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_FLGS_L1SEL2_3_MAX_INDEX\t2\n+#define GL_ACLEXT_FLGS_L1SEL2_3_FLS2_S\t\t0\n+#define GL_ACLEXT_FLGS_L1SEL2_3_FLS2_M\t\tMAKEMASK(0x1FF, 0)\n+#define GL_ACLEXT_FLGS_L1SEL2_3_FLS3_S\t\t16\n+#define GL_ACLEXT_FLGS_L1SEL2_3_FLS3_M\t\tMAKEMASK(0x1FF, 16)\n+#define GL_ACLEXT_FLGS_L1TBL(_i)\t\t(0x00210060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_FLGS_L1TBL_MAX_INDEX\t\t2\n+#define GL_ACLEXT_FLGS_L1TBL_LSB_S\t\t0\n+#define GL_ACLEXT_FLGS_L1TBL_LSB_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_ACLEXT_FLGS_L1TBL_MSB_S\t\t16\n+#define GL_ACLEXT_FLGS_L1TBL_MSB_M\t\tMAKEMASK(0xFFFF, 16)\n+#define GL_ACLEXT_FORCE_L1CDID(_i)\t\t(0x00210018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_FORCE_L1CDID_MAX_INDEX\t2\n+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_S\t0\n+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_M\tMAKEMASK(0xF, 0)\n+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31\n+#define GL_ACLEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)\n+#define GL_ACLEXT_FORCE_PID(_i)\t\t\t(0x00210000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_FORCE_PID_MAX_INDEX\t\t2\n+#define GL_ACLEXT_FORCE_PID_STATIC_PID_S\t0\n+#define GL_ACLEXT_FORCE_PID_STATIC_PID_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_S\t31\n+#define GL_ACLEXT_FORCE_PID_STATIC_PID_EN_M\tBIT(31)\n+#define GL_ACLEXT_K2N_L2ADDR(_i)\t\t(0x00210144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_K2N_L2ADDR_MAX_INDEX\t\t2\n+#define GL_ACLEXT_K2N_L2ADDR_LINE_IDX_S\t\t0\n+#define GL_ACLEXT_K2N_L2ADDR_LINE_IDX_M\t\tMAKEMASK(0x7F, 0)\n+#define GL_ACLEXT_K2N_L2ADDR_AUTO_INC_S\t\t31\n+#define GL_ACLEXT_K2N_L2ADDR_AUTO_INC_M\t\tBIT(31)\n+#define GL_ACLEXT_K2N_L2DATA(_i)\t\t(0x00210150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_K2N_L2DATA_MAX_INDEX\t\t2\n+#define GL_ACLEXT_K2N_L2DATA_DATA0_S\t\t0\n+#define GL_ACLEXT_K2N_L2DATA_DATA0_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_ACLEXT_K2N_L2DATA_DATA1_S\t\t8\n+#define GL_ACLEXT_K2N_L2DATA_DATA1_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_ACLEXT_K2N_L2DATA_DATA2_S\t\t16\n+#define GL_ACLEXT_K2N_L2DATA_DATA2_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_ACLEXT_K2N_L2DATA_DATA3_S\t\t24\n+#define GL_ACLEXT_K2N_L2DATA_DATA3_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_ACLEXT_L2_PMASK0(_i)\t\t\t(0x002100FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_L2_PMASK0_MAX_INDEX\t\t2\n+#define GL_ACLEXT_L2_PMASK0_BITMASK_S\t\t0\n+#define GL_ACLEXT_L2_PMASK0_BITMASK_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_ACLEXT_L2_PMASK1(_i)\t\t\t(0x00210108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_L2_PMASK1_MAX_INDEX\t\t2\n+#define GL_ACLEXT_L2_PMASK1_BITMASK_S\t\t0\n+#define GL_ACLEXT_L2_PMASK1_BITMASK_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_ACLEXT_L2_TMASK0(_i)\t\t\t(0x00210498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_L2_TMASK0_MAX_INDEX\t\t2\n+#define GL_ACLEXT_L2_TMASK0_BITMASK_S\t\t0\n+#define GL_ACLEXT_L2_TMASK0_BITMASK_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_ACLEXT_L2_TMASK1(_i)\t\t\t(0x002104A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_L2_TMASK1_MAX_INDEX\t\t2\n+#define GL_ACLEXT_L2_TMASK1_BITMASK_S\t\t0\n+#define GL_ACLEXT_L2_TMASK1_BITMASK_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_ACLEXT_L2BMP0_3(_i)\t\t\t(0x002100A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_L2BMP0_3_MAX_INDEX\t\t2\n+#define GL_ACLEXT_L2BMP0_3_BMP0_S\t\t0\n+#define GL_ACLEXT_L2BMP0_3_BMP0_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_ACLEXT_L2BMP0_3_BMP1_S\t\t8\n+#define GL_ACLEXT_L2BMP0_3_BMP1_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_ACLEXT_L2BMP0_3_BMP2_S\t\t16\n+#define GL_ACLEXT_L2BMP0_3_BMP2_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_ACLEXT_L2BMP0_3_BMP3_S\t\t24\n+#define GL_ACLEXT_L2BMP0_3_BMP3_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_ACLEXT_L2BMP4_7(_i)\t\t\t(0x002100B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_L2BMP4_7_MAX_INDEX\t\t2\n+#define GL_ACLEXT_L2BMP4_7_BMP4_S\t\t0\n+#define GL_ACLEXT_L2BMP4_7_BMP4_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_ACLEXT_L2BMP4_7_BMP5_S\t\t8\n+#define GL_ACLEXT_L2BMP4_7_BMP5_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_ACLEXT_L2BMP4_7_BMP6_S\t\t16\n+#define GL_ACLEXT_L2BMP4_7_BMP6_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_ACLEXT_L2BMP4_7_BMP7_S\t\t24\n+#define GL_ACLEXT_L2BMP4_7_BMP7_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_ACLEXT_L2PRTMOD(_i)\t\t\t(0x0021009C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_L2PRTMOD_MAX_INDEX\t\t2\n+#define GL_ACLEXT_L2PRTMOD_XLT1_S\t\t0\n+#define GL_ACLEXT_L2PRTMOD_XLT1_M\t\tMAKEMASK(0x3, 0)\n+#define GL_ACLEXT_L2PRTMOD_XLT2_S\t\t8\n+#define GL_ACLEXT_L2PRTMOD_XLT2_M\t\tMAKEMASK(0x3, 8)\n+#define GL_ACLEXT_N2N_L2ADDR(_i)\t\t(0x0021015C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_N2N_L2ADDR_MAX_INDEX\t\t2\n+#define GL_ACLEXT_N2N_L2ADDR_LINE_IDX_S\t\t0\n+#define GL_ACLEXT_N2N_L2ADDR_LINE_IDX_M\t\tMAKEMASK(0x3F, 0)\n+#define GL_ACLEXT_N2N_L2ADDR_AUTO_INC_S\t\t31\n+#define GL_ACLEXT_N2N_L2ADDR_AUTO_INC_M\t\tBIT(31)\n+#define GL_ACLEXT_N2N_L2DATA(_i)\t\t(0x00210168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_N2N_L2DATA_MAX_INDEX\t\t2\n+#define GL_ACLEXT_N2N_L2DATA_DATA0_S\t\t0\n+#define GL_ACLEXT_N2N_L2DATA_DATA0_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_ACLEXT_N2N_L2DATA_DATA1_S\t\t8\n+#define GL_ACLEXT_N2N_L2DATA_DATA1_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_ACLEXT_N2N_L2DATA_DATA2_S\t\t16\n+#define GL_ACLEXT_N2N_L2DATA_DATA2_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_ACLEXT_N2N_L2DATA_DATA3_S\t\t24\n+#define GL_ACLEXT_N2N_L2DATA_DATA3_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_ACLEXT_P2P_L1ADDR(_i)\t\t(0x00210024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_P2P_L1ADDR_MAX_INDEX\t\t2\n+#define GL_ACLEXT_P2P_L1ADDR_LINE_IDX_S\t\t0\n+#define GL_ACLEXT_P2P_L1ADDR_LINE_IDX_M\t\tBIT(0)\n+#define GL_ACLEXT_P2P_L1ADDR_AUTO_INC_S\t\t31\n+#define GL_ACLEXT_P2P_L1ADDR_AUTO_INC_M\t\tBIT(31)\n+#define GL_ACLEXT_P2P_L1DATA(_i)\t\t(0x00210030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_P2P_L1DATA_MAX_INDEX\t\t2\n+#define GL_ACLEXT_P2P_L1DATA_DATA_S\t\t0\n+#define GL_ACLEXT_P2P_L1DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_ACLEXT_PID_L2GKTYPE(_i)\t\t(0x002100F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_PID_L2GKTYPE_MAX_INDEX\t2\n+#define GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_S\t0\n+#define GL_ACLEXT_PID_L2GKTYPE_PID_GKTYPE_M\tMAKEMASK(0x3, 0)\n+#define GL_ACLEXT_PLVL_SEL(_i)\t\t\t(0x0021000C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_PLVL_SEL_MAX_INDEX\t\t2\n+#define GL_ACLEXT_PLVL_SEL_PLVL_SEL_S\t\t0\n+#define GL_ACLEXT_PLVL_SEL_PLVL_SEL_M\t\tBIT(0)\n+#define GL_ACLEXT_TCAM_L2ADDR(_i)\t\t(0x00210114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_TCAM_L2ADDR_MAX_INDEX\t\t2\n+#define GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_S\t0\n+#define GL_ACLEXT_TCAM_L2ADDR_LINE_IDX_M\tMAKEMASK(0x3FF, 0)\n+#define GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_S\t31\n+#define GL_ACLEXT_TCAM_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_ACLEXT_TCAM_L2DATALSB(_i)\t\t(0x00210120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_TCAM_L2DATALSB_MAX_INDEX\t2\n+#define GL_ACLEXT_TCAM_L2DATALSB_DATALSB_S\t0\n+#define GL_ACLEXT_TCAM_L2DATALSB_DATALSB_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_ACLEXT_TCAM_L2DATAMSB(_i)\t\t(0x0021012C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_TCAM_L2DATAMSB_MAX_INDEX\t2\n+#define GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_S\t0\n+#define GL_ACLEXT_TCAM_L2DATAMSB_DATAMSB_M\tMAKEMASK(0xFF, 0)\n+#define GL_ACLEXT_XLT0_L1ADDR(_i)\t\t(0x0021003C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_XLT0_L1ADDR_MAX_INDEX\t\t2\n+#define GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_S\t0\n+#define GL_ACLEXT_XLT0_L1ADDR_LINE_IDX_M\tMAKEMASK(0xFF, 0)\n+#define GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_S\t31\n+#define GL_ACLEXT_XLT0_L1ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_ACLEXT_XLT0_L1DATA(_i)\t\t(0x00210048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_XLT0_L1DATA_MAX_INDEX\t\t2\n+#define GL_ACLEXT_XLT0_L1DATA_DATA_S\t\t0\n+#define GL_ACLEXT_XLT0_L1DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_ACLEXT_XLT1_L2ADDR(_i)\t\t(0x002100C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_XLT1_L2ADDR_MAX_INDEX\t\t2\n+#define GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_S\t0\n+#define GL_ACLEXT_XLT1_L2ADDR_LINE_IDX_M\tMAKEMASK(0x7FF, 0)\n+#define GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_S\t31\n+#define GL_ACLEXT_XLT1_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_ACLEXT_XLT1_L2DATA(_i)\t\t(0x002100CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_XLT1_L2DATA_MAX_INDEX\t\t2\n+#define GL_ACLEXT_XLT1_L2DATA_DATA_S\t\t0\n+#define GL_ACLEXT_XLT1_L2DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_ACLEXT_XLT2_L2ADDR(_i)\t\t(0x002100D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_XLT2_L2ADDR_MAX_INDEX\t\t2\n+#define GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_S\t0\n+#define GL_ACLEXT_XLT2_L2ADDR_LINE_IDX_M\tMAKEMASK(0x1FF, 0)\n+#define GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_S\t31\n+#define GL_ACLEXT_XLT2_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_ACLEXT_XLT2_L2DATA(_i)\t\t(0x002100E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_ACLEXT_XLT2_L2DATA_MAX_INDEX\t\t2\n+#define GL_ACLEXT_XLT2_L2DATA_DATA_S\t\t0\n+#define GL_ACLEXT_XLT2_L2DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PREEXT_CDMD_L1SEL(_i)\t\t(0x0020F054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_CDMD_L1SEL_MAX_INDEX\t\t2\n+#define GL_PREEXT_CDMD_L1SEL_RX_SEL_S\t\t0\n+#define GL_PREEXT_CDMD_L1SEL_RX_SEL_M\t\tMAKEMASK(0x1F, 0)\n+#define GL_PREEXT_CDMD_L1SEL_TX_SEL_S\t\t8\n+#define GL_PREEXT_CDMD_L1SEL_TX_SEL_M\t\tMAKEMASK(0x1F, 8)\n+#define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_S\t\t16\n+#define GL_PREEXT_CDMD_L1SEL_AUX0_SEL_M\t\tMAKEMASK(0x1F, 16)\n+#define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_S\t\t24\n+#define GL_PREEXT_CDMD_L1SEL_AUX1_SEL_M\t\tMAKEMASK(0x1F, 24)\n+#define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_S\t30\n+#define GL_PREEXT_CDMD_L1SEL_BIDIR_ENA_M\tMAKEMASK(0x3, 30)\n+#define GL_PREEXT_CTLTBL_L2ADDR(_i)\t\t(0x0020F084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_CTLTBL_L2ADDR_MAX_INDEX\t2\n+#define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_S\t0\n+#define GL_PREEXT_CTLTBL_L2ADDR_LINE_OFF_M\tMAKEMASK(0x7, 0)\n+#define GL_PREEXT_CTLTBL_L2ADDR_LINE_IDX_S\t8\n+#define GL_PREEXT_CTLTBL_L2ADDR_LINE_IDX_M\tMAKEMASK(0x7, 8)\n+#define GL_PREEXT_CTLTBL_L2ADDR_AUTO_INC_S\t31\n+#define GL_PREEXT_CTLTBL_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PREEXT_CTLTBL_L2DATA(_i)\t\t(0x0020F090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_CTLTBL_L2DATA_MAX_INDEX\t2\n+#define GL_PREEXT_CTLTBL_L2DATA_DATA_S\t\t0\n+#define GL_PREEXT_CTLTBL_L2DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PREEXT_DFLT_L2PRFL(_i)\t\t(0x0020F138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_DFLT_L2PRFL_MAX_INDEX\t\t2\n+#define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_S\t0\n+#define GL_PREEXT_DFLT_L2PRFL_DFLT_PRFL_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PREEXT_FLGS_L1SEL0_1(_i)\t\t(0x0020F06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_FLGS_L1SEL0_1_MAX_INDEX\t2\n+#define GL_PREEXT_FLGS_L1SEL0_1_FLS0_S\t\t0\n+#define GL_PREEXT_FLGS_L1SEL0_1_FLS0_M\t\tMAKEMASK(0x1FF, 0)\n+#define GL_PREEXT_FLGS_L1SEL0_1_FLS1_S\t\t16\n+#define GL_PREEXT_FLGS_L1SEL0_1_FLS1_M\t\tMAKEMASK(0x1FF, 16)\n+#define GL_PREEXT_FLGS_L1SEL2_3(_i)\t\t(0x0020F078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_FLGS_L1SEL2_3_MAX_INDEX\t2\n+#define GL_PREEXT_FLGS_L1SEL2_3_FLS2_S\t\t0\n+#define GL_PREEXT_FLGS_L1SEL2_3_FLS2_M\t\tMAKEMASK(0x1FF, 0)\n+#define GL_PREEXT_FLGS_L1SEL2_3_FLS3_S\t\t16\n+#define GL_PREEXT_FLGS_L1SEL2_3_FLS3_M\t\tMAKEMASK(0x1FF, 16)\n+#define GL_PREEXT_FLGS_L1TBL(_i)\t\t(0x0020F060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_FLGS_L1TBL_MAX_INDEX\t\t2\n+#define GL_PREEXT_FLGS_L1TBL_LSB_S\t\t0\n+#define GL_PREEXT_FLGS_L1TBL_LSB_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_PREEXT_FLGS_L1TBL_MSB_S\t\t16\n+#define GL_PREEXT_FLGS_L1TBL_MSB_M\t\tMAKEMASK(0xFFFF, 16)\n+#define GL_PREEXT_FORCE_L1CDID(_i)\t\t(0x0020F018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_FORCE_L1CDID_MAX_INDEX\t2\n+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_S\t0\n+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_M\tMAKEMASK(0xF, 0)\n+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31\n+#define GL_PREEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)\n+#define GL_PREEXT_FORCE_PID(_i)\t\t\t(0x0020F000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_FORCE_PID_MAX_INDEX\t\t2\n+#define GL_PREEXT_FORCE_PID_STATIC_PID_S\t0\n+#define GL_PREEXT_FORCE_PID_STATIC_PID_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PREEXT_FORCE_PID_STATIC_PID_EN_S\t31\n+#define GL_PREEXT_FORCE_PID_STATIC_PID_EN_M\tBIT(31)\n+#define GL_PREEXT_K2N_L2ADDR(_i)\t\t(0x0020F144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_K2N_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PREEXT_K2N_L2ADDR_LINE_IDX_S\t\t0\n+#define GL_PREEXT_K2N_L2ADDR_LINE_IDX_M\t\tMAKEMASK(0x7F, 0)\n+#define GL_PREEXT_K2N_L2ADDR_AUTO_INC_S\t\t31\n+#define GL_PREEXT_K2N_L2ADDR_AUTO_INC_M\t\tBIT(31)\n+#define GL_PREEXT_K2N_L2DATA(_i)\t\t(0x0020F150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_K2N_L2DATA_MAX_INDEX\t\t2\n+#define GL_PREEXT_K2N_L2DATA_DATA0_S\t\t0\n+#define GL_PREEXT_K2N_L2DATA_DATA0_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PREEXT_K2N_L2DATA_DATA1_S\t\t8\n+#define GL_PREEXT_K2N_L2DATA_DATA1_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_PREEXT_K2N_L2DATA_DATA2_S\t\t16\n+#define GL_PREEXT_K2N_L2DATA_DATA2_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_PREEXT_K2N_L2DATA_DATA3_S\t\t24\n+#define GL_PREEXT_K2N_L2DATA_DATA3_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_PREEXT_L2_PMASK0(_i)\t\t\t(0x0020F0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_L2_PMASK0_MAX_INDEX\t\t2\n+#define GL_PREEXT_L2_PMASK0_BITMASK_S\t\t0\n+#define GL_PREEXT_L2_PMASK0_BITMASK_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PREEXT_L2_PMASK1(_i)\t\t\t(0x0020F108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_L2_PMASK1_MAX_INDEX\t\t2\n+#define GL_PREEXT_L2_PMASK1_BITMASK_S\t\t0\n+#define GL_PREEXT_L2_PMASK1_BITMASK_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_PREEXT_L2_TMASK0(_i)\t\t\t(0x0020F498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_L2_TMASK0_MAX_INDEX\t\t2\n+#define GL_PREEXT_L2_TMASK0_BITMASK_S\t\t0\n+#define GL_PREEXT_L2_TMASK0_BITMASK_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PREEXT_L2_TMASK1(_i)\t\t\t(0x0020F4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_L2_TMASK1_MAX_INDEX\t\t2\n+#define GL_PREEXT_L2_TMASK1_BITMASK_S\t\t0\n+#define GL_PREEXT_L2_TMASK1_BITMASK_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PREEXT_L2BMP0_3(_i)\t\t\t(0x0020F0A8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_L2BMP0_3_MAX_INDEX\t\t2\n+#define GL_PREEXT_L2BMP0_3_BMP0_S\t\t0\n+#define GL_PREEXT_L2BMP0_3_BMP0_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PREEXT_L2BMP0_3_BMP1_S\t\t8\n+#define GL_PREEXT_L2BMP0_3_BMP1_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_PREEXT_L2BMP0_3_BMP2_S\t\t16\n+#define GL_PREEXT_L2BMP0_3_BMP2_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_PREEXT_L2BMP0_3_BMP3_S\t\t24\n+#define GL_PREEXT_L2BMP0_3_BMP3_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_PREEXT_L2BMP4_7(_i)\t\t\t(0x0020F0B4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_L2BMP4_7_MAX_INDEX\t\t2\n+#define GL_PREEXT_L2BMP4_7_BMP4_S\t\t0\n+#define GL_PREEXT_L2BMP4_7_BMP4_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PREEXT_L2BMP4_7_BMP5_S\t\t8\n+#define GL_PREEXT_L2BMP4_7_BMP5_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_PREEXT_L2BMP4_7_BMP6_S\t\t16\n+#define GL_PREEXT_L2BMP4_7_BMP6_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_PREEXT_L2BMP4_7_BMP7_S\t\t24\n+#define GL_PREEXT_L2BMP4_7_BMP7_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_PREEXT_L2PRTMOD(_i)\t\t\t(0x0020F09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_L2PRTMOD_MAX_INDEX\t\t2\n+#define GL_PREEXT_L2PRTMOD_XLT1_S\t\t0\n+#define GL_PREEXT_L2PRTMOD_XLT1_M\t\tMAKEMASK(0x3, 0)\n+#define GL_PREEXT_L2PRTMOD_XLT2_S\t\t8\n+#define GL_PREEXT_L2PRTMOD_XLT2_M\t\tMAKEMASK(0x3, 8)\n+#define GL_PREEXT_N2N_L2ADDR(_i)\t\t(0x0020F15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_N2N_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PREEXT_N2N_L2ADDR_LINE_IDX_S\t\t0\n+#define GL_PREEXT_N2N_L2ADDR_LINE_IDX_M\t\tMAKEMASK(0x3F, 0)\n+#define GL_PREEXT_N2N_L2ADDR_AUTO_INC_S\t\t31\n+#define GL_PREEXT_N2N_L2ADDR_AUTO_INC_M\t\tBIT(31)\n+#define GL_PREEXT_N2N_L2DATA(_i)\t\t(0x0020F168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_N2N_L2DATA_MAX_INDEX\t\t2\n+#define GL_PREEXT_N2N_L2DATA_DATA0_S\t\t0\n+#define GL_PREEXT_N2N_L2DATA_DATA0_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PREEXT_N2N_L2DATA_DATA1_S\t\t8\n+#define GL_PREEXT_N2N_L2DATA_DATA1_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_PREEXT_N2N_L2DATA_DATA2_S\t\t16\n+#define GL_PREEXT_N2N_L2DATA_DATA2_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_PREEXT_N2N_L2DATA_DATA3_S\t\t24\n+#define GL_PREEXT_N2N_L2DATA_DATA3_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_PREEXT_P2P_L1ADDR(_i)\t\t(0x0020F024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_P2P_L1ADDR_MAX_INDEX\t\t2\n+#define GL_PREEXT_P2P_L1ADDR_LINE_IDX_S\t\t0\n+#define GL_PREEXT_P2P_L1ADDR_LINE_IDX_M\t\tBIT(0)\n+#define GL_PREEXT_P2P_L1ADDR_AUTO_INC_S\t\t31\n+#define GL_PREEXT_P2P_L1ADDR_AUTO_INC_M\t\tBIT(31)\n+#define GL_PREEXT_P2P_L1DATA(_i)\t\t(0x0020F030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_P2P_L1DATA_MAX_INDEX\t\t2\n+#define GL_PREEXT_P2P_L1DATA_DATA_S\t\t0\n+#define GL_PREEXT_P2P_L1DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PREEXT_PID_L2GKTYPE(_i)\t\t(0x0020F0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_PID_L2GKTYPE_MAX_INDEX\t2\n+#define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_S\t0\n+#define GL_PREEXT_PID_L2GKTYPE_PID_GKTYPE_M\tMAKEMASK(0x3, 0)\n+#define GL_PREEXT_PLVL_SEL(_i)\t\t\t(0x0020F00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_PLVL_SEL_MAX_INDEX\t\t2\n+#define GL_PREEXT_PLVL_SEL_PLVL_SEL_S\t\t0\n+#define GL_PREEXT_PLVL_SEL_PLVL_SEL_M\t\tBIT(0)\n+#define GL_PREEXT_TCAM_L2ADDR(_i)\t\t(0x0020F114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_TCAM_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_S\t0\n+#define GL_PREEXT_TCAM_L2ADDR_LINE_IDX_M\tMAKEMASK(0x3FF, 0)\n+#define GL_PREEXT_TCAM_L2ADDR_AUTO_INC_S\t31\n+#define GL_PREEXT_TCAM_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PREEXT_TCAM_L2DATALSB(_i)\t\t(0x0020F120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_TCAM_L2DATALSB_MAX_INDEX\t2\n+#define GL_PREEXT_TCAM_L2DATALSB_DATALSB_S\t0\n+#define GL_PREEXT_TCAM_L2DATALSB_DATALSB_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PREEXT_TCAM_L2DATAMSB(_i)\t\t(0x0020F12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_TCAM_L2DATAMSB_MAX_INDEX\t2\n+#define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_S\t0\n+#define GL_PREEXT_TCAM_L2DATAMSB_DATAMSB_M\tMAKEMASK(0xFF, 0)\n+#define GL_PREEXT_XLT0_L1ADDR(_i)\t\t(0x0020F03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_XLT0_L1ADDR_MAX_INDEX\t\t2\n+#define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_S\t0\n+#define GL_PREEXT_XLT0_L1ADDR_LINE_IDX_M\tMAKEMASK(0xFF, 0)\n+#define GL_PREEXT_XLT0_L1ADDR_AUTO_INC_S\t31\n+#define GL_PREEXT_XLT0_L1ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PREEXT_XLT0_L1DATA(_i)\t\t(0x0020F048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_XLT0_L1DATA_MAX_INDEX\t\t2\n+#define GL_PREEXT_XLT0_L1DATA_DATA_S\t\t0\n+#define GL_PREEXT_XLT0_L1DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PREEXT_XLT1_L2ADDR(_i)\t\t(0x0020F0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_XLT1_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_S\t0\n+#define GL_PREEXT_XLT1_L2ADDR_LINE_IDX_M\tMAKEMASK(0x7FF, 0)\n+#define GL_PREEXT_XLT1_L2ADDR_AUTO_INC_S\t31\n+#define GL_PREEXT_XLT1_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PREEXT_XLT1_L2DATA(_i)\t\t(0x0020F0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_XLT1_L2DATA_MAX_INDEX\t\t2\n+#define GL_PREEXT_XLT1_L2DATA_DATA_S\t\t0\n+#define GL_PREEXT_XLT1_L2DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PREEXT_XLT2_L2ADDR(_i)\t\t(0x0020F0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_XLT2_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_S\t0\n+#define GL_PREEXT_XLT2_L2ADDR_LINE_IDX_M\tMAKEMASK(0x1FF, 0)\n+#define GL_PREEXT_XLT2_L2ADDR_AUTO_INC_S\t31\n+#define GL_PREEXT_XLT2_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PREEXT_XLT2_L2DATA(_i)\t\t(0x0020F0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PREEXT_XLT2_L2DATA_MAX_INDEX\t\t2\n+#define GL_PREEXT_XLT2_L2DATA_DATA_S\t\t0\n+#define GL_PREEXT_XLT2_L2DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_CDMD_L1SEL(_i)\t\t(0x0020E054 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_CDMD_L1SEL_MAX_INDEX\t\t2\n+#define GL_PSTEXT_CDMD_L1SEL_RX_SEL_S\t\t0\n+#define GL_PSTEXT_CDMD_L1SEL_RX_SEL_M\t\tMAKEMASK(0x1F, 0)\n+#define GL_PSTEXT_CDMD_L1SEL_TX_SEL_S\t\t8\n+#define GL_PSTEXT_CDMD_L1SEL_TX_SEL_M\t\tMAKEMASK(0x1F, 8)\n+#define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_S\t\t16\n+#define GL_PSTEXT_CDMD_L1SEL_AUX0_SEL_M\t\tMAKEMASK(0x1F, 16)\n+#define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_S\t\t24\n+#define GL_PSTEXT_CDMD_L1SEL_AUX1_SEL_M\t\tMAKEMASK(0x1F, 24)\n+#define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_S\t30\n+#define GL_PSTEXT_CDMD_L1SEL_BIDIR_ENA_M\tMAKEMASK(0x3, 30)\n+#define GL_PSTEXT_CTLTBL_L2ADDR(_i)\t\t(0x0020E084 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_CTLTBL_L2ADDR_MAX_INDEX\t2\n+#define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_S\t0\n+#define GL_PSTEXT_CTLTBL_L2ADDR_LINE_OFF_M\tMAKEMASK(0x7, 0)\n+#define GL_PSTEXT_CTLTBL_L2ADDR_LINE_IDX_S\t8\n+#define GL_PSTEXT_CTLTBL_L2ADDR_LINE_IDX_M\tMAKEMASK(0x7, 8)\n+#define GL_PSTEXT_CTLTBL_L2ADDR_AUTO_INC_S\t31\n+#define GL_PSTEXT_CTLTBL_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PSTEXT_CTLTBL_L2DATA(_i)\t\t(0x0020E090 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_CTLTBL_L2DATA_MAX_INDEX\t2\n+#define GL_PSTEXT_CTLTBL_L2DATA_DATA_S\t\t0\n+#define GL_PSTEXT_CTLTBL_L2DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_DFLT_L2PRFL(_i)\t\t(0x0020E138 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_DFLT_L2PRFL_MAX_INDEX\t\t2\n+#define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_S\t0\n+#define GL_PSTEXT_DFLT_L2PRFL_DFLT_PRFL_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PSTEXT_FL15_BMPLSB(_i)\t\t(0x0020E480 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_FL15_BMPLSB_MAX_INDEX\t\t2\n+#define GL_PSTEXT_FL15_BMPLSB_BMPLSB_S\t\t0\n+#define GL_PSTEXT_FL15_BMPLSB_BMPLSB_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_FL15_BMPMSB(_i)\t\t(0x0020E48C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_FL15_BMPMSB_MAX_INDEX\t\t2\n+#define GL_PSTEXT_FL15_BMPMSB_BMPMSB_S\t\t0\n+#define GL_PSTEXT_FL15_BMPMSB_BMPMSB_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_FLGS_L1SEL0_1(_i)\t\t(0x0020E06C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_FLGS_L1SEL0_1_MAX_INDEX\t2\n+#define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_S\t\t0\n+#define GL_PSTEXT_FLGS_L1SEL0_1_FLS0_M\t\tMAKEMASK(0x1FF, 0)\n+#define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_S\t\t16\n+#define GL_PSTEXT_FLGS_L1SEL0_1_FLS1_M\t\tMAKEMASK(0x1FF, 16)\n+#define GL_PSTEXT_FLGS_L1SEL2_3(_i)\t\t(0x0020E078 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_FLGS_L1SEL2_3_MAX_INDEX\t2\n+#define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_S\t\t0\n+#define GL_PSTEXT_FLGS_L1SEL2_3_FLS2_M\t\tMAKEMASK(0x1FF, 0)\n+#define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_S\t\t16\n+#define GL_PSTEXT_FLGS_L1SEL2_3_FLS3_M\t\tMAKEMASK(0x1FF, 16)\n+#define GL_PSTEXT_FLGS_L1TBL(_i)\t\t(0x0020E060 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_FLGS_L1TBL_MAX_INDEX\t\t2\n+#define GL_PSTEXT_FLGS_L1TBL_LSB_S\t\t0\n+#define GL_PSTEXT_FLGS_L1TBL_LSB_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_PSTEXT_FLGS_L1TBL_MSB_S\t\t16\n+#define GL_PSTEXT_FLGS_L1TBL_MSB_M\t\tMAKEMASK(0xFFFF, 16)\n+#define GL_PSTEXT_FORCE_L1CDID(_i)\t\t(0x0020E018 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_FORCE_L1CDID_MAX_INDEX\t2\n+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_S\t0\n+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_M\tMAKEMASK(0xF, 0)\n+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_S 31\n+#define GL_PSTEXT_FORCE_L1CDID_STATIC_CDID_EN_M BIT(31)\n+#define GL_PSTEXT_FORCE_PID(_i)\t\t\t(0x0020E000 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_FORCE_PID_MAX_INDEX\t\t2\n+#define GL_PSTEXT_FORCE_PID_STATIC_PID_S\t0\n+#define GL_PSTEXT_FORCE_PID_STATIC_PID_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_S\t31\n+#define GL_PSTEXT_FORCE_PID_STATIC_PID_EN_M\tBIT(31)\n+#define GL_PSTEXT_K2N_L2ADDR(_i)\t\t(0x0020E144 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_K2N_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_S\t\t0\n+#define GL_PSTEXT_K2N_L2ADDR_LINE_IDX_M\t\tMAKEMASK(0x7F, 0)\n+#define GL_PSTEXT_K2N_L2ADDR_AUTO_INC_S\t\t31\n+#define GL_PSTEXT_K2N_L2ADDR_AUTO_INC_M\t\tBIT(31)\n+#define GL_PSTEXT_K2N_L2DATA(_i)\t\t(0x0020E150 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_K2N_L2DATA_MAX_INDEX\t\t2\n+#define GL_PSTEXT_K2N_L2DATA_DATA0_S\t\t0\n+#define GL_PSTEXT_K2N_L2DATA_DATA0_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PSTEXT_K2N_L2DATA_DATA1_S\t\t8\n+#define GL_PSTEXT_K2N_L2DATA_DATA1_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_PSTEXT_K2N_L2DATA_DATA2_S\t\t16\n+#define GL_PSTEXT_K2N_L2DATA_DATA2_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_PSTEXT_K2N_L2DATA_DATA3_S\t\t24\n+#define GL_PSTEXT_K2N_L2DATA_DATA3_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_PSTEXT_L2_PMASK0(_i)\t\t\t(0x0020E0FC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_L2_PMASK0_MAX_INDEX\t\t2\n+#define GL_PSTEXT_L2_PMASK0_BITMASK_S\t\t0\n+#define GL_PSTEXT_L2_PMASK0_BITMASK_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_L2_PMASK1(_i)\t\t\t(0x0020E108 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_L2_PMASK1_MAX_INDEX\t\t2\n+#define GL_PSTEXT_L2_PMASK1_BITMASK_S\t\t0\n+#define GL_PSTEXT_L2_PMASK1_BITMASK_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_PSTEXT_L2_TMASK0(_i)\t\t\t(0x0020E498 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_L2_TMASK0_MAX_INDEX\t\t2\n+#define GL_PSTEXT_L2_TMASK0_BITMASK_S\t\t0\n+#define GL_PSTEXT_L2_TMASK0_BITMASK_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_L2_TMASK1(_i)\t\t\t(0x0020E4A4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_L2_TMASK1_MAX_INDEX\t\t2\n+#define GL_PSTEXT_L2_TMASK1_BITMASK_S\t\t0\n+#define GL_PSTEXT_L2_TMASK1_BITMASK_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PSTEXT_L2PRTMOD(_i)\t\t\t(0x0020E09C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_L2PRTMOD_MAX_INDEX\t\t2\n+#define GL_PSTEXT_L2PRTMOD_XLT1_S\t\t0\n+#define GL_PSTEXT_L2PRTMOD_XLT1_M\t\tMAKEMASK(0x3, 0)\n+#define GL_PSTEXT_L2PRTMOD_XLT2_S\t\t8\n+#define GL_PSTEXT_L2PRTMOD_XLT2_M\t\tMAKEMASK(0x3, 8)\n+#define GL_PSTEXT_N2N_L2ADDR(_i)\t\t(0x0020E15C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_N2N_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_S\t\t0\n+#define GL_PSTEXT_N2N_L2ADDR_LINE_IDX_M\t\tMAKEMASK(0x3F, 0)\n+#define GL_PSTEXT_N2N_L2ADDR_AUTO_INC_S\t\t31\n+#define GL_PSTEXT_N2N_L2ADDR_AUTO_INC_M\t\tBIT(31)\n+#define GL_PSTEXT_N2N_L2DATA(_i)\t\t(0x0020E168 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_N2N_L2DATA_MAX_INDEX\t\t2\n+#define GL_PSTEXT_N2N_L2DATA_DATA0_S\t\t0\n+#define GL_PSTEXT_N2N_L2DATA_DATA0_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PSTEXT_N2N_L2DATA_DATA1_S\t\t8\n+#define GL_PSTEXT_N2N_L2DATA_DATA1_M\t\tMAKEMASK(0xFF, 8)\n+#define GL_PSTEXT_N2N_L2DATA_DATA2_S\t\t16\n+#define GL_PSTEXT_N2N_L2DATA_DATA2_M\t\tMAKEMASK(0xFF, 16)\n+#define GL_PSTEXT_N2N_L2DATA_DATA3_S\t\t24\n+#define GL_PSTEXT_N2N_L2DATA_DATA3_M\t\tMAKEMASK(0xFF, 24)\n+#define GL_PSTEXT_P2P_L1ADDR(_i)\t\t(0x0020E024 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_P2P_L1ADDR_MAX_INDEX\t\t2\n+#define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_S\t\t0\n+#define GL_PSTEXT_P2P_L1ADDR_LINE_IDX_M\t\tBIT(0)\n+#define GL_PSTEXT_P2P_L1ADDR_AUTO_INC_S\t\t31\n+#define GL_PSTEXT_P2P_L1ADDR_AUTO_INC_M\t\tBIT(31)\n+#define GL_PSTEXT_P2P_L1DATA(_i)\t\t(0x0020E030 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_P2P_L1DATA_MAX_INDEX\t\t2\n+#define GL_PSTEXT_P2P_L1DATA_DATA_S\t\t0\n+#define GL_PSTEXT_P2P_L1DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_PID_L2GKTYPE(_i)\t\t(0x0020E0F0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_PID_L2GKTYPE_MAX_INDEX\t2\n+#define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_S\t0\n+#define GL_PSTEXT_PID_L2GKTYPE_PID_GKTYPE_M\tMAKEMASK(0x3, 0)\n+#define GL_PSTEXT_PLVL_SEL(_i)\t\t\t(0x0020E00C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_PLVL_SEL_MAX_INDEX\t\t2\n+#define GL_PSTEXT_PLVL_SEL_PLVL_SEL_S\t\t0\n+#define GL_PSTEXT_PLVL_SEL_PLVL_SEL_M\t\tBIT(0)\n+#define GL_PSTEXT_PRFLM_CTRL(_i)\t\t(0x0020E474 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_PRFLM_CTRL_MAX_INDEX\t\t2\n+#define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_S\t\t0\n+#define GL_PSTEXT_PRFLM_CTRL_PRFL_IDX_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PSTEXT_PRFLM_CTRL_RD_REQ_S\t\t30\n+#define GL_PSTEXT_PRFLM_CTRL_RD_REQ_M\t\tBIT(30)\n+#define GL_PSTEXT_PRFLM_CTRL_WR_REQ_S\t\t31\n+#define GL_PSTEXT_PRFLM_CTRL_WR_REQ_M\t\tBIT(31)\n+#define GL_PSTEXT_PRFLM_DATA_0(_i)\t\t(0x0020E174 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_PRFLM_DATA_0_MAX_INDEX\t63\n+#define GL_PSTEXT_PRFLM_DATA_0_PROT_S\t\t0\n+#define GL_PSTEXT_PRFLM_DATA_0_PROT_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PSTEXT_PRFLM_DATA_0_OFF_S\t\t16\n+#define GL_PSTEXT_PRFLM_DATA_0_OFF_M\t\tMAKEMASK(0x1FF, 16)\n+#define GL_PSTEXT_PRFLM_DATA_1(_i)\t\t(0x0020E274 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_PRFLM_DATA_1_MAX_INDEX\t63\n+#define GL_PSTEXT_PRFLM_DATA_1_PROT_S\t\t0\n+#define GL_PSTEXT_PRFLM_DATA_1_PROT_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PSTEXT_PRFLM_DATA_1_OFF_S\t\t16\n+#define GL_PSTEXT_PRFLM_DATA_1_OFF_M\t\tMAKEMASK(0x1FF, 16)\n+#define GL_PSTEXT_PRFLM_DATA_2(_i)\t\t(0x0020E374 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_PRFLM_DATA_2_MAX_INDEX\t63\n+#define GL_PSTEXT_PRFLM_DATA_2_PROT_S\t\t0\n+#define GL_PSTEXT_PRFLM_DATA_2_PROT_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_PSTEXT_PRFLM_DATA_2_OFF_S\t\t16\n+#define GL_PSTEXT_PRFLM_DATA_2_OFF_M\t\tMAKEMASK(0x1FF, 16)\n+#define GL_PSTEXT_TCAM_L2ADDR(_i)\t\t(0x0020E114 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_TCAM_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_S\t0\n+#define GL_PSTEXT_TCAM_L2ADDR_LINE_IDX_M\tMAKEMASK(0x3FF, 0)\n+#define GL_PSTEXT_TCAM_L2ADDR_AUTO_INC_S\t31\n+#define GL_PSTEXT_TCAM_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PSTEXT_TCAM_L2DATALSB(_i)\t\t(0x0020E120 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_TCAM_L2DATALSB_MAX_INDEX\t2\n+#define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_S\t0\n+#define GL_PSTEXT_TCAM_L2DATALSB_DATALSB_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_TCAM_L2DATAMSB(_i)\t\t(0x0020E12C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_TCAM_L2DATAMSB_MAX_INDEX\t2\n+#define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_S\t0\n+#define GL_PSTEXT_TCAM_L2DATAMSB_DATAMSB_M\tMAKEMASK(0xFF, 0)\n+#define GL_PSTEXT_XLT0_L1ADDR(_i)\t\t(0x0020E03C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_XLT0_L1ADDR_MAX_INDEX\t\t2\n+#define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_S\t0\n+#define GL_PSTEXT_XLT0_L1ADDR_LINE_IDX_M\tMAKEMASK(0xFF, 0)\n+#define GL_PSTEXT_XLT0_L1ADDR_AUTO_INC_S\t31\n+#define GL_PSTEXT_XLT0_L1ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PSTEXT_XLT0_L1DATA(_i)\t\t(0x0020E048 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_XLT0_L1DATA_MAX_INDEX\t\t2\n+#define GL_PSTEXT_XLT0_L1DATA_DATA_S\t\t0\n+#define GL_PSTEXT_XLT0_L1DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_XLT1_L2ADDR(_i)\t\t(0x0020E0C0 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_XLT1_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_S\t0\n+#define GL_PSTEXT_XLT1_L2ADDR_LINE_IDX_M\tMAKEMASK(0x7FF, 0)\n+#define GL_PSTEXT_XLT1_L2ADDR_AUTO_INC_S\t31\n+#define GL_PSTEXT_XLT1_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PSTEXT_XLT1_L2DATA(_i)\t\t(0x0020E0CC + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_XLT1_L2DATA_MAX_INDEX\t\t2\n+#define GL_PSTEXT_XLT1_L2DATA_DATA_S\t\t0\n+#define GL_PSTEXT_XLT1_L2DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PSTEXT_XLT2_L2ADDR(_i)\t\t(0x0020E0D8 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_XLT2_L2ADDR_MAX_INDEX\t\t2\n+#define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_S\t0\n+#define GL_PSTEXT_XLT2_L2ADDR_LINE_IDX_M\tMAKEMASK(0x1FF, 0)\n+#define GL_PSTEXT_XLT2_L2ADDR_AUTO_INC_S\t31\n+#define GL_PSTEXT_XLT2_L2ADDR_AUTO_INC_M\tBIT(31)\n+#define GL_PSTEXT_XLT2_L2DATA(_i)\t\t(0x0020E0E4 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GL_PSTEXT_XLT2_L2DATA_MAX_INDEX\t\t2\n+#define GL_PSTEXT_XLT2_L2DATA_DATA_S\t\t0\n+#define GL_PSTEXT_XLT2_L2DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLFLXP_PTYPE_TRANSLATION(_i)\t\t(0x0045C000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define GLFLXP_PTYPE_TRANSLATION_MAX_INDEX\t255\n+#define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_S\t0\n+#define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_M\tMAKEMASK(0xFF, 0)\n+#define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_1_S\t8\n+#define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_1_M\tMAKEMASK(0xFF, 8)\n+#define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_2_S\t16\n+#define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_2_M\tMAKEMASK(0xFF, 16)\n+#define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_3_S\t24\n+#define GLFLXP_PTYPE_TRANSLATION_PTYPE_4N_3_M\tMAKEMASK(0xFF, 24)\n+#define GLFLXP_RX_CMD_LX_PROT_IDX(_i)\t\t(0x0045C400 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_MAX_INDEX\t255\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_S 0\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_INNER_CLOUD_OFFSET_INDEX_M MAKEMASK(0x7, 0)\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_S 4\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_OFFSET_INDEX_M MAKEMASK(0x7, 4)\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_S 8\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_PAYLOAD_OFFSET_INDEX_M MAKEMASK(0x7, 8)\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_S 12\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L3_PROTOCOL_M MAKEMASK(0x3, 12)\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_S 14\n+#define GLFLXP_RX_CMD_LX_PROT_IDX_L4_PROTOCOL_M MAKEMASK(0x3, 14)\n+#define GLFLXP_RX_CMD_PROTIDS(_i, _j)\t\t(0x0045A000 + ((_i) * 4 + (_j) * 1024)) /* _i=0...255, _j=0...5 */ /* Reset Source: CORER */\n+#define GLFLXP_RX_CMD_PROTIDS_MAX_INDEX\t\t255\n+#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_S\t0\n+#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_M\tMAKEMASK(0xFF, 0)\n+#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_S\t8\n+#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_1_M\tMAKEMASK(0xFF, 8)\n+#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_S\t16\n+#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_2_M\tMAKEMASK(0xFF, 16)\n+#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_3_S\t24\n+#define GLFLXP_RX_CMD_PROTIDS_PROTID_4N_3_M\tMAKEMASK(0xFF, 24)\n+#define GLFLXP_RXDID_FLAGS(_i, _j)\t\t(0x0045D000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...4 */ /* Reset Source: CORER */\n+#define GLFLXP_RXDID_FLAGS_MAX_INDEX\t\t63\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S\t0\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M\tMAKEMASK(0x3F, 0)\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S\t8\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M\tMAKEMASK(0x3F, 8)\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S\t16\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M\tMAKEMASK(0x3F, 16)\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S\t24\n+#define GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M\tMAKEMASK(0x3F, 24)\n+#define GLFLXP_RXDID_FLAGS1_OVERRIDE(_i)\t(0x0045D600 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GLFLXP_RXDID_FLAGS1_OVERRIDE_MAX_INDEX\t63\n+#define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_S 0\n+#define GLFLXP_RXDID_FLAGS1_OVERRIDE_FLEXIFLAGS1_OVERRIDE_M MAKEMASK(0xF, 0)\n+#define GLFLXP_RXDID_FLX_WRD_0(_i)\t\t(0x0045c800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GLFLXP_RXDID_FLX_WRD_0_MAX_INDEX\t63\n+#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S\t0\n+#define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M\tMAKEMASK(0xFF, 0)\n+#define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_S 8\n+#define GLFLXP_RXDID_FLX_WRD_0_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)\n+#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S\t30\n+#define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M\tMAKEMASK(0x3, 30)\n+#define GLFLXP_RXDID_FLX_WRD_1(_i)\t\t(0x0045c900 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GLFLXP_RXDID_FLX_WRD_1_MAX_INDEX\t63\n+#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S\t0\n+#define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M\tMAKEMASK(0xFF, 0)\n+#define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_S 8\n+#define GLFLXP_RXDID_FLX_WRD_1_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)\n+#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S\t30\n+#define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M\tMAKEMASK(0x3, 30)\n+#define GLFLXP_RXDID_FLX_WRD_2(_i)\t\t(0x0045ca00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GLFLXP_RXDID_FLX_WRD_2_MAX_INDEX\t63\n+#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S\t0\n+#define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M\tMAKEMASK(0xFF, 0)\n+#define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_S 8\n+#define GLFLXP_RXDID_FLX_WRD_2_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)\n+#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S\t30\n+#define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M\tMAKEMASK(0x3, 30)\n+#define GLFLXP_RXDID_FLX_WRD_3(_i)\t\t(0x0045cb00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GLFLXP_RXDID_FLX_WRD_3_MAX_INDEX\t63\n+#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S\t0\n+#define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M\tMAKEMASK(0xFF, 0)\n+#define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_S 8\n+#define GLFLXP_RXDID_FLX_WRD_3_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)\n+#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S\t30\n+#define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M\tMAKEMASK(0x3, 30)\n+#define GLFLXP_RXDID_FLX_WRD_4(_i)\t\t(0x0045cc00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GLFLXP_RXDID_FLX_WRD_4_MAX_INDEX\t63\n+#define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_S\t0\n+#define GLFLXP_RXDID_FLX_WRD_4_PROT_MDID_M\tMAKEMASK(0xFF, 0)\n+#define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_S 8\n+#define GLFLXP_RXDID_FLX_WRD_4_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)\n+#define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_S\t30\n+#define GLFLXP_RXDID_FLX_WRD_4_RXDID_OPCODE_M\tMAKEMASK(0x3, 30)\n+#define GLFLXP_RXDID_FLX_WRD_5(_i)\t\t(0x0045cd00 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GLFLXP_RXDID_FLX_WRD_5_MAX_INDEX\t63\n+#define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_S\t0\n+#define GLFLXP_RXDID_FLX_WRD_5_PROT_MDID_M\tMAKEMASK(0xFF, 0)\n+#define GLFLXP_RXDID_FLX_WRD_5_EXTRACTION_OFFSET_S 8\n+#define GLFLXP_RXDID_FLX_WRD_5_EXTRACTION_OFFSET_M MAKEMASK(0x3FF, 8)\n+#define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_S\t30\n+#define GLFLXP_RXDID_FLX_WRD_5_RXDID_OPCODE_M\tMAKEMASK(0x3, 30)\n+#define GLFLXP_TX_SCHED_CORRECT(_i, _j)\t\t(0x00458000 + ((_i) * 4 + (_j) * 256)) /* _i=0...63, _j=0...31 */ /* Reset Source: CORER */\n+#define GLFLXP_TX_SCHED_CORRECT_MAX_INDEX\t63\n+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_S\t0\n+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_M\tMAKEMASK(0xFF, 0)\n+#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_S\t8\n+#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_M\tMAKEMASK(0x1F, 8)\n+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_S 16\n+#define GLFLXP_TX_SCHED_CORRECT_PROTD_ID_2N_1_M MAKEMASK(0xFF, 16)\n+#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_S\t24\n+#define GLFLXP_TX_SCHED_CORRECT_RECIPE_2N_1_M\tMAKEMASK(0x1F, 24)\n+#define QRXFLXP_CNTXT(_QRX)\t\t\t(0x00480000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define QRXFLXP_CNTXT_MAX_INDEX\t\t\t2047\n+#define QRXFLXP_CNTXT_RXDID_IDX_S\t\t0\n+#define QRXFLXP_CNTXT_RXDID_IDX_M\t\tMAKEMASK(0x3F, 0)\n+#define QRXFLXP_CNTXT_RXDID_PRIO_S\t\t8\n+#define QRXFLXP_CNTXT_RXDID_PRIO_M\t\tMAKEMASK(0x7, 8)\n+#define QRXFLXP_CNTXT_TS_S\t\t\t11\n+#define QRXFLXP_CNTXT_TS_M\t\t\tBIT(11)\n+#define GL_FWSTS\t\t\t\t0x00083048 /* Reset Source: POR */\n+#define GL_FWSTS_FWS0B_S\t\t\t0\n+#define GL_FWSTS_FWS0B_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GL_FWSTS_FWROWD_S\t\t\t8\n+#define GL_FWSTS_FWROWD_M\t\t\tBIT(8)\n+#define GL_FWSTS_FWRI_S\t\t\t\t9\n+#define GL_FWSTS_FWRI_M\t\t\t\tBIT(9)\n+#define GL_FWSTS_FWS1B_S\t\t\t16\n+#define GL_FWSTS_FWS1B_M\t\t\tMAKEMASK(0xFF, 16)\n+#define GL_TCVMLR_DRAIN_CNTR_CTL\t\t0x000A21E0 /* Reset Source: CORER */\n+#define GL_TCVMLR_DRAIN_CNTR_CTL_OP_S\t\t0\n+#define GL_TCVMLR_DRAIN_CNTR_CTL_OP_M\t\tBIT(0)\n+#define GL_TCVMLR_DRAIN_CNTR_CTL_PORT_S\t\t1\n+#define GL_TCVMLR_DRAIN_CNTR_CTL_PORT_M\t\tMAKEMASK(0x7, 1)\n+#define GL_TCVMLR_DRAIN_CNTR_CTL_VALUE_S\t4\n+#define GL_TCVMLR_DRAIN_CNTR_CTL_VALUE_M\tMAKEMASK(0x3FFF, 4)\n+#define GL_TCVMLR_DRAIN_DONE_DEC\t\t0x000A21A8 /* Reset Source: CORER */\n+#define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_S\t0\n+#define GL_TCVMLR_DRAIN_DONE_DEC_TARGET_M\tBIT(0)\n+#define GL_TCVMLR_DRAIN_DONE_DEC_INDEX_S\t1\n+#define GL_TCVMLR_DRAIN_DONE_DEC_INDEX_M\tMAKEMASK(0x1F, 1)\n+#define GL_TCVMLR_DRAIN_DONE_DEC_VALUE_S\t6\n+#define GL_TCVMLR_DRAIN_DONE_DEC_VALUE_M\tMAKEMASK(0xFF, 6)\n+#define GL_TCVMLR_DRAIN_DONE_TCLAN(_i)\t\t(0x000A20A8 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GL_TCVMLR_DRAIN_DONE_TCLAN_MAX_INDEX\t31\n+#define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_S\t0\n+#define GL_TCVMLR_DRAIN_DONE_TCLAN_COUNT_M\tMAKEMASK(0xFF, 0)\n+#define GL_TCVMLR_DRAIN_DONE_TPB(_i)\t\t(0x000A2128 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GL_TCVMLR_DRAIN_DONE_TPB_MAX_INDEX\t31\n+#define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_S\t0\n+#define GL_TCVMLR_DRAIN_DONE_TPB_COUNT_M\tMAKEMASK(0xFF, 0)\n+#define GL_TCVMLR_DRAIN_MARKER\t\t\t0x000A2008 /* Reset Source: CORER */\n+#define GL_TCVMLR_DRAIN_MARKER_PORT_S\t\t0\n+#define GL_TCVMLR_DRAIN_MARKER_PORT_M\t\tMAKEMASK(0x7, 0)\n+#define GL_TCVMLR_DRAIN_MARKER_TC_S\t\t3\n+#define GL_TCVMLR_DRAIN_MARKER_TC_M\t\tMAKEMASK(0x1F, 3)\n+#define GL_TCVMLR_ERR_STAT\t\t\t0x000A2024 /* Reset Source: CORER */\n+#define GL_TCVMLR_ERR_STAT_ERROR_S\t\t0\n+#define GL_TCVMLR_ERR_STAT_ERROR_M\t\tBIT(0)\n+#define GL_TCVMLR_ERR_STAT_FW_REQ_S\t\t1\n+#define GL_TCVMLR_ERR_STAT_FW_REQ_M\t\tBIT(1)\n+#define GL_TCVMLR_ERR_STAT_STAT_S\t\t2\n+#define GL_TCVMLR_ERR_STAT_STAT_M\t\tMAKEMASK(0x7, 2)\n+#define GL_TCVMLR_ERR_STAT_ENT_TYPE_S\t\t5\n+#define GL_TCVMLR_ERR_STAT_ENT_TYPE_M\t\tMAKEMASK(0x7, 5)\n+#define GL_TCVMLR_ERR_STAT_ENT_ID_S\t\t8\n+#define GL_TCVMLR_ERR_STAT_ENT_ID_M\t\tMAKEMASK(0x3FFF, 8)\n+#define GL_TCVMLR_QCFG\t\t\t\t0x000A2010 /* Reset Source: CORER */\n+#define GL_TCVMLR_QCFG_QID_S\t\t\t0\n+#define GL_TCVMLR_QCFG_QID_M\t\t\tMAKEMASK(0x3FFF, 0)\n+#define GL_TCVMLR_QCFG_OP_S\t\t\t14\n+#define GL_TCVMLR_QCFG_OP_M\t\t\tBIT(14)\n+#define GL_TCVMLR_QCFG_PORT_S\t\t\t15\n+#define GL_TCVMLR_QCFG_PORT_M\t\t\tMAKEMASK(0x7, 15)\n+#define GL_TCVMLR_QCFG_TC_S\t\t\t18\n+#define GL_TCVMLR_QCFG_TC_M\t\t\tMAKEMASK(0x1F, 18)\n+#define GL_TCVMLR_QCFG_RD\t\t\t0x000A2014 /* Reset Source: CORER */\n+#define GL_TCVMLR_QCFG_RD_QID_S\t\t\t0\n+#define GL_TCVMLR_QCFG_RD_QID_M\t\t\tMAKEMASK(0x3FFF, 0)\n+#define GL_TCVMLR_QCFG_RD_PORT_S\t\t14\n+#define GL_TCVMLR_QCFG_RD_PORT_M\t\tMAKEMASK(0x7, 14)\n+#define GL_TCVMLR_QCFG_RD_TC_S\t\t\t17\n+#define GL_TCVMLR_QCFG_RD_TC_M\t\t\tMAKEMASK(0x1F, 17)\n+#define GL_TCVMLR_QCNTR\t\t\t\t0x000A200C /* Reset Source: CORER */\n+#define GL_TCVMLR_QCNTR_CNTR_S\t\t\t0\n+#define GL_TCVMLR_QCNTR_CNTR_M\t\t\tMAKEMASK(0x7FFF, 0)\n+#define GL_TCVMLR_QCTL\t\t\t\t0x000A2004 /* Reset Source: CORER */\n+#define GL_TCVMLR_QCTL_QID_S\t\t\t0\n+#define GL_TCVMLR_QCTL_QID_M\t\t\tMAKEMASK(0x3FFF, 0)\n+#define GL_TCVMLR_QCTL_OP_S\t\t\t14\n+#define GL_TCVMLR_QCTL_OP_M\t\t\tBIT(14)\n+#define GL_TCVMLR_REQ_STAT\t\t\t0x000A2018 /* Reset Source: CORER */\n+#define GL_TCVMLR_REQ_STAT_ENT_TYPE_S\t\t0\n+#define GL_TCVMLR_REQ_STAT_ENT_TYPE_M\t\tMAKEMASK(0x7, 0)\n+#define GL_TCVMLR_REQ_STAT_ENT_ID_S\t\t3\n+#define GL_TCVMLR_REQ_STAT_ENT_ID_M\t\tMAKEMASK(0x3FFF, 3)\n+#define GL_TCVMLR_REQ_STAT_OP_S\t\t\t17\n+#define GL_TCVMLR_REQ_STAT_OP_M\t\t\tBIT(17)\n+#define GL_TCVMLR_REQ_STAT_WRITE_STATUS_S\t18\n+#define GL_TCVMLR_REQ_STAT_WRITE_STATUS_M\tMAKEMASK(0x7, 18)\n+#define GL_TCVMLR_STAT\t\t\t\t0x000A201C /* Reset Source: CORER */\n+#define GL_TCVMLR_STAT_ENT_TYPE_S\t\t0\n+#define GL_TCVMLR_STAT_ENT_TYPE_M\t\tMAKEMASK(0x7, 0)\n+#define GL_TCVMLR_STAT_ENT_ID_S\t\t\t3\n+#define GL_TCVMLR_STAT_ENT_ID_M\t\t\tMAKEMASK(0x3FFF, 3)\n+#define GL_TCVMLR_STAT_STATUS_S\t\t\t17\n+#define GL_TCVMLR_STAT_STATUS_M\t\t\tMAKEMASK(0x7, 17)\n+#define GL_XLR_MARKER_TRIG_TCVMLR\t\t0x000A2000 /* Reset Source: CORER */\n+#define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_S\t0\n+#define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_NUM_M\tMAKEMASK(0x3FF, 0)\n+#define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_TYPE_S\t10\n+#define GL_XLR_MARKER_TRIG_TCVMLR_VM_VF_TYPE_M\tMAKEMASK(0x3, 10)\n+#define GL_XLR_MARKER_TRIG_TCVMLR_PF_NUM_S\t12\n+#define GL_XLR_MARKER_TRIG_TCVMLR_PF_NUM_M\tMAKEMASK(0x7, 12)\n+#define GL_XLR_MARKER_TRIG_TCVMLR_PORT_NUM_S\t16\n+#define GL_XLR_MARKER_TRIG_TCVMLR_PORT_NUM_M\tMAKEMASK(0x7, 16)\n+#define GL_XLR_MARKER_TRIG_VMLR\t\t\t0x00093804 /* Reset Source: CORER */\n+#define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_S\t0\n+#define GL_XLR_MARKER_TRIG_VMLR_VM_VF_NUM_M\tMAKEMASK(0x3FF, 0)\n+#define GL_XLR_MARKER_TRIG_VMLR_VM_VF_TYPE_S\t10\n+#define GL_XLR_MARKER_TRIG_VMLR_VM_VF_TYPE_M\tMAKEMASK(0x3, 10)\n+#define GL_XLR_MARKER_TRIG_VMLR_PF_NUM_S\t12\n+#define GL_XLR_MARKER_TRIG_VMLR_PF_NUM_M\tMAKEMASK(0x7, 12)\n+#define GL_XLR_MARKER_TRIG_VMLR_PORT_NUM_S\t16\n+#define GL_XLR_MARKER_TRIG_VMLR_PORT_NUM_M\tMAKEMASK(0x7, 16)\n+#define GLGEN_ANA_ABORT_PTYPE\t\t\t0x0020C21C /* Reset Source: CORER */\n+#define GLGEN_ANA_ABORT_PTYPE_ABORT_S\t\t0\n+#define GLGEN_ANA_ABORT_PTYPE_ABORT_M\t\tMAKEMASK(0x3FF, 0)\n+#define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT\t\t0x0020C208 /* Reset Source: CORER */\n+#define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_S\t0\n+#define GLGEN_ANA_ALU_ACCSS_OUT_OF_PKT_NPC_M\tMAKEMASK(0xFF, 0)\n+#define GLGEN_ANA_CFG_CTRL\t\t\t0x0020C104 /* Reset Source: CORER */\n+#define GLGEN_ANA_CFG_CTRL_LINE_IDX_S\t\t0\n+#define GLGEN_ANA_CFG_CTRL_LINE_IDX_M\t\tMAKEMASK(0x3FFFF, 0)\n+#define GLGEN_ANA_CFG_CTRL_TABLE_ID_S\t\t18\n+#define GLGEN_ANA_CFG_CTRL_TABLE_ID_M\t\tMAKEMASK(0xFF, 18)\n+#define GLGEN_ANA_CFG_CTRL_RESRVED_S\t\t26\n+#define GLGEN_ANA_CFG_CTRL_RESRVED_M\t\tMAKEMASK(0x7, 26)\n+#define GLGEN_ANA_CFG_CTRL_OPERATION_ID_S\t29\n+#define GLGEN_ANA_CFG_CTRL_OPERATION_ID_M\tMAKEMASK(0x7, 29)\n+#define GLGEN_ANA_CFG_HTBL_LU_RESULT\t\t0x0020C158 /* Reset Source: CORER */\n+#define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_S\t0\n+#define GLGEN_ANA_CFG_HTBL_LU_RESULT_HIT_M\tBIT(0)\n+#define GLGEN_ANA_CFG_HTBL_LU_RESULT_PG_MEM_IDX_S 1\n+#define GLGEN_ANA_CFG_HTBL_LU_RESULT_PG_MEM_IDX_M MAKEMASK(0x7, 1)\n+#define GLGEN_ANA_CFG_HTBL_LU_RESULT_ADDR_S\t4\n+#define GLGEN_ANA_CFG_HTBL_LU_RESULT_ADDR_M\tMAKEMASK(0x1FF, 4)\n+#define GLGEN_ANA_CFG_LU_KEY(_i)\t\t(0x0020C14C + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_CFG_LU_KEY_MAX_INDEX\t\t2\n+#define GLGEN_ANA_CFG_LU_KEY_LU_KEY_S\t\t0\n+#define GLGEN_ANA_CFG_LU_KEY_LU_KEY_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_CFG_RDDATA(_i)\t\t(0x0020C10C + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_CFG_RDDATA_MAX_INDEX\t\t15\n+#define GLGEN_ANA_CFG_RDDATA_RD_DATA_S\t\t0\n+#define GLGEN_ANA_CFG_RDDATA_RD_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_CFG_SPLBUF_LU_RESULT\t\t0x0020C15C /* Reset Source: CORER */\n+#define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_S\t0\n+#define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_HIT_M\tBIT(0)\n+#define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_RSV_S\t1\n+#define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_RSV_M\tMAKEMASK(0x7, 1)\n+#define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_ADDR_S\t4\n+#define GLGEN_ANA_CFG_SPLBUF_LU_RESULT_ADDR_M\tMAKEMASK(0x1FF, 4)\n+#define GLGEN_ANA_CFG_WRDATA\t\t\t0x0020C108 /* Reset Source: CORER */\n+#define GLGEN_ANA_CFG_WRDATA_WR_DATA_S\t\t0\n+#define GLGEN_ANA_CFG_WRDATA_WR_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_DEF_PTYPE\t\t\t0x0020C100 /* Reset Source: CORER */\n+#define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_S\t\t0\n+#define GLGEN_ANA_DEF_PTYPE_DEF_PTYPE_M\t\tMAKEMASK(0x3FF, 0)\n+#define GLGEN_ANA_DFD_FIFO_0\t\t\t0x0020C398 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_FIFO_0_PC_NXT_S\t\t0\n+#define GLGEN_ANA_DFD_FIFO_0_PC_NXT_M\t\tBIT(0)\n+#define GLGEN_ANA_DFD_FIFO_0_HO_NXT_S\t\t1\n+#define GLGEN_ANA_DFD_FIFO_0_HO_NXT_M\t\tBIT(1)\n+#define GLGEN_ANA_DFD_FIFO_0_NID_NXT_S\t\t2\n+#define GLGEN_ANA_DFD_FIFO_0_NID_NXT_M\t\tBIT(2)\n+#define GLGEN_ANA_DFD_FIFO_0_PG_KEY_SEL_S\t8\n+#define GLGEN_ANA_DFD_FIFO_0_PG_KEY_SEL_M\tBIT(8)\n+#define GLGEN_ANA_DFD_FIFO_PTR\t\t\t0x0020C43C /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_FIFO_PTR_HEAD_S\t\t0\n+#define GLGEN_ANA_DFD_FIFO_PTR_HEAD_M\t\tMAKEMASK(0x1FF, 0)\n+#define GLGEN_ANA_DFD_FIFO_PTR_USED_SPACE_S\t16\n+#define GLGEN_ANA_DFD_FIFO_PTR_USED_SPACE_M\tMAKEMASK(0x3FF, 16)\n+#define GLGEN_ANA_DFD_GEN_CTRL\t\t\t0x0020C38C /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_GEN_CTRL_ENABLE_S\t\t0\n+#define GLGEN_ANA_DFD_GEN_CTRL_ENABLE_M\t\tBIT(0)\n+#define GLGEN_ANA_DFD_GEN_CTRL_BLK_INPUT_S\t1\n+#define GLGEN_ANA_DFD_GEN_CTRL_BLK_INPUT_M\tBIT(1)\n+#define GLGEN_ANA_DFD_LOG_0\t\t\t0x0020C3A8 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_LOG_0_SOURCE_S\t\t0\n+#define GLGEN_ANA_DFD_LOG_0_SOURCE_M\t\tMAKEMASK(0x7, 0)\n+#define GLGEN_ANA_DFD_LOG_0_LVL_OR_EDGE_S\t3\n+#define GLGEN_ANA_DFD_LOG_0_LVL_OR_EDGE_M\tBIT(3)\n+#define GLGEN_ANA_DFD_LOG_0_RC_DISP_TRIG_S\t4\n+#define GLGEN_ANA_DFD_LOG_0_RC_DISP_TRIG_M\tMAKEMASK(0x7, 4)\n+#define GLGEN_ANA_DFD_LOG_0_FLD_MODE_S\t\t8\n+#define GLGEN_ANA_DFD_LOG_0_FLD_MODE_M\t\tBIT(8)\n+#define GLGEN_ANA_DFD_LOG_0_DLY_CYCL_S\t\t16\n+#define GLGEN_ANA_DFD_LOG_0_DLY_CYCL_M\t\tMAKEMASK(0x3FF, 16)\n+#define GLGEN_ANA_DFD_LOG_1\t\t\t0x0020C3AC /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_LOG_1_NUM_EVENTS_S\t0\n+#define GLGEN_ANA_DFD_LOG_1_NUM_EVENTS_M\tMAKEMASK(0x3FF, 0)\n+#define GLGEN_ANA_DFD_LOG_1_NUM_TRIGS_S\t\t16\n+#define GLGEN_ANA_DFD_LOG_1_NUM_TRIGS_M\t\tMAKEMASK(0x3FF, 16)\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN\t\t0x0020C3F8 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_PH_ARB_S\t0\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_PH_ARB_M\tBIT(0)\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_PH_FB_S\t1\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_PH_FB_M\tBIT(1)\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_INPUT_S\t2\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_BLK_INPUT_M\tBIT(2)\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_STP_OUTPUT_S\t3\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_STP_OUTPUT_M\tBIT(3)\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_S 4\n+#define GLGEN_ANA_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_M BIT(4)\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST\t\t0x0020C3FC /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_PH_ARB_S 0\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_PH_ARB_M BIT(0)\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_PH_FB_S\t1\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_PH_FB_M\tBIT(1)\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_INPUT_S\t2\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_BLK_INPUT_M\tBIT(2)\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_STP_OUTPUT_S 3\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_STP_OUTPUT_M BIT(3)\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_S 4\n+#define GLGEN_ANA_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_M BIT(4)\n+#define GLGEN_ANA_DFD_LOG_DATA(_i)\t\t(0x0020C3B0 + ((_i) * 4)) /* _i=0...8 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_LOG_DATA_MAX_INDEX\t8\n+#define GLGEN_ANA_DFD_LOG_DATA_DATA_S\t\t0\n+#define GLGEN_ANA_DFD_LOG_DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_DFD_LOG_MASK(_i)\t\t(0x0020C3D4 + ((_i) * 4)) /* _i=0...8 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_LOG_MASK_MAX_INDEX\t8\n+#define GLGEN_ANA_DFD_LOG_MASK_MASK_S\t\t0\n+#define GLGEN_ANA_DFD_LOG_MASK_MASK_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_DFD_LOG_RST_ALL\t\t0x0020C400 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_LOG_RST_ALL_RST_S\t\t0\n+#define GLGEN_ANA_DFD_LOG_RST_ALL_RST_M\t\tBIT(0)\n+#define GLGEN_ANA_DFD_LOG_RST_ALL_GEN_RST_S\t1\n+#define GLGEN_ANA_DFD_LOG_RST_ALL_GEN_RST_M\tBIT(1)\n+#define GLGEN_ANA_DFD_LOG_TRG_0\t\t\t0x0020C404 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_LOG_TRG_0_TAGID_S\t\t0\n+#define GLGEN_ANA_DFD_LOG_TRG_0_TAGID_M\t\tMAKEMASK(0x3F, 0)\n+#define GLGEN_ANA_DFD_LOG_TRG_0_ACT_TRIGGED_S\t16\n+#define GLGEN_ANA_DFD_LOG_TRG_0_ACT_TRIGGED_M\tBIT(16)\n+#define GLGEN_ANA_DFD_LOG_TRG_0_MAX_NUM_RND_S\t24\n+#define GLGEN_ANA_DFD_LOG_TRG_0_MAX_NUM_RND_M\tMAKEMASK(0x7F, 24)\n+#define GLGEN_ANA_DFD_LOG_TRG_0_TRIGGED_S\t31\n+#define GLGEN_ANA_DFD_LOG_TRG_0_TRIGGED_M\tBIT(31)\n+#define GLGEN_ANA_DFD_LOG_TRG_DATA(_i)\t\t(0x0020C408 + ((_i) * 4)) /* _i=0...8 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_LOG_TRG_DATA_MAX_INDEX\t8\n+#define GLGEN_ANA_DFD_LOG_TRG_DATA_DATA_S\t0\n+#define GLGEN_ANA_DFD_LOG_TRG_DATA_DATA_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_DFD_PACE_OUT\t\t\t0x0020C4CC /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_PACE_OUT_PUSH_S\t\t0\n+#define GLGEN_ANA_DFD_PACE_OUT_PUSH_M\t\tBIT(0)\n+#define GLGEN_ANA_DFD_PACING_0\t\t\t0x0020C390 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_PACING_0_STOP_FEEDBK_S\t0\n+#define GLGEN_ANA_DFD_PACING_0_STOP_FEEDBK_M\tBIT(0)\n+#define GLGEN_ANA_DFD_PACING_0_STOP_ARB_S\t1\n+#define GLGEN_ANA_DFD_PACING_0_STOP_ARB_M\tBIT(1)\n+#define GLGEN_ANA_DFD_PACING_0_NUM_CHUNKS_S\t2\n+#define GLGEN_ANA_DFD_PACING_0_NUM_CHUNKS_M\tMAKEMASK(0x1F, 2)\n+#define GLGEN_ANA_DFD_PACING_1\t\t\t0x0020C394 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_PACING_1_PUSH_S\t\t0\n+#define GLGEN_ANA_DFD_PACING_1_PUSH_M\t\tBIT(0)\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_0\t\t0x0020C39C /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_0_SLOT_ID_S\t0\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_0_SLOT_ID_M\tMAKEMASK(0xF, 0)\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_1\t\t0x0020C3A0 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_1_REGID_S\t0\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_1_REGID_M\tMAKEMASK(0xFF, 0)\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_RES\t\t0x0020C3A4 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_RES_REG_VAL_S 0\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_RES_REG_VAL_M MAKEMASK(0xFFFF, 0)\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_RES_EXCEPTIONS_S 16\n+#define GLGEN_ANA_DFD_REG_FILE_ACC_RES_EXCEPTIONS_M MAKEMASK(0x7FFF, 16)\n+#define GLGEN_ANA_DFD_TAGIDS\t\t\t0x0020C438 /* Reset Source: CORER */\n+#define GLGEN_ANA_DFD_TAGIDS_TAGID_IN_DFD_FIFO_S 0\n+#define GLGEN_ANA_DFD_TAGIDS_TAGID_IN_DFD_FIFO_M MAKEMASK(0x3F, 0)\n+#define GLGEN_ANA_DFD_TAGIDS_TAGID_NXT_ANA_S\t8\n+#define GLGEN_ANA_DFD_TAGIDS_TAGID_NXT_ANA_M\tMAKEMASK(0x3F, 8)\n+#define GLGEN_ANA_DFD_TAGIDS_TAGID_OUT_S\t16\n+#define GLGEN_ANA_DFD_TAGIDS_TAGID_OUT_M\tMAKEMASK(0x3F, 16)\n+#define GLGEN_ANA_DFD_TAGIDS_SLOTID_IN_DFD_FIFO_S 24\n+#define GLGEN_ANA_DFD_TAGIDS_SLOTID_IN_DFD_FIFO_M MAKEMASK(0xF, 24)\n+#define GLGEN_ANA_DFD_TAGIDS_SLOTID_NXT_ANA_S\t28\n+#define GLGEN_ANA_DFD_TAGIDS_SLOTID_NXT_ANA_M\tMAKEMASK(0xF, 28)\n+#define GLGEN_ANA_ERR_AUX\t\t\t0x0020C228 /* Reset Source: CORER */\n+#define GLGEN_ANA_ERR_AUX_IPLEN_GPREG_S\t\t0\n+#define GLGEN_ANA_ERR_AUX_IPLEN_GPREG_M\t\tMAKEMASK(0xF, 0)\n+#define GLGEN_ANA_ERR_CTRL\t\t\t0x0020C220 /* Reset Source: CORER */\n+#define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_S\t0\n+#define GLGEN_ANA_ERR_CTRL_ERR_MASK_EN_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_FLAG_MAP(_i)\t\t\t(0x0020C000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_FLAG_MAP_MAX_INDEX\t\t63\n+#define GLGEN_ANA_FLAG_MAP_FLAG_EN_S\t\t0\n+#define GLGEN_ANA_FLAG_MAP_FLAG_EN_M\t\tBIT(0)\n+#define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_S\t1\n+#define GLGEN_ANA_FLAG_MAP_EXT_FLAG_ID_M\tMAKEMASK(0x3F, 1)\n+#define GLGEN_ANA_GEN_DFD_RO\t\t\t0x0020C4C8 /* Reset Source: CORER */\n+#define GLGEN_ANA_GEN_DFD_RO_GEN_VAL_S\t\t0\n+#define GLGEN_ANA_GEN_DFD_RO_GEN_VAL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_GIGO_FIFO_PTR\t\t\t0x0020C448 /* Reset Source: CORER */\n+#define GLGEN_ANA_GIGO_FIFO_PTR_HEAD_S\t\t0\n+#define GLGEN_ANA_GIGO_FIFO_PTR_HEAD_M\t\tMAKEMASK(0x1FF, 0)\n+#define GLGEN_ANA_GIGO_FIFO_PTR_USED_SPACE_S\t16\n+#define GLGEN_ANA_GIGO_FIFO_PTR_USED_SPACE_M\tMAKEMASK(0x3FF, 16)\n+#define GLGEN_ANA_HDR_FIFO_FIFO_PTR\t\t0x0020C44C /* Reset Source: CORER */\n+#define GLGEN_ANA_HDR_FIFO_FIFO_PTR_HEAD_S\t0\n+#define GLGEN_ANA_HDR_FIFO_FIFO_PTR_HEAD_M\tMAKEMASK(0x1FF, 0)\n+#define GLGEN_ANA_HDR_FIFO_FIFO_PTR_USED_SPACE_S 16\n+#define GLGEN_ANA_HDR_FIFO_FIFO_PTR_USED_SPACE_M MAKEMASK(0x3FF, 16)\n+#define GLGEN_ANA_INV_NODE_PTYPE\t\t0x0020C210 /* Reset Source: CORER */\n+#define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_S 0\n+#define GLGEN_ANA_INV_NODE_PTYPE_INV_NODE_PTYPE_M MAKEMASK(0x7FF, 0)\n+#define GLGEN_ANA_INV_PROT_ID\t\t\t0x0020C214 /* Reset Source: CORER */\n+#define GLGEN_ANA_INV_PROT_ID_INV_PROT_ID_S\t0\n+#define GLGEN_ANA_INV_PROT_ID_INV_PROT_ID_M\tMAKEMASK(0xFF, 0)\n+#define GLGEN_ANA_INV_PTYPE_MARKER\t\t0x0020C218 /* Reset Source: CORER */\n+#define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_S 0\n+#define GLGEN_ANA_INV_PTYPE_MARKER_INV_PTYPE_MARKER_M MAKEMASK(0x7F, 0)\n+#define GLGEN_ANA_LAST_PROT_ID(_i)\t\t(0x0020C1E4 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_LAST_PROT_ID_MAX_INDEX\t5\n+#define GLGEN_ANA_LAST_PROT_ID_EN_S\t\t0\n+#define GLGEN_ANA_LAST_PROT_ID_EN_M\t\tBIT(0)\n+#define GLGEN_ANA_LAST_PROT_ID_PROT_ID_S\t1\n+#define GLGEN_ANA_LAST_PROT_ID_PROT_ID_M\tMAKEMASK(0xFF, 1)\n+#define GLGEN_ANA_MAX_HDRLEN\t\t\t0x0020C1E0 /* Reset Source: CORER */\n+#define GLGEN_ANA_MAX_HDRLEN_NPC_S\t\t0\n+#define GLGEN_ANA_MAX_HDRLEN_NPC_M\t\tMAKEMASK(0xFF, 0)\n+#define GLGEN_ANA_MAX_HDRLEN_MAX_HDR_LEN_S\t8\n+#define GLGEN_ANA_MAX_HDRLEN_MAX_HDR_LEN_M\tMAKEMASK(0x1FF, 8)\n+#define GLGEN_ANA_MAX_PROT\t\t\t0x0020C224 /* Reset Source: CORER */\n+#define GLGEN_ANA_MAX_PROT_MAX_PRTS_S\t\t0\n+#define GLGEN_ANA_MAX_PROT_MAX_PRTS_M\t\tMAKEMASK(0x7F, 0)\n+#define GLGEN_ANA_MAX_ROUND\t\t\t0x0020C20C /* Reset Source: CORER */\n+#define GLGEN_ANA_MAX_ROUND_MAX_ROUND_ABS_S\t0\n+#define GLGEN_ANA_MAX_ROUND_MAX_ROUND_ABS_M\tMAKEMASK(0x7F, 0)\n+#define GLGEN_ANA_MIN_PKT\t\t\t0x0020C42C /* Reset Source: CORER */\n+#define GLGEN_ANA_MIN_PKT_MIN_LEN_S\t\t0\n+#define GLGEN_ANA_MIN_PKT_MIN_LEN_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLGEN_ANA_NMPG_KEYMASK(_i)\t\t(0x0020C1D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_NMPG_KEYMASK_MAX_INDEX\t3\n+#define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_S\t0\n+#define GLGEN_ANA_NMPG_KEYMASK_HASH_KEY_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_NMPG0_HASHKEY(_i)\t\t(0x0020C1B0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_NMPG0_HASHKEY_MAX_INDEX\t3\n+#define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_S\t0\n+#define GLGEN_ANA_NMPG0_HASHKEY_HASH_KEY_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_NO_HIT_PG_NM_PG\t\t0x0020C204 /* Reset Source: CORER */\n+#define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_S\t\t0\n+#define GLGEN_ANA_NO_HIT_PG_NM_PG_NPC_M\t\tMAKEMASK(0xFF, 0)\n+#define GLGEN_ANA_OUT_OF_PKT\t\t\t0x0020C200 /* Reset Source: CORER */\n+#define GLGEN_ANA_OUT_OF_PKT_NPC_S\t\t0\n+#define GLGEN_ANA_OUT_OF_PKT_NPC_M\t\tMAKEMASK(0xFF, 0)\n+#define GLGEN_ANA_P2P(_i)\t\t\t(0x0020C160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_P2P_MAX_INDEX\t\t\t15\n+#define GLGEN_ANA_P2P_TARGET_PROF_S\t\t0\n+#define GLGEN_ANA_P2P_TARGET_PROF_M\t\tMAKEMASK(0xF, 0)\n+#define GLGEN_ANA_PG_KEYMASK(_i)\t\t(0x0020C1C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_PG_KEYMASK_MAX_INDEX\t\t3\n+#define GLGEN_ANA_PG_KEYMASK_HASH_KEY_S\t\t0\n+#define GLGEN_ANA_PG_KEYMASK_HASH_KEY_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_PG0_HASHKEY(_i)\t\t(0x0020C1A0 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_PG0_HASHKEY_MAX_INDEX\t\t3\n+#define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_S\t0\n+#define GLGEN_ANA_PG0_HASHKEY_HASH_KEY_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_PROFIL_CTRL\t\t\t0x0020C1FC /* Reset Source: CORER */\n+#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_S 0\n+#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDID_M MAKEMASK(0x1F, 0)\n+#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_S 5\n+#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MDSTART_M MAKEMASK(0xF, 5)\n+#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_S 9\n+#define GLGEN_ANA_PROFIL_CTRL_PROFILE_SELECT_MD_LEN_M MAKEMASK(0x1F, 9)\n+#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_S 14\n+#define GLGEN_ANA_PROFIL_CTRL_NUM_CTRL_DOMAIN_M MAKEMASK(0x3, 14)\n+#define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_S\t16\n+#define GLGEN_ANA_PROFIL_CTRL_DEF_PROF_ID_M\tMAKEMASK(0xF, 16)\n+#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_S 20\n+#define GLGEN_ANA_PROFIL_CTRL_SEL_DEF_PROF_ID_M BIT(20)\n+#define GLGEN_ANA_PSTAT_FIFO_PTR\t\t0x0020C444 /* Reset Source: CORER */\n+#define GLGEN_ANA_PSTAT_FIFO_PTR_HEAD_S\t\t0\n+#define GLGEN_ANA_PSTAT_FIFO_PTR_HEAD_M\t\tMAKEMASK(0x1FF, 0)\n+#define GLGEN_ANA_PSTAT_FIFO_PTR_USED_SPACE_S\t16\n+#define GLGEN_ANA_PSTAT_FIFO_PTR_USED_SPACE_M\tMAKEMASK(0x3FF, 16)\n+#define GLGEN_ANA_STAT_FIFO_PTR\t\t\t0x0020C440 /* Reset Source: CORER */\n+#define GLGEN_ANA_STAT_FIFO_PTR_HEAD_S\t\t0\n+#define GLGEN_ANA_STAT_FIFO_PTR_HEAD_M\t\tMAKEMASK(0x1FF, 0)\n+#define GLGEN_ANA_STAT_FIFO_PTR_USED_SPACE_S\t16\n+#define GLGEN_ANA_STAT_FIFO_PTR_USED_SPACE_M\tMAKEMASK(0x3FF, 16)\n+#define GLGEN_ANA_TX_DFD_LOG_0\t\t\t0x0020D3A8 /* Reset Source: CORER */\n+#define GLGEN_ANA_TX_DFD_LOG_0_SOURCE_S\t\t0\n+#define GLGEN_ANA_TX_DFD_LOG_0_SOURCE_M\t\tMAKEMASK(0x7, 0)\n+#define GLGEN_ANA_TX_DFD_LOG_0_LVL_OR_EDGE_S\t3\n+#define GLGEN_ANA_TX_DFD_LOG_0_LVL_OR_EDGE_M\tBIT(3)\n+#define GLGEN_ANA_TX_DFD_LOG_0_RC_DISP_TRIG_S\t4\n+#define GLGEN_ANA_TX_DFD_LOG_0_RC_DISP_TRIG_M\tMAKEMASK(0x7, 4)\n+#define GLGEN_ANA_TX_DFD_LOG_0_FLD_MODE_S\t8\n+#define GLGEN_ANA_TX_DFD_LOG_0_FLD_MODE_M\tBIT(8)\n+#define GLGEN_ANA_TX_DFD_LOG_0_DLY_CYCL_S\t16\n+#define GLGEN_ANA_TX_DFD_LOG_0_DLY_CYCL_M\tMAKEMASK(0x3FF, 16)\n+#define GLGEN_ANA_TX_DFD_PACE_OUT\t\t0x0020D4CC /* Reset Source: CORER */\n+#define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_S\t0\n+#define GLGEN_ANA_TX_DFD_PACE_OUT_PUSH_M\tBIT(0)\n+#define GLGEN_ANA_TX_GEN_DFD_RO\t\t\t0x0020D4C8 /* Reset Source: CORER */\n+#define GLGEN_ANA_TX_GEN_DFD_RO_GEN_VAL_S\t0\n+#define GLGEN_ANA_TX_GEN_DFD_RO_GEN_VAL_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ANA_TX_P2P(_i)\t\t\t(0x0020D160 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLGEN_ANA_TX_P2P_MAX_INDEX\t\t15\n+#define GLGEN_ANA_TX_P2P_TARGET_PROF_S\t\t0\n+#define GLGEN_ANA_TX_P2P_TARGET_PROF_M\t\tMAKEMASK(0xF, 0)\n+#define GLGEN_ASSERT_HLP\t\t\t0x000B81E4 /* Reset Source: POR */\n+#define GLGEN_ASSERT_HLP_CORE_ON_RST_S\t\t0\n+#define GLGEN_ASSERT_HLP_CORE_ON_RST_M\t\tBIT(0)\n+#define GLGEN_ASSERT_HLP_FULL_ON_RST_S\t\t1\n+#define GLGEN_ASSERT_HLP_FULL_ON_RST_M\t\tBIT(1)\n+#define GLGEN_CLKSTAT\t\t\t\t0x000B8184 /* Reset Source: POR */\n+#define GLGEN_CLKSTAT_U_CLK_SPEED_S\t\t0\n+#define GLGEN_CLKSTAT_U_CLK_SPEED_M\t\tMAKEMASK(0x7, 0)\n+#define GLGEN_CLKSTAT_L_CLK_SPEED_S\t\t3\n+#define GLGEN_CLKSTAT_L_CLK_SPEED_M\t\tMAKEMASK(0x7, 3)\n+#define GLGEN_CLKSTAT_PSM_CLK_SPEED_S\t\t6\n+#define GLGEN_CLKSTAT_PSM_CLK_SPEED_M\t\tMAKEMASK(0x7, 6)\n+#define GLGEN_CLKSTAT_RXCTL_CLK_SPEED_S\t\t9\n+#define GLGEN_CLKSTAT_RXCTL_CLK_SPEED_M\t\tMAKEMASK(0x7, 9)\n+#define GLGEN_CLKSTAT_UANA_CLK_SPEED_S\t\t12\n+#define GLGEN_CLKSTAT_UANA_CLK_SPEED_M\t\tMAKEMASK(0x7, 12)\n+#define GLGEN_CLKSTAT_PE_CLK_SPEED_S\t\t18\n+#define GLGEN_CLKSTAT_PE_CLK_SPEED_M\t\tMAKEMASK(0x7, 18)\n+#define GLGEN_CLKSTAT_SRC\t\t\t0x000B826C /* Reset Source: POR */\n+#define GLGEN_CLKSTAT_SRC_U_CLK_SRC_S\t\t0\n+#define GLGEN_CLKSTAT_SRC_U_CLK_SRC_M\t\tMAKEMASK(0x3, 0)\n+#define GLGEN_CLKSTAT_SRC_L_CLK_SRC_S\t\t2\n+#define GLGEN_CLKSTAT_SRC_L_CLK_SRC_M\t\tMAKEMASK(0x3, 2)\n+#define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S\t\t4\n+#define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M\t\tMAKEMASK(0x3, 4)\n+#define GLGEN_CLKSTAT_SRC_RXCTL_CLK_SRC_S\t6\n+#define GLGEN_CLKSTAT_SRC_RXCTL_CLK_SRC_M\tMAKEMASK(0x3, 6)\n+#define GLGEN_CLKSTAT_SRC_UANA_CLK_SRC_S\t8\n+#define GLGEN_CLKSTAT_SRC_UANA_CLK_SRC_M\tMAKEMASK(0xF, 8)\n+#define GLGEN_ECC_ERR_INT_TOG_MASK_H\t\t0x00093A00 /* Reset Source: CORER */\n+#define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_S 0\n+#define GLGEN_ECC_ERR_INT_TOG_MASK_H_CLIENT_NUM_M MAKEMASK(0x7F, 0)\n+#define GLGEN_ECC_ERR_INT_TOG_MASK_L\t\t0x000939FC /* Reset Source: CORER */\n+#define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_S 0\n+#define GLGEN_ECC_ERR_INT_TOG_MASK_L_CLIENT_NUM_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_ECC_ERR_RST_MASK_H\t\t0x000939F8 /* Reset Source: CORER */\n+#define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_S\t0\n+#define GLGEN_ECC_ERR_RST_MASK_H_CLIENT_NUM_M\tMAKEMASK(0x7F, 0)\n+#define GLGEN_ECC_ERR_RST_MASK_L\t\t0x000939F4 /* Reset Source: CORER */\n+#define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_S\t0\n+#define GLGEN_ECC_ERR_RST_MASK_L_CLIENT_NUM_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_GPIO_CTL(_i)\t\t\t(0x000880C8 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: POR */\n+#define GLGEN_GPIO_CTL_MAX_INDEX\t\t6\n+#define GLGEN_GPIO_CTL_IN_VALUE_S\t\t0\n+#define GLGEN_GPIO_CTL_IN_VALUE_M\t\tBIT(0)\n+#define GLGEN_GPIO_CTL_IN_TRANSIT_S\t\t1\n+#define GLGEN_GPIO_CTL_IN_TRANSIT_M\t\tBIT(1)\n+#define GLGEN_GPIO_CTL_OUT_VALUE_S\t\t2\n+#define GLGEN_GPIO_CTL_OUT_VALUE_M\t\tBIT(2)\n+#define GLGEN_GPIO_CTL_NO_P_UP_S\t\t3\n+#define GLGEN_GPIO_CTL_NO_P_UP_M\t\tBIT(3)\n+#define GLGEN_GPIO_CTL_PIN_DIR_S\t\t4\n+#define GLGEN_GPIO_CTL_PIN_DIR_M\t\tBIT(4)\n+#define GLGEN_GPIO_CTL_TRI_CTL_S\t\t5\n+#define GLGEN_GPIO_CTL_TRI_CTL_M\t\tBIT(5)\n+#define GLGEN_GPIO_CTL_PIN_FUNC_S\t\t8\n+#define GLGEN_GPIO_CTL_PIN_FUNC_M\t\tMAKEMASK(0xF, 8)\n+#define GLGEN_GPIO_CTL_INT_MODE_S\t\t12\n+#define GLGEN_GPIO_CTL_INT_MODE_M\t\tMAKEMASK(0x3, 12)\n+#define GLGEN_MARKER_COUNT\t\t\t0x000939E8 /* Reset Source: CORER */\n+#define GLGEN_MARKER_COUNT_MARKER_COUNT_S\t0\n+#define GLGEN_MARKER_COUNT_MARKER_COUNT_M\tMAKEMASK(0xFF, 0)\n+#define GLGEN_MARKER_COUNT_MARKER_COUNT_EN_S\t31\n+#define GLGEN_MARKER_COUNT_MARKER_COUNT_EN_M\tBIT(31)\n+#define GLGEN_RSTAT\t\t\t\t0x000B8188 /* Reset Source: POR */\n+#define GLGEN_RSTAT_DEVSTATE_S\t\t\t0\n+#define GLGEN_RSTAT_DEVSTATE_M\t\t\tMAKEMASK(0x3, 0)\n+#define GLGEN_RSTAT_RESET_TYPE_S\t\t2\n+#define GLGEN_RSTAT_RESET_TYPE_M\t\tMAKEMASK(0x3, 2)\n+#define GLGEN_RSTAT_CORERCNT_S\t\t\t4\n+#define GLGEN_RSTAT_CORERCNT_M\t\t\tMAKEMASK(0x3, 4)\n+#define GLGEN_RSTAT_GLOBRCNT_S\t\t\t6\n+#define GLGEN_RSTAT_GLOBRCNT_M\t\t\tMAKEMASK(0x3, 6)\n+#define GLGEN_RSTAT_EMPRCNT_S\t\t\t8\n+#define GLGEN_RSTAT_EMPRCNT_M\t\t\tMAKEMASK(0x3, 8)\n+#define GLGEN_RSTAT_TIME_TO_RST_S\t\t10\n+#define GLGEN_RSTAT_TIME_TO_RST_M\t\tMAKEMASK(0x3F, 10)\n+#define GLGEN_RSTAT_RTRIG_FLR_S\t\t\t16\n+#define GLGEN_RSTAT_RTRIG_FLR_M\t\t\tBIT(16)\n+#define GLGEN_RSTAT_RTRIG_ECC_S\t\t\t17\n+#define GLGEN_RSTAT_RTRIG_ECC_M\t\t\tBIT(17)\n+#define GLGEN_RSTAT_RTRIG_FW_AUX_S\t\t18\n+#define GLGEN_RSTAT_RTRIG_FW_AUX_M\t\tBIT(18)\n+#define GLGEN_RTRIG\t\t\t\t0x000B8190 /* Reset Source: CORER */\n+#define GLGEN_RTRIG_CORER_S\t\t\t0\n+#define GLGEN_RTRIG_CORER_M\t\t\tBIT(0)\n+#define GLGEN_RTRIG_GLOBR_S\t\t\t1\n+#define GLGEN_RTRIG_GLOBR_M\t\t\tBIT(1)\n+#define GLGEN_RTRIG_EMPFWR_S\t\t\t2\n+#define GLGEN_RTRIG_EMPFWR_M\t\t\tBIT(2)\n+#define GLGEN_STAT\t\t\t\t0x000B612C /* Reset Source: POR */\n+#define GLGEN_STAT_RSVD4FW_S\t\t\t0\n+#define GLGEN_STAT_RSVD4FW_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLGEN_VFLRSTAT(_i)\t\t\t(0x00093A04 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLGEN_VFLRSTAT_MAX_INDEX\t\t7\n+#define GLGEN_VFLRSTAT_VFLRS_S\t\t\t0\n+#define GLGEN_VFLRSTAT_VFLRS_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLGEN_XLR_MSK2HLP_RDY\t\t\t0x000939F0 /* Reset Source: CORER */\n+#define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_S 0\n+#define GLGEN_XLR_MSK2HLP_RDY_GLGEN_XLR_MSK2HLP_RDY_M BIT(0)\n+#define GLGEN_XLR_TRNS_WAIT_COUNT\t\t0x000939EC /* Reset Source: CORER */\n+#define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_S 0\n+#define GLGEN_XLR_TRNS_WAIT_COUNT_W_BTWN_TRNS_COUNT_M MAKEMASK(0x1F, 0)\n+#define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_S 8\n+#define GLGEN_XLR_TRNS_WAIT_COUNT_W_PEND_TRNS_COUNT_M MAKEMASK(0xFF, 8)\n+#define GLQDC_DFD_CAM_ACC\t\t\t0x002D2E24 /* Reset Source: CORER */\n+#define GLQDC_DFD_CAM_ACC_CLNUM_S\t\t0\n+#define GLQDC_DFD_CAM_ACC_CLNUM_M\t\tMAKEMASK(0x7F, 0)\n+#define GLQDC_DFD_CAM_ACC_RES_0\t\t\t0x002D2E28 /* Reset Source: CORER */\n+#define GLQDC_DFD_CAM_ACC_RES_0_QID_S\t\t0\n+#define GLQDC_DFD_CAM_ACC_RES_0_QID_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLQDC_DFD_CAM_ACC_RES_0_CAM_V_S\t\t16\n+#define GLQDC_DFD_CAM_ACC_RES_0_CAM_V_M\t\tBIT(16)\n+#define GLQDC_DFD_CAM_ACC_RES_0_CAM_E_S\t\t31\n+#define GLQDC_DFD_CAM_ACC_RES_0_CAM_E_M\t\tBIT(31)\n+#define GLQDC_DFD_CAM_ACC_RES_1\t\t\t0x002D2E2C /* Reset Source: CORER */\n+#define GLQDC_DFD_CAM_ACC_RES_1_CL_HEAD_S\t0\n+#define GLQDC_DFD_CAM_ACC_RES_1_CL_HEAD_M\tMAKEMASK(0x3F, 0)\n+#define GLQDC_DFD_CAM_ACC_RES_1_CL_TAIL_S\t8\n+#define GLQDC_DFD_CAM_ACC_RES_1_CL_TAIL_M\tMAKEMASK(0x3F, 8)\n+#define GLQDC_DFD_CAM_ACC_RES_1_CL_EMPTY_S\t16\n+#define GLQDC_DFD_CAM_ACC_RES_1_CL_EMPTY_M\tBIT(16)\n+#define GLQDC_DFD_CAM_ACC_RES_1_CL_MALC_S\t24\n+#define GLQDC_DFD_CAM_ACC_RES_1_CL_MALC_M\tMAKEMASK(0x3F, 24)\n+#define GLQDC_DFD_FIFO_CFG_0\t\t\t0x002D2E34 /* Reset Source: CORER */\n+#define GLQDC_DFD_FIFO_CFG_0_QID_S\t\t0\n+#define GLQDC_DFD_FIFO_CFG_0_QID_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLQDC_DFD_FIFO_CFG_0_SMPL_PT_S\t\t16\n+#define GLQDC_DFD_FIFO_CFG_0_SMPL_PT_M\t\tMAKEMASK(0xFF, 16)\n+#define GLQDC_DFD_FIFO_CFG_0_ALL_QID_S\t\t31\n+#define GLQDC_DFD_FIFO_CFG_0_ALL_QID_M\t\tBIT(31)\n+#define GLQDC_DFD_FIFO_CFG_1\t\t\t0x002D2E38 /* Reset Source: CORER */\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_0_S\t\t0\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_0_M\t\tMAKEMASK(0x7, 0)\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_1_S\t\t4\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_1_M\t\tMAKEMASK(0x7, 4)\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_2_S\t\t8\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_2_M\t\tMAKEMASK(0x7, 8)\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_3_S\t\t12\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_3_M\t\tMAKEMASK(0x7, 12)\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_4_S\t\t16\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_4_M\t\tMAKEMASK(0x7, 16)\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_5_S\t\t20\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_5_M\t\tMAKEMASK(0x7, 20)\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_6_S\t\t24\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_6_M\t\tMAKEMASK(0x7, 24)\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_7_S\t\t28\n+#define GLQDC_DFD_FIFO_CFG_1_PRIO_7_M\t\tMAKEMASK(0x7, 28)\n+#define GLQDC_DFD_FIFO_SZ_CFG\t\t\t0x002D30AC /* Reset Source: CORER */\n+#define GLQDC_DFD_FIFO_SZ_CFG_COMP_S\t\t0\n+#define GLQDC_DFD_FIFO_SZ_CFG_COMP_M\t\tMAKEMASK(0xFF, 0)\n+#define GLQDC_DFD_FIFO_SZ_CFG_MISS_S\t\t8\n+#define GLQDC_DFD_FIFO_SZ_CFG_MISS_M\t\tMAKEMASK(0xFF, 8)\n+#define GLQDC_DFD_FIFO_SZ_CFG_MISS_COMP_S\t16\n+#define GLQDC_DFD_FIFO_SZ_CFG_MISS_COMP_M\tMAKEMASK(0xFF, 16)\n+#define GLQDC_DFD_GEN_CHKN\t\t\t0x002D30A0 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_CHKN_GEN_BITS_S\t\t0\n+#define GLQDC_DFD_GEN_CHKN_GEN_BITS_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_GEN_CHKN_2\t\t\t0x002D30A4 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_CHKN_2_GEN_BITS_S\t\t0\n+#define GLQDC_DFD_GEN_CHKN_2_GEN_BITS_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_GEN_CTRL\t\t\t0x002D2E20 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_CTRL_ENABLE_S\t\t0\n+#define GLQDC_DFD_GEN_CTRL_ENABLE_M\t\tBIT(0)\n+#define GLQDC_DFD_GEN_CTRL_BLK_INJECT_M1_S\t1\n+#define GLQDC_DFD_GEN_CTRL_BLK_INJECT_M1_M\tBIT(1)\n+#define GLQDC_DFD_GEN_CTRL_NUM_PAUSE_M1_S\t16\n+#define GLQDC_DFD_GEN_CTRL_NUM_PAUSE_M1_M\tMAKEMASK(0x3FF, 16)\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0\t\t0x002D2EE8 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_ACK_S 0\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_ACK_M MAKEMASK(0x7F, 0)\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_S 7\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_MISS_COMP_M MAKEMASK(0x7F, 7)\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_DATA_S 14\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_DATA_M MAKEMASK(0x3, 14)\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_S\t16\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_COMP_FSM_M\tMAKEMASK(0x7F, 16)\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_PCIE_OUT_S\t23\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_0_PCIE_OUT_M\tMAKEMASK(0x7, 23)\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_1\t\t0x002D2EEC /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_MISS_FSM_S\t0\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_MISS_FSM_M\tMAKEMASK(0x7F, 0)\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_DFD_S\t7\n+#define GLQDC_DFD_GEN_LOG_FIFO_ST_1_DFD_M\tMAKEMASK(0xFF, 7)\n+#define GLQDC_DFD_GEN_LOG_FSM\t\t\t0x002D2EF0 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOG_FSM_FTSTATE_S\t\t0\n+#define GLQDC_DFD_GEN_LOG_FSM_FTSTATE_M\t\tMAKEMASK(0x3, 0)\n+#define GLQDC_DFD_GEN_LOG_FSM_MISS_FIFO_FSM_ST_S 2\n+#define GLQDC_DFD_GEN_LOG_FSM_MISS_FIFO_FSM_ST_M MAKEMASK(0x7, 2)\n+#define GLQDC_DFD_GEN_LOG_FSM_IN_MISS_FIFO_S\t5\n+#define GLQDC_DFD_GEN_LOG_FSM_IN_MISS_FIFO_M\tMAKEMASK(0x3, 5)\n+#define GLQDC_DFD_GEN_LOG_FSM_CPSTATE_S\t\t7\n+#define GLQDC_DFD_GEN_LOG_FSM_CPSTATE_M\t\tMAKEMASK(0x7, 7)\n+#define GLQDC_DFD_GEN_LOGGNG_0\t\t\t0x002D2EE0 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOGGNG_0_RINGH_WR_RD_S\t0\n+#define GLQDC_DFD_GEN_LOGGNG_0_RINGH_WR_RD_M\tBIT(0)\n+#define GLQDC_DFD_GEN_LOGGNG_0_QD_WR_RD_S\t1\n+#define GLQDC_DFD_GEN_LOGGNG_0_QD_WR_RD_M\tBIT(1)\n+#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_RD_REQ_VLD_S 2\n+#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_RD_REQ_VLD_M BIT(2)\n+#define GLQDC_DFD_GEN_LOGGNG_0_NXT_SQ_VLD_S\t3\n+#define GLQDC_DFD_GEN_LOGGNG_0_NXT_SQ_VLD_M\tBIT(3)\n+#define GLQDC_DFD_GEN_LOGGNG_0_SQ_VLD_TO_DONE_S 4\n+#define GLQDC_DFD_GEN_LOGGNG_0_SQ_VLD_TO_DONE_M BIT(4)\n+#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_COMP_VLD_S\t5\n+#define GLQDC_DFD_GEN_LOGGNG_0_PCIE_COMP_VLD_M\tBIT(5)\n+#define GLQDC_DFD_GEN_LOGGNG_0_FETCH_NXT_SQ_VLD_S 6\n+#define GLQDC_DFD_GEN_LOGGNG_0_FETCH_NXT_SQ_VLD_M BIT(6)\n+#define GLQDC_DFD_GEN_LOGGNG_0_MALC_RPT_S\t8\n+#define GLQDC_DFD_GEN_LOGGNG_0_MALC_RPT_M\tMAKEMASK(0xF, 8)\n+#define GLQDC_DFD_GEN_LOGGNG_0_DFD_FIFO_ADD_S\t16\n+#define GLQDC_DFD_GEN_LOGGNG_0_DFD_FIFO_ADD_M\tMAKEMASK(0x7F, 16)\n+#define GLQDC_DFD_GEN_LOGGNG_1\t\t\t0x002D2EE4 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_WM_S\t0\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_WM_M\tMAKEMASK(0x3, 0)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_S\t2\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_RFIL_M\tMAKEMASK(0x3, 2)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_WM_S\t4\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_WM_M\tMAKEMASK(0x3, 4)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_S\t6\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_MRED_M\tMAKEMASK(0x3, 6)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_WM_S\t8\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_WM_M\tMAKEMASK(0x3, 8)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_S\t\t10\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_M3_M\t\tMAKEMASK(0x3, 10)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_WM_S 12\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_WM_M MAKEMASK(0x3, 12)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_S\t14\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_LSO_MT_M3_M\tMAKEMASK(0x3, 14)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_WM_S 16\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_WM_M MAKEMASK(0x3, 16)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_S 18\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_ACK_MISS_FIFO_M3_M MAKEMASK(0x3, 18)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_WM_S\t20\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_WM_M\tMAKEMASK(0x3, 20)\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_S\t22\n+#define GLQDC_DFD_GEN_LOGGNG_1_WS_EVICT_M\tMAKEMASK(0x3, 22)\n+#define GLQDC_DFD_GEN_LOGGNG_2\t\t\t0x002D2FFC /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_S\t0\n+#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_M\tMAKEMASK(0x3F, 0)\n+#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_LT_S 6\n+#define GLQDC_DFD_GEN_LOGGNG_2_WR_WHEN_FULL_LT_M MAKEMASK(0x3F, 6)\n+#define GLQDC_DFD_GEN_LOGGNG_2_TEST_S\t\t24\n+#define GLQDC_DFD_GEN_LOGGNG_2_TEST_M\t\tMAKEMASK(0xFF, 24)\n+#define GLQDC_DFD_GEN_LOGGNG_3\t\t\t0x002D3008 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOGGNG_3_GEN_S\t\t0\n+#define GLQDC_DFD_GEN_LOGGNG_3_GEN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_GEN_LOGGNG_4\t\t\t0x002D300C /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOGGNG_4_GEN_S\t\t0\n+#define GLQDC_DFD_GEN_LOGGNG_4_GEN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_GEN_LOGGNG_5\t\t\t0x002D3010 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOGGNG_5_GEN_S\t\t0\n+#define GLQDC_DFD_GEN_LOGGNG_5_GEN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_GEN_LOGGNG_6\t\t\t0x002D3014 /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_LOGGNG_6_GEN_S\t\t0\n+#define GLQDC_DFD_GEN_LOGGNG_6_GEN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_GEN_STAT_REGS(_i)\t\t(0x002D3018 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLQDC_DFD_GEN_STAT_REGS_MAX_INDEX\t15\n+#define GLQDC_DFD_GEN_STAT_REGS_COUNT_S\t\t0\n+#define GLQDC_DFD_GEN_STAT_REGS_COUNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_LOG_0\t\t\t\t0x002D2E3C /* Reset Source: CORER */\n+#define GLQDC_DFD_LOG_0_SOURCE_S\t\t0\n+#define GLQDC_DFD_LOG_0_SOURCE_M\t\tMAKEMASK(0x3, 0)\n+#define GLQDC_DFD_LOG_0_LVL_OR_EDGE_S\t\t4\n+#define GLQDC_DFD_LOG_0_LVL_OR_EDGE_M\t\tBIT(4)\n+#define GLQDC_DFD_LOG_0_DLY_CYCL_S\t\t16\n+#define GLQDC_DFD_LOG_0_DLY_CYCL_M\t\tMAKEMASK(0x3FF, 16)\n+#define GLQDC_DFD_LOG_1\t\t\t\t0x002D2E40 /* Reset Source: CORER */\n+#define GLQDC_DFD_LOG_1_NUM_EVENTS_S\t\t0\n+#define GLQDC_DFD_LOG_1_NUM_EVENTS_M\t\tMAKEMASK(0x3FF, 0)\n+#define GLQDC_DFD_LOG_1_NUM_TRIGS_S\t\t16\n+#define GLQDC_DFD_LOG_1_NUM_TRIGS_M\t\tMAKEMASK(0x3FF, 16)\n+#define GLQDC_DFD_LOG_1_TRIG_B2B_S\t\t31\n+#define GLQDC_DFD_LOG_1_TRIG_B2B_M\t\tBIT(31)\n+#define GLQDC_DFD_LOG_ACTN_EN\t\t\t0x002D2EA4 /* Reset Source: CORER */\n+#define GLQDC_DFD_LOG_ACTN_EN_BLK_INJECT_M1_S\t0\n+#define GLQDC_DFD_LOG_ACTN_EN_BLK_INJECT_M1_M\tBIT(0)\n+#define GLQDC_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_S 1\n+#define GLQDC_DFD_LOG_ACTN_EN_STP_WR_DFD_FIFO_M BIT(1)\n+#define GLQDC_DFD_LOG_ACTN_EN_STP_UPDT_MALC_RPT_CSR_S 2\n+#define GLQDC_DFD_LOG_ACTN_EN_STP_UPDT_MALC_RPT_CSR_M BIT(2)\n+#define GLQDC_DFD_LOG_ACTN_RST\t\t\t0x002D2EA8 /* Reset Source: CORER */\n+#define GLQDC_DFD_LOG_ACTN_RST_BLK_INJECT_M1_S\t0\n+#define GLQDC_DFD_LOG_ACTN_RST_BLK_INJECT_M1_M\tBIT(0)\n+#define GLQDC_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_S 1\n+#define GLQDC_DFD_LOG_ACTN_RST_STP_WR_DFD_FIFO_M BIT(1)\n+#define GLQDC_DFD_LOG_ACTN_RST_STP_UPDT_MALC_RPT_CSR_S 2\n+#define GLQDC_DFD_LOG_ACTN_RST_STP_UPDT_MALC_RPT_CSR_M BIT(2)\n+#define GLQDC_DFD_LOG_DATA(_i)\t\t\t(0x002D2E44 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: CORER */\n+#define GLQDC_DFD_LOG_DATA_MAX_INDEX\t\t11\n+#define GLQDC_DFD_LOG_DATA_DATA_S\t\t0\n+#define GLQDC_DFD_LOG_DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_LOG_MASK(_i)\t\t\t(0x002D2E74 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: CORER */\n+#define GLQDC_DFD_LOG_MASK_MAX_INDEX\t\t11\n+#define GLQDC_DFD_LOG_MASK_MASK_S\t\t0\n+#define GLQDC_DFD_LOG_MASK_MASK_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_LOG_TRG_0\t\t\t0x002D2EAC /* Reset Source: CORER */\n+#define GLQDC_DFD_LOG_TRG_0_QID_S\t\t0\n+#define GLQDC_DFD_LOG_TRG_0_QID_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLQDC_DFD_LOG_TRG_0_ACT_TRIGGED_S\t16\n+#define GLQDC_DFD_LOG_TRG_0_ACT_TRIGGED_M\tBIT(16)\n+#define GLQDC_DFD_LOG_TRG_0_TRIGGED_S\t\t31\n+#define GLQDC_DFD_LOG_TRG_0_TRIGGED_M\t\tBIT(31)\n+#define GLQDC_DFD_LOG_TRG_DATA(_i)\t\t(0x002D2EB0 + ((_i) * 4)) /* _i=0...11 */ /* Reset Source: CORER */\n+#define GLQDC_DFD_LOG_TRG_DATA_MAX_INDEX\t11\n+#define GLQDC_DFD_LOG_TRG_DATA_DATA_S\t\t0\n+#define GLQDC_DFD_LOG_TRG_DATA_DATA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQDC_DFD_PACE\t\t\t\t0x002D3000 /* Reset Source: CORER */\n+#define GLQDC_DFD_PACE_PUSH_S\t\t\t0\n+#define GLQDC_DFD_PACE_PUSH_M\t\t\tBIT(0)\n+#define GLQDC_DFD_RST\t\t\t\t0x002D2E30 /* Reset Source: CORER */\n+#define GLQDC_DFD_RST_RST_S\t\t\t0\n+#define GLQDC_DFD_RST_RST_M\t\t\tBIT(0)\n+#define GLQDC_DFD_RST_CLR_MALC_RPT_S\t\t1\n+#define GLQDC_DFD_RST_CLR_MALC_RPT_M\t\tBIT(1)\n+#define GLQDC_DFD_RST_LOG_RST_S\t\t\t2\n+#define GLQDC_DFD_RST_LOG_RST_M\t\t\tBIT(2)\n+#define GLQDC_DFD_SAMPLE_RO_CSR\t\t\t0x002D3004 /* Reset Source: CORER */\n+#define GLQDC_DFD_SAMPLE_RO_CSR_SMPL_S\t\t0\n+#define GLQDC_DFD_SAMPLE_RO_CSR_SMPL_M\t\tBIT(0)\n+#define GLQDC_DFD_STATS_CFG_0\t\t\t0x002D3058 /* Reset Source: CORER */\n+#define GLQDC_DFD_STATS_CFG_0_CLR_S\t\t0\n+#define GLQDC_DFD_STATS_CFG_0_CLR_M\t\tBIT(0)\n+#define GLQDC_DFD_STATS_CFG_1\t\t\t0x002D305C /* Reset Source: CORER */\n+#define GLQDC_DFD_STATS_CFG_1_QID_S\t\t0\n+#define GLQDC_DFD_STATS_CFG_1_QID_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLQDC_DFD_STATS_CFG_1_GEN_CFG_S\t\t16\n+#define GLQDC_DFD_STATS_CFG_1_GEN_CFG_M\t\tMAKEMASK(0x1F, 16)\n+#define GLQDC_DFD_STATS_CFG_EVNT(_i)\t\t(0x002D3060 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLQDC_DFD_STATS_CFG_EVNT_MAX_INDEX\t15\n+#define GLQDC_DFD_STATS_CFG_EVNT_EVNT_ID_S\t0\n+#define GLQDC_DFD_STATS_CFG_EVNT_EVNT_ID_M\tMAKEMASK(0x1F, 0)\n+#define GLQDC_DFD_STATS_CFG_EVNT_WRAP_EN_S\t31\n+#define GLQDC_DFD_STATS_CFG_EVNT_WRAP_EN_M\tBIT(31)\n+#define GLQDC_DFD_TEST_MNG\t\t\t0x002D30A8 /* Reset Source: CORER */\n+#define GLQDC_DFD_TEST_MNG_TST_S\t\t2\n+#define GLQDC_DFD_TEST_MNG_TST_M\t\tBIT(2)\n+#define GLVFGEN_TIMER\t\t\t\t0x000B8214 /* Reset Source: POR */\n+#define GLVFGEN_TIMER_GTIME_S\t\t\t0\n+#define GLVFGEN_TIMER_GTIME_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFGEN_CTRL\t\t\t\t0x00091000 /* Reset Source: CORER */\n+#define PFGEN_CTRL_PFSWR_S\t\t\t0\n+#define PFGEN_CTRL_PFSWR_M\t\t\tBIT(0)\n+#define PFGEN_DRUN\t\t\t\t0x00091180 /* Reset Source: CORER */\n+#define PFGEN_DRUN_DRVUNLD_S\t\t\t0\n+#define PFGEN_DRUN_DRVUNLD_M\t\t\tBIT(0)\n+#define PFGEN_PFRSTAT\t\t\t\t0x00091080 /* Reset Source: CORER */\n+#define PFGEN_PFRSTAT_PFRD_S\t\t\t0\n+#define PFGEN_PFRSTAT_PFRD_M\t\t\tBIT(0)\n+#define PFGEN_PORTNUM\t\t\t\t0x001D2400 /* Reset Source: CORER */\n+#define PFGEN_PORTNUM_PORT_NUM_S\t\t0\n+#define PFGEN_PORTNUM_PORT_NUM_M\t\tMAKEMASK(0x7, 0)\n+#define PFGEN_STATE\t\t\t\t0x00088000 /* Reset Source: CORER */\n+#define PFGEN_STATE_PFPEEN_S\t\t\t0\n+#define PFGEN_STATE_PFPEEN_M\t\t\tBIT(0)\n+#define PFGEN_STATE_RSVD_S\t\t\t1\n+#define PFGEN_STATE_RSVD_M\t\t\tBIT(1)\n+#define PFGEN_STATE_PFLINKEN_S\t\t\t2\n+#define PFGEN_STATE_PFLINKEN_M\t\t\tBIT(2)\n+#define PFGEN_STATE_PFSCEN_S\t\t\t3\n+#define PFGEN_STATE_PFSCEN_M\t\t\tBIT(3)\n+#define PRT_TCVMLR_DRAIN_CNTR\t\t\t0x000A21C0 /* Reset Source: CORER */\n+#define PRT_TCVMLR_DRAIN_CNTR_CNTR_S\t\t0\n+#define PRT_TCVMLR_DRAIN_CNTR_CNTR_M\t\tMAKEMASK(0x3FFF, 0)\n+#define PRTGEN_CNF\t\t\t\t0x000B8120 /* Reset Source: POR */\n+#define PRTGEN_CNF_PORT_DIS_S\t\t\t0\n+#define PRTGEN_CNF_PORT_DIS_M\t\t\tBIT(0)\n+#define PRTGEN_CNF_ALLOW_PORT_DIS_S\t\t1\n+#define PRTGEN_CNF_ALLOW_PORT_DIS_M\t\tBIT(1)\n+#define PRTGEN_CNF_EMP_PORT_DIS_S\t\t2\n+#define PRTGEN_CNF_EMP_PORT_DIS_M\t\tBIT(2)\n+#define PRTGEN_CNF2\t\t\t\t0x000B8160 /* Reset Source: POR */\n+#define PRTGEN_CNF2_ACTIVATE_PORT_LINK_S\t0\n+#define PRTGEN_CNF2_ACTIVATE_PORT_LINK_M\tBIT(0)\n+#define PRTGEN_CNF3\t\t\t\t0x000B8280 /* Reset Source: POR */\n+#define PRTGEN_CNF3_PORT_STAGERING_EN_S\t\t0\n+#define PRTGEN_CNF3_PORT_STAGERING_EN_M\t\tBIT(0)\n+#define PRTGEN_STATUS\t\t\t\t0x000B8100 /* Reset Source: POR */\n+#define PRTGEN_STATUS_PORT_VALID_S\t\t0\n+#define PRTGEN_STATUS_PORT_VALID_M\t\tBIT(0)\n+#define PRTGEN_STATUS_PORT_ACTIVE_S\t\t1\n+#define PRTGEN_STATUS_PORT_ACTIVE_M\t\tBIT(1)\n+#define VFGEN_RSTAT(_VF)\t\t\t(0x00074000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: VFR */\n+#define VFGEN_RSTAT_MAX_INDEX\t\t\t255\n+#define VFGEN_RSTAT_VFR_STATE_S\t\t\t0\n+#define VFGEN_RSTAT_VFR_STATE_M\t\t\tMAKEMASK(0x3, 0)\n+#define VPGEN_VFRSTAT(_VF)\t\t\t(0x00090800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPGEN_VFRSTAT_MAX_INDEX\t\t\t255\n+#define VPGEN_VFRSTAT_VFRD_S\t\t\t0\n+#define VPGEN_VFRSTAT_VFRD_M\t\t\tBIT(0)\n+#define VPGEN_VFRTRIG(_VF)\t\t\t(0x00090000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPGEN_VFRTRIG_MAX_INDEX\t\t\t255\n+#define VPGEN_VFRTRIG_VFSWR_S\t\t\t0\n+#define VPGEN_VFRTRIG_VFSWR_M\t\t\tBIT(0)\n+#define VSIGEN_RSTAT(_VSI)\t\t\t(0x00092800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSIGEN_RSTAT_MAX_INDEX\t\t\t767\n+#define VSIGEN_RSTAT_VMRD_S\t\t\t0\n+#define VSIGEN_RSTAT_VMRD_M\t\t\tBIT(0)\n+#define VSIGEN_RTRIG(_VSI)\t\t\t(0x00091800 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSIGEN_RTRIG_MAX_INDEX\t\t\t767\n+#define VSIGEN_RTRIG_VMSWR_S\t\t\t0\n+#define VSIGEN_RTRIG_VMSWR_M\t\t\tBIT(0)\n+#define GLHMC_APBVTINUSEBASE(_i)\t\t(0x00524A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_APBVTINUSEBASE_MAX_INDEX\t\t7\n+#define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_S\t0\n+#define GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_CEQPART(_i)\t\t\t(0x005031C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_CEQPART_MAX_INDEX\t\t\t7\n+#define GLHMC_CEQPART_PMCEQBASE_S\t\t0\n+#define GLHMC_CEQPART_PMCEQBASE_M\t\tMAKEMASK(0x3FF, 0)\n+#define GLHMC_CEQPART_PMCEQSIZE_S\t\t16\n+#define GLHMC_CEQPART_PMCEQSIZE_M\t\tMAKEMASK(0x3FF, 16)\n+#define GLHMC_DBCQMAX\t\t\t\t0x005220F0 /* Reset Source: CORER */\n+#define GLHMC_DBCQMAX_GLHMC_DBCQMAX_S\t\t0\n+#define GLHMC_DBCQMAX_GLHMC_DBCQMAX_M\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLHMC_DBCQPART(_i)\t\t\t(0x00503180 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_DBCQPART_MAX_INDEX\t\t7\n+#define GLHMC_DBCQPART_PMDBCQBASE_S\t\t0\n+#define GLHMC_DBCQPART_PMDBCQBASE_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLHMC_DBCQPART_PMDBCQSIZE_S\t\t16\n+#define GLHMC_DBCQPART_PMDBCQSIZE_M\t\tMAKEMASK(0x7FFF, 16)\n+#define GLHMC_DBQPMAX\t\t\t\t0x005220EC /* Reset Source: CORER */\n+#define GLHMC_DBQPMAX_GLHMC_DBQPMAX_S\t\t0\n+#define GLHMC_DBQPMAX_GLHMC_DBQPMAX_M\t\tMAKEMASK(0x7FFFF, 0)\n+#define GLHMC_DBQPPART(_i)\t\t\t(0x005044C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_DBQPPART_MAX_INDEX\t\t7\n+#define GLHMC_DBQPPART_PMDBQPBASE_S\t\t0\n+#define GLHMC_DBQPPART_PMDBQPBASE_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLHMC_DBQPPART_PMDBQPSIZE_S\t\t16\n+#define GLHMC_DBQPPART_PMDBQPSIZE_M\t\tMAKEMASK(0x7FFF, 16)\n+#define GLHMC_FSIAVBASE(_i)\t\t\t(0x00525600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_FSIAVBASE_MAX_INDEX\t\t7\n+#define GLHMC_FSIAVBASE_FPMFSIAVBASE_S\t\t0\n+#define GLHMC_FSIAVBASE_FPMFSIAVBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_FSIAVCNT(_i)\t\t\t(0x00525700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_FSIAVCNT_MAX_INDEX\t\t7\n+#define GLHMC_FSIAVCNT_FPMFSIAVCNT_S\t\t0\n+#define GLHMC_FSIAVCNT_FPMFSIAVCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_FSIAVMAX\t\t\t\t0x00522068 /* Reset Source: CORER */\n+#define GLHMC_FSIAVMAX_PMFSIAVMAX_S\t\t0\n+#define GLHMC_FSIAVMAX_PMFSIAVMAX_M\t\tMAKEMASK(0x1FFFF, 0)\n+#define GLHMC_FSIAVOBJSZ\t\t\t0x00522064 /* Reset Source: CORER */\n+#define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_S\t\t0\n+#define GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_FSIMCBASE(_i)\t\t\t(0x00526000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_FSIMCBASE_MAX_INDEX\t\t7\n+#define GLHMC_FSIMCBASE_FPMFSIMCBASE_S\t\t0\n+#define GLHMC_FSIMCBASE_FPMFSIMCBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_FSIMCCNT(_i)\t\t\t(0x00526100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_FSIMCCNT_MAX_INDEX\t\t7\n+#define GLHMC_FSIMCCNT_FPMFSIMCSZ_S\t\t0\n+#define GLHMC_FSIMCCNT_FPMFSIMCSZ_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_FSIMCMAX\t\t\t\t0x00522060 /* Reset Source: CORER */\n+#define GLHMC_FSIMCMAX_PMFSIMCMAX_S\t\t0\n+#define GLHMC_FSIMCMAX_PMFSIMCMAX_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLHMC_FSIMCOBJSZ\t\t\t0x0052205C /* Reset Source: CORER */\n+#define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_S\t\t0\n+#define GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_FWPDINV\t\t\t\t0x0052207C /* Reset Source: CORER */\n+#define GLHMC_FWPDINV_PMSDIDX_S\t\t\t0\n+#define GLHMC_FWPDINV_PMSDIDX_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_FWPDINV_PMSDPARTSEL_S\t\t15\n+#define GLHMC_FWPDINV_PMSDPARTSEL_M\t\tBIT(15)\n+#define GLHMC_FWPDINV_PMPDIDX_S\t\t\t16\n+#define GLHMC_FWPDINV_PMPDIDX_M\t\t\tMAKEMASK(0x1FF, 16)\n+#define GLHMC_FWPDINV_FPMAT\t\t\t0x0010207c /* Reset Source: CORER */\n+#define GLHMC_FWPDINV_FPMAT_PMSDIDX_S\t\t0\n+#define GLHMC_FWPDINV_FPMAT_PMSDIDX_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_S\t15\n+#define GLHMC_FWPDINV_FPMAT_PMSDPARTSEL_M\tBIT(15)\n+#define GLHMC_FWPDINV_FPMAT_PMPDIDX_S\t\t16\n+#define GLHMC_FWPDINV_FPMAT_PMPDIDX_M\t\tMAKEMASK(0x1FF, 16)\n+#define GLHMC_FWSDDATAHIGH\t\t\t0x00522078 /* Reset Source: CORER */\n+#define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_S\t0\n+#define GLHMC_FWSDDATAHIGH_PMSDDATAHIGH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_FWSDDATAHIGH_FPMAT\t\t0x00102078 /* Reset Source: CORER */\n+#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0\n+#define GLHMC_FWSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_FWSDDATALOW\t\t\t0x00522074 /* Reset Source: CORER */\n+#define GLHMC_FWSDDATALOW_PMSDVALID_S\t\t0\n+#define GLHMC_FWSDDATALOW_PMSDVALID_M\t\tBIT(0)\n+#define GLHMC_FWSDDATALOW_PMSDTYPE_S\t\t1\n+#define GLHMC_FWSDDATALOW_PMSDTYPE_M\t\tBIT(1)\n+#define GLHMC_FWSDDATALOW_PMSDBPCOUNT_S\t\t2\n+#define GLHMC_FWSDDATALOW_PMSDBPCOUNT_M\t\tMAKEMASK(0x3FF, 2)\n+#define GLHMC_FWSDDATALOW_PMSDDATALOW_S\t\t12\n+#define GLHMC_FWSDDATALOW_PMSDDATALOW_M\t\tMAKEMASK(0xFFFFF, 12)\n+#define GLHMC_FWSDDATALOW_FPMAT\t\t\t0x00102074 /* Reset Source: CORER */\n+#define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_S\t0\n+#define GLHMC_FWSDDATALOW_FPMAT_PMSDVALID_M\tBIT(0)\n+#define GLHMC_FWSDDATALOW_FPMAT_PMSDTYPE_S\t1\n+#define GLHMC_FWSDDATALOW_FPMAT_PMSDTYPE_M\tBIT(1)\n+#define GLHMC_FWSDDATALOW_FPMAT_PMSDBPCOUNT_S\t2\n+#define GLHMC_FWSDDATALOW_FPMAT_PMSDBPCOUNT_M\tMAKEMASK(0x3FF, 2)\n+#define GLHMC_FWSDDATALOW_FPMAT_PMSDDATALOW_S\t12\n+#define GLHMC_FWSDDATALOW_FPMAT_PMSDDATALOW_M\tMAKEMASK(0xFFFFF, 12)\n+#define GLHMC_PEARPBASE(_i)\t\t\t(0x00524800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEARPBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEARPBASE_FPMPEARPBASE_S\t\t0\n+#define GLHMC_PEARPBASE_FPMPEARPBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEARPCNT(_i)\t\t\t(0x00524900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEARPCNT_MAX_INDEX\t\t7\n+#define GLHMC_PEARPCNT_FPMPEARPCNT_S\t\t0\n+#define GLHMC_PEARPCNT_FPMPEARPCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEARPMAX\t\t\t\t0x00522038 /* Reset Source: CORER */\n+#define GLHMC_PEARPMAX_PMPEARPMAX_S\t\t0\n+#define GLHMC_PEARPMAX_PMPEARPMAX_M\t\tMAKEMASK(0x1FFFF, 0)\n+#define GLHMC_PEARPOBJSZ\t\t\t0x00522034 /* Reset Source: CORER */\n+#define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_S\t\t0\n+#define GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_M\t\tMAKEMASK(0x7, 0)\n+#define GLHMC_PECQBASE(_i)\t\t\t(0x00524200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PECQBASE_MAX_INDEX\t\t7\n+#define GLHMC_PECQBASE_FPMPECQBASE_S\t\t0\n+#define GLHMC_PECQBASE_FPMPECQBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PECQCNT(_i)\t\t\t(0x00524300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PECQCNT_MAX_INDEX\t\t\t7\n+#define GLHMC_PECQCNT_FPMPECQCNT_S\t\t0\n+#define GLHMC_PECQCNT_FPMPECQCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PECQOBJSZ\t\t\t\t0x00522020 /* Reset Source: CORER */\n+#define GLHMC_PECQOBJSZ_PMPECQOBJSZ_S\t\t0\n+#define GLHMC_PECQOBJSZ_PMPECQOBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_PEHDRBASE(_i)\t\t\t(0x00526200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEHDRBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_S\t0\n+#define GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PEHDRCNT(_i)\t\t\t(0x00526300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEHDRCNT_MAX_INDEX\t\t7\n+#define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_S\t\t0\n+#define GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PEHDRMAX\t\t\t\t0x00522008 /* Reset Source: CORER */\n+#define GLHMC_PEHDRMAX_PMPEHDRMAX_S\t\t0\n+#define GLHMC_PEHDRMAX_PMPEHDRMAX_M\t\tMAKEMASK(0x7FFFF, 0)\n+#define GLHMC_PEHDRMAX_RSVD_S\t\t\t19\n+#define GLHMC_PEHDRMAX_RSVD_M\t\t\tMAKEMASK(0x1FFF, 19)\n+#define GLHMC_PEHDROBJSZ\t\t\t0x00522004 /* Reset Source: CORER */\n+#define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_S\t\t0\n+#define GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_PEHDROBJSZ_RSVD_S\t\t\t4\n+#define GLHMC_PEHDROBJSZ_RSVD_M\t\t\tMAKEMASK(0xFFFFFFF, 4)\n+#define GLHMC_PEHTCNT(_i)\t\t\t(0x00524700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEHTCNT_MAX_INDEX\t\t\t7\n+#define GLHMC_PEHTCNT_FPMPEHTCNT_S\t\t0\n+#define GLHMC_PEHTCNT_FPMPEHTCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEHTCNT_FPMAT(_i)\t\t\t(0x00104700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEHTCNT_FPMAT_MAX_INDEX\t\t7\n+#define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_S\t0\n+#define GLHMC_PEHTCNT_FPMAT_FPMPEHTCNT_M\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEHTEBASE(_i)\t\t\t(0x00524600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEHTEBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEHTEBASE_FPMPEHTEBASE_S\t\t0\n+#define GLHMC_PEHTEBASE_FPMPEHTEBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEHTEBASE_FPMAT(_i)\t\t(0x00104600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEHTEBASE_FPMAT_MAX_INDEX\t\t7\n+#define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_S\t0\n+#define GLHMC_PEHTEBASE_FPMAT_FPMPEHTEBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEHTEOBJSZ\t\t\t0x0052202C /* Reset Source: CORER */\n+#define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_S\t\t0\n+#define GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_PEHTEOBJSZ_FPMAT\t\t\t0x0010202c /* Reset Source: CORER */\n+#define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_S\t0\n+#define GLHMC_PEHTEOBJSZ_FPMAT_PMPEHTEOBJSZ_M\tMAKEMASK(0xF, 0)\n+#define GLHMC_PEHTMAX\t\t\t\t0x00522030 /* Reset Source: CORER */\n+#define GLHMC_PEHTMAX_PMPEHTMAX_S\t\t0\n+#define GLHMC_PEHTMAX_PMPEHTMAX_M\t\tMAKEMASK(0x1FFFFF, 0)\n+#define GLHMC_PEHTMAX_FPMAT\t\t\t0x00102030 /* Reset Source: CORER */\n+#define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_S\t\t0\n+#define GLHMC_PEHTMAX_FPMAT_PMPEHTMAX_M\t\tMAKEMASK(0x1FFFFF, 0)\n+#define GLHMC_PEMDBASE(_i)\t\t\t(0x00526400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEMDBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEMDBASE_GLHMC_PEMDBASE_S\t\t0\n+#define GLHMC_PEMDBASE_GLHMC_PEMDBASE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PEMDCNT(_i)\t\t\t(0x00526500 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEMDCNT_MAX_INDEX\t\t\t7\n+#define GLHMC_PEMDCNT_GLHMC_PEMDCNT_S\t\t0\n+#define GLHMC_PEMDCNT_GLHMC_PEMDCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PEMDMAX\t\t\t\t0x00522010 /* Reset Source: CORER */\n+#define GLHMC_PEMDMAX_PMPEMDMAX_S\t\t0\n+#define GLHMC_PEMDMAX_PMPEMDMAX_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEMDMAX_RSVD_S\t\t\t24\n+#define GLHMC_PEMDMAX_RSVD_M\t\t\tMAKEMASK(0xFF, 24)\n+#define GLHMC_PEMDOBJSZ\t\t\t\t0x0052200C /* Reset Source: CORER */\n+#define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_S\t\t0\n+#define GLHMC_PEMDOBJSZ_PMPEMDOBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_PEMDOBJSZ_RSVD_S\t\t\t4\n+#define GLHMC_PEMDOBJSZ_RSVD_M\t\t\tMAKEMASK(0xFFFFFFF, 4)\n+#define GLHMC_PEMRBASE(_i)\t\t\t(0x00524C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEMRBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEMRBASE_FPMPEMRBASE_S\t\t0\n+#define GLHMC_PEMRBASE_FPMPEMRBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEMRCNT(_i)\t\t\t(0x00524D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEMRCNT_MAX_INDEX\t\t\t7\n+#define GLHMC_PEMRCNT_FPMPEMRSZ_S\t\t0\n+#define GLHMC_PEMRCNT_FPMPEMRSZ_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEMRMAX\t\t\t\t0x00522040 /* Reset Source: CORER */\n+#define GLHMC_PEMRMAX_PMPEMRMAX_S\t\t0\n+#define GLHMC_PEMRMAX_PMPEMRMAX_M\t\tMAKEMASK(0x7FFFFF, 0)\n+#define GLHMC_PEMROBJSZ\t\t\t\t0x0052203c /* Reset Source: CORER */\n+#define GLHMC_PEMROBJSZ_PMPEMROBJSZ_S\t\t0\n+#define GLHMC_PEMROBJSZ_PMPEMROBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_PEOOISCBASE(_i)\t\t\t(0x00526600 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEOOISCBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_S\t0\n+#define GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PEOOISCCNT(_i)\t\t\t(0x00526700 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEOOISCCNT_MAX_INDEX\t\t7\n+#define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_S\t0\n+#define GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PEOOISCFFLBASE(_i)\t\t(0x00526C00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEOOISCFFLBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0\n+#define GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PEOOISCFFLCNT_PMAT(_i)\t\t(0x00526D00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEOOISCFFLCNT_PMAT_MAX_INDEX\t7\n+#define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_S 0\n+#define GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFLCNT_M MAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEOOISCFFLMAX\t\t\t0x005220A4 /* Reset Source: CORER */\n+#define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_S\t0\n+#define GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_M\tMAKEMASK(0x7FFFF, 0)\n+#define GLHMC_PEOOISCFFLMAX_RSVD_S\t\t19\n+#define GLHMC_PEOOISCFFLMAX_RSVD_M\t\tMAKEMASK(0x1FFF, 19)\n+#define GLHMC_PEOOISCMAX\t\t\t0x00522018 /* Reset Source: CORER */\n+#define GLHMC_PEOOISCMAX_PMPEOOISCMAX_S\t\t0\n+#define GLHMC_PEOOISCMAX_PMPEOOISCMAX_M\t\tMAKEMASK(0x7FFFF, 0)\n+#define GLHMC_PEOOISCMAX_RSVD_S\t\t\t19\n+#define GLHMC_PEOOISCMAX_RSVD_M\t\t\tMAKEMASK(0x1FFF, 19)\n+#define GLHMC_PEOOISCOBJSZ\t\t\t0x00522014 /* Reset Source: CORER */\n+#define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_S\t0\n+#define GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_M\tMAKEMASK(0xF, 0)\n+#define GLHMC_PEOOISCOBJSZ_RSVD_S\t\t4\n+#define GLHMC_PEOOISCOBJSZ_RSVD_M\t\tMAKEMASK(0xFFFFFFF, 4)\n+#define GLHMC_PEPBLBASE(_i)\t\t\t(0x00525800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEPBLBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEPBLBASE_FPMPEPBLBASE_S\t\t0\n+#define GLHMC_PEPBLBASE_FPMPEPBLBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEPBLCNT(_i)\t\t\t(0x00525900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEPBLCNT_MAX_INDEX\t\t7\n+#define GLHMC_PEPBLCNT_FPMPEPBLCNT_S\t\t0\n+#define GLHMC_PEPBLCNT_FPMPEPBLCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEPBLMAX\t\t\t\t0x0052206C /* Reset Source: CORER */\n+#define GLHMC_PEPBLMAX_PMPEPBLMAX_S\t\t0\n+#define GLHMC_PEPBLMAX_PMPEPBLMAX_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEQ1BASE(_i)\t\t\t(0x00525200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEQ1BASE_MAX_INDEX\t\t7\n+#define GLHMC_PEQ1BASE_FPMPEQ1BASE_S\t\t0\n+#define GLHMC_PEQ1BASE_FPMPEQ1BASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEQ1CNT(_i)\t\t\t(0x00525300 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEQ1CNT_MAX_INDEX\t\t\t7\n+#define GLHMC_PEQ1CNT_FPMPEQ1CNT_S\t\t0\n+#define GLHMC_PEQ1CNT_FPMPEQ1CNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEQ1FLBASE(_i)\t\t\t(0x00525400 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEQ1FLBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_S\t0\n+#define GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEQ1FLMAX\t\t\t\t0x00522058 /* Reset Source: CORER */\n+#define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_S\t\t0\n+#define GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_M\t\tMAKEMASK(0x3FFFFFF, 0)\n+#define GLHMC_PEQ1MAX\t\t\t\t0x00522054 /* Reset Source: CORER */\n+#define GLHMC_PEQ1MAX_PMPEQ1MAX_S\t\t0\n+#define GLHMC_PEQ1MAX_PMPEQ1MAX_M\t\tMAKEMASK(0xFFFFFFF, 0)\n+#define GLHMC_PEQ1OBJSZ\t\t\t\t0x00522050 /* Reset Source: CORER */\n+#define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_S\t\t0\n+#define GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_PEQPBASE(_i)\t\t\t(0x00524000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEQPBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEQPBASE_FPMPEQPBASE_S\t\t0\n+#define GLHMC_PEQPBASE_FPMPEQPBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEQPCNT(_i)\t\t\t(0x00524100 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEQPCNT_MAX_INDEX\t\t\t7\n+#define GLHMC_PEQPCNT_FPMPEQPCNT_S\t\t0\n+#define GLHMC_PEQPCNT_FPMPEQPCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEQPOBJSZ\t\t\t\t0x0052201C /* Reset Source: CORER */\n+#define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_S\t\t0\n+#define GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_PERRFBASE(_i)\t\t\t(0x00526800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PERRFBASE_MAX_INDEX\t\t7\n+#define GLHMC_PERRFBASE_GLHMC_PERRFBASE_S\t0\n+#define GLHMC_PERRFBASE_GLHMC_PERRFBASE_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PERRFCNT(_i)\t\t\t(0x00526900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PERRFCNT_MAX_INDEX\t\t7\n+#define GLHMC_PERRFCNT_GLHMC_PERRFCNT_S\t\t0\n+#define GLHMC_PERRFCNT_GLHMC_PERRFCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PERRFFLBASE(_i)\t\t\t(0x00526A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PERRFFLBASE_MAX_INDEX\t\t7\n+#define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_S\t0\n+#define GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_PERRFFLCNT_PMAT(_i)\t\t(0x00526B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PERRFFLCNT_PMAT_MAX_INDEX\t\t7\n+#define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_S\t0\n+#define GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_M\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PERRFFLMAX\t\t\t0x005220A0 /* Reset Source: CORER */\n+#define GLHMC_PERRFFLMAX_PMPERRFFLMAX_S\t\t0\n+#define GLHMC_PERRFFLMAX_PMPERRFFLMAX_M\t\tMAKEMASK(0x3FFFFFF, 0)\n+#define GLHMC_PERRFFLMAX_RSVD_S\t\t\t26\n+#define GLHMC_PERRFFLMAX_RSVD_M\t\t\tMAKEMASK(0x3F, 26)\n+#define GLHMC_PERRFMAX\t\t\t\t0x0052209C /* Reset Source: CORER */\n+#define GLHMC_PERRFMAX_PMPERRFMAX_S\t\t0\n+#define GLHMC_PERRFMAX_PMPERRFMAX_M\t\tMAKEMASK(0xFFFFFFF, 0)\n+#define GLHMC_PERRFMAX_RSVD_S\t\t\t28\n+#define GLHMC_PERRFMAX_RSVD_M\t\t\tMAKEMASK(0xF, 28)\n+#define GLHMC_PERRFOBJSZ\t\t\t0x00522098 /* Reset Source: CORER */\n+#define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_S\t\t0\n+#define GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_PERRFOBJSZ_RSVD_S\t\t\t4\n+#define GLHMC_PERRFOBJSZ_RSVD_M\t\t\tMAKEMASK(0xFFFFFFF, 4)\n+#define GLHMC_PETIMERBASE(_i)\t\t\t(0x00525A00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PETIMERBASE_MAX_INDEX\t\t7\n+#define GLHMC_PETIMERBASE_FPMPETIMERBASE_S\t0\n+#define GLHMC_PETIMERBASE_FPMPETIMERBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PETIMERCNT(_i)\t\t\t(0x00525B00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PETIMERCNT_MAX_INDEX\t\t7\n+#define GLHMC_PETIMERCNT_FPMPETIMERCNT_S\t0\n+#define GLHMC_PETIMERCNT_FPMPETIMERCNT_M\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PETIMERMAX\t\t\t0x00522084 /* Reset Source: CORER */\n+#define GLHMC_PETIMERMAX_PMPETIMERMAX_S\t\t0\n+#define GLHMC_PETIMERMAX_PMPETIMERMAX_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PETIMEROBJSZ\t\t\t0x00522080 /* Reset Source: CORER */\n+#define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_S\t0\n+#define GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_M\tMAKEMASK(0xF, 0)\n+#define GLHMC_PEXFBASE(_i)\t\t\t(0x00524E00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEXFBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEXFBASE_FPMPEXFBASE_S\t\t0\n+#define GLHMC_PEXFBASE_FPMPEXFBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEXFCNT(_i)\t\t\t(0x00524F00 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEXFCNT_MAX_INDEX\t\t\t7\n+#define GLHMC_PEXFCNT_FPMPEXFCNT_S\t\t0\n+#define GLHMC_PEXFCNT_FPMPEXFCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_PEXFFLBASE(_i)\t\t\t(0x00525000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PEXFFLBASE_MAX_INDEX\t\t7\n+#define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_S\t0\n+#define GLHMC_PEXFFLBASE_FPMPEXFFLBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_PEXFFLMAX\t\t\t\t0x0052204C /* Reset Source: CORER */\n+#define GLHMC_PEXFFLMAX_PMPEXFFLMAX_S\t\t0\n+#define GLHMC_PEXFFLMAX_PMPEXFFLMAX_M\t\tMAKEMASK(0x3FFFFFF, 0)\n+#define GLHMC_PEXFMAX\t\t\t\t0x00522048 /* Reset Source: CORER */\n+#define GLHMC_PEXFMAX_PMPEXFMAX_S\t\t0\n+#define GLHMC_PEXFMAX_PMPEXFMAX_M\t\tMAKEMASK(0xFFFFFFF, 0)\n+#define GLHMC_PEXFOBJSZ\t\t\t\t0x00522044 /* Reset Source: CORER */\n+#define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_S\t\t0\n+#define GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_M\t\tMAKEMASK(0xF, 0)\n+#define GLHMC_PFPESDPART(_i)\t\t\t(0x00520880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PFPESDPART_MAX_INDEX\t\t7\n+#define GLHMC_PFPESDPART_PMSDBASE_S\t\t0\n+#define GLHMC_PFPESDPART_PMSDBASE_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_PFPESDPART_PMSDSIZE_S\t\t16\n+#define GLHMC_PFPESDPART_PMSDSIZE_M\t\tMAKEMASK(0x1FFF, 16)\n+#define GLHMC_PFPESDPART_FPMAT(_i)\t\t(0x00100880 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_PFPESDPART_FPMAT_MAX_INDEX\t7\n+#define GLHMC_PFPESDPART_FPMAT_PMSDBASE_S\t0\n+#define GLHMC_PFPESDPART_FPMAT_PMSDBASE_M\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_PFPESDPART_FPMAT_PMSDSIZE_S\t16\n+#define GLHMC_PFPESDPART_FPMAT_PMSDSIZE_M\tMAKEMASK(0x1FFF, 16)\n+#define GLHMC_SDPART(_i)\t\t\t(0x00520800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_SDPART_MAX_INDEX\t\t\t7\n+#define GLHMC_SDPART_PMSDBASE_S\t\t\t0\n+#define GLHMC_SDPART_PMSDBASE_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_SDPART_PMSDSIZE_S\t\t\t16\n+#define GLHMC_SDPART_PMSDSIZE_M\t\t\tMAKEMASK(0x1FFF, 16)\n+#define GLHMC_SDPART_FPMAT(_i)\t\t\t(0x00100800 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLHMC_SDPART_FPMAT_MAX_INDEX\t\t7\n+#define GLHMC_SDPART_FPMAT_PMSDBASE_S\t\t0\n+#define GLHMC_SDPART_FPMAT_PMSDBASE_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_SDPART_FPMAT_PMSDSIZE_S\t\t16\n+#define GLHMC_SDPART_FPMAT_PMSDSIZE_M\t\tMAKEMASK(0x1FFF, 16)\n+#define GLHMC_VFAPBVTINUSEBASE(_i)\t\t(0x0052CA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFAPBVTINUSEBASE_MAX_INDEX\t31\n+#define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_S 0\n+#define GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_M MAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFCEQPART(_i)\t\t\t(0x00502F00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFCEQPART_MAX_INDEX\t\t31\n+#define GLHMC_VFCEQPART_PMCEQBASE_S\t\t0\n+#define GLHMC_VFCEQPART_PMCEQBASE_M\t\tMAKEMASK(0x3FF, 0)\n+#define GLHMC_VFCEQPART_PMCEQSIZE_S\t\t16\n+#define GLHMC_VFCEQPART_PMCEQSIZE_M\t\tMAKEMASK(0x3FF, 16)\n+#define GLHMC_VFDBCQPART(_i)\t\t\t(0x00502E00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFDBCQPART_MAX_INDEX\t\t31\n+#define GLHMC_VFDBCQPART_PMDBCQBASE_S\t\t0\n+#define GLHMC_VFDBCQPART_PMDBCQBASE_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLHMC_VFDBCQPART_PMDBCQSIZE_S\t\t16\n+#define GLHMC_VFDBCQPART_PMDBCQSIZE_M\t\tMAKEMASK(0x7FFF, 16)\n+#define GLHMC_VFDBQPPART(_i)\t\t\t(0x00504520 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFDBQPPART_MAX_INDEX\t\t31\n+#define GLHMC_VFDBQPPART_PMDBQPBASE_S\t\t0\n+#define GLHMC_VFDBQPPART_PMDBQPBASE_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLHMC_VFDBQPPART_PMDBQPSIZE_S\t\t16\n+#define GLHMC_VFDBQPPART_PMDBQPSIZE_M\t\tMAKEMASK(0x7FFF, 16)\n+#define GLHMC_VFFSIAVBASE(_i)\t\t\t(0x0052D600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFFSIAVBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_S\t0\n+#define GLHMC_VFFSIAVBASE_FPMFSIAVBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFFSIAVCNT(_i)\t\t\t(0x0052D700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFFSIAVCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_S\t\t0\n+#define GLHMC_VFFSIAVCNT_FPMFSIAVCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFFSIMCBASE(_i)\t\t\t(0x0052E000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFFSIMCBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_S\t0\n+#define GLHMC_VFFSIMCBASE_FPMFSIMCBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFFSIMCCNT(_i)\t\t\t(0x0052E100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFFSIMCCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_S\t\t0\n+#define GLHMC_VFFSIMCCNT_FPMFSIMCSZ_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPDINV(_i)\t\t\t(0x00528300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPDINV_MAX_INDEX\t\t\t31\n+#define GLHMC_VFPDINV_PMSDIDX_S\t\t\t0\n+#define GLHMC_VFPDINV_PMSDIDX_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_VFPDINV_PMSDPARTSEL_S\t\t15\n+#define GLHMC_VFPDINV_PMSDPARTSEL_M\t\tBIT(15)\n+#define GLHMC_VFPDINV_PMPDIDX_S\t\t\t16\n+#define GLHMC_VFPDINV_PMPDIDX_M\t\t\tMAKEMASK(0x1FF, 16)\n+#define GLHMC_VFPDINV_FPMAT(_i)\t\t\t(0x00108300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPDINV_FPMAT_MAX_INDEX\t\t31\n+#define GLHMC_VFPDINV_FPMAT_PMSDIDX_S\t\t0\n+#define GLHMC_VFPDINV_FPMAT_PMSDIDX_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_VFPDINV_FPMAT_PMSDPARTSEL_S\t15\n+#define GLHMC_VFPDINV_FPMAT_PMSDPARTSEL_M\tBIT(15)\n+#define GLHMC_VFPDINV_FPMAT_PMPDIDX_S\t\t16\n+#define GLHMC_VFPDINV_FPMAT_PMPDIDX_M\t\tMAKEMASK(0x1FF, 16)\n+#define GLHMC_VFPEARPBASE(_i)\t\t\t(0x0052C800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEARPBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEARPBASE_FPMPEARPBASE_S\t0\n+#define GLHMC_VFPEARPBASE_FPMPEARPBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPEARPCNT(_i)\t\t\t(0x0052C900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEARPCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEARPCNT_FPMPEARPCNT_S\t\t0\n+#define GLHMC_VFPEARPCNT_FPMPEARPCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPECQBASE(_i)\t\t\t(0x0052C200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPECQBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPECQBASE_FPMPECQBASE_S\t\t0\n+#define GLHMC_VFPECQBASE_FPMPECQBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPECQCNT(_i)\t\t\t(0x0052C300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPECQCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPECQCNT_FPMPECQCNT_S\t\t0\n+#define GLHMC_VFPECQCNT_FPMPECQCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPEHDRBASE(_i)\t\t\t(0x0052E200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEHDRBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_S\t0\n+#define GLHMC_VFPEHDRBASE_GLHMC_PEHDRBASE_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPEHDRCNT(_i)\t\t\t(0x0052E300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEHDRCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_S\t0\n+#define GLHMC_VFPEHDRCNT_GLHMC_PEHDRCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPEHTCNT(_i)\t\t\t(0x0052C700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEHTCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEHTCNT_FPMPEHTCNT_S\t\t0\n+#define GLHMC_VFPEHTCNT_FPMPEHTCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPEHTCNT_FPMAT(_i)\t\t(0x0010c700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEHTCNT_FPMAT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_S\t0\n+#define GLHMC_VFPEHTCNT_FPMAT_FPMPEHTCNT_M\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPEHTEBASE(_i)\t\t\t(0x0052C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEHTEBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_S\t0\n+#define GLHMC_VFPEHTEBASE_FPMPEHTEBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPEHTEBASE_FPMAT(_i)\t\t(0x0010C600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEHTEBASE_FPMAT_MAX_INDEX\t31\n+#define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_S\t0\n+#define GLHMC_VFPEHTEBASE_FPMAT_FPMPEHTEBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPEMDBASE(_i)\t\t\t(0x0052E400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEMDBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_S\t0\n+#define GLHMC_VFPEMDBASE_GLHMC_PEMDBASE_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPEMDCNT(_i)\t\t\t(0x0052E500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEMDCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_S\t\t0\n+#define GLHMC_VFPEMDCNT_GLHMC_PEMDCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPEMRBASE(_i)\t\t\t(0x0052CC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEMRBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEMRBASE_FPMPEMRBASE_S\t\t0\n+#define GLHMC_VFPEMRBASE_FPMPEMRBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPEMRCNT(_i)\t\t\t(0x0052CD00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEMRCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEMRCNT_FPMPEMRSZ_S\t\t0\n+#define GLHMC_VFPEMRCNT_FPMPEMRSZ_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPEOOISCBASE(_i)\t\t\t(0x0052E600 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEOOISCBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_S 0\n+#define GLHMC_VFPEOOISCBASE_GLHMC_PEOOISCBASE_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPEOOISCCNT(_i)\t\t\t(0x0052E700 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEOOISCCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_S\t0\n+#define GLHMC_VFPEOOISCCNT_GLHMC_PEOOISCCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPEOOISCFFLBASE(_i)\t\t(0x0052EC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEOOISCFFLBASE_MAX_INDEX\t31\n+#define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0\n+#define GLHMC_VFPEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPEPBLBASE(_i)\t\t\t(0x0052D800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEPBLBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_S\t0\n+#define GLHMC_VFPEPBLBASE_FPMPEPBLBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPEPBLCNT(_i)\t\t\t(0x0052D900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEPBLCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_S\t\t0\n+#define GLHMC_VFPEPBLCNT_FPMPEPBLCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPEQ1BASE(_i)\t\t\t(0x0052D200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEQ1BASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_S\t\t0\n+#define GLHMC_VFPEQ1BASE_FPMPEQ1BASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPEQ1CNT(_i)\t\t\t(0x0052D300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEQ1CNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_S\t\t0\n+#define GLHMC_VFPEQ1CNT_FPMPEQ1CNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPEQ1FLBASE(_i)\t\t\t(0x0052D400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEQ1FLBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_S\t0\n+#define GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPEQPBASE(_i)\t\t\t(0x0052C000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEQPBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEQPBASE_FPMPEQPBASE_S\t\t0\n+#define GLHMC_VFPEQPBASE_FPMPEQPBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPEQPCNT(_i)\t\t\t(0x0052C100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEQPCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEQPCNT_FPMPEQPCNT_S\t\t0\n+#define GLHMC_VFPEQPCNT_FPMPEQPCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPERRFBASE(_i)\t\t\t(0x0052E800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPERRFBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_S\t0\n+#define GLHMC_VFPERRFBASE_GLHMC_PERRFBASE_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPERRFCNT(_i)\t\t\t(0x0052E900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPERRFCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_S\t0\n+#define GLHMC_VFPERRFCNT_GLHMC_PERRFCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPERRFFLBASE(_i)\t\t\t(0x0052EA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPERRFFLBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_S 0\n+#define GLHMC_VFPERRFFLBASE_GLHMC_PERRFFLBASE_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFPETIMERBASE(_i)\t\t\t(0x0052DA00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPETIMERBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_S\t0\n+#define GLHMC_VFPETIMERBASE_FPMPETIMERBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPETIMERCNT(_i)\t\t\t(0x0052DB00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPETIMERCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_S\t0\n+#define GLHMC_VFPETIMERCNT_FPMPETIMERCNT_M\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPEXFBASE(_i)\t\t\t(0x0052CE00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEXFBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEXFBASE_FPMPEXFBASE_S\t\t0\n+#define GLHMC_VFPEXFBASE_FPMPEXFBASE_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFPEXFCNT(_i)\t\t\t(0x0052CF00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEXFCNT_MAX_INDEX\t\t31\n+#define GLHMC_VFPEXFCNT_FPMPEXFCNT_S\t\t0\n+#define GLHMC_VFPEXFCNT_FPMPEXFCNT_M\t\tMAKEMASK(0x1FFFFFFF, 0)\n+#define GLHMC_VFPEXFFLBASE(_i)\t\t\t(0x0052D000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFPEXFFLBASE_MAX_INDEX\t\t31\n+#define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_S\t0\n+#define GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLHMC_VFSDDATAHIGH(_i)\t\t\t(0x00528200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFSDDATAHIGH_MAX_INDEX\t\t31\n+#define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_S\t0\n+#define GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFSDDATAHIGH_FPMAT(_i)\t\t(0x00108200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFSDDATAHIGH_FPMAT_MAX_INDEX\t31\n+#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_S 0\n+#define GLHMC_VFSDDATAHIGH_FPMAT_PMSDDATAHIGH_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLHMC_VFSDDATALOW(_i)\t\t\t(0x00528100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFSDDATALOW_MAX_INDEX\t\t31\n+#define GLHMC_VFSDDATALOW_PMSDVALID_S\t\t0\n+#define GLHMC_VFSDDATALOW_PMSDVALID_M\t\tBIT(0)\n+#define GLHMC_VFSDDATALOW_PMSDTYPE_S\t\t1\n+#define GLHMC_VFSDDATALOW_PMSDTYPE_M\t\tBIT(1)\n+#define GLHMC_VFSDDATALOW_PMSDBPCOUNT_S\t\t2\n+#define GLHMC_VFSDDATALOW_PMSDBPCOUNT_M\t\tMAKEMASK(0x3FF, 2)\n+#define GLHMC_VFSDDATALOW_PMSDDATALOW_S\t\t12\n+#define GLHMC_VFSDDATALOW_PMSDDATALOW_M\t\tMAKEMASK(0xFFFFF, 12)\n+#define GLHMC_VFSDDATALOW_FPMAT(_i)\t\t(0x00108100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFSDDATALOW_FPMAT_MAX_INDEX\t31\n+#define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_S\t0\n+#define GLHMC_VFSDDATALOW_FPMAT_PMSDVALID_M\tBIT(0)\n+#define GLHMC_VFSDDATALOW_FPMAT_PMSDTYPE_S\t1\n+#define GLHMC_VFSDDATALOW_FPMAT_PMSDTYPE_M\tBIT(1)\n+#define GLHMC_VFSDDATALOW_FPMAT_PMSDBPCOUNT_S\t2\n+#define GLHMC_VFSDDATALOW_FPMAT_PMSDBPCOUNT_M\tMAKEMASK(0x3FF, 2)\n+#define GLHMC_VFSDDATALOW_FPMAT_PMSDDATALOW_S\t12\n+#define GLHMC_VFSDDATALOW_FPMAT_PMSDDATALOW_M\tMAKEMASK(0xFFFFF, 12)\n+#define GLHMC_VFSDPART(_i)\t\t\t(0x00528800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFSDPART_MAX_INDEX\t\t31\n+#define GLHMC_VFSDPART_PMSDBASE_S\t\t0\n+#define GLHMC_VFSDPART_PMSDBASE_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_VFSDPART_PMSDSIZE_S\t\t16\n+#define GLHMC_VFSDPART_PMSDSIZE_M\t\tMAKEMASK(0x1FFF, 16)\n+#define GLHMC_VFSDPART_FPMAT(_i)\t\t(0x00108800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLHMC_VFSDPART_FPMAT_MAX_INDEX\t\t31\n+#define GLHMC_VFSDPART_FPMAT_PMSDBASE_S\t\t0\n+#define GLHMC_VFSDPART_FPMAT_PMSDBASE_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLHMC_VFSDPART_FPMAT_PMSDSIZE_S\t\t16\n+#define GLHMC_VFSDPART_FPMAT_PMSDSIZE_M\t\tMAKEMASK(0x1FFF, 16)\n+#define GLMDOC_CACHESIZE\t\t\t0x0051C06C /* Reset Source: CORER */\n+#define GLMDOC_CACHESIZE_WORD_SIZE_S\t\t0\n+#define GLMDOC_CACHESIZE_WORD_SIZE_M\t\tMAKEMASK(0xFF, 0)\n+#define GLMDOC_CACHESIZE_SETS_S\t\t\t8\n+#define GLMDOC_CACHESIZE_SETS_M\t\t\tMAKEMASK(0xFFF, 8)\n+#define GLMDOC_CACHESIZE_WAYS_S\t\t\t20\n+#define GLMDOC_CACHESIZE_WAYS_M\t\t\tMAKEMASK(0xF, 20)\n+#define GLPBLOC0_CACHESIZE\t\t\t0x00518074 /* Reset Source: CORER */\n+#define GLPBLOC0_CACHESIZE_WORD_SIZE_S\t\t0\n+#define GLPBLOC0_CACHESIZE_WORD_SIZE_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPBLOC0_CACHESIZE_SETS_S\t\t8\n+#define GLPBLOC0_CACHESIZE_SETS_M\t\tMAKEMASK(0xFFF, 8)\n+#define GLPBLOC0_CACHESIZE_WAYS_S\t\t20\n+#define GLPBLOC0_CACHESIZE_WAYS_M\t\tMAKEMASK(0xF, 20)\n+#define GLPBLOC1_CACHESIZE\t\t\t0x0051A074 /* Reset Source: CORER */\n+#define GLPBLOC1_CACHESIZE_WORD_SIZE_S\t\t0\n+#define GLPBLOC1_CACHESIZE_WORD_SIZE_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPBLOC1_CACHESIZE_SETS_S\t\t8\n+#define GLPBLOC1_CACHESIZE_SETS_M\t\tMAKEMASK(0xFFF, 8)\n+#define GLPBLOC1_CACHESIZE_WAYS_S\t\t20\n+#define GLPBLOC1_CACHESIZE_WAYS_M\t\tMAKEMASK(0xF, 20)\n+#define GLPDOC_CACHESIZE\t\t\t0x00530048 /* Reset Source: CORER */\n+#define GLPDOC_CACHESIZE_WORD_SIZE_S\t\t0\n+#define GLPDOC_CACHESIZE_WORD_SIZE_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPDOC_CACHESIZE_SETS_S\t\t\t8\n+#define GLPDOC_CACHESIZE_SETS_M\t\t\tMAKEMASK(0xFFF, 8)\n+#define GLPDOC_CACHESIZE_WAYS_S\t\t\t20\n+#define GLPDOC_CACHESIZE_WAYS_M\t\t\tMAKEMASK(0xF, 20)\n+#define GLPDOC_CACHESIZE_FPMAT\t\t\t0x00110088 /* Reset Source: CORER */\n+#define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_S\t0\n+#define GLPDOC_CACHESIZE_FPMAT_WORD_SIZE_M\tMAKEMASK(0xFF, 0)\n+#define GLPDOC_CACHESIZE_FPMAT_SETS_S\t\t8\n+#define GLPDOC_CACHESIZE_FPMAT_SETS_M\t\tMAKEMASK(0xFFF, 8)\n+#define GLPDOC_CACHESIZE_FPMAT_WAYS_S\t\t20\n+#define GLPDOC_CACHESIZE_FPMAT_WAYS_M\t\tMAKEMASK(0xF, 20)\n+#define GLPEOC0_CACHESIZE\t\t\t0x005140A8 /* Reset Source: CORER */\n+#define GLPEOC0_CACHESIZE_WORD_SIZE_S\t\t0\n+#define GLPEOC0_CACHESIZE_WORD_SIZE_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPEOC0_CACHESIZE_SETS_S\t\t8\n+#define GLPEOC0_CACHESIZE_SETS_M\t\tMAKEMASK(0xFFF, 8)\n+#define GLPEOC0_CACHESIZE_WAYS_S\t\t20\n+#define GLPEOC0_CACHESIZE_WAYS_M\t\tMAKEMASK(0xF, 20)\n+#define GLPEOC1_CACHESIZE\t\t\t0x005160A8 /* Reset Source: CORER */\n+#define GLPEOC1_CACHESIZE_WORD_SIZE_S\t\t0\n+#define GLPEOC1_CACHESIZE_WORD_SIZE_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPEOC1_CACHESIZE_SETS_S\t\t8\n+#define GLPEOC1_CACHESIZE_SETS_M\t\tMAKEMASK(0xFFF, 8)\n+#define GLPEOC1_CACHESIZE_WAYS_S\t\t20\n+#define GLPEOC1_CACHESIZE_WAYS_M\t\tMAKEMASK(0xF, 20)\n+#define PFHMC_ERRORDATA\t\t\t\t0x00520500 /* Reset Source: PFR */\n+#define PFHMC_ERRORDATA_HMC_ERROR_DATA_S\t0\n+#define PFHMC_ERRORDATA_HMC_ERROR_DATA_M\tMAKEMASK(0x3FFFFFFF, 0)\n+#define PFHMC_ERRORDATA_FPMAT\t\t\t0x00100500 /* Reset Source: PFR */\n+#define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_S\t0\n+#define PFHMC_ERRORDATA_FPMAT_HMC_ERROR_DATA_M\tMAKEMASK(0x3FFFFFFF, 0)\n+#define PFHMC_ERRORINFO\t\t\t\t0x00520400 /* Reset Source: PFR */\n+#define PFHMC_ERRORINFO_PMF_INDEX_S\t\t0\n+#define PFHMC_ERRORINFO_PMF_INDEX_M\t\tMAKEMASK(0x1F, 0)\n+#define PFHMC_ERRORINFO_PMF_ISVF_S\t\t7\n+#define PFHMC_ERRORINFO_PMF_ISVF_M\t\tBIT(7)\n+#define PFHMC_ERRORINFO_HMC_ERROR_TYPE_S\t8\n+#define PFHMC_ERRORINFO_HMC_ERROR_TYPE_M\tMAKEMASK(0xF, 8)\n+#define PFHMC_ERRORINFO_HMC_OBJECT_TYPE_S\t16\n+#define PFHMC_ERRORINFO_HMC_OBJECT_TYPE_M\tMAKEMASK(0x1F, 16)\n+#define PFHMC_ERRORINFO_ERROR_DETECTED_S\t31\n+#define PFHMC_ERRORINFO_ERROR_DETECTED_M\tBIT(31)\n+#define PFHMC_ERRORINFO_FPMAT\t\t\t0x00100400 /* Reset Source: PFR */\n+#define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_S\t0\n+#define PFHMC_ERRORINFO_FPMAT_PMF_INDEX_M\tMAKEMASK(0x1F, 0)\n+#define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_S\t7\n+#define PFHMC_ERRORINFO_FPMAT_PMF_ISVF_M\tBIT(7)\n+#define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_S\t8\n+#define PFHMC_ERRORINFO_FPMAT_HMC_ERROR_TYPE_M\tMAKEMASK(0xF, 8)\n+#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_S 16\n+#define PFHMC_ERRORINFO_FPMAT_HMC_OBJECT_TYPE_M MAKEMASK(0x1F, 16)\n+#define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_S\t31\n+#define PFHMC_ERRORINFO_FPMAT_ERROR_DETECTED_M\tBIT(31)\n+#define PFHMC_PDINV\t\t\t\t0x00520300 /* Reset Source: PFR */\n+#define PFHMC_PDINV_PMSDIDX_S\t\t\t0\n+#define PFHMC_PDINV_PMSDIDX_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define PFHMC_PDINV_PMSDPARTSEL_S\t\t15\n+#define PFHMC_PDINV_PMSDPARTSEL_M\t\tBIT(15)\n+#define PFHMC_PDINV_PMPDIDX_S\t\t\t16\n+#define PFHMC_PDINV_PMPDIDX_M\t\t\tMAKEMASK(0x1FF, 16)\n+#define PFHMC_PDINV_FPMAT\t\t\t0x00100300 /* Reset Source: PFR */\n+#define PFHMC_PDINV_FPMAT_PMSDIDX_S\t\t0\n+#define PFHMC_PDINV_FPMAT_PMSDIDX_M\t\tMAKEMASK(0xFFF, 0)\n+#define PFHMC_PDINV_FPMAT_PMSDPARTSEL_S\t\t15\n+#define PFHMC_PDINV_FPMAT_PMSDPARTSEL_M\t\tBIT(15)\n+#define PFHMC_PDINV_FPMAT_PMPDIDX_S\t\t16\n+#define PFHMC_PDINV_FPMAT_PMPDIDX_M\t\tMAKEMASK(0x1FF, 16)\n+#define PFHMC_SDCMD\t\t\t\t0x00520000 /* Reset Source: PFR */\n+#define PFHMC_SDCMD_PMSDIDX_S\t\t\t0\n+#define PFHMC_SDCMD_PMSDIDX_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define PFHMC_SDCMD_PMSDPARTSEL_S\t\t15\n+#define PFHMC_SDCMD_PMSDPARTSEL_M\t\tBIT(15)\n+#define PFHMC_SDCMD_PMSDWR_S\t\t\t31\n+#define PFHMC_SDCMD_PMSDWR_M\t\t\tBIT(31)\n+#define PFHMC_SDCMD_FPMAT\t\t\t0x00100000 /* Reset Source: PFR */\n+#define PFHMC_SDCMD_FPMAT_PMSDIDX_S\t\t0\n+#define PFHMC_SDCMD_FPMAT_PMSDIDX_M\t\tMAKEMASK(0xFFF, 0)\n+#define PFHMC_SDCMD_FPMAT_PMSDPARTSEL_S\t\t15\n+#define PFHMC_SDCMD_FPMAT_PMSDPARTSEL_M\t\tBIT(15)\n+#define PFHMC_SDCMD_FPMAT_PMSDWR_S\t\t31\n+#define PFHMC_SDCMD_FPMAT_PMSDWR_M\t\tBIT(31)\n+#define PFHMC_SDDATAHIGH\t\t\t0x00520200 /* Reset Source: PFR */\n+#define PFHMC_SDDATAHIGH_PMSDDATAHIGH_S\t\t0\n+#define PFHMC_SDDATAHIGH_PMSDDATAHIGH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFHMC_SDDATAHIGH_FPMAT\t\t\t0x00100200 /* Reset Source: PFR */\n+#define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_S\t0\n+#define PFHMC_SDDATAHIGH_FPMAT_PMSDDATAHIGH_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFHMC_SDDATALOW\t\t\t\t0x00520100 /* Reset Source: PFR */\n+#define PFHMC_SDDATALOW_PMSDVALID_S\t\t0\n+#define PFHMC_SDDATALOW_PMSDVALID_M\t\tBIT(0)\n+#define PFHMC_SDDATALOW_PMSDTYPE_S\t\t1\n+#define PFHMC_SDDATALOW_PMSDTYPE_M\t\tBIT(1)\n+#define PFHMC_SDDATALOW_PMSDBPCOUNT_S\t\t2\n+#define PFHMC_SDDATALOW_PMSDBPCOUNT_M\t\tMAKEMASK(0x3FF, 2)\n+#define PFHMC_SDDATALOW_PMSDDATALOW_S\t\t12\n+#define PFHMC_SDDATALOW_PMSDDATALOW_M\t\tMAKEMASK(0xFFFFF, 12)\n+#define PFHMC_SDDATALOW_FPMAT\t\t\t0x00100100 /* Reset Source: PFR */\n+#define PFHMC_SDDATALOW_FPMAT_PMSDVALID_S\t0\n+#define PFHMC_SDDATALOW_FPMAT_PMSDVALID_M\tBIT(0)\n+#define PFHMC_SDDATALOW_FPMAT_PMSDTYPE_S\t1\n+#define PFHMC_SDDATALOW_FPMAT_PMSDTYPE_M\tBIT(1)\n+#define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_S\t2\n+#define PFHMC_SDDATALOW_FPMAT_PMSDBPCOUNT_M\tMAKEMASK(0x3FF, 2)\n+#define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_S\t12\n+#define PFHMC_SDDATALOW_FPMAT_PMSDDATALOW_M\tMAKEMASK(0xFFFFF, 12)\n+#define GL_DSI_RDPC\t\t\t\t0x00294204 /* Reset Source: CORER */\n+#define GL_DSI_RDPC_RDPC_S\t\t\t0\n+#define GL_DSI_RDPC_RDPC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_DSI_REPC\t\t\t\t0x00294208 /* Reset Source: CORER */\n+#define GL_DSI_REPC_NO_DESC_CNT_S\t\t0\n+#define GL_DSI_REPC_NO_DESC_CNT_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GL_DSI_REPC_ERROR_CNT_S\t\t\t16\n+#define GL_DSI_REPC_ERROR_CNT_M\t\t\tMAKEMASK(0xFFFF, 16)\n+#define GL_MDCK_TDAT_TCLAN\t\t\t0x000FC0DC /* Reset Source: CORER */\n+#define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_S 0\n+#define GL_MDCK_TDAT_TCLAN_WRONG_ORDER_FORMAT_DESC_M BIT(0)\n+#define GL_MDCK_TDAT_TCLAN_UR_S\t\t\t1\n+#define GL_MDCK_TDAT_TCLAN_UR_M\t\t\tBIT(1)\n+#define GL_MDCK_TDAT_TCLAN_TAIL_DESC_NOT_DDESC_EOP_NOP_S 2\n+#define GL_MDCK_TDAT_TCLAN_TAIL_DESC_NOT_DDESC_EOP_NOP_M BIT(2)\n+#define GL_MDCK_TDAT_TCLAN_FALSE_SCHEDULING_S\t3\n+#define GL_MDCK_TDAT_TCLAN_FALSE_SCHEDULING_M\tBIT(3)\n+#define GL_MDCK_TDAT_TCLAN_TAIL_VALUE_BIGGER_THAN_RING_LEN_S 4\n+#define GL_MDCK_TDAT_TCLAN_TAIL_VALUE_BIGGER_THAN_RING_LEN_M BIT(4)\n+#define GL_MDCK_TDAT_TCLAN_MORE_THAN_8_DCMDS_IN_PKT_S 5\n+#define GL_MDCK_TDAT_TCLAN_MORE_THAN_8_DCMDS_IN_PKT_M BIT(5)\n+#define GL_MDCK_TDAT_TCLAN_NO_HEAD_UPDATE_IN_QUANTA_S 6\n+#define GL_MDCK_TDAT_TCLAN_NO_HEAD_UPDATE_IN_QUANTA_M BIT(6)\n+#define GL_MDCK_TDAT_TCLAN_PKT_LEN_NOT_LEGAL_S\t7\n+#define GL_MDCK_TDAT_TCLAN_PKT_LEN_NOT_LEGAL_M\tBIT(7)\n+#define GL_MDCK_TDAT_TCLAN_TSO_TLEN_NOT_COHERENT_WITH_SUM_BUFS_S 8\n+#define GL_MDCK_TDAT_TCLAN_TSO_TLEN_NOT_COHERENT_WITH_SUM_BUFS_M BIT(8)\n+#define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_S 9\n+#define GL_MDCK_TDAT_TCLAN_TSO_TAIL_REACHED_BEFORE_TLEN_END_M BIT(9)\n+#define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_S 10\n+#define GL_MDCK_TDAT_TCLAN_TSO_MORE_THAN_3_HDRS_M BIT(10)\n+#define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_S 11\n+#define GL_MDCK_TDAT_TCLAN_TSO_SUM_BUFFS_LT_SUM_HDRS_M BIT(11)\n+#define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_S 12\n+#define GL_MDCK_TDAT_TCLAN_TSO_ZERO_MSS_TLEN_HDRS_M BIT(12)\n+#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_S 13\n+#define GL_MDCK_TDAT_TCLAN_TSO_CTX_DESC_IPSEC_M BIT(13)\n+#define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_S 14\n+#define GL_MDCK_TDAT_TCLAN_SSO_COMS_NOT_WHOLE_PKT_NUM_IN_QUANTA_M BIT(14)\n+#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_S 15\n+#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_BYTES_EXCEED_PKTLEN_X_64_M BIT(15)\n+#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_S 16\n+#define GL_MDCK_TDAT_TCLAN_COMS_QUANTA_CMDS_EXCEED_M BIT(16)\n+#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_S 17\n+#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_LAST_LSO_QUANTA_M BIT(17)\n+#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_TLEN_S 18\n+#define GL_MDCK_TDAT_TCLAN_TSO_COMS_TSO_DESCS_TLEN_M BIT(18)\n+#define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_S 19\n+#define GL_MDCK_TDAT_TCLAN_TSO_COMS_QUANTA_FINISHED_TOO_EARLY_M BIT(19)\n+#define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_S 20\n+#define GL_MDCK_TDAT_TCLAN_COMS_NUM_PKTS_IN_QUANTA_M BIT(20)\n+#define GL_PPRS_SPARE_0\t\t\t\t0x000841A8 /* Reset Source: CORER */\n+#define GL_PPRS_SPARE_0_GL_PPRS_SPARE_S\t\t0\n+#define GL_PPRS_SPARE_0_GL_PPRS_SPARE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PPRS_SPARE_1\t\t\t\t0x000851A8 /* Reset Source: CORER */\n+#define GL_PPRS_SPARE_1_GL_PPRS_SPARE_S\t\t0\n+#define GL_PPRS_SPARE_1_GL_PPRS_SPARE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PPRS_SPARE_2\t\t\t\t0x000861A8 /* Reset Source: CORER */\n+#define GL_PPRS_SPARE_2_GL_PPRS_SPARE_S\t\t0\n+#define GL_PPRS_SPARE_2_GL_PPRS_SPARE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PPRS_SPARE_3\t\t\t\t0x000871A8 /* Reset Source: CORER */\n+#define GL_PPRS_SPARE_3_GL_PPRS_SPARE_S\t\t0\n+#define GL_PPRS_SPARE_3_GL_PPRS_SPARE_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLCORE_CLKCTL_H\t\t\t\t0x000B81E8 /* Reset Source: POR */\n+#define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_S\t0\n+#define GLCORE_CLKCTL_H_UPPER_CLK_SRC_H_M\tMAKEMASK(0x3, 0)\n+#define GLCORE_CLKCTL_H_LOWER_CLK_SRC_H_S\t2\n+#define GLCORE_CLKCTL_H_LOWER_CLK_SRC_H_M\tMAKEMASK(0x3, 2)\n+#define GLCORE_CLKCTL_H_PSM_CLK_SRC_H_S\t\t4\n+#define GLCORE_CLKCTL_H_PSM_CLK_SRC_H_M\t\tMAKEMASK(0x3, 4)\n+#define GLCORE_CLKCTL_H_RXCTL_CLK_SRC_H_S\t6\n+#define GLCORE_CLKCTL_H_RXCTL_CLK_SRC_H_M\tMAKEMASK(0x3, 6)\n+#define GLCORE_CLKCTL_H_UANA_CLK_SRC_H_S\t8\n+#define GLCORE_CLKCTL_H_UANA_CLK_SRC_H_M\tMAKEMASK(0x7, 8)\n+#define GLCORE_CLKCTL_L\t\t\t\t0x000B8254 /* Reset Source: POR */\n+#define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_S\t0\n+#define GLCORE_CLKCTL_L_UPPER_CLK_SRC_L_M\tMAKEMASK(0x3, 0)\n+#define GLCORE_CLKCTL_L_LOWER_CLK_SRC_L_S\t2\n+#define GLCORE_CLKCTL_L_LOWER_CLK_SRC_L_M\tMAKEMASK(0x3, 2)\n+#define GLCORE_CLKCTL_L_PSM_CLK_SRC_L_S\t\t4\n+#define GLCORE_CLKCTL_L_PSM_CLK_SRC_L_M\t\tMAKEMASK(0x3, 4)\n+#define GLCORE_CLKCTL_L_RXCTL_CLK_SRC_L_S\t6\n+#define GLCORE_CLKCTL_L_RXCTL_CLK_SRC_L_M\tMAKEMASK(0x3, 6)\n+#define GLCORE_CLKCTL_L_UANA_CLK_SRC_L_S\t8\n+#define GLCORE_CLKCTL_L_UANA_CLK_SRC_L_M\tMAKEMASK(0x7, 8)\n+#define GLCORE_CLKCTL_M\t\t\t\t0x000B8258 /* Reset Source: POR */\n+#define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_S\t0\n+#define GLCORE_CLKCTL_M_UPPER_CLK_SRC_M_M\tMAKEMASK(0x3, 0)\n+#define GLCORE_CLKCTL_M_LOWER_CLK_SRC_M_S\t2\n+#define GLCORE_CLKCTL_M_LOWER_CLK_SRC_M_M\tMAKEMASK(0x3, 2)\n+#define GLCORE_CLKCTL_M_PSM_CLK_SRC_M_S\t\t4\n+#define GLCORE_CLKCTL_M_PSM_CLK_SRC_M_M\t\tMAKEMASK(0x3, 4)\n+#define GLCORE_CLKCTL_M_RXCTL_CLK_SRC_M_S\t6\n+#define GLCORE_CLKCTL_M_RXCTL_CLK_SRC_M_M\tMAKEMASK(0x3, 6)\n+#define GLCORE_CLKCTL_M_UANA_CLK_SRC_M_S\t8\n+#define GLCORE_CLKCTL_M_UANA_CLK_SRC_M_M\tMAKEMASK(0x7, 8)\n+#define GLFOC_CACHESIZE\t\t\t\t0x000AA074 /* Reset Source: CORER */\n+#define GLFOC_CACHESIZE_WORD_SIZE_S\t\t0\n+#define GLFOC_CACHESIZE_WORD_SIZE_M\t\tMAKEMASK(0xFF, 0)\n+#define GLFOC_CACHESIZE_SETS_S\t\t\t8\n+#define GLFOC_CACHESIZE_SETS_M\t\t\tMAKEMASK(0xFFF, 8)\n+#define GLFOC_CACHESIZE_WAYS_S\t\t\t20\n+#define GLFOC_CACHESIZE_WAYS_M\t\t\tMAKEMASK(0xF, 20)\n+#define GLGEN_CAR_DEBUG\t\t\t\t0x000B81C0 /* Reset Source: POR */\n+#define GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_S 0\n+#define GLGEN_CAR_DEBUG_CAR_UPPER_CORE_CLK_EN_M BIT(0)\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_S\t1\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_HIU_CLK_EN_M\tBIT(1)\n+#define GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_S\t\t2\n+#define GLGEN_CAR_DEBUG_CAR_PE_CLK_EN_M\t\tBIT(2)\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_S 3\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_PRIM_CLK_ACTIVE_M BIT(3)\n+#define GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_S\t\t4\n+#define GLGEN_CAR_DEBUG_CDC_PE_ACTIVE_M\t\tBIT(4)\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_S 5\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_PRST_RESET_N_M BIT(5)\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_S 6\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_SCLR_RESET_N_M BIT(6)\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_S 7\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IB_RESET_N_M BIT(7)\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_S 8\n+#define GLGEN_CAR_DEBUG_CAR_PCIE_RAW_IMIB_RESET_N_M BIT(8)\n+#define GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_S\t9\n+#define GLGEN_CAR_DEBUG_CAR_RAW_EMP_RESET_N_M\tBIT(9)\n+#define GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_S 10\n+#define GLGEN_CAR_DEBUG_CAR_RAW_GLOBAL_RESET_N_M BIT(10)\n+#define GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_S 11\n+#define GLGEN_CAR_DEBUG_CAR_RAW_LAN_POWER_GOOD_M BIT(11)\n+#define GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_S 12\n+#define GLGEN_CAR_DEBUG_CDC_IOSF_PRIMERY_RST_B_M BIT(12)\n+#define GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_S\t13\n+#define GLGEN_CAR_DEBUG_GBE_GLOBALRST_B_M\tBIT(13)\n+#define GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_S\t14\n+#define GLGEN_CAR_DEBUG_FLEEP_AL_GLOBR_DONE_M\tBIT(14)\n+#define GLGEN_CAR_DEBUG_CAR_RST_STATE_S\t\t15\n+#define GLGEN_CAR_DEBUG_CAR_RST_STATE_M\t\tMAKEMASK(0xF, 15)\n+#define GLGEN_CAR_SPARE\t\t\t\t0x000B81C4 /* Reset Source: POR */\n+#define GLGEN_CAR_SPARE_SPARE_CLEAR_S\t\t0\n+#define GLGEN_CAR_SPARE_SPARE_CLEAR_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GLGEN_CAR_SPARE_SPARE_SET_S\t\t16\n+#define GLGEN_CAR_SPARE_SPARE_SET_M\t\tMAKEMASK(0xFFFF, 16)\n+#define GLMAC_CLKSTAT\t\t\t\t0x000B8210 /* Reset Source: POR */\n+#define GLMAC_CLKSTAT_P0_CLK_SPEED_S\t\t0\n+#define GLMAC_CLKSTAT_P0_CLK_SPEED_M\t\tMAKEMASK(0xF, 0)\n+#define GLMAC_CLKSTAT_P1_CLK_SPEED_S\t\t4\n+#define GLMAC_CLKSTAT_P1_CLK_SPEED_M\t\tMAKEMASK(0xF, 4)\n+#define GLMAC_CLKSTAT_P2_CLK_SPEED_S\t\t8\n+#define GLMAC_CLKSTAT_P2_CLK_SPEED_M\t\tMAKEMASK(0xF, 8)\n+#define GLMAC_CLKSTAT_P3_CLK_SPEED_S\t\t12\n+#define GLMAC_CLKSTAT_P3_CLK_SPEED_M\t\tMAKEMASK(0xF, 12)\n+#define GLMAC_CLKSTAT_P4_CLK_SPEED_S\t\t16\n+#define GLMAC_CLKSTAT_P4_CLK_SPEED_M\t\tMAKEMASK(0xF, 16)\n+#define GLMAC_CLKSTAT_P5_CLK_SPEED_S\t\t20\n+#define GLMAC_CLKSTAT_P5_CLK_SPEED_M\t\tMAKEMASK(0xF, 20)\n+#define GLMAC_CLKSTAT_P6_CLK_SPEED_S\t\t24\n+#define GLMAC_CLKSTAT_P6_CLK_SPEED_M\t\tMAKEMASK(0xF, 24)\n+#define GLMAC_CLKSTAT_P7_CLK_SPEED_S\t\t28\n+#define GLMAC_CLKSTAT_P7_CLK_SPEED_M\t\tMAKEMASK(0xF, 28)\n+#define GLRCB_DCB_LAN_PMS\t\t\t0x001223F8 /* Reset Source: CORER */\n+#define GLRCB_DCB_LAN_PMS_PSM_LAN_S\t\t0\n+#define GLRCB_DCB_LAN_PMS_PSM_LAN_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLRCB_DCB_RDMA_PMS\t\t\t0x001223FC /* Reset Source: CORER */\n+#define GLRCB_DCB_RDMA_PMS_PSM_RDMA_S\t\t0\n+#define GLRCB_DCB_RDMA_PMS_PSM_RDMA_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLRLAN_MDET\t\t\t\t0x00294200 /* Reset Source: CORER */\n+#define GLRLAN_MDET_PCKT_EXTRCT_ERR_S\t\t0\n+#define GLRLAN_MDET_PCKT_EXTRCT_ERR_M\t\tBIT(0)\n+#define GLTPB_100G_MAC_FC_THRESH\t\t0x00099510 /* Reset Source: CORER */\n+#define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_S 0\n+#define GLTPB_100G_MAC_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_S 16\n+#define GLTPB_100G_MAC_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define GLTPB_100G_RPB_FC_THRESH\t\t0x0009963C /* Reset Source: CORER */\n+#define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_S 0\n+#define GLTPB_100G_RPB_FC_THRESH_PORT0_FC_THRESH_M MAKEMASK(0xFFFF, 0)\n+#define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_S 16\n+#define GLTPB_100G_RPB_FC_THRESH_PORT1_FC_THRESH_M MAKEMASK(0xFFFF, 16)\n+#define GLTPB_PACING_10G\t\t\t0x000994E4 /* Reset Source: CORER */\n+#define GLTPB_PACING_10G_N_S\t\t\t0\n+#define GLTPB_PACING_10G_N_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLTPB_PACING_10G_K_S\t\t\t8\n+#define GLTPB_PACING_10G_K_M\t\t\tMAKEMASK(0xFF, 8)\n+#define GLTPB_PACING_10G_S_S\t\t\t16\n+#define GLTPB_PACING_10G_S_M\t\t\tMAKEMASK(0x1FF, 16)\n+#define GLTPB_PACING_25G\t\t\t0x000994E0 /* Reset Source: CORER */\n+#define GLTPB_PACING_25G_N_S\t\t\t0\n+#define GLTPB_PACING_25G_N_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLTPB_PACING_25G_K_S\t\t\t8\n+#define GLTPB_PACING_25G_K_M\t\t\tMAKEMASK(0xFF, 8)\n+#define GLTPB_PACING_25G_S_S\t\t\t16\n+#define GLTPB_PACING_25G_S_M\t\t\tMAKEMASK(0x1FF, 16)\n+#define GLTPB_PORT_PACING_SPEED\t\t\t0x000994E8 /* Reset Source: CORER */\n+#define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_S\t0\n+#define GLTPB_PORT_PACING_SPEED_PORT0_SPEED_M\tBIT(0)\n+#define GLTPB_PORT_PACING_SPEED_PORT1_SPEED_S\t1\n+#define GLTPB_PORT_PACING_SPEED_PORT1_SPEED_M\tBIT(1)\n+#define GLTPB_PORT_PACING_SPEED_PORT2_SPEED_S\t2\n+#define GLTPB_PORT_PACING_SPEED_PORT2_SPEED_M\tBIT(2)\n+#define GLTPB_PORT_PACING_SPEED_PORT3_SPEED_S\t3\n+#define GLTPB_PORT_PACING_SPEED_PORT3_SPEED_M\tBIT(3)\n+#define GLTPB_PORT_PACING_SPEED_PORT4_SPEED_S\t4\n+#define GLTPB_PORT_PACING_SPEED_PORT4_SPEED_M\tBIT(4)\n+#define GLTPB_PORT_PACING_SPEED_PORT5_SPEED_S\t5\n+#define GLTPB_PORT_PACING_SPEED_PORT5_SPEED_M\tBIT(5)\n+#define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_S\t6\n+#define GLTPB_PORT_PACING_SPEED_PORT6_SPEED_M\tBIT(6)\n+#define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_S\t7\n+#define GLTPB_PORT_PACING_SPEED_PORT7_SPEED_M\tBIT(7)\n+#define GLTSYN_HH_DBG\t\t\t\t0x000889F0 /* Reset Source: CORER */\n+#define GLTSYN_HH_DBG_HH_SYNC_S\t\t\t0\n+#define GLTSYN_HH_DBG_HH_SYNC_M\t\t\tBIT(0)\n+#define GLTSYN_HH_DBG_HH_LATCH_EN_S\t\t1\n+#define GLTSYN_HH_DBG_HH_LATCH_EN_M\t\tBIT(1)\n+#define TPB_CFG_SCHEDULED_BC_THRESHOLD\t\t0x00099494 /* Reset Source: CORER */\n+#define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_S 0\n+#define TPB_CFG_SCHEDULED_BC_THRESHOLD_THRESHOLD_M MAKEMASK(0x7FFF, 0)\n+#define GL_UFUSE_SOC\t\t\t\t0x000A400C /* Reset Source: POR */\n+#define GL_UFUSE_SOC_PORT_MODE_S\t\t0\n+#define GL_UFUSE_SOC_PORT_MODE_M\t\tMAKEMASK(0x3, 0)\n+#define GL_UFUSE_SOC_BANDWIDTH_S\t\t2\n+#define GL_UFUSE_SOC_BANDWIDTH_M\t\tMAKEMASK(0x3, 2)\n+#define GL_UFUSE_SOC_PE_DISABLE_S\t\t4\n+#define GL_UFUSE_SOC_PE_DISABLE_M\t\tBIT(4)\n+#define GL_UFUSE_SOC_SWITCH_MODE_S\t\t5\n+#define GL_UFUSE_SOC_SWITCH_MODE_M\t\tBIT(5)\n+#define GL_UFUSE_SOC_CSR_PROTECTION_ENABLE_S\t6\n+#define GL_UFUSE_SOC_CSR_PROTECTION_ENABLE_M\tBIT(6)\n+#define GL_UFUSE_SOC_SERIAL_50G_S\t\t7\n+#define GL_UFUSE_SOC_SERIAL_50G_M\t\tBIT(7)\n+#define GL_UFUSE_SOC_NIC_ID_S\t\t\t8\n+#define GL_UFUSE_SOC_NIC_ID_M\t\t\tBIT(8)\n+#define GL_UFUSE_SOC_BLOCK_BME_TO_FW_S\t\t9\n+#define GL_UFUSE_SOC_BLOCK_BME_TO_FW_M\t\tBIT(9)\n+#define GL_UFUSE_SOC_SOC_TYPE_S\t\t\t10\n+#define GL_UFUSE_SOC_SOC_TYPE_M\t\t\tBIT(10)\n+#define GL_UFUSE_SOC_BTS_MODE_S\t\t\t11\n+#define GL_UFUSE_SOC_BTS_MODE_M\t\t\tBIT(11)\n+#define GL_UFUSE_SOC_SPARE_FUSES_S\t\t12\n+#define GL_UFUSE_SOC_SPARE_FUSES_M\t\tMAKEMASK(0xF, 12)\n+#define EMPINT_GPIO_ENA\t\t\t\t0x000880C0 /* Reset Source: POR */\n+#define EMPINT_GPIO_ENA_GPIO0_ENA_S\t\t0\n+#define EMPINT_GPIO_ENA_GPIO0_ENA_M\t\tBIT(0)\n+#define EMPINT_GPIO_ENA_GPIO1_ENA_S\t\t1\n+#define EMPINT_GPIO_ENA_GPIO1_ENA_M\t\tBIT(1)\n+#define EMPINT_GPIO_ENA_GPIO2_ENA_S\t\t2\n+#define EMPINT_GPIO_ENA_GPIO2_ENA_M\t\tBIT(2)\n+#define EMPINT_GPIO_ENA_GPIO3_ENA_S\t\t3\n+#define EMPINT_GPIO_ENA_GPIO3_ENA_M\t\tBIT(3)\n+#define EMPINT_GPIO_ENA_GPIO4_ENA_S\t\t4\n+#define EMPINT_GPIO_ENA_GPIO4_ENA_M\t\tBIT(4)\n+#define EMPINT_GPIO_ENA_GPIO5_ENA_S\t\t5\n+#define EMPINT_GPIO_ENA_GPIO5_ENA_M\t\tBIT(5)\n+#define EMPINT_GPIO_ENA_GPIO6_ENA_S\t\t6\n+#define EMPINT_GPIO_ENA_GPIO6_ENA_M\t\tBIT(6)\n+#define GL_CLKGEN_DEBUG\t\t\t\t0x000B8268 /* Reset Source: POR */\n+#define GL_CLKGEN_DEBUG_PROBE_S\t\t\t0\n+#define GL_CLKGEN_DEBUG_PROBE_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_CLKGEN_DEBUG_SEL\t\t\t0x000B8264 /* Reset Source: POR */\n+#define GL_CLKGEN_DEBUG_SEL_GL_CLKGEN_DEBUG_SEL_S 0\n+#define GL_CLKGEN_DEBUG_SEL_GL_CLKGEN_DEBUG_SEL_M MAKEMASK(0xFFFF, 0)\n+#define GLGEN_MAC_LINK_TOPO\t\t\t0x000B81DC /* Reset Source: GLOBR */\n+#define GLGEN_MAC_LINK_TOPO_LINK_TOPO_S\t\t0\n+#define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M\t\tMAKEMASK(0x3, 0)\n+#define GLINT_CEQCTL(_INT)\t\t\t(0x0015C000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define GLINT_CEQCTL_MAX_INDEX\t\t\t2047\n+#define GLINT_CEQCTL_MSIX_INDX_S\t\t0\n+#define GLINT_CEQCTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define GLINT_CEQCTL_ITR_INDX_S\t\t\t11\n+#define GLINT_CEQCTL_ITR_INDX_M\t\t\tMAKEMASK(0x3, 11)\n+#define GLINT_CEQCTL_CAUSE_ENA_S\t\t30\n+#define GLINT_CEQCTL_CAUSE_ENA_M\t\tBIT(30)\n+#define GLINT_CEQCTL_INTEVENT_S\t\t\t31\n+#define GLINT_CEQCTL_INTEVENT_M\t\t\tBIT(31)\n+#define GLINT_CTL\t\t\t\t0x0016CC54 /* Reset Source: CORER */\n+#define GLINT_CTL_DIS_AUTOMASK_S\t\t0\n+#define GLINT_CTL_DIS_AUTOMASK_M\t\tBIT(0)\n+#define GLINT_CTL_RSVD_S\t\t\t1\n+#define GLINT_CTL_RSVD_M\t\t\tMAKEMASK(0x7FFF, 1)\n+#define GLINT_CTL_ITR_GRAN_200_S\t\t16\n+#define GLINT_CTL_ITR_GRAN_200_M\t\tMAKEMASK(0xF, 16)\n+#define GLINT_CTL_ITR_GRAN_100_S\t\t20\n+#define GLINT_CTL_ITR_GRAN_100_M\t\tMAKEMASK(0xF, 20)\n+#define GLINT_CTL_ITR_GRAN_50_S\t\t\t24\n+#define GLINT_CTL_ITR_GRAN_50_M\t\t\tMAKEMASK(0xF, 24)\n+#define GLINT_CTL_ITR_GRAN_25_S\t\t\t28\n+#define GLINT_CTL_ITR_GRAN_25_M\t\t\tMAKEMASK(0xF, 28)\n+#define GLINT_DYN_CTL(_INT)\t\t\t(0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: PFR */\n+#define GLINT_DYN_CTL_MAX_INDEX\t\t\t2047\n+#define GLINT_DYN_CTL_INTENA_S\t\t\t0\n+#define GLINT_DYN_CTL_INTENA_M\t\t\tBIT(0)\n+#define GLINT_DYN_CTL_CLEARPBA_S\t\t1\n+#define GLINT_DYN_CTL_CLEARPBA_M\t\tBIT(1)\n+#define GLINT_DYN_CTL_SWINT_TRIG_S\t\t2\n+#define GLINT_DYN_CTL_SWINT_TRIG_M\t\tBIT(2)\n+#define GLINT_DYN_CTL_ITR_INDX_S\t\t3\n+#define GLINT_DYN_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 3)\n+#define GLINT_DYN_CTL_INTERVAL_S\t\t5\n+#define GLINT_DYN_CTL_INTERVAL_M\t\tMAKEMASK(0xFFF, 5)\n+#define GLINT_DYN_CTL_SW_ITR_INDX_ENA_S\t\t24\n+#define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M\t\tBIT(24)\n+#define GLINT_DYN_CTL_SW_ITR_INDX_S\t\t25\n+#define GLINT_DYN_CTL_SW_ITR_INDX_M\t\tMAKEMASK(0x3, 25)\n+#define GLINT_DYN_CTL_WB_ON_ITR_S\t\t30\n+#define GLINT_DYN_CTL_WB_ON_ITR_M\t\tBIT(30)\n+#define GLINT_DYN_CTL_INTENA_MSK_S\t\t31\n+#define GLINT_DYN_CTL_INTENA_MSK_M\t\tBIT(31)\n+#define GLINT_FW_TOOL_CTL\t\t\t0x0016C840 /* Reset Source: CORER */\n+#define GLINT_FW_TOOL_CTL_MSIX_INDX_S\t\t0\n+#define GLINT_FW_TOOL_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define GLINT_FW_TOOL_CTL_ITR_INDX_S\t\t11\n+#define GLINT_FW_TOOL_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define GLINT_FW_TOOL_CTL_CAUSE_ENA_S\t\t30\n+#define GLINT_FW_TOOL_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define GLINT_FW_TOOL_CTL_INTEVENT_S\t\t31\n+#define GLINT_FW_TOOL_CTL_INTEVENT_M\t\tBIT(31)\n+#define GLINT_ITR(_i, _INT)\t\t\t(0x00154000 + ((_i) * 8192 + (_INT) * 4)) /* _i=0...2, _INT=0...2047 */ /* Reset Source: PFR */\n+#define GLINT_ITR_MAX_INDEX\t\t\t2\n+#define GLINT_ITR_INTERVAL_S\t\t\t0\n+#define GLINT_ITR_INTERVAL_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define GLINT_RATE(_INT)\t\t\t(0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: PFR */\n+#define GLINT_RATE_MAX_INDEX\t\t\t2047\n+#define GLINT_RATE_INTERVAL_S\t\t\t0\n+#define GLINT_RATE_INTERVAL_M\t\t\tMAKEMASK(0x3F, 0)\n+#define GLINT_RATE_INTRL_ENA_S\t\t\t6\n+#define GLINT_RATE_INTRL_ENA_M\t\t\tBIT(6)\n+#define GLINT_TSYN_PFMSTR(_i)\t\t\t(0x0016CCC0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLINT_TSYN_PFMSTR_MAX_INDEX\t\t1\n+#define GLINT_TSYN_PFMSTR_PF_MASTER_S\t\t0\n+#define GLINT_TSYN_PFMSTR_PF_MASTER_M\t\tMAKEMASK(0x7, 0)\n+#define GLINT_TSYN_PHY\t\t\t\t0x0016CC50 /* Reset Source: CORER */\n+#define GLINT_TSYN_PHY_PHY_INDX_S\t\t0\n+#define GLINT_TSYN_PHY_PHY_INDX_M\t\tMAKEMASK(0x1F, 0)\n+#define GLINT_VECT2FUNC(_INT)\t\t\t(0x00162000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define GLINT_VECT2FUNC_MAX_INDEX\t\t2047\n+#define GLINT_VECT2FUNC_VF_NUM_S\t\t0\n+#define GLINT_VECT2FUNC_VF_NUM_M\t\tMAKEMASK(0xFF, 0)\n+#define GLINT_VECT2FUNC_PF_NUM_S\t\t12\n+#define GLINT_VECT2FUNC_PF_NUM_M\t\tMAKEMASK(0x7, 12)\n+#define GLINT_VECT2FUNC_IS_PF_S\t\t\t16\n+#define GLINT_VECT2FUNC_IS_PF_M\t\t\tBIT(16)\n+#define PF0INT_FW_HLP_CTL\t\t\t0x0016C844 /* Reset Source: CORER */\n+#define PF0INT_FW_HLP_CTL_MSIX_INDX_S\t\t0\n+#define PF0INT_FW_HLP_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_FW_HLP_CTL_ITR_INDX_S\t\t11\n+#define PF0INT_FW_HLP_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_FW_HLP_CTL_CAUSE_ENA_S\t\t30\n+#define PF0INT_FW_HLP_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_FW_HLP_CTL_INTEVENT_S\t\t31\n+#define PF0INT_FW_HLP_CTL_INTEVENT_M\t\tBIT(31)\n+#define PF0INT_FW_PSM_CTL\t\t\t0x0016C848 /* Reset Source: CORER */\n+#define PF0INT_FW_PSM_CTL_MSIX_INDX_S\t\t0\n+#define PF0INT_FW_PSM_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_FW_PSM_CTL_ITR_INDX_S\t\t11\n+#define PF0INT_FW_PSM_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_FW_PSM_CTL_CAUSE_ENA_S\t\t30\n+#define PF0INT_FW_PSM_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_FW_PSM_CTL_INTEVENT_S\t\t31\n+#define PF0INT_FW_PSM_CTL_INTEVENT_M\t\tBIT(31)\n+#define PF0INT_MBX_CPM_CTL\t\t\t0x0016B2C0 /* Reset Source: CORER */\n+#define PF0INT_MBX_CPM_CTL_MSIX_INDX_S\t\t0\n+#define PF0INT_MBX_CPM_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_MBX_CPM_CTL_ITR_INDX_S\t\t11\n+#define PF0INT_MBX_CPM_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_MBX_CPM_CTL_CAUSE_ENA_S\t\t30\n+#define PF0INT_MBX_CPM_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_MBX_CPM_CTL_INTEVENT_S\t\t31\n+#define PF0INT_MBX_CPM_CTL_INTEVENT_M\t\tBIT(31)\n+#define PF0INT_MBX_HLP_CTL\t\t\t0x0016B2C4 /* Reset Source: CORER */\n+#define PF0INT_MBX_HLP_CTL_MSIX_INDX_S\t\t0\n+#define PF0INT_MBX_HLP_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_MBX_HLP_CTL_ITR_INDX_S\t\t11\n+#define PF0INT_MBX_HLP_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_MBX_HLP_CTL_CAUSE_ENA_S\t\t30\n+#define PF0INT_MBX_HLP_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_MBX_HLP_CTL_INTEVENT_S\t\t31\n+#define PF0INT_MBX_HLP_CTL_INTEVENT_M\t\tBIT(31)\n+#define PF0INT_MBX_PSM_CTL\t\t\t0x0016B2C8 /* Reset Source: CORER */\n+#define PF0INT_MBX_PSM_CTL_MSIX_INDX_S\t\t0\n+#define PF0INT_MBX_PSM_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_MBX_PSM_CTL_ITR_INDX_S\t\t11\n+#define PF0INT_MBX_PSM_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_MBX_PSM_CTL_CAUSE_ENA_S\t\t30\n+#define PF0INT_MBX_PSM_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_MBX_PSM_CTL_INTEVENT_S\t\t31\n+#define PF0INT_MBX_PSM_CTL_INTEVENT_M\t\tBIT(31)\n+#define PF0INT_OICR_CPM\t\t\t\t0x0016CC40 /* Reset Source: CORER */\n+#define PF0INT_OICR_CPM_INTEVENT_S\t\t0\n+#define PF0INT_OICR_CPM_INTEVENT_M\t\tBIT(0)\n+#define PF0INT_OICR_CPM_QUEUE_S\t\t\t1\n+#define PF0INT_OICR_CPM_QUEUE_M\t\t\tBIT(1)\n+#define PF0INT_OICR_CPM_RSV1_S\t\t\t2\n+#define PF0INT_OICR_CPM_RSV1_M\t\t\tMAKEMASK(0xFF, 2)\n+#define PF0INT_OICR_CPM_HH_COMP_S\t\t10\n+#define PF0INT_OICR_CPM_HH_COMP_M\t\tBIT(10)\n+#define PF0INT_OICR_CPM_TSYN_TX_S\t\t11\n+#define PF0INT_OICR_CPM_TSYN_TX_M\t\tBIT(11)\n+#define PF0INT_OICR_CPM_TSYN_EVNT_S\t\t12\n+#define PF0INT_OICR_CPM_TSYN_EVNT_M\t\tBIT(12)\n+#define PF0INT_OICR_CPM_TSYN_TGT_S\t\t13\n+#define PF0INT_OICR_CPM_TSYN_TGT_M\t\tBIT(13)\n+#define PF0INT_OICR_CPM_HLP_RDY_S\t\t14\n+#define PF0INT_OICR_CPM_HLP_RDY_M\t\tBIT(14)\n+#define PF0INT_OICR_CPM_CPM_RDY_S\t\t15\n+#define PF0INT_OICR_CPM_CPM_RDY_M\t\tBIT(15)\n+#define PF0INT_OICR_CPM_ECC_ERR_S\t\t16\n+#define PF0INT_OICR_CPM_ECC_ERR_M\t\tBIT(16)\n+#define PF0INT_OICR_CPM_RSV2_S\t\t\t17\n+#define PF0INT_OICR_CPM_RSV2_M\t\t\tMAKEMASK(0x3, 17)\n+#define PF0INT_OICR_CPM_MAL_DETECT_S\t\t19\n+#define PF0INT_OICR_CPM_MAL_DETECT_M\t\tBIT(19)\n+#define PF0INT_OICR_CPM_GRST_S\t\t\t20\n+#define PF0INT_OICR_CPM_GRST_M\t\t\tBIT(20)\n+#define PF0INT_OICR_CPM_PCI_EXCEPTION_S\t\t21\n+#define PF0INT_OICR_CPM_PCI_EXCEPTION_M\t\tBIT(21)\n+#define PF0INT_OICR_CPM_GPIO_S\t\t\t22\n+#define PF0INT_OICR_CPM_GPIO_M\t\t\tBIT(22)\n+#define PF0INT_OICR_CPM_RSV3_S\t\t\t23\n+#define PF0INT_OICR_CPM_RSV3_M\t\t\tBIT(23)\n+#define PF0INT_OICR_CPM_STORM_DETECT_S\t\t24\n+#define PF0INT_OICR_CPM_STORM_DETECT_M\t\tBIT(24)\n+#define PF0INT_OICR_CPM_LINK_STAT_CHANGE_S\t25\n+#define PF0INT_OICR_CPM_LINK_STAT_CHANGE_M\tBIT(25)\n+#define PF0INT_OICR_CPM_HMC_ERR_S\t\t26\n+#define PF0INT_OICR_CPM_HMC_ERR_M\t\tBIT(26)\n+#define PF0INT_OICR_CPM_PE_PUSH_S\t\t27\n+#define PF0INT_OICR_CPM_PE_PUSH_M\t\tBIT(27)\n+#define PF0INT_OICR_CPM_PE_CRITERR_S\t\t28\n+#define PF0INT_OICR_CPM_PE_CRITERR_M\t\tBIT(28)\n+#define PF0INT_OICR_CPM_VFLR_S\t\t\t29\n+#define PF0INT_OICR_CPM_VFLR_M\t\t\tBIT(29)\n+#define PF0INT_OICR_CPM_XLR_HW_DONE_S\t\t30\n+#define PF0INT_OICR_CPM_XLR_HW_DONE_M\t\tBIT(30)\n+#define PF0INT_OICR_CPM_SWINT_S\t\t\t31\n+#define PF0INT_OICR_CPM_SWINT_M\t\t\tBIT(31)\n+#define PF0INT_OICR_CTL_CPM\t\t\t0x0016CC48 /* Reset Source: CORER */\n+#define PF0INT_OICR_CTL_CPM_MSIX_INDX_S\t\t0\n+#define PF0INT_OICR_CTL_CPM_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_OICR_CTL_CPM_ITR_INDX_S\t\t11\n+#define PF0INT_OICR_CTL_CPM_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_OICR_CTL_CPM_CAUSE_ENA_S\t\t30\n+#define PF0INT_OICR_CTL_CPM_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_OICR_CTL_CPM_INTEVENT_S\t\t31\n+#define PF0INT_OICR_CTL_CPM_INTEVENT_M\t\tBIT(31)\n+#define PF0INT_OICR_CTL_HLP\t\t\t0x0016CC5C /* Reset Source: CORER */\n+#define PF0INT_OICR_CTL_HLP_MSIX_INDX_S\t\t0\n+#define PF0INT_OICR_CTL_HLP_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_OICR_CTL_HLP_ITR_INDX_S\t\t11\n+#define PF0INT_OICR_CTL_HLP_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_OICR_CTL_HLP_CAUSE_ENA_S\t\t30\n+#define PF0INT_OICR_CTL_HLP_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_OICR_CTL_HLP_INTEVENT_S\t\t31\n+#define PF0INT_OICR_CTL_HLP_INTEVENT_M\t\tBIT(31)\n+#define PF0INT_OICR_CTL_PSM\t\t\t0x0016CC64 /* Reset Source: CORER */\n+#define PF0INT_OICR_CTL_PSM_MSIX_INDX_S\t\t0\n+#define PF0INT_OICR_CTL_PSM_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_OICR_CTL_PSM_ITR_INDX_S\t\t11\n+#define PF0INT_OICR_CTL_PSM_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_OICR_CTL_PSM_CAUSE_ENA_S\t\t30\n+#define PF0INT_OICR_CTL_PSM_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_OICR_CTL_PSM_INTEVENT_S\t\t31\n+#define PF0INT_OICR_CTL_PSM_INTEVENT_M\t\tBIT(31)\n+#define PF0INT_OICR_ENA_CPM\t\t\t0x0016CC60 /* Reset Source: CORER */\n+#define PF0INT_OICR_ENA_CPM_RSV0_S\t\t0\n+#define PF0INT_OICR_ENA_CPM_RSV0_M\t\tBIT(0)\n+#define PF0INT_OICR_ENA_CPM_INT_ENA_S\t\t1\n+#define PF0INT_OICR_ENA_CPM_INT_ENA_M\t\tMAKEMASK(0x7FFFFFFF, 1)\n+#define PF0INT_OICR_ENA_HLP\t\t\t0x0016CC4C /* Reset Source: CORER */\n+#define PF0INT_OICR_ENA_HLP_RSV0_S\t\t0\n+#define PF0INT_OICR_ENA_HLP_RSV0_M\t\tBIT(0)\n+#define PF0INT_OICR_ENA_HLP_INT_ENA_S\t\t1\n+#define PF0INT_OICR_ENA_HLP_INT_ENA_M\t\tMAKEMASK(0x7FFFFFFF, 1)\n+#define PF0INT_OICR_ENA_PSM\t\t\t0x0016CC58 /* Reset Source: CORER */\n+#define PF0INT_OICR_ENA_PSM_RSV0_S\t\t0\n+#define PF0INT_OICR_ENA_PSM_RSV0_M\t\tBIT(0)\n+#define PF0INT_OICR_ENA_PSM_INT_ENA_S\t\t1\n+#define PF0INT_OICR_ENA_PSM_INT_ENA_M\t\tMAKEMASK(0x7FFFFFFF, 1)\n+#define PF0INT_OICR_HLP\t\t\t\t0x0016CC68 /* Reset Source: CORER */\n+#define PF0INT_OICR_HLP_INTEVENT_S\t\t0\n+#define PF0INT_OICR_HLP_INTEVENT_M\t\tBIT(0)\n+#define PF0INT_OICR_HLP_QUEUE_S\t\t\t1\n+#define PF0INT_OICR_HLP_QUEUE_M\t\t\tBIT(1)\n+#define PF0INT_OICR_HLP_RSV1_S\t\t\t2\n+#define PF0INT_OICR_HLP_RSV1_M\t\t\tMAKEMASK(0xFF, 2)\n+#define PF0INT_OICR_HLP_HH_COMP_S\t\t10\n+#define PF0INT_OICR_HLP_HH_COMP_M\t\tBIT(10)\n+#define PF0INT_OICR_HLP_TSYN_TX_S\t\t11\n+#define PF0INT_OICR_HLP_TSYN_TX_M\t\tBIT(11)\n+#define PF0INT_OICR_HLP_TSYN_EVNT_S\t\t12\n+#define PF0INT_OICR_HLP_TSYN_EVNT_M\t\tBIT(12)\n+#define PF0INT_OICR_HLP_TSYN_TGT_S\t\t13\n+#define PF0INT_OICR_HLP_TSYN_TGT_M\t\tBIT(13)\n+#define PF0INT_OICR_HLP_HLP_RDY_S\t\t14\n+#define PF0INT_OICR_HLP_HLP_RDY_M\t\tBIT(14)\n+#define PF0INT_OICR_HLP_CPM_RDY_S\t\t15\n+#define PF0INT_OICR_HLP_CPM_RDY_M\t\tBIT(15)\n+#define PF0INT_OICR_HLP_ECC_ERR_S\t\t16\n+#define PF0INT_OICR_HLP_ECC_ERR_M\t\tBIT(16)\n+#define PF0INT_OICR_HLP_RSV2_S\t\t\t17\n+#define PF0INT_OICR_HLP_RSV2_M\t\t\tMAKEMASK(0x3, 17)\n+#define PF0INT_OICR_HLP_MAL_DETECT_S\t\t19\n+#define PF0INT_OICR_HLP_MAL_DETECT_M\t\tBIT(19)\n+#define PF0INT_OICR_HLP_GRST_S\t\t\t20\n+#define PF0INT_OICR_HLP_GRST_M\t\t\tBIT(20)\n+#define PF0INT_OICR_HLP_PCI_EXCEPTION_S\t\t21\n+#define PF0INT_OICR_HLP_PCI_EXCEPTION_M\t\tBIT(21)\n+#define PF0INT_OICR_HLP_GPIO_S\t\t\t22\n+#define PF0INT_OICR_HLP_GPIO_M\t\t\tBIT(22)\n+#define PF0INT_OICR_HLP_RSV3_S\t\t\t23\n+#define PF0INT_OICR_HLP_RSV3_M\t\t\tBIT(23)\n+#define PF0INT_OICR_HLP_STORM_DETECT_S\t\t24\n+#define PF0INT_OICR_HLP_STORM_DETECT_M\t\tBIT(24)\n+#define PF0INT_OICR_HLP_LINK_STAT_CHANGE_S\t25\n+#define PF0INT_OICR_HLP_LINK_STAT_CHANGE_M\tBIT(25)\n+#define PF0INT_OICR_HLP_HMC_ERR_S\t\t26\n+#define PF0INT_OICR_HLP_HMC_ERR_M\t\tBIT(26)\n+#define PF0INT_OICR_HLP_PE_PUSH_S\t\t27\n+#define PF0INT_OICR_HLP_PE_PUSH_M\t\tBIT(27)\n+#define PF0INT_OICR_HLP_PE_CRITERR_S\t\t28\n+#define PF0INT_OICR_HLP_PE_CRITERR_M\t\tBIT(28)\n+#define PF0INT_OICR_HLP_VFLR_S\t\t\t29\n+#define PF0INT_OICR_HLP_VFLR_M\t\t\tBIT(29)\n+#define PF0INT_OICR_HLP_XLR_HW_DONE_S\t\t30\n+#define PF0INT_OICR_HLP_XLR_HW_DONE_M\t\tBIT(30)\n+#define PF0INT_OICR_HLP_SWINT_S\t\t\t31\n+#define PF0INT_OICR_HLP_SWINT_M\t\t\tBIT(31)\n+#define PF0INT_OICR_PSM\t\t\t\t0x0016CC44 /* Reset Source: CORER */\n+#define PF0INT_OICR_PSM_INTEVENT_S\t\t0\n+#define PF0INT_OICR_PSM_INTEVENT_M\t\tBIT(0)\n+#define PF0INT_OICR_PSM_QUEUE_S\t\t\t1\n+#define PF0INT_OICR_PSM_QUEUE_M\t\t\tBIT(1)\n+#define PF0INT_OICR_PSM_RSV1_S\t\t\t2\n+#define PF0INT_OICR_PSM_RSV1_M\t\t\tMAKEMASK(0xFF, 2)\n+#define PF0INT_OICR_PSM_HH_COMP_S\t\t10\n+#define PF0INT_OICR_PSM_HH_COMP_M\t\tBIT(10)\n+#define PF0INT_OICR_PSM_TSYN_TX_S\t\t11\n+#define PF0INT_OICR_PSM_TSYN_TX_M\t\tBIT(11)\n+#define PF0INT_OICR_PSM_TSYN_EVNT_S\t\t12\n+#define PF0INT_OICR_PSM_TSYN_EVNT_M\t\tBIT(12)\n+#define PF0INT_OICR_PSM_TSYN_TGT_S\t\t13\n+#define PF0INT_OICR_PSM_TSYN_TGT_M\t\tBIT(13)\n+#define PF0INT_OICR_PSM_HLP_RDY_S\t\t14\n+#define PF0INT_OICR_PSM_HLP_RDY_M\t\tBIT(14)\n+#define PF0INT_OICR_PSM_CPM_RDY_S\t\t15\n+#define PF0INT_OICR_PSM_CPM_RDY_M\t\tBIT(15)\n+#define PF0INT_OICR_PSM_ECC_ERR_S\t\t16\n+#define PF0INT_OICR_PSM_ECC_ERR_M\t\tBIT(16)\n+#define PF0INT_OICR_PSM_RSV2_S\t\t\t17\n+#define PF0INT_OICR_PSM_RSV2_M\t\t\tMAKEMASK(0x3, 17)\n+#define PF0INT_OICR_PSM_MAL_DETECT_S\t\t19\n+#define PF0INT_OICR_PSM_MAL_DETECT_M\t\tBIT(19)\n+#define PF0INT_OICR_PSM_GRST_S\t\t\t20\n+#define PF0INT_OICR_PSM_GRST_M\t\t\tBIT(20)\n+#define PF0INT_OICR_PSM_PCI_EXCEPTION_S\t\t21\n+#define PF0INT_OICR_PSM_PCI_EXCEPTION_M\t\tBIT(21)\n+#define PF0INT_OICR_PSM_GPIO_S\t\t\t22\n+#define PF0INT_OICR_PSM_GPIO_M\t\t\tBIT(22)\n+#define PF0INT_OICR_PSM_RSV3_S\t\t\t23\n+#define PF0INT_OICR_PSM_RSV3_M\t\t\tBIT(23)\n+#define PF0INT_OICR_PSM_STORM_DETECT_S\t\t24\n+#define PF0INT_OICR_PSM_STORM_DETECT_M\t\tBIT(24)\n+#define PF0INT_OICR_PSM_LINK_STAT_CHANGE_S\t25\n+#define PF0INT_OICR_PSM_LINK_STAT_CHANGE_M\tBIT(25)\n+#define PF0INT_OICR_PSM_HMC_ERR_S\t\t26\n+#define PF0INT_OICR_PSM_HMC_ERR_M\t\tBIT(26)\n+#define PF0INT_OICR_PSM_PE_PUSH_S\t\t27\n+#define PF0INT_OICR_PSM_PE_PUSH_M\t\tBIT(27)\n+#define PF0INT_OICR_PSM_PE_CRITERR_S\t\t28\n+#define PF0INT_OICR_PSM_PE_CRITERR_M\t\tBIT(28)\n+#define PF0INT_OICR_PSM_VFLR_S\t\t\t29\n+#define PF0INT_OICR_PSM_VFLR_M\t\t\tBIT(29)\n+#define PF0INT_OICR_PSM_XLR_HW_DONE_S\t\t30\n+#define PF0INT_OICR_PSM_XLR_HW_DONE_M\t\tBIT(30)\n+#define PF0INT_OICR_PSM_SWINT_S\t\t\t31\n+#define PF0INT_OICR_PSM_SWINT_M\t\t\tBIT(31)\n+#define PF0INT_SB_CPM_CTL\t\t\t0x0016B2CC /* Reset Source: CORER */\n+#define PF0INT_SB_CPM_CTL_MSIX_INDX_S\t\t0\n+#define PF0INT_SB_CPM_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_SB_CPM_CTL_ITR_INDX_S\t\t11\n+#define PF0INT_SB_CPM_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_SB_CPM_CTL_CAUSE_ENA_S\t\t30\n+#define PF0INT_SB_CPM_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_SB_CPM_CTL_INTEVENT_S\t\t31\n+#define PF0INT_SB_CPM_CTL_INTEVENT_M\t\tBIT(31)\n+#define PF0INT_SB_HLP_CTL\t\t\t0x0016B640 /* Reset Source: CORER */\n+#define PF0INT_SB_HLP_CTL_MSIX_INDX_S\t\t0\n+#define PF0INT_SB_HLP_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PF0INT_SB_HLP_CTL_ITR_INDX_S\t\t11\n+#define PF0INT_SB_HLP_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PF0INT_SB_HLP_CTL_CAUSE_ENA_S\t\t30\n+#define PF0INT_SB_HLP_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PF0INT_SB_HLP_CTL_INTEVENT_S\t\t31\n+#define PF0INT_SB_HLP_CTL_INTEVENT_M\t\tBIT(31)\n+#define PFINT_AEQCTL\t\t\t\t0x0016CB00 /* Reset Source: CORER */\n+#define PFINT_AEQCTL_MSIX_INDX_S\t\t0\n+#define PFINT_AEQCTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PFINT_AEQCTL_ITR_INDX_S\t\t\t11\n+#define PFINT_AEQCTL_ITR_INDX_M\t\t\tMAKEMASK(0x3, 11)\n+#define PFINT_AEQCTL_CAUSE_ENA_S\t\t30\n+#define PFINT_AEQCTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PFINT_AEQCTL_INTEVENT_S\t\t\t31\n+#define PFINT_AEQCTL_INTEVENT_M\t\t\tBIT(31)\n+#define PFINT_ALLOC\t\t\t\t0x001D2600 /* Reset Source: CORER */\n+#define PFINT_ALLOC_FIRST_S\t\t\t0\n+#define PFINT_ALLOC_FIRST_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define PFINT_ALLOC_LAST_S\t\t\t12\n+#define PFINT_ALLOC_LAST_M\t\t\tMAKEMASK(0x7FF, 12)\n+#define PFINT_ALLOC_VALID_S\t\t\t31\n+#define PFINT_ALLOC_VALID_M\t\t\tBIT(31)\n+#define PFINT_ALLOC_PCI\t\t\t\t0x0009D800 /* Reset Source: PCIR */\n+#define PFINT_ALLOC_PCI_FIRST_S\t\t\t0\n+#define PFINT_ALLOC_PCI_FIRST_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define PFINT_ALLOC_PCI_LAST_S\t\t\t12\n+#define PFINT_ALLOC_PCI_LAST_M\t\t\tMAKEMASK(0x7FF, 12)\n+#define PFINT_ALLOC_PCI_VALID_S\t\t\t31\n+#define PFINT_ALLOC_PCI_VALID_M\t\t\tBIT(31)\n+#define PFINT_FW_CTL\t\t\t\t0x0016C800 /* Reset Source: CORER */\n+#define PFINT_FW_CTL_MSIX_INDX_S\t\t0\n+#define PFINT_FW_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PFINT_FW_CTL_ITR_INDX_S\t\t\t11\n+#define PFINT_FW_CTL_ITR_INDX_M\t\t\tMAKEMASK(0x3, 11)\n+#define PFINT_FW_CTL_CAUSE_ENA_S\t\t30\n+#define PFINT_FW_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PFINT_FW_CTL_INTEVENT_S\t\t\t31\n+#define PFINT_FW_CTL_INTEVENT_M\t\t\tBIT(31)\n+#define PFINT_GPIO_ENA\t\t\t\t0x00088080 /* Reset Source: CORER */\n+#define PFINT_GPIO_ENA_GPIO0_ENA_S\t\t0\n+#define PFINT_GPIO_ENA_GPIO0_ENA_M\t\tBIT(0)\n+#define PFINT_GPIO_ENA_GPIO1_ENA_S\t\t1\n+#define PFINT_GPIO_ENA_GPIO1_ENA_M\t\tBIT(1)\n+#define PFINT_GPIO_ENA_GPIO2_ENA_S\t\t2\n+#define PFINT_GPIO_ENA_GPIO2_ENA_M\t\tBIT(2)\n+#define PFINT_GPIO_ENA_GPIO3_ENA_S\t\t3\n+#define PFINT_GPIO_ENA_GPIO3_ENA_M\t\tBIT(3)\n+#define PFINT_GPIO_ENA_GPIO4_ENA_S\t\t4\n+#define PFINT_GPIO_ENA_GPIO4_ENA_M\t\tBIT(4)\n+#define PFINT_GPIO_ENA_GPIO5_ENA_S\t\t5\n+#define PFINT_GPIO_ENA_GPIO5_ENA_M\t\tBIT(5)\n+#define PFINT_GPIO_ENA_GPIO6_ENA_S\t\t6\n+#define PFINT_GPIO_ENA_GPIO6_ENA_M\t\tBIT(6)\n+#define PFINT_MBX_CTL\t\t\t\t0x0016B280 /* Reset Source: CORER */\n+#define PFINT_MBX_CTL_MSIX_INDX_S\t\t0\n+#define PFINT_MBX_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PFINT_MBX_CTL_ITR_INDX_S\t\t11\n+#define PFINT_MBX_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PFINT_MBX_CTL_CAUSE_ENA_S\t\t30\n+#define PFINT_MBX_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PFINT_MBX_CTL_INTEVENT_S\t\t31\n+#define PFINT_MBX_CTL_INTEVENT_M\t\tBIT(31)\n+#define PFINT_OICR\t\t\t\t0x0016CA00 /* Reset Source: CORER */\n+#define PFINT_OICR_INTEVENT_S\t\t\t0\n+#define PFINT_OICR_INTEVENT_M\t\t\tBIT(0)\n+#define PFINT_OICR_QUEUE_S\t\t\t1\n+#define PFINT_OICR_QUEUE_M\t\t\tBIT(1)\n+#define PFINT_OICR_RSV1_S\t\t\t2\n+#define PFINT_OICR_RSV1_M\t\t\tMAKEMASK(0xFF, 2)\n+#define PFINT_OICR_HH_COMP_S\t\t\t10\n+#define PFINT_OICR_HH_COMP_M\t\t\tBIT(10)\n+#define PFINT_OICR_TSYN_TX_S\t\t\t11\n+#define PFINT_OICR_TSYN_TX_M\t\t\tBIT(11)\n+#define PFINT_OICR_TSYN_EVNT_S\t\t\t12\n+#define PFINT_OICR_TSYN_EVNT_M\t\t\tBIT(12)\n+#define PFINT_OICR_TSYN_TGT_S\t\t\t13\n+#define PFINT_OICR_TSYN_TGT_M\t\t\tBIT(13)\n+#define PFINT_OICR_HLP_RDY_S\t\t\t14\n+#define PFINT_OICR_HLP_RDY_M\t\t\tBIT(14)\n+#define PFINT_OICR_CPM_RDY_S\t\t\t15\n+#define PFINT_OICR_CPM_RDY_M\t\t\tBIT(15)\n+#define PFINT_OICR_ECC_ERR_S\t\t\t16\n+#define PFINT_OICR_ECC_ERR_M\t\t\tBIT(16)\n+#define PFINT_OICR_RSV2_S\t\t\t17\n+#define PFINT_OICR_RSV2_M\t\t\tMAKEMASK(0x3, 17)\n+#define PFINT_OICR_MAL_DETECT_S\t\t\t19\n+#define PFINT_OICR_MAL_DETECT_M\t\t\tBIT(19)\n+#define PFINT_OICR_GRST_S\t\t\t20\n+#define PFINT_OICR_GRST_M\t\t\tBIT(20)\n+#define PFINT_OICR_PCI_EXCEPTION_S\t\t21\n+#define PFINT_OICR_PCI_EXCEPTION_M\t\tBIT(21)\n+#define PFINT_OICR_GPIO_S\t\t\t22\n+#define PFINT_OICR_GPIO_M\t\t\tBIT(22)\n+#define PFINT_OICR_RSV3_S\t\t\t23\n+#define PFINT_OICR_RSV3_M\t\t\tBIT(23)\n+#define PFINT_OICR_STORM_DETECT_S\t\t24\n+#define PFINT_OICR_STORM_DETECT_M\t\tBIT(24)\n+#define PFINT_OICR_LINK_STAT_CHANGE_S\t\t25\n+#define PFINT_OICR_LINK_STAT_CHANGE_M\t\tBIT(25)\n+#define PFINT_OICR_HMC_ERR_S\t\t\t26\n+#define PFINT_OICR_HMC_ERR_M\t\t\tBIT(26)\n+#define PFINT_OICR_PE_PUSH_S\t\t\t27\n+#define PFINT_OICR_PE_PUSH_M\t\t\tBIT(27)\n+#define PFINT_OICR_PE_CRITERR_S\t\t\t28\n+#define PFINT_OICR_PE_CRITERR_M\t\t\tBIT(28)\n+#define PFINT_OICR_VFLR_S\t\t\t29\n+#define PFINT_OICR_VFLR_M\t\t\tBIT(29)\n+#define PFINT_OICR_XLR_HW_DONE_S\t\t30\n+#define PFINT_OICR_XLR_HW_DONE_M\t\tBIT(30)\n+#define PFINT_OICR_SWINT_S\t\t\t31\n+#define PFINT_OICR_SWINT_M\t\t\tBIT(31)\n+#define PFINT_OICR_CTL\t\t\t\t0x0016CA80 /* Reset Source: CORER */\n+#define PFINT_OICR_CTL_MSIX_INDX_S\t\t0\n+#define PFINT_OICR_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PFINT_OICR_CTL_ITR_INDX_S\t\t11\n+#define PFINT_OICR_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define PFINT_OICR_CTL_CAUSE_ENA_S\t\t30\n+#define PFINT_OICR_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PFINT_OICR_CTL_INTEVENT_S\t\t31\n+#define PFINT_OICR_CTL_INTEVENT_M\t\tBIT(31)\n+#define PFINT_OICR_ENA\t\t\t\t0x0016C900 /* Reset Source: CORER */\n+#define PFINT_OICR_ENA_RSV0_S\t\t\t0\n+#define PFINT_OICR_ENA_RSV0_M\t\t\tBIT(0)\n+#define PFINT_OICR_ENA_INT_ENA_S\t\t1\n+#define PFINT_OICR_ENA_INT_ENA_M\t\tMAKEMASK(0x7FFFFFFF, 1)\n+#define PFINT_SB_CTL\t\t\t\t0x0016B600 /* Reset Source: CORER */\n+#define PFINT_SB_CTL_MSIX_INDX_S\t\t0\n+#define PFINT_SB_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define PFINT_SB_CTL_ITR_INDX_S\t\t\t11\n+#define PFINT_SB_CTL_ITR_INDX_M\t\t\tMAKEMASK(0x3, 11)\n+#define PFINT_SB_CTL_CAUSE_ENA_S\t\t30\n+#define PFINT_SB_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define PFINT_SB_CTL_INTEVENT_S\t\t\t31\n+#define PFINT_SB_CTL_INTEVENT_M\t\t\tBIT(31)\n+#define PFINT_TSYN_MSK\t\t\t\t0x0016C980 /* Reset Source: CORER */\n+#define PFINT_TSYN_MSK_PHY_INDX_S\t\t0\n+#define PFINT_TSYN_MSK_PHY_INDX_M\t\tMAKEMASK(0x1F, 0)\n+#define QINT_RQCTL(_QRX)\t\t\t(0x00150000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define QINT_RQCTL_MAX_INDEX\t\t\t2047\n+#define QINT_RQCTL_MSIX_INDX_S\t\t\t0\n+#define QINT_RQCTL_MSIX_INDX_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define QINT_RQCTL_ITR_INDX_S\t\t\t11\n+#define QINT_RQCTL_ITR_INDX_M\t\t\tMAKEMASK(0x3, 11)\n+#define QINT_RQCTL_CAUSE_ENA_S\t\t\t30\n+#define QINT_RQCTL_CAUSE_ENA_M\t\t\tBIT(30)\n+#define QINT_RQCTL_INTEVENT_S\t\t\t31\n+#define QINT_RQCTL_INTEVENT_M\t\t\tBIT(31)\n+#define QINT_TQCTL(_DBQM)\t\t\t(0x00140000 + ((_DBQM) * 4)) /* _i=0...16383 */ /* Reset Source: CORER */\n+#define QINT_TQCTL_MAX_INDEX\t\t\t16383\n+#define QINT_TQCTL_MSIX_INDX_S\t\t\t0\n+#define QINT_TQCTL_MSIX_INDX_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define QINT_TQCTL_ITR_INDX_S\t\t\t11\n+#define QINT_TQCTL_ITR_INDX_M\t\t\tMAKEMASK(0x3, 11)\n+#define QINT_TQCTL_CAUSE_ENA_S\t\t\t30\n+#define QINT_TQCTL_CAUSE_ENA_M\t\t\tBIT(30)\n+#define QINT_TQCTL_INTEVENT_S\t\t\t31\n+#define QINT_TQCTL_INTEVENT_M\t\t\tBIT(31)\n+#define VPINT_AEQCTL(_VF)\t\t\t(0x0016B800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPINT_AEQCTL_MAX_INDEX\t\t\t255\n+#define VPINT_AEQCTL_MSIX_INDX_S\t\t0\n+#define VPINT_AEQCTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define VPINT_AEQCTL_ITR_INDX_S\t\t\t11\n+#define VPINT_AEQCTL_ITR_INDX_M\t\t\tMAKEMASK(0x3, 11)\n+#define VPINT_AEQCTL_CAUSE_ENA_S\t\t30\n+#define VPINT_AEQCTL_CAUSE_ENA_M\t\tBIT(30)\n+#define VPINT_AEQCTL_INTEVENT_S\t\t\t31\n+#define VPINT_AEQCTL_INTEVENT_M\t\t\tBIT(31)\n+#define VPINT_ALLOC(_VF)\t\t\t(0x001D1000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPINT_ALLOC_MAX_INDEX\t\t\t255\n+#define VPINT_ALLOC_FIRST_S\t\t\t0\n+#define VPINT_ALLOC_FIRST_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define VPINT_ALLOC_LAST_S\t\t\t12\n+#define VPINT_ALLOC_LAST_M\t\t\tMAKEMASK(0x7FF, 12)\n+#define VPINT_ALLOC_VALID_S\t\t\t31\n+#define VPINT_ALLOC_VALID_M\t\t\tBIT(31)\n+#define VPINT_ALLOC_PCI(_VF)\t\t\t(0x0009D000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */\n+#define VPINT_ALLOC_PCI_MAX_INDEX\t\t255\n+#define VPINT_ALLOC_PCI_FIRST_S\t\t\t0\n+#define VPINT_ALLOC_PCI_FIRST_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define VPINT_ALLOC_PCI_LAST_S\t\t\t12\n+#define VPINT_ALLOC_PCI_LAST_M\t\t\tMAKEMASK(0x7FF, 12)\n+#define VPINT_ALLOC_PCI_VALID_S\t\t\t31\n+#define VPINT_ALLOC_PCI_VALID_M\t\t\tBIT(31)\n+#define VPINT_MBX_CPM_CTL(_VP128)\t\t(0x0016B000 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VPINT_MBX_CPM_CTL_MAX_INDEX\t\t127\n+#define VPINT_MBX_CPM_CTL_MSIX_INDX_S\t\t0\n+#define VPINT_MBX_CPM_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define VPINT_MBX_CPM_CTL_ITR_INDX_S\t\t11\n+#define VPINT_MBX_CPM_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define VPINT_MBX_CPM_CTL_CAUSE_ENA_S\t\t30\n+#define VPINT_MBX_CPM_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define VPINT_MBX_CPM_CTL_INTEVENT_S\t\t31\n+#define VPINT_MBX_CPM_CTL_INTEVENT_M\t\tBIT(31)\n+#define VPINT_MBX_CTL(_VSI)\t\t\t(0x0016A000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VPINT_MBX_CTL_MAX_INDEX\t\t\t767\n+#define VPINT_MBX_CTL_MSIX_INDX_S\t\t0\n+#define VPINT_MBX_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define VPINT_MBX_CTL_ITR_INDX_S\t\t11\n+#define VPINT_MBX_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define VPINT_MBX_CTL_CAUSE_ENA_S\t\t30\n+#define VPINT_MBX_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define VPINT_MBX_CTL_INTEVENT_S\t\t31\n+#define VPINT_MBX_CTL_INTEVENT_M\t\tBIT(31)\n+#define VPINT_MBX_HLP_CTL(_VP16)\t\t(0x0016B200 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VPINT_MBX_HLP_CTL_MAX_INDEX\t\t15\n+#define VPINT_MBX_HLP_CTL_MSIX_INDX_S\t\t0\n+#define VPINT_MBX_HLP_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define VPINT_MBX_HLP_CTL_ITR_INDX_S\t\t11\n+#define VPINT_MBX_HLP_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define VPINT_MBX_HLP_CTL_CAUSE_ENA_S\t\t30\n+#define VPINT_MBX_HLP_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define VPINT_MBX_HLP_CTL_INTEVENT_S\t\t31\n+#define VPINT_MBX_HLP_CTL_INTEVENT_M\t\tBIT(31)\n+#define VPINT_MBX_PSM_CTL(_VP16)\t\t(0x0016B240 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VPINT_MBX_PSM_CTL_MAX_INDEX\t\t15\n+#define VPINT_MBX_PSM_CTL_MSIX_INDX_S\t\t0\n+#define VPINT_MBX_PSM_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define VPINT_MBX_PSM_CTL_ITR_INDX_S\t\t11\n+#define VPINT_MBX_PSM_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define VPINT_MBX_PSM_CTL_CAUSE_ENA_S\t\t30\n+#define VPINT_MBX_PSM_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define VPINT_MBX_PSM_CTL_INTEVENT_S\t\t31\n+#define VPINT_MBX_PSM_CTL_INTEVENT_M\t\tBIT(31)\n+#define VPINT_SB_CPM_CTL(_VP128)\t\t(0x0016B400 + ((_VP128) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define VPINT_SB_CPM_CTL_MAX_INDEX\t\t127\n+#define VPINT_SB_CPM_CTL_MSIX_INDX_S\t\t0\n+#define VPINT_SB_CPM_CTL_MSIX_INDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define VPINT_SB_CPM_CTL_ITR_INDX_S\t\t11\n+#define VPINT_SB_CPM_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 11)\n+#define VPINT_SB_CPM_CTL_CAUSE_ENA_S\t\t30\n+#define VPINT_SB_CPM_CTL_CAUSE_ENA_M\t\tBIT(30)\n+#define VPINT_SB_CPM_CTL_INTEVENT_S\t\t31\n+#define VPINT_SB_CPM_CTL_INTEVENT_M\t\tBIT(31)\n+#define GL_HLP_PRT_IPG_PREAMBLE_SIZE(_i)\t(0x00049240 + ((_i) * 4)) /* _i=0...20 */ /* Reset Source: CORER */\n+#define GL_HLP_PRT_IPG_PREAMBLE_SIZE_MAX_INDEX\t20\n+#define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_S 0\n+#define GL_HLP_PRT_IPG_PREAMBLE_SIZE_IPG_PREAMBLE_SIZE_M MAKEMASK(0xFF, 0)\n+#define GL_TDPU_PSM_DEFAULT_RECIPE(_i)\t\t(0x00049294 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_MAX_INDEX\t3\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_S\t0\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_ADD_IPG_M\tBIT(0)\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_CRC_S\t1\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_CRC_M\tBIT(1)\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_ESP_TRAILER_S 2\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_SUB_ESP_TRAILER_M BIT(2)\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_INCLUDE_L2_PAD_S 3\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_INCLUDE_L2_PAD_M BIT(3)\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_DEFAULT_UPDATE_MODE_S 4\n+#define GL_TDPU_PSM_DEFAULT_RECIPE_DEFAULT_UPDATE_MODE_M BIT(4)\n+#define GLLAN_PF_RECIPE(_i)\t\t\t(0x0029420C + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLLAN_PF_RECIPE_MAX_INDEX\t\t7\n+#define GLLAN_PF_RECIPE_RECIPE_S\t\t0\n+#define GLLAN_PF_RECIPE_RECIPE_M\t\tMAKEMASK(0x3, 0)\n+#define GLLAN_RCTL_0\t\t\t\t0x002941F8 /* Reset Source: CORER */\n+#define GLLAN_RCTL_0_PXE_MODE_S\t\t\t0\n+#define GLLAN_RCTL_0_PXE_MODE_M\t\t\tBIT(0)\n+#define GLLAN_RCTL_1\t\t\t\t0x002941FC /* Reset Source: CORER */\n+#define GLLAN_RCTL_1_RXMAX_EXPANSION_S\t\t12\n+#define GLLAN_RCTL_1_RXMAX_EXPANSION_M\t\tMAKEMASK(0xF, 12)\n+#define GLLAN_RCTL_1_RXDRDCTL_S\t\t\t17\n+#define GLLAN_RCTL_1_RXDRDCTL_M\t\t\tBIT(17)\n+#define GLLAN_RCTL_1_RXDESCRDROEN_S\t\t18\n+#define GLLAN_RCTL_1_RXDESCRDROEN_M\t\tBIT(18)\n+#define GLLAN_RCTL_1_RXDATAWRROEN_S\t\t19\n+#define GLLAN_RCTL_1_RXDATAWRROEN_M\t\tBIT(19)\n+#define GLLAN_TSOMSK_F\t\t\t\t0x00049308 /* Reset Source: CORER */\n+#define GLLAN_TSOMSK_F_TCPMSKF_S\t\t0\n+#define GLLAN_TSOMSK_F_TCPMSKF_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLLAN_TSOMSK_L\t\t\t\t0x00049310 /* Reset Source: CORER */\n+#define GLLAN_TSOMSK_L_TCPMSKL_S\t\t0\n+#define GLLAN_TSOMSK_L_TCPMSKL_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLLAN_TSOMSK_M\t\t\t\t0x0004930C /* Reset Source: CORER */\n+#define GLLAN_TSOMSK_M_TCPMSKM_S\t\t0\n+#define GLLAN_TSOMSK_M_TCPMSKM_M\t\tMAKEMASK(0xFFF, 0)\n+#define PFLAN_CP_QALLOC\t\t\t\t0x00075700 /* Reset Source: CORER */\n+#define PFLAN_CP_QALLOC_FIRSTQ_S\t\t0\n+#define PFLAN_CP_QALLOC_FIRSTQ_M\t\tMAKEMASK(0x1FF, 0)\n+#define PFLAN_CP_QALLOC_LASTQ_S\t\t\t16\n+#define PFLAN_CP_QALLOC_LASTQ_M\t\t\tMAKEMASK(0x1FF, 16)\n+#define PFLAN_CP_QALLOC_VALID_S\t\t\t31\n+#define PFLAN_CP_QALLOC_VALID_M\t\t\tBIT(31)\n+#define PFLAN_DB_QALLOC\t\t\t\t0x00075680 /* Reset Source: CORER */\n+#define PFLAN_DB_QALLOC_FIRSTQ_S\t\t0\n+#define PFLAN_DB_QALLOC_FIRSTQ_M\t\tMAKEMASK(0xFF, 0)\n+#define PFLAN_DB_QALLOC_LASTQ_S\t\t\t16\n+#define PFLAN_DB_QALLOC_LASTQ_M\t\t\tMAKEMASK(0xFF, 16)\n+#define PFLAN_DB_QALLOC_VALID_S\t\t\t31\n+#define PFLAN_DB_QALLOC_VALID_M\t\t\tBIT(31)\n+#define PFLAN_RX_QALLOC\t\t\t\t0x001D2500 /* Reset Source: CORER */\n+#define PFLAN_RX_QALLOC_FIRSTQ_S\t\t0\n+#define PFLAN_RX_QALLOC_FIRSTQ_M\t\tMAKEMASK(0x7FF, 0)\n+#define PFLAN_RX_QALLOC_LASTQ_S\t\t\t16\n+#define PFLAN_RX_QALLOC_LASTQ_M\t\t\tMAKEMASK(0x7FF, 16)\n+#define PFLAN_RX_QALLOC_VALID_S\t\t\t31\n+#define PFLAN_RX_QALLOC_VALID_M\t\t\tBIT(31)\n+#define PFLAN_TX_QALLOC\t\t\t\t0x001D2580 /* Reset Source: CORER */\n+#define PFLAN_TX_QALLOC_FIRSTQ_S\t\t0\n+#define PFLAN_TX_QALLOC_FIRSTQ_M\t\tMAKEMASK(0x3FFF, 0)\n+#define PFLAN_TX_QALLOC_LASTQ_S\t\t\t16\n+#define PFLAN_TX_QALLOC_LASTQ_M\t\t\tMAKEMASK(0x3FFF, 16)\n+#define PFLAN_TX_QALLOC_VALID_S\t\t\t31\n+#define PFLAN_TX_QALLOC_VALID_M\t\t\tBIT(31)\n+#define QRX_CONTEXT(_i, _QRX)\t\t\t(0x00280000 + ((_i) * 8192 + (_QRX) * 4)) /* _i=0...7, _QRX=0...2047 */ /* Reset Source: CORER */\n+#define QRX_CONTEXT_MAX_INDEX\t\t\t7\n+#define QRX_CONTEXT_RXQ_CONTEXT_S\t\t0\n+#define QRX_CONTEXT_RXQ_CONTEXT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define QRX_CTRL(_QRX)\t\t\t\t(0x00120000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: PFR */\n+#define QRX_CTRL_MAX_INDEX\t\t\t2047\n+#define QRX_CTRL_QENA_REQ_S\t\t\t0\n+#define QRX_CTRL_QENA_REQ_M\t\t\tBIT(0)\n+#define QRX_CTRL_FAST_QDIS_S\t\t\t1\n+#define QRX_CTRL_FAST_QDIS_M\t\t\tBIT(1)\n+#define QRX_CTRL_QENA_STAT_S\t\t\t2\n+#define QRX_CTRL_QENA_STAT_M\t\t\tBIT(2)\n+#define QRX_CTRL_CDE_S\t\t\t\t3\n+#define QRX_CTRL_CDE_M\t\t\t\tBIT(3)\n+#define QRX_CTRL_CDS_S\t\t\t\t4\n+#define QRX_CTRL_CDS_M\t\t\t\tBIT(4)\n+#define QRX_ITR(_QRX)\t\t\t\t(0x00292000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define QRX_ITR_MAX_INDEX\t\t\t2047\n+#define QRX_ITR_NO_EXPR_S\t\t\t0\n+#define QRX_ITR_NO_EXPR_M\t\t\tBIT(0)\n+#define QRX_TAIL(_QRX)\t\t\t\t(0x00290000 + ((_QRX) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define QRX_TAIL_MAX_INDEX\t\t\t2047\n+#define QRX_TAIL_TAIL_S\t\t\t\t0\n+#define QRX_TAIL_TAIL_M\t\t\t\tMAKEMASK(0x1FFF, 0)\n+#define VPDSI_RX_QTABLE(_i, _VP16)\t\t(0x00074C00 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */\n+#define VPDSI_RX_QTABLE_MAX_INDEX\t\t15\n+#define VPDSI_RX_QTABLE_PAGE_INDEX0_S\t\t0\n+#define VPDSI_RX_QTABLE_PAGE_INDEX0_M\t\tMAKEMASK(0x7F, 0)\n+#define VPDSI_RX_QTABLE_PAGE_INDEX1_S\t\t8\n+#define VPDSI_RX_QTABLE_PAGE_INDEX1_M\t\tMAKEMASK(0x7F, 8)\n+#define VPDSI_RX_QTABLE_PAGE_INDEX2_S\t\t16\n+#define VPDSI_RX_QTABLE_PAGE_INDEX2_M\t\tMAKEMASK(0x7F, 16)\n+#define VPDSI_RX_QTABLE_PAGE_INDEX3_S\t\t24\n+#define VPDSI_RX_QTABLE_PAGE_INDEX3_M\t\tMAKEMASK(0x7F, 24)\n+#define VPDSI_TX_QTABLE(_i, _VP16)\t\t(0x001D2000 + ((_i) * 64 + (_VP16) * 4)) /* _i=0...15, _VP16=0...15 */ /* Reset Source: CORER */\n+#define VPDSI_TX_QTABLE_MAX_INDEX\t\t15\n+#define VPDSI_TX_QTABLE_PAGE_INDEX0_S\t\t0\n+#define VPDSI_TX_QTABLE_PAGE_INDEX0_M\t\tMAKEMASK(0x7F, 0)\n+#define VPDSI_TX_QTABLE_PAGE_INDEX1_S\t\t8\n+#define VPDSI_TX_QTABLE_PAGE_INDEX1_M\t\tMAKEMASK(0x7F, 8)\n+#define VPDSI_TX_QTABLE_PAGE_INDEX2_S\t\t16\n+#define VPDSI_TX_QTABLE_PAGE_INDEX2_M\t\tMAKEMASK(0x7F, 16)\n+#define VPDSI_TX_QTABLE_PAGE_INDEX3_S\t\t24\n+#define VPDSI_TX_QTABLE_PAGE_INDEX3_M\t\tMAKEMASK(0x7F, 24)\n+#define VPLAN_DB_QTABLE(_i, _VF)\t\t(0x00070000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...3, _VF=0...255 */ /* Reset Source: CORER */\n+#define VPLAN_DB_QTABLE_MAX_INDEX\t\t3\n+#define VPLAN_DB_QTABLE_QINDEX_S\t\t0\n+#define VPLAN_DB_QTABLE_QINDEX_M\t\tMAKEMASK(0x1FF, 0)\n+#define VPLAN_DSI_VF_MODE(_VP16)\t\t(0x002D2C00 + ((_VP16) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define VPLAN_DSI_VF_MODE_MAX_INDEX\t\t15\n+#define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_S\t0\n+#define VPLAN_DSI_VF_MODE_LAN_DSI_VF_MODE_M\tBIT(0)\n+#define VPLAN_RX_QBASE(_VF)\t\t\t(0x00072000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPLAN_RX_QBASE_MAX_INDEX\t\t255\n+#define VPLAN_RX_QBASE_VFFIRSTQ_S\t\t0\n+#define VPLAN_RX_QBASE_VFFIRSTQ_M\t\tMAKEMASK(0x7FF, 0)\n+#define VPLAN_RX_QBASE_VFNUMQ_S\t\t\t16\n+#define VPLAN_RX_QBASE_VFNUMQ_M\t\t\tMAKEMASK(0xFF, 16)\n+#define VPLAN_RX_QBASE_VFQTABLE_ENA_S\t\t31\n+#define VPLAN_RX_QBASE_VFQTABLE_ENA_M\t\tBIT(31)\n+#define VPLAN_RX_QTABLE(_i, _VF)\t\t(0x00060000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */\n+#define VPLAN_RX_QTABLE_MAX_INDEX\t\t15\n+#define VPLAN_RX_QTABLE_QINDEX_S\t\t0\n+#define VPLAN_RX_QTABLE_QINDEX_M\t\tMAKEMASK(0xFFF, 0)\n+#define VPLAN_RXQ_MAPENA(_VF)\t\t\t(0x00073000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPLAN_RXQ_MAPENA_MAX_INDEX\t\t255\n+#define VPLAN_RXQ_MAPENA_RX_ENA_S\t\t0\n+#define VPLAN_RXQ_MAPENA_RX_ENA_M\t\tBIT(0)\n+#define VPLAN_TX_QBASE(_VF)\t\t\t(0x001D1800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPLAN_TX_QBASE_MAX_INDEX\t\t255\n+#define VPLAN_TX_QBASE_VFFIRSTQ_S\t\t0\n+#define VPLAN_TX_QBASE_VFFIRSTQ_M\t\tMAKEMASK(0x3FFF, 0)\n+#define VPLAN_TX_QBASE_VFNUMQ_S\t\t\t16\n+#define VPLAN_TX_QBASE_VFNUMQ_M\t\t\tMAKEMASK(0xFF, 16)\n+#define VPLAN_TX_QBASE_VFQTABLE_ENA_S\t\t31\n+#define VPLAN_TX_QBASE_VFQTABLE_ENA_M\t\tBIT(31)\n+#define VPLAN_TX_QTABLE(_i, _VF)\t\t(0x001C0000 + ((_i) * 2048 + (_VF) * 4)) /* _i=0...15, _VF=0...255 */ /* Reset Source: CORER */\n+#define VPLAN_TX_QTABLE_MAX_INDEX\t\t15\n+#define VPLAN_TX_QTABLE_QINDEX_S\t\t0\n+#define VPLAN_TX_QTABLE_QINDEX_M\t\tMAKEMASK(0x7FFF, 0)\n+#define VPLAN_TXQ_MAPENA(_VF)\t\t\t(0x00073800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPLAN_TXQ_MAPENA_MAX_INDEX\t\t255\n+#define VPLAN_TXQ_MAPENA_TX_ENA_S\t\t0\n+#define VPLAN_TXQ_MAPENA_TX_ENA_M\t\tBIT(0)\n+#define VSILAN_QBASE(_VSI)\t\t\t(0x0044c000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSILAN_QBASE_MAX_INDEX\t\t\t767\n+#define VSILAN_QBASE_VSIBASE_S\t\t\t0\n+#define VSILAN_QBASE_VSIBASE_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define VSILAN_QBASE_VSIQTABLE_ENA_S\t\t11\n+#define VSILAN_QBASE_VSIQTABLE_ENA_M\t\tBIT(11)\n+#define VSILAN_QTABLE(_i, _VSI)\t\t\t(0x00440000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...7, _VSI=0...767 */ /* Reset Source: PFR */\n+#define VSILAN_QTABLE_MAX_INDEX\t\t\t7\n+#define VSILAN_QTABLE_QINDEX_0_S\t\t0\n+#define VSILAN_QTABLE_QINDEX_0_M\t\tMAKEMASK(0x7FF, 0)\n+#define VSILAN_QTABLE_QINDEX_1_S\t\t16\n+#define VSILAN_QTABLE_QINDEX_1_M\t\tMAKEMASK(0x7FF, 16)\n+#define PRTMAC_HSEC_CTL_RX_ENABLE_GCP\t\t0x001E31C0 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_S 0\n+#define PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_M BIT(0)\n+#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP\t\t0x001E34C0 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_S 0\n+#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_M BIT(0)\n+#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP\t\t0x001E35C0 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_S 0\n+#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_M BIT(0)\n+#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL\t0x001E36C0 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_S 0\n+#define PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_M BIT(0)\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3220 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_S 0\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_M MAKEMASK(0xFFFFFFFF, 0)\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3240 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_S 0\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_M MAKEMASK(0xFFFF, 0)\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE\t\t0x001E3180 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S 0\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1\t0x001E3280 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_S 0\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2\t0x001E32A0 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_S 0\n+#define PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_M MAKEMASK(0xFFFF, 0)\n+#define PRTMAC_HSEC_CTL_RX_QUANTA_S\t\t0x001E3C40 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_S 0\n+#define PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_PRTMAC_HSEC_CTL_RX_QUANTA_SHIFT_M MAKEMASK(0xFFFF, 0)\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE\t\t0x001E31A0 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S 0\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M MAKEMASK(0x1FF, 0)\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i)\t(0x001E36E0 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_S 0\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M MAKEMASK(0xFFFF, 0)\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32)) /* _i=0...8 */ /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_S 0\n+#define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M MAKEMASK(0xFFFF, 0)\n+#define PRTMAC_HSEC_CTL_TX_SA_PART1\t\t0x001E3960 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_S 0\n+#define PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_M MAKEMASK(0xFFFFFFFF, 0)\n+#define PRTMAC_HSEC_CTL_TX_SA_PART2\t\t0x001E3980 /* Reset Source: GLOBR */\n+#define PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_S 0\n+#define PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_M MAKEMASK(0xFFFF, 0)\n+#define PRTMAC_LINK_DOWN_COUNTER\t\t0x001E47C0 /* Reset Source: GLOBR */\n+#define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_S 0\n+#define PRTMAC_LINK_DOWN_COUNTER_LINK_DOWN_COUNTER_M MAKEMASK(0xFFFF, 0)\n+#define PRTMAC_MD_OVRRIDE_ENABLE(_i)\t\t(0x001E3C60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */\n+#define PRTMAC_MD_OVRRIDE_ENABLE_MAX_INDEX\t7\n+#define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_S 0\n+#define PRTMAC_MD_OVRRIDE_ENABLE_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)\n+#define PRTMAC_MD_OVRRIDE_VAL(_i)\t\t(0x001E3D60 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: GLOBR */\n+#define PRTMAC_MD_OVRRIDE_VAL_MAX_INDEX\t\t7\n+#define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_S 0\n+#define PRTMAC_MD_OVRRIDE_VAL_PRTMAC_MD_OVRRIDE_ENABLE_M MAKEMASK(0xFFFFFFFF, 0)\n+#define PRTMAC_RX_CNT_MRKR\t\t\t0x001E48E0 /* Reset Source: GLOBR */\n+#define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_S\t0\n+#define PRTMAC_RX_CNT_MRKR_RX_CNT_MRKR_M\tMAKEMASK(0xFFFF, 0)\n+#define PRTMAC_RX_PKT_DRP_CNT\t\t\t0x001E3C20 /* Reset Source: GLOBR */\n+#define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_S\t0\n+#define PRTMAC_RX_PKT_DRP_CNT_RX_PKT_DRP_CNT_M\tMAKEMASK(0xFFFF, 0)\n+#define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_S 16\n+#define PRTMAC_RX_PKT_DRP_CNT_RX_MKR_PKT_DRP_CNT_M MAKEMASK(0xFFFF, 16)\n+#define PRTMAC_TX_CNT_MRKR\t\t\t0x001E48C0 /* Reset Source: GLOBR */\n+#define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_S\t0\n+#define PRTMAC_TX_CNT_MRKR_TX_CNT_MRKR_M\tMAKEMASK(0xFFFF, 0)\n+#define PRTMAC_TX_LNK_UP_CNT\t\t\t0x001E4840 /* Reset Source: GLOBR */\n+#define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_S\t0\n+#define PRTMAC_TX_LNK_UP_CNT_TX_LINK_UP_CNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_MDCK_CFG1_TX_PQM\t\t\t0x002D2DF4 /* Reset Source: CORER */\n+#define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_S\t0\n+#define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DATA_LEN_M\tMAKEMASK(0xFF, 0)\n+#define GL_MDCK_CFG1_TX_PQM_SSO_MAX_PKT_CNT_S\t8\n+#define GL_MDCK_CFG1_TX_PQM_SSO_MAX_PKT_CNT_M\tMAKEMASK(0x3F, 8)\n+#define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DESC_CNT_S\t16\n+#define GL_MDCK_CFG1_TX_PQM_SSO_MAX_DESC_CNT_M\tMAKEMASK(0x3F, 16)\n+#define GL_MDCK_EN_TX_PQM\t\t\t0x002D2DFC /* Reset Source: CORER */\n+#define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_S\t0\n+#define GL_MDCK_EN_TX_PQM_PCI_DUMMY_COMP_M\tBIT(0)\n+#define GL_MDCK_EN_TX_PQM_PCI_UR_COMP_S\t\t1\n+#define GL_MDCK_EN_TX_PQM_PCI_UR_COMP_M\t\tBIT(1)\n+#define GL_MDCK_EN_TX_PQM_RCV_SH_BE_LSO_S\t3\n+#define GL_MDCK_EN_TX_PQM_RCV_SH_BE_LSO_M\tBIT(3)\n+#define GL_MDCK_EN_TX_PQM_Q_FL_MNG_EPY_CH_S\t4\n+#define GL_MDCK_EN_TX_PQM_Q_FL_MNG_EPY_CH_M\tBIT(4)\n+#define GL_MDCK_EN_TX_PQM_Q_EPY_MNG_FL_CH_S\t5\n+#define GL_MDCK_EN_TX_PQM_Q_EPY_MNG_FL_CH_M\tBIT(5)\n+#define GL_MDCK_EN_TX_PQM_LSO_NUMDESCS_ZERO_S\t6\n+#define GL_MDCK_EN_TX_PQM_LSO_NUMDESCS_ZERO_M\tBIT(6)\n+#define GL_MDCK_EN_TX_PQM_LSO_LENGTH_ZERO_S\t7\n+#define GL_MDCK_EN_TX_PQM_LSO_LENGTH_ZERO_M\tBIT(7)\n+#define GL_MDCK_EN_TX_PQM_LSO_MSS_BELOW_MIN_S\t8\n+#define GL_MDCK_EN_TX_PQM_LSO_MSS_BELOW_MIN_M\tBIT(8)\n+#define GL_MDCK_EN_TX_PQM_LSO_MSS_ABOVE_MAX_S\t9\n+#define GL_MDCK_EN_TX_PQM_LSO_MSS_ABOVE_MAX_M\tBIT(9)\n+#define GL_MDCK_EN_TX_PQM_LSO_HDR_SIZE_ZERO_S\t10\n+#define GL_MDCK_EN_TX_PQM_LSO_HDR_SIZE_ZERO_M\tBIT(10)\n+#define GL_MDCK_EN_TX_PQM_RCV_CNT_BE_LSO_S\t11\n+#define GL_MDCK_EN_TX_PQM_RCV_CNT_BE_LSO_M\tBIT(11)\n+#define GL_MDCK_EN_TX_PQM_SKIP_ONE_QT_ONLY_S\t12\n+#define GL_MDCK_EN_TX_PQM_SKIP_ONE_QT_ONLY_M\tBIT(12)\n+#define GL_MDCK_EN_TX_PQM_LSO_PKTCNT_ZERO_S\t13\n+#define GL_MDCK_EN_TX_PQM_LSO_PKTCNT_ZERO_M\tBIT(13)\n+#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_ZERO_S\t14\n+#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_ZERO_M\tBIT(14)\n+#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_S\t15\n+#define GL_MDCK_EN_TX_PQM_SSO_LENGTH_EXCEED_M\tBIT(15)\n+#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_S\t16\n+#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_ZERO_M\tBIT(16)\n+#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_S\t17\n+#define GL_MDCK_EN_TX_PQM_SSO_PKTCNT_EXCEED_M\tBIT(17)\n+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_S\t18\n+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_ZERO_M\tBIT(18)\n+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_S 19\n+#define GL_MDCK_EN_TX_PQM_SSO_NUMDESCS_EXCEED_M BIT(19)\n+#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_S 20\n+#define GL_MDCK_EN_TX_PQM_TAIL_GT_RING_LENGTH_M BIT(20)\n+#define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_S\t21\n+#define GL_MDCK_EN_TX_PQM_RESERVED_DBL_TYPE_M\tBIT(21)\n+#define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_S 22\n+#define GL_MDCK_EN_TX_PQM_ILLEGAL_HEAD_DROP_DBL_M BIT(22)\n+#define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_S\t23\n+#define GL_MDCK_EN_TX_PQM_LSO_OVER_COMMS_Q_M\tBIT(23)\n+#define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_S\t24\n+#define GL_MDCK_EN_TX_PQM_ILLEGAL_VF_QNUM_M\tBIT(24)\n+#define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_S 25\n+#define GL_MDCK_EN_TX_PQM_QTAIL_GT_RING_LENGTH_M BIT(25)\n+#define GL_MDCK_EN_TX_PQM_RSVD_S\t\t26\n+#define GL_MDCK_EN_TX_PQM_RSVD_M\t\tMAKEMASK(0x3F, 26)\n+#define GL_MDCK_RX\t\t\t\t0x0029422C /* Reset Source: CORER */\n+#define GL_MDCK_RX_DESC_ADDR_S\t\t\t0\n+#define GL_MDCK_RX_DESC_ADDR_M\t\t\tBIT(0)\n+#define GL_MDET_RX\t\t\t\t0x00294C00 /* Reset Source: CORER */\n+#define GL_MDET_RX_QNUM_S\t\t\t0\n+#define GL_MDET_RX_QNUM_M\t\t\tMAKEMASK(0x7FFF, 0)\n+#define GL_MDET_RX_VF_NUM_S\t\t\t15\n+#define GL_MDET_RX_VF_NUM_M\t\t\tMAKEMASK(0xFF, 15)\n+#define GL_MDET_RX_PF_NUM_S\t\t\t23\n+#define GL_MDET_RX_PF_NUM_M\t\t\tMAKEMASK(0x7, 23)\n+#define GL_MDET_RX_MAL_TYPE_S\t\t\t26\n+#define GL_MDET_RX_MAL_TYPE_M\t\t\tMAKEMASK(0x1F, 26)\n+#define GL_MDET_RX_VALID_S\t\t\t31\n+#define GL_MDET_RX_VALID_M\t\t\tBIT(31)\n+#define GL_MDET_TX_PQM\t\t\t\t0x002D2E00 /* Reset Source: CORER */\n+#define GL_MDET_TX_PQM_PF_NUM_S\t\t\t0\n+#define GL_MDET_TX_PQM_PF_NUM_M\t\t\tMAKEMASK(0x7, 0)\n+#define GL_MDET_TX_PQM_VF_NUM_S\t\t\t4\n+#define GL_MDET_TX_PQM_VF_NUM_M\t\t\tMAKEMASK(0xFF, 4)\n+#define GL_MDET_TX_PQM_QNUM_S\t\t\t12\n+#define GL_MDET_TX_PQM_QNUM_M\t\t\tMAKEMASK(0x3FFF, 12)\n+#define GL_MDET_TX_PQM_MAL_TYPE_S\t\t26\n+#define GL_MDET_TX_PQM_MAL_TYPE_M\t\tMAKEMASK(0x1F, 26)\n+#define GL_MDET_TX_PQM_VALID_S\t\t\t31\n+#define GL_MDET_TX_PQM_VALID_M\t\t\tBIT(31)\n+#define GL_MDET_TX_TCLAN\t\t\t0x000FC068 /* Reset Source: CORER */\n+#define GL_MDET_TX_TCLAN_QNUM_S\t\t\t0\n+#define GL_MDET_TX_TCLAN_QNUM_M\t\t\tMAKEMASK(0x7FFF, 0)\n+#define GL_MDET_TX_TCLAN_VF_NUM_S\t\t15\n+#define GL_MDET_TX_TCLAN_VF_NUM_M\t\tMAKEMASK(0xFF, 15)\n+#define GL_MDET_TX_TCLAN_PF_NUM_S\t\t23\n+#define GL_MDET_TX_TCLAN_PF_NUM_M\t\tMAKEMASK(0x7, 23)\n+#define GL_MDET_TX_TCLAN_MAL_TYPE_S\t\t26\n+#define GL_MDET_TX_TCLAN_MAL_TYPE_M\t\tMAKEMASK(0x1F, 26)\n+#define GL_MDET_TX_TCLAN_VALID_S\t\t31\n+#define GL_MDET_TX_TCLAN_VALID_M\t\tBIT(31)\n+#define PF_MDET_RX\t\t\t\t0x00294280 /* Reset Source: CORER */\n+#define PF_MDET_RX_VALID_S\t\t\t0\n+#define PF_MDET_RX_VALID_M\t\t\tBIT(0)\n+#define PF_MDET_TX_PQM\t\t\t\t0x002D2C80 /* Reset Source: CORER */\n+#define PF_MDET_TX_PQM_VALID_S\t\t\t0\n+#define PF_MDET_TX_PQM_VALID_M\t\t\tBIT(0)\n+#define PF_MDET_TX_TCLAN\t\t\t0x000FC000 /* Reset Source: CORER */\n+#define PF_MDET_TX_TCLAN_VALID_S\t\t0\n+#define PF_MDET_TX_TCLAN_VALID_M\t\tBIT(0)\n+#define PF_MDET_TX_TDPU\t\t\t\t0x00040800 /* Reset Source: CORER */\n+#define PF_MDET_TX_TDPU_VALID_S\t\t\t0\n+#define PF_MDET_TX_TDPU_VALID_M\t\t\tBIT(0)\n+#define VP_MDET_RX(_VF)\t\t\t\t(0x00294400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VP_MDET_RX_MAX_INDEX\t\t\t255\n+#define VP_MDET_RX_VALID_S\t\t\t0\n+#define VP_MDET_RX_VALID_M\t\t\tBIT(0)\n+#define VP_MDET_TX_PQM(_VF)\t\t\t(0x002D2000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VP_MDET_TX_PQM_MAX_INDEX\t\t255\n+#define VP_MDET_TX_PQM_VALID_S\t\t\t0\n+#define VP_MDET_TX_PQM_VALID_M\t\t\tBIT(0)\n+#define VP_MDET_TX_TCLAN(_VF)\t\t\t(0x000FB800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VP_MDET_TX_TCLAN_MAX_INDEX\t\t255\n+#define VP_MDET_TX_TCLAN_VALID_S\t\t0\n+#define VP_MDET_TX_TCLAN_VALID_M\t\tBIT(0)\n+#define VP_MDET_TX_TDPU(_VF)\t\t\t(0x00040000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VP_MDET_TX_TDPU_MAX_INDEX\t\t255\n+#define VP_MDET_TX_TDPU_VALID_S\t\t\t0\n+#define VP_MDET_TX_TDPU_VALID_M\t\t\tBIT(0)\n+#define GENERAL_MNG_FW_DBG_CSR(_i)\t\t(0x000B6180 + ((_i) * 4)) /* _i=0...9 */ /* Reset Source: POR */\n+#define GENERAL_MNG_FW_DBG_CSR_MAX_INDEX\t9\n+#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_S 0\n+#define GENERAL_MNG_FW_DBG_CSR_GENERAL_FW_DBG_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GL_FWRESETCNT\t\t\t\t0x00083100 /* Reset Source: POR */\n+#define GL_FWRESETCNT_FWRESETCNT_S\t\t0\n+#define GL_FWRESETCNT_FWRESETCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_MNG_FW_RAM_STAT\t\t\t0x0008309C /* Reset Source: POR */\n+#define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_S\t0\n+#define GL_MNG_FW_RAM_STAT_FW_RAM_RST_STAT_M\tBIT(0)\n+#define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_S\t1\n+#define GL_MNG_FW_RAM_STAT_MNG_MEM_ECC_ERR_M\tBIT(1)\n+#define GL_MNG_FWSM\t\t\t\t0x000B6134 /* Reset Source: POR */\n+#define GL_MNG_FWSM_FW_MODES_S\t\t\t0\n+#define GL_MNG_FWSM_FW_MODES_M\t\t\tMAKEMASK(0x3, 0)\n+#define GL_MNG_FWSM_RSV0_S\t\t\t2\n+#define GL_MNG_FWSM_RSV0_M\t\t\tMAKEMASK(0xFF, 2)\n+#define GL_MNG_FWSM_EEP_RELOAD_IND_S\t\t10\n+#define GL_MNG_FWSM_EEP_RELOAD_IND_M\t\tBIT(10)\n+#define GL_MNG_FWSM_RSV1_S\t\t\t11\n+#define GL_MNG_FWSM_RSV1_M\t\t\tMAKEMASK(0xF, 11)\n+#define GL_MNG_FWSM_RSV2_S\t\t\t15\n+#define GL_MNG_FWSM_RSV2_M\t\t\tBIT(15)\n+#define GL_MNG_FWSM_PCIR_AL_FAILURE_S\t\t16\n+#define GL_MNG_FWSM_PCIR_AL_FAILURE_M\t\tBIT(16)\n+#define GL_MNG_FWSM_POR_AL_FAILURE_S\t\t17\n+#define GL_MNG_FWSM_POR_AL_FAILURE_M\t\tBIT(17)\n+#define GL_MNG_FWSM_RSV3_S\t\t\t18\n+#define GL_MNG_FWSM_RSV3_M\t\t\tBIT(18)\n+#define GL_MNG_FWSM_EXT_ERR_IND_S\t\t19\n+#define GL_MNG_FWSM_EXT_ERR_IND_M\t\tMAKEMASK(0x3F, 19)\n+#define GL_MNG_FWSM_RSV4_S\t\t\t25\n+#define GL_MNG_FWSM_RSV4_M\t\t\tBIT(25)\n+#define GL_MNG_FWSM_RESERVED_11_S\t\t26\n+#define GL_MNG_FWSM_RESERVED_11_M\t\tMAKEMASK(0xF, 26)\n+#define GL_MNG_FWSM_RSV5_S\t\t\t30\n+#define GL_MNG_FWSM_RSV5_M\t\t\tMAKEMASK(0x3, 30)\n+#define GL_MNG_HWARB_CTRL\t\t\t0x000B6130 /* Reset Source: POR */\n+#define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_S\t\t0\n+#define GL_MNG_HWARB_CTRL_NCSI_ARB_EN_M\t\tBIT(0)\n+#define GL_MNG_SHA_EXTEND(_i)\t\t\t(0x00083120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */\n+#define GL_MNG_SHA_EXTEND_MAX_INDEX\t\t7\n+#define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_S\t0\n+#define GL_MNG_SHA_EXTEND_GL_MNG_SHA_EXTEND_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_MNG_SHA_EXTEND_ROM(_i)\t\t(0x00083160 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: EMPR */\n+#define GL_MNG_SHA_EXTEND_ROM_MAX_INDEX\t\t7\n+#define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_S 0\n+#define GL_MNG_SHA_EXTEND_ROM_GL_MNG_SHA_EXTEND_ROM_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GL_MNG_SHA_EXTEND_STATUS\t\t0x00083148 /* Reset Source: EMPR */\n+#define GL_MNG_SHA_EXTEND_STATUS_STAGE_S\t0\n+#define GL_MNG_SHA_EXTEND_STATUS_STAGE_M\tMAKEMASK(0x7, 0)\n+#define GL_MNG_SHA_EXTEND_STATUS_FW_HALTED_S\t30\n+#define GL_MNG_SHA_EXTEND_STATUS_FW_HALTED_M\tBIT(30)\n+#define GL_MNG_SHA_EXTEND_STATUS_DONE_S\t\t31\n+#define GL_MNG_SHA_EXTEND_STATUS_DONE_M\t\tBIT(31)\n+#define GL_SWT_PRT2MDEF(_i)\t\t\t(0x00216018 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: POR */\n+#define GL_SWT_PRT2MDEF_MAX_INDEX\t\t31\n+#define GL_SWT_PRT2MDEF_MDEFIDX_S\t\t0\n+#define GL_SWT_PRT2MDEF_MDEFIDX_M\t\tMAKEMASK(0x7, 0)\n+#define GL_SWT_PRT2MDEF_MDEFENA_S\t\t31\n+#define GL_SWT_PRT2MDEF_MDEFENA_M\t\tBIT(31)\n+#define PRT_MNG_MANC\t\t\t\t0x00214720 /* Reset Source: POR */\n+#define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_S\t0\n+#define PRT_MNG_MANC_FLOW_CONTROL_DISCARD_M\tBIT(0)\n+#define PRT_MNG_MANC_NCSI_DISCARD_S\t\t1\n+#define PRT_MNG_MANC_NCSI_DISCARD_M\t\tBIT(1)\n+#define PRT_MNG_MANC_RCV_TCO_EN_S\t\t17\n+#define PRT_MNG_MANC_RCV_TCO_EN_M\t\tBIT(17)\n+#define PRT_MNG_MANC_RCV_ALL_S\t\t\t19\n+#define PRT_MNG_MANC_RCV_ALL_M\t\t\tBIT(19)\n+#define PRT_MNG_MANC_FIXED_NET_TYPE_S\t\t25\n+#define PRT_MNG_MANC_FIXED_NET_TYPE_M\t\tBIT(25)\n+#define PRT_MNG_MANC_NET_TYPE_S\t\t\t26\n+#define PRT_MNG_MANC_NET_TYPE_M\t\t\tBIT(26)\n+#define PRT_MNG_MANC_EN_BMC2OS_S\t\t28\n+#define PRT_MNG_MANC_EN_BMC2OS_M\t\tBIT(28)\n+#define PRT_MNG_MANC_EN_BMC2NET_S\t\t29\n+#define PRT_MNG_MANC_EN_BMC2NET_M\t\tBIT(29)\n+#define PRT_MNG_MAVTV(_i)\t\t\t(0x00214780 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */\n+#define PRT_MNG_MAVTV_MAX_INDEX\t\t\t7\n+#define PRT_MNG_MAVTV_VID_S\t\t\t0\n+#define PRT_MNG_MAVTV_VID_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define PRT_MNG_MDEF(_i)\t\t\t(0x00214880 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */\n+#define PRT_MNG_MDEF_MAX_INDEX\t\t\t7\n+#define PRT_MNG_MDEF_MAC_EXACT_AND_S\t\t0\n+#define PRT_MNG_MDEF_MAC_EXACT_AND_M\t\tMAKEMASK(0xF, 0)\n+#define PRT_MNG_MDEF_BROADCAST_AND_S\t\t4\n+#define PRT_MNG_MDEF_BROADCAST_AND_M\t\tBIT(4)\n+#define PRT_MNG_MDEF_VLAN_AND_S\t\t\t5\n+#define PRT_MNG_MDEF_VLAN_AND_M\t\t\tMAKEMASK(0xFF, 5)\n+#define PRT_MNG_MDEF_IPV4_ADDRESS_AND_S\t\t13\n+#define PRT_MNG_MDEF_IPV4_ADDRESS_AND_M\t\tMAKEMASK(0xF, 13)\n+#define PRT_MNG_MDEF_IPV6_ADDRESS_AND_S\t\t17\n+#define PRT_MNG_MDEF_IPV6_ADDRESS_AND_M\t\tMAKEMASK(0xF, 17)\n+#define PRT_MNG_MDEF_MAC_EXACT_OR_S\t\t21\n+#define PRT_MNG_MDEF_MAC_EXACT_OR_M\t\tMAKEMASK(0xF, 21)\n+#define PRT_MNG_MDEF_BROADCAST_OR_S\t\t25\n+#define PRT_MNG_MDEF_BROADCAST_OR_M\t\tBIT(25)\n+#define PRT_MNG_MDEF_MULTICAST_AND_S\t\t26\n+#define PRT_MNG_MDEF_MULTICAST_AND_M\t\tBIT(26)\n+#define PRT_MNG_MDEF_ARP_REQUEST_OR_S\t\t27\n+#define PRT_MNG_MDEF_ARP_REQUEST_OR_M\t\tBIT(27)\n+#define PRT_MNG_MDEF_ARP_RESPONSE_OR_S\t\t28\n+#define PRT_MNG_MDEF_ARP_RESPONSE_OR_M\t\tBIT(28)\n+#define PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_S 29\n+#define PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_M BIT(29)\n+#define PRT_MNG_MDEF_PORT_0X298_OR_S\t\t30\n+#define PRT_MNG_MDEF_PORT_0X298_OR_M\t\tBIT(30)\n+#define PRT_MNG_MDEF_PORT_0X26F_OR_S\t\t31\n+#define PRT_MNG_MDEF_PORT_0X26F_OR_M\t\tBIT(31)\n+#define PRT_MNG_MDEF_EXT(_i)\t\t\t(0x00214A00 + ((_i) * 32)) /* _i=0...7 */ /* Reset Source: POR */\n+#define PRT_MNG_MDEF_EXT_MAX_INDEX\t\t7\n+#define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_S\t0\n+#define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_M\tMAKEMASK(0xF, 0)\n+#define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_S\t4\n+#define PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_M\tMAKEMASK(0xF, 4)\n+#define PRT_MNG_MDEF_EXT_FLEX_PORT_OR_S\t\t8\n+#define PRT_MNG_MDEF_EXT_FLEX_PORT_OR_M\t\tMAKEMASK(0xFFFF, 8)\n+#define PRT_MNG_MDEF_EXT_FLEX_TCO_S\t\t24\n+#define PRT_MNG_MDEF_EXT_FLEX_TCO_M\t\tBIT(24)\n+#define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_S 25\n+#define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_M BIT(25)\n+#define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_S 26\n+#define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_M BIT(26)\n+#define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_S 27\n+#define PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_M BIT(27)\n+#define PRT_MNG_MDEF_EXT_ICMP_OR_S\t\t28\n+#define PRT_MNG_MDEF_EXT_ICMP_OR_M\t\tBIT(28)\n+#define PRT_MNG_MDEF_EXT_MLD_S\t\t\t29\n+#define PRT_MNG_MDEF_EXT_MLD_M\t\t\tBIT(29)\n+#define PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_S 30\n+#define PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_M BIT(30)\n+#define PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_S 31\n+#define PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_M BIT(31)\n+#define PRT_MNG_MDEFVSI(_i)\t\t\t(0x00214980 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */\n+#define PRT_MNG_MDEFVSI_MAX_INDEX\t\t3\n+#define PRT_MNG_MDEFVSI_MDEFVSI_2N_S\t\t0\n+#define PRT_MNG_MDEFVSI_MDEFVSI_2N_M\t\tMAKEMASK(0xFFFF, 0)\n+#define PRT_MNG_MDEFVSI_MDEFVSI_2NP1_S\t\t16\n+#define PRT_MNG_MDEFVSI_MDEFVSI_2NP1_M\t\tMAKEMASK(0xFFFF, 16)\n+#define PRT_MNG_METF(_i)\t\t\t(0x00214120 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */\n+#define PRT_MNG_METF_MAX_INDEX\t\t\t3\n+#define PRT_MNG_METF_ETYPE_S\t\t\t0\n+#define PRT_MNG_METF_ETYPE_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define PRT_MNG_METF_POLARITY_S\t\t\t30\n+#define PRT_MNG_METF_POLARITY_M\t\t\tBIT(30)\n+#define PRT_MNG_MFUTP(_i)\t\t\t(0x00214320 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */\n+#define PRT_MNG_MFUTP_MAX_INDEX\t\t\t15\n+#define PRT_MNG_MFUTP_MFUTP_N_S\t\t\t0\n+#define PRT_MNG_MFUTP_MFUTP_N_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define PRT_MNG_MFUTP_UDP_S\t\t\t16\n+#define PRT_MNG_MFUTP_UDP_M\t\t\tBIT(16)\n+#define PRT_MNG_MFUTP_TCP_S\t\t\t17\n+#define PRT_MNG_MFUTP_TCP_M\t\t\tBIT(17)\n+#define PRT_MNG_MFUTP_SOURCE_DESTINATION_S\t18\n+#define PRT_MNG_MFUTP_SOURCE_DESTINATION_M\tBIT(18)\n+#define PRT_MNG_MIPAF4(_i)\t\t\t(0x002141A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */\n+#define PRT_MNG_MIPAF4_MAX_INDEX\t\t3\n+#define PRT_MNG_MIPAF4_MIPAF_S\t\t\t0\n+#define PRT_MNG_MIPAF4_MIPAF_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PRT_MNG_MIPAF6(_i)\t\t\t(0x00214520 + ((_i) * 32)) /* _i=0...15 */ /* Reset Source: POR */\n+#define PRT_MNG_MIPAF6_MAX_INDEX\t\t15\n+#define PRT_MNG_MIPAF6_MIPAF_S\t\t\t0\n+#define PRT_MNG_MIPAF6_MIPAF_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PRT_MNG_MMAH(_i)\t\t\t(0x00214220 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */\n+#define PRT_MNG_MMAH_MAX_INDEX\t\t\t3\n+#define PRT_MNG_MMAH_MMAH_S\t\t\t0\n+#define PRT_MNG_MMAH_MMAH_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define PRT_MNG_MMAL(_i)\t\t\t(0x002142A0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: POR */\n+#define PRT_MNG_MMAL_MAX_INDEX\t\t\t3\n+#define PRT_MNG_MMAL_MMAL_S\t\t\t0\n+#define PRT_MNG_MMAL_MMAL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PRT_MNG_MNGONLY\t\t\t\t0x00214740 /* Reset Source: POR */\n+#define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_S 0\n+#define PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_M MAKEMASK(0xFF, 0)\n+#define PRT_MNG_MSFM\t\t\t\t0x00214760 /* Reset Source: POR */\n+#define PRT_MNG_MSFM_PORT_26F_UDP_S\t\t0\n+#define PRT_MNG_MSFM_PORT_26F_UDP_M\t\tBIT(0)\n+#define PRT_MNG_MSFM_PORT_26F_TCP_S\t\t1\n+#define PRT_MNG_MSFM_PORT_26F_TCP_M\t\tBIT(1)\n+#define PRT_MNG_MSFM_PORT_298_UDP_S\t\t2\n+#define PRT_MNG_MSFM_PORT_298_UDP_M\t\tBIT(2)\n+#define PRT_MNG_MSFM_PORT_298_TCP_S\t\t3\n+#define PRT_MNG_MSFM_PORT_298_TCP_M\t\tBIT(3)\n+#define PRT_MNG_MSFM_IPV6_0_MASK_S\t\t4\n+#define PRT_MNG_MSFM_IPV6_0_MASK_M\t\tBIT(4)\n+#define PRT_MNG_MSFM_IPV6_1_MASK_S\t\t5\n+#define PRT_MNG_MSFM_IPV6_1_MASK_M\t\tBIT(5)\n+#define PRT_MNG_MSFM_IPV6_2_MASK_S\t\t6\n+#define PRT_MNG_MSFM_IPV6_2_MASK_M\t\tBIT(6)\n+#define PRT_MNG_MSFM_IPV6_3_MASK_S\t\t7\n+#define PRT_MNG_MSFM_IPV6_3_MASK_M\t\tBIT(7)\n+#define MSIX_PBA_PAGE(_i)\t\t\t(0x02E08000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */\n+#define MSIX_PBA_PAGE_MAX_INDEX\t\t\t63\n+#define MSIX_PBA_PAGE_PENBIT_S\t\t\t0\n+#define MSIX_PBA_PAGE_PENBIT_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define MSIX_PBA1(_i)\t\t\t\t(0x00008000 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: FLR */\n+#define MSIX_PBA1_MAX_INDEX\t\t\t63\n+#define MSIX_PBA1_PENBIT_S\t\t\t0\n+#define MSIX_PBA1_PENBIT_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define MSIX_TADD_PAGE(_i)\t\t\t(0x02E00000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */\n+#define MSIX_TADD_PAGE_MAX_INDEX\t\t2047\n+#define MSIX_TADD_PAGE_MSIXTADD10_S\t\t0\n+#define MSIX_TADD_PAGE_MSIXTADD10_M\t\tMAKEMASK(0x3, 0)\n+#define MSIX_TADD_PAGE_MSIXTADD_S\t\t2\n+#define MSIX_TADD_PAGE_MSIXTADD_M\t\tMAKEMASK(0x3FFFFFFF, 2)\n+#define MSIX_TADD1(_i)\t\t\t\t(0x00000000 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */\n+#define MSIX_TADD1_MAX_INDEX\t\t\t2047\n+#define MSIX_TADD1_MSIXTADD10_S\t\t\t0\n+#define MSIX_TADD1_MSIXTADD10_M\t\t\tMAKEMASK(0x3, 0)\n+#define MSIX_TADD1_MSIXTADD_S\t\t\t2\n+#define MSIX_TADD1_MSIXTADD_M\t\t\tMAKEMASK(0x3FFFFFFF, 2)\n+#define MSIX_TMSG(_i)\t\t\t\t(0x00000008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */\n+#define MSIX_TMSG_MAX_INDEX\t\t\t2047\n+#define MSIX_TMSG_MSIXTMSG_S\t\t\t0\n+#define MSIX_TMSG_MSIXTMSG_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define MSIX_TMSG_PAGE(_i)\t\t\t(0x02E00008 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */\n+#define MSIX_TMSG_PAGE_MAX_INDEX\t\t2047\n+#define MSIX_TMSG_PAGE_MSIXTMSG_S\t\t0\n+#define MSIX_TMSG_PAGE_MSIXTMSG_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define MSIX_TUADD_PAGE(_i)\t\t\t(0x02E00004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */\n+#define MSIX_TUADD_PAGE_MAX_INDEX\t\t2047\n+#define MSIX_TUADD_PAGE_MSIXTUADD_S\t\t0\n+#define MSIX_TUADD_PAGE_MSIXTUADD_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define MSIX_TUADD1(_i)\t\t\t\t(0x00000004 + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */\n+#define MSIX_TUADD1_MAX_INDEX\t\t\t2047\n+#define MSIX_TUADD1_MSIXTUADD_S\t\t\t0\n+#define MSIX_TUADD1_MSIXTUADD_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define MSIX_TVCTRL_PAGE(_i)\t\t\t(0x02E0000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */\n+#define MSIX_TVCTRL_PAGE_MAX_INDEX\t\t2047\n+#define MSIX_TVCTRL_PAGE_MASK_S\t\t\t0\n+#define MSIX_TVCTRL_PAGE_MASK_M\t\t\tBIT(0)\n+#define MSIX_TVCTRL1(_i)\t\t\t(0x0000000C + ((_i) * 16)) /* _i=0...2047 */ /* Reset Source: FLR */\n+#define MSIX_TVCTRL1_MAX_INDEX\t\t\t2047\n+#define MSIX_TVCTRL1_MASK_S\t\t\t0\n+#define MSIX_TVCTRL1_MASK_M\t\t\tBIT(0)\n+#define GLNVM_AL_DONE_HLP\t\t\t0x000824C4 /* Reset Source: POR */\n+#define GLNVM_AL_DONE_HLP_HLP_CORER_S\t\t0\n+#define GLNVM_AL_DONE_HLP_HLP_CORER_M\t\tBIT(0)\n+#define GLNVM_AL_DONE_HLP_HLP_FULLR_S\t\t1\n+#define GLNVM_AL_DONE_HLP_HLP_FULLR_M\t\tBIT(1)\n+#define GLNVM_ALTIMERS\t\t\t\t0x000B6140 /* Reset Source: POR */\n+#define GLNVM_ALTIMERS_PCI_ALTIMER_S\t\t0\n+#define GLNVM_ALTIMERS_PCI_ALTIMER_M\t\tMAKEMASK(0xFFF, 0)\n+#define GLNVM_ALTIMERS_GEN_ALTIMER_S\t\t12\n+#define GLNVM_ALTIMERS_GEN_ALTIMER_M\t\tMAKEMASK(0xFFFFF, 12)\n+#define GLNVM_FLA\t\t\t\t0x000B6108 /* Reset Source: POR */\n+#define GLNVM_FLA_LOCKED_S\t\t\t6\n+#define GLNVM_FLA_LOCKED_M\t\t\tBIT(6)\n+#define GLNVM_GENS\t\t\t\t0x000B6100 /* Reset Source: POR */\n+#define GLNVM_GENS_NVM_PRES_S\t\t\t0\n+#define GLNVM_GENS_NVM_PRES_M\t\t\tBIT(0)\n+#define GLNVM_GENS_SR_SIZE_S\t\t\t5\n+#define GLNVM_GENS_SR_SIZE_M\t\t\tMAKEMASK(0x7, 5)\n+#define GLNVM_GENS_BANK1VAL_S\t\t\t8\n+#define GLNVM_GENS_BANK1VAL_M\t\t\tBIT(8)\n+#define GLNVM_GENS_ALT_PRST_S\t\t\t23\n+#define GLNVM_GENS_ALT_PRST_M\t\t\tBIT(23)\n+#define GLNVM_GENS_FL_AUTO_RD_S\t\t\t25\n+#define GLNVM_GENS_FL_AUTO_RD_M\t\t\tBIT(25)\n+#define GLNVM_PROTCSR(_i)\t\t\t(0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset Source: POR */\n+#define GLNVM_PROTCSR_MAX_INDEX\t\t\t59\n+#define GLNVM_PROTCSR_ADDR_BLOCK_S\t\t0\n+#define GLNVM_PROTCSR_ADDR_BLOCK_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLNVM_ULD\t\t\t\t0x000B6008 /* Reset Source: POR */\n+#define GLNVM_ULD_PCIER_DONE_S\t\t\t0\n+#define GLNVM_ULD_PCIER_DONE_M\t\t\tBIT(0)\n+#define GLNVM_ULD_PCIER_DONE_1_S\t\t1\n+#define GLNVM_ULD_PCIER_DONE_1_M\t\tBIT(1)\n+#define GLNVM_ULD_CORER_DONE_S\t\t\t3\n+#define GLNVM_ULD_CORER_DONE_M\t\t\tBIT(3)\n+#define GLNVM_ULD_GLOBR_DONE_S\t\t\t4\n+#define GLNVM_ULD_GLOBR_DONE_M\t\t\tBIT(4)\n+#define GLNVM_ULD_POR_DONE_S\t\t\t5\n+#define GLNVM_ULD_POR_DONE_M\t\t\tBIT(5)\n+#define GLNVM_ULD_POR_DONE_1_S\t\t\t8\n+#define GLNVM_ULD_POR_DONE_1_M\t\t\tBIT(8)\n+#define GLNVM_ULD_PCIER_DONE_2_S\t\t9\n+#define GLNVM_ULD_PCIER_DONE_2_M\t\tBIT(9)\n+#define GLNVM_ULD_PE_DONE_S\t\t\t10\n+#define GLNVM_ULD_PE_DONE_M\t\t\tBIT(10)\n+#define GLNVM_ULD_HLP_CORE_DONE_S\t\t11\n+#define GLNVM_ULD_HLP_CORE_DONE_M\t\tBIT(11)\n+#define GLNVM_ULD_HLP_FULL_DONE_S\t\t12\n+#define GLNVM_ULD_HLP_FULL_DONE_M\t\tBIT(12)\n+#define GLNVM_ULT\t\t\t\t0x000B6154 /* Reset Source: POR */\n+#define GLNVM_ULT_CONF_PCIR_AE_S\t\t0\n+#define GLNVM_ULT_CONF_PCIR_AE_M\t\tBIT(0)\n+#define GLNVM_ULT_CONF_PCIRTL_AE_S\t\t1\n+#define GLNVM_ULT_CONF_PCIRTL_AE_M\t\tBIT(1)\n+#define GLNVM_ULT_RESERVED_1_S\t\t\t2\n+#define GLNVM_ULT_RESERVED_1_M\t\t\tBIT(2)\n+#define GLNVM_ULT_CONF_CORE_AE_S\t\t3\n+#define GLNVM_ULT_CONF_CORE_AE_M\t\tBIT(3)\n+#define GLNVM_ULT_CONF_GLOBAL_AE_S\t\t4\n+#define GLNVM_ULT_CONF_GLOBAL_AE_M\t\tBIT(4)\n+#define GLNVM_ULT_CONF_POR_AE_S\t\t\t5\n+#define GLNVM_ULT_CONF_POR_AE_M\t\t\tBIT(5)\n+#define GLNVM_ULT_RESERVED_2_S\t\t\t6\n+#define GLNVM_ULT_RESERVED_2_M\t\t\tBIT(6)\n+#define GLNVM_ULT_RESERVED_3_S\t\t\t7\n+#define GLNVM_ULT_RESERVED_3_M\t\t\tBIT(7)\n+#define GLNVM_ULT_RESERVED_5_S\t\t\t8\n+#define GLNVM_ULT_RESERVED_5_M\t\t\tBIT(8)\n+#define GLNVM_ULT_CONF_PCIALT_AE_S\t\t9\n+#define GLNVM_ULT_CONF_PCIALT_AE_M\t\tBIT(9)\n+#define GLNVM_ULT_CONF_PE_AE_S\t\t\t10\n+#define GLNVM_ULT_CONF_PE_AE_M\t\t\tBIT(10)\n+#define GLNVM_ULT_RESERVED_4_S\t\t\t11\n+#define GLNVM_ULT_RESERVED_4_M\t\t\tMAKEMASK(0x1FFFFF, 11)\n+#define GL_COTF_MARKER_STATUS\t\t\t0x00200200 /* Reset Source: CORER */\n+#define GL_COTF_MARKER_STATUS_MRKR_BUSY_S\t0\n+#define GL_COTF_MARKER_STATUS_MRKR_BUSY_M\tMAKEMASK(0xFF, 0)\n+#define GL_COTF_MARKER_TRIG_RCU_PRS(_i)\t\t(0x002001D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GL_COTF_MARKER_TRIG_RCU_PRS_MAX_INDEX\t7\n+#define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_S\t0\n+#define GL_COTF_MARKER_TRIG_RCU_PRS_SET_RST_M\tBIT(0)\n+#define GL_PRS_MARKER_ERROR\t\t\t0x00200204 /* Reset Source: CORER */\n+#define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_S\t0\n+#define GL_PRS_MARKER_ERROR_XLR_CFG_ERR_M\tBIT(0)\n+#define GL_PRS_MARKER_ERROR_QH_CFG_ERR_S\t1\n+#define GL_PRS_MARKER_ERROR_QH_CFG_ERR_M\tBIT(1)\n+#define GL_PRS_MARKER_ERROR_COTF_CFG_ERR_S\t2\n+#define GL_PRS_MARKER_ERROR_COTF_CFG_ERR_M\tBIT(2)\n+#define GL_PRS_RX_PIPE_INIT0(_i)\t\t(0x0020000C + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */\n+#define GL_PRS_RX_PIPE_INIT0_MAX_INDEX\t\t6\n+#define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_S\t0\n+#define GL_PRS_RX_PIPE_INIT0_GPCSR_INIT_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PRS_RX_PIPE_INIT1\t\t\t0x00200028 /* Reset Source: CORER */\n+#define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_S\t0\n+#define GL_PRS_RX_PIPE_INIT1_GPCSR_INIT_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PRS_RX_PIPE_INIT2\t\t\t0x0020002C /* Reset Source: CORER */\n+#define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_S\t0\n+#define GL_PRS_RX_PIPE_INIT2_GPCSR_INIT_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PRS_RX_SIZE_CTRL\t\t\t0x00200004 /* Reset Source: CORER */\n+#define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_S\t\t0\n+#define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_M\t\tMAKEMASK(0x3FF, 0)\n+#define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_EN_S\t15\n+#define GL_PRS_RX_SIZE_CTRL_MIN_SIZE_EN_M\tBIT(15)\n+#define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_S\t\t16\n+#define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_M\t\tMAKEMASK(0x3FF, 16)\n+#define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_EN_S\t31\n+#define GL_PRS_RX_SIZE_CTRL_MAX_SIZE_EN_M\tBIT(31)\n+#define GL_PRS_TX_PIPE_INIT0(_i)\t\t(0x00202018 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */\n+#define GL_PRS_TX_PIPE_INIT0_MAX_INDEX\t\t6\n+#define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_S\t0\n+#define GL_PRS_TX_PIPE_INIT0_GPCSR_INIT_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PRS_TX_PIPE_INIT1\t\t\t0x00202034 /* Reset Source: CORER */\n+#define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_S\t0\n+#define GL_PRS_TX_PIPE_INIT1_GPCSR_INIT_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PRS_TX_PIPE_INIT2\t\t\t0x00202038 /* Reset Source: CORER */\n+#define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_S\t0\n+#define GL_PRS_TX_PIPE_INIT2_GPCSR_INIT_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_PRS_TX_SIZE_CTRL\t\t\t0x00202014 /* Reset Source: CORER */\n+#define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_S\t\t0\n+#define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_M\t\tMAKEMASK(0x3FF, 0)\n+#define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_EN_S\t15\n+#define GL_PRS_TX_SIZE_CTRL_MIN_SIZE_EN_M\tBIT(15)\n+#define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_S\t\t16\n+#define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_M\t\tMAKEMASK(0x3FF, 16)\n+#define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_EN_S\t31\n+#define GL_PRS_TX_SIZE_CTRL_MAX_SIZE_EN_M\tBIT(31)\n+#define GL_QH_MARKER_STATUS\t\t\t0x002001FC /* Reset Source: CORER */\n+#define GL_QH_MARKER_STATUS_MRKR_BUSY_S\t\t0\n+#define GL_QH_MARKER_STATUS_MRKR_BUSY_M\t\tMAKEMASK(0xF, 0)\n+#define GL_QH_MARKER_TRIG_RCU_PRS(_i)\t\t(0x002001C4 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */\n+#define GL_QH_MARKER_TRIG_RCU_PRS_MAX_INDEX\t3\n+#define GL_QH_MARKER_TRIG_RCU_PRS_QPID_S\t0\n+#define GL_QH_MARKER_TRIG_RCU_PRS_QPID_M\tMAKEMASK(0x3FFFF, 0)\n+#define GL_QH_MARKER_TRIG_RCU_PRS_PE_TAG_S\t18\n+#define GL_QH_MARKER_TRIG_RCU_PRS_PE_TAG_M\tMAKEMASK(0xFF, 18)\n+#define GL_QH_MARKER_TRIG_RCU_PRS_PORT_NUM_S\t26\n+#define GL_QH_MARKER_TRIG_RCU_PRS_PORT_NUM_M\tMAKEMASK(0x7, 26)\n+#define GL_QH_MARKER_TRIG_RCU_PRS_SET_RST_S\t31\n+#define GL_QH_MARKER_TRIG_RCU_PRS_SET_RST_M\tBIT(31)\n+#define GL_RPRS_ANA_CSR_CTRL\t\t\t0x00200708 /* Reset Source: CORER */\n+#define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_S\t0\n+#define GL_RPRS_ANA_CSR_CTRL_SELECT_EN_M\tBIT(0)\n+#define GL_RPRS_ANA_CSR_CTRL_SELECTED_ANA_S\t1\n+#define GL_RPRS_ANA_CSR_CTRL_SELECTED_ANA_M\tBIT(1)\n+#define GL_TPRS_ANA_CSR_CTRL\t\t\t0x00202100 /* Reset Source: CORER */\n+#define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_S\t0\n+#define GL_TPRS_ANA_CSR_CTRL_SELECT_EN_M\tBIT(0)\n+#define GL_TPRS_ANA_CSR_CTRL_SELECTED_ANA_S\t1\n+#define GL_TPRS_ANA_CSR_CTRL_SELECTED_ANA_M\tBIT(1)\n+#define GL_TPRS_MNG_PM_THR\t\t\t0x00202004 /* Reset Source: CORER */\n+#define GL_TPRS_MNG_PM_THR_MNG_PM_THR_S\t\t0\n+#define GL_TPRS_MNG_PM_THR_MNG_PM_THR_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GL_TPRS_PM_CNT(_i)\t\t\t(0x00202008 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GL_TPRS_PM_CNT_MAX_INDEX\t\t1\n+#define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_S\t\t0\n+#define GL_TPRS_PM_CNT_GL_PRS_PM_CNT_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GL_TPRS_PM_THR\t\t\t\t0x00202000 /* Reset Source: CORER */\n+#define GL_TPRS_PM_THR_PM_THR_S\t\t\t0\n+#define GL_TPRS_PM_THR_PM_THR_M\t\t\tMAKEMASK(0x3FFF, 0)\n+#define GL_XLR_MARKER_LOG_RCU_PRS(_i)\t\t(0x00200208 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GL_XLR_MARKER_LOG_RCU_PRS_MAX_INDEX\t63\n+#define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_S\t0\n+#define GL_XLR_MARKER_LOG_RCU_PRS_XLR_TRIG_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_XLR_MARKER_STATUS(_i)\t\t(0x002001F4 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GL_XLR_MARKER_STATUS_MAX_INDEX\t\t1\n+#define GL_XLR_MARKER_STATUS_MRKR_BUSY_S\t0\n+#define GL_XLR_MARKER_STATUS_MRKR_BUSY_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_XLR_MARKER_TRIG_PE\t\t\t0x005008C0 /* Reset Source: CORER */\n+#define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_S\t0\n+#define GL_XLR_MARKER_TRIG_PE_VM_VF_NUM_M\tMAKEMASK(0x3FF, 0)\n+#define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_S\t10\n+#define GL_XLR_MARKER_TRIG_PE_VM_VF_TYPE_M\tMAKEMASK(0x3, 10)\n+#define GL_XLR_MARKER_TRIG_PE_PF_NUM_S\t\t12\n+#define GL_XLR_MARKER_TRIG_PE_PF_NUM_M\t\tMAKEMASK(0x7, 12)\n+#define GL_XLR_MARKER_TRIG_PE_PORT_NUM_S\t16\n+#define GL_XLR_MARKER_TRIG_PE_PORT_NUM_M\tMAKEMASK(0x7, 16)\n+#define GL_XLR_MARKER_TRIG_RCU_PRS\t\t0x002001C0 /* Reset Source: CORER */\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_S\t0\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_NUM_M\tMAKEMASK(0x3FF, 0)\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_S 10\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_VM_VF_TYPE_M MAKEMASK(0x3, 10)\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_S\t12\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_PF_NUM_M\tMAKEMASK(0x7, 12)\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_S\t16\n+#define GL_XLR_MARKER_TRIG_RCU_PRS_PORT_NUM_M\tMAKEMASK(0x7, 16)\n+#define GL_CLKGATE_EVENTS\t\t\t0x0009DE70 /* Reset Source: PERST */\n+#define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_S 0\n+#define GL_CLKGATE_EVENTS_PRIMARY_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 0)\n+#define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_S 16\n+#define GL_CLKGATE_EVENTS_SIDEBAND_CLKGATE_EVENTS_M MAKEMASK(0xFFFF, 16)\n+#define GLPCI_BYTCTH_NP_C\t\t\t0x000BFDA8 /* Reset Source: PCIR */\n+#define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_S\t0\n+#define GLPCI_BYTCTH_NP_C_PCI_COUNT_BW_BCT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPCI_BYTCTH_P\t\t\t\t0x0009E970 /* Reset Source: PCIR */\n+#define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_S\t0\n+#define GLPCI_BYTCTH_P_PCI_COUNT_BW_BCT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPCI_BYTCTL_NP_C\t\t\t0x000BFDAC /* Reset Source: PCIR */\n+#define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_S\t0\n+#define GLPCI_BYTCTL_NP_C_PCI_COUNT_BW_BCT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPCI_BYTCTL_P\t\t\t\t0x0009E994 /* Reset Source: PCIR */\n+#define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_S\t0\n+#define GLPCI_BYTCTL_P_PCI_COUNT_BW_BCT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPCI_CAPCTRL\t\t\t\t0x0009DE88 /* Reset Source: PCIR */\n+#define GLPCI_CAPCTRL_VPD_EN_S\t\t\t0\n+#define GLPCI_CAPCTRL_VPD_EN_M\t\t\tBIT(0)\n+#define GLPCI_CAPSUP\t\t\t\t0x0009DE8C /* Reset Source: PCIR */\n+#define GLPCI_CAPSUP_PCIE_VER_S\t\t\t0\n+#define GLPCI_CAPSUP_PCIE_VER_M\t\t\tBIT(0)\n+#define GLPCI_CAPSUP_RESERVED_2_S\t\t1\n+#define GLPCI_CAPSUP_RESERVED_2_M\t\tBIT(1)\n+#define GLPCI_CAPSUP_LTR_EN_S\t\t\t2\n+#define GLPCI_CAPSUP_LTR_EN_M\t\t\tBIT(2)\n+#define GLPCI_CAPSUP_TPH_EN_S\t\t\t3\n+#define GLPCI_CAPSUP_TPH_EN_M\t\t\tBIT(3)\n+#define GLPCI_CAPSUP_ARI_EN_S\t\t\t4\n+#define GLPCI_CAPSUP_ARI_EN_M\t\t\tBIT(4)\n+#define GLPCI_CAPSUP_IOV_EN_S\t\t\t5\n+#define GLPCI_CAPSUP_IOV_EN_M\t\t\tBIT(5)\n+#define GLPCI_CAPSUP_ACS_EN_S\t\t\t6\n+#define GLPCI_CAPSUP_ACS_EN_M\t\t\tBIT(6)\n+#define GLPCI_CAPSUP_SEC_EN_S\t\t\t7\n+#define GLPCI_CAPSUP_SEC_EN_M\t\t\tBIT(7)\n+#define GLPCI_CAPSUP_PASID_EN_S\t\t\t8\n+#define GLPCI_CAPSUP_PASID_EN_M\t\t\tBIT(8)\n+#define GLPCI_CAPSUP_DLFE_EN_S\t\t\t9\n+#define GLPCI_CAPSUP_DLFE_EN_M\t\t\tBIT(9)\n+#define GLPCI_CAPSUP_GEN4_EXT_EN_S\t\t10\n+#define GLPCI_CAPSUP_GEN4_EXT_EN_M\t\tBIT(10)\n+#define GLPCI_CAPSUP_GEN4_MARG_EN_S\t\t11\n+#define GLPCI_CAPSUP_GEN4_MARG_EN_M\t\tBIT(11)\n+#define GLPCI_CAPSUP_ECRC_GEN_EN_S\t\t16\n+#define GLPCI_CAPSUP_ECRC_GEN_EN_M\t\tBIT(16)\n+#define GLPCI_CAPSUP_ECRC_CHK_EN_S\t\t17\n+#define GLPCI_CAPSUP_ECRC_CHK_EN_M\t\tBIT(17)\n+#define GLPCI_CAPSUP_IDO_EN_S\t\t\t18\n+#define GLPCI_CAPSUP_IDO_EN_M\t\t\tBIT(18)\n+#define GLPCI_CAPSUP_MSI_MASK_S\t\t\t19\n+#define GLPCI_CAPSUP_MSI_MASK_M\t\t\tBIT(19)\n+#define GLPCI_CAPSUP_CSR_CONF_EN_S\t\t20\n+#define GLPCI_CAPSUP_CSR_CONF_EN_M\t\tBIT(20)\n+#define GLPCI_CAPSUP_WAKUP_EN_S\t\t\t21\n+#define GLPCI_CAPSUP_WAKUP_EN_M\t\t\tBIT(21)\n+#define GLPCI_CAPSUP_LOAD_SUBSYS_ID_S\t\t30\n+#define GLPCI_CAPSUP_LOAD_SUBSYS_ID_M\t\tBIT(30)\n+#define GLPCI_CAPSUP_LOAD_DEV_ID_S\t\t31\n+#define GLPCI_CAPSUP_LOAD_DEV_ID_M\t\tBIT(31)\n+#define GLPCI_CNF\t\t\t\t0x0009DEA0 /* Reset Source: POR */\n+#define GLPCI_CNF_FLEX10_S\t\t\t1\n+#define GLPCI_CNF_FLEX10_M\t\t\tBIT(1)\n+#define GLPCI_CNF_WAKE_PIN_EN_S\t\t\t2\n+#define GLPCI_CNF_WAKE_PIN_EN_M\t\t\tBIT(2)\n+#define GLPCI_CNF_MSIX_ECC_BLOCK_DISABLE_S\t3\n+#define GLPCI_CNF_MSIX_ECC_BLOCK_DISABLE_M\tBIT(3)\n+#define GLPCI_CNF2\t\t\t\t0x000BE004 /* Reset Source: PCIR */\n+#define GLPCI_CNF2_RO_DIS_S\t\t\t0\n+#define GLPCI_CNF2_RO_DIS_M\t\t\tBIT(0)\n+#define GLPCI_CNF2_CACHELINE_SIZE_S\t\t1\n+#define GLPCI_CNF2_CACHELINE_SIZE_M\t\tBIT(1)\n+#define GLPCI_DREVID\t\t\t\t0x0009E9AC /* Reset Source: PCIR */\n+#define GLPCI_DREVID_DEFAULT_REVID_S\t\t0\n+#define GLPCI_DREVID_DEFAULT_REVID_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPCI_GSCL_1_NP_C\t\t\t0x000BFDA4 /* Reset Source: PCIR */\n+#define GLPCI_GSCL_1_NP_C_RT_MODE_S\t\t8\n+#define GLPCI_GSCL_1_NP_C_RT_MODE_M\t\tBIT(8)\n+#define GLPCI_GSCL_1_NP_C_RT_EVENT_S\t\t9\n+#define GLPCI_GSCL_1_NP_C_RT_EVENT_M\t\tMAKEMASK(0x1F, 9)\n+#define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EN_S\t14\n+#define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EN_M\tBIT(14)\n+#define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EV_S\t15\n+#define GLPCI_GSCL_1_NP_C_PCI_COUNT_BW_EV_M\tMAKEMASK(0x1F, 15)\n+#define GLPCI_GSCL_1_NP_C_GIO_COUNT_RESET_S\t29\n+#define GLPCI_GSCL_1_NP_C_GIO_COUNT_RESET_M\tBIT(29)\n+#define GLPCI_GSCL_1_NP_C_GIO_COUNT_STOP_S\t30\n+#define GLPCI_GSCL_1_NP_C_GIO_COUNT_STOP_M\tBIT(30)\n+#define GLPCI_GSCL_1_NP_C_GIO_COUNT_START_S\t31\n+#define GLPCI_GSCL_1_NP_C_GIO_COUNT_START_M\tBIT(31)\n+#define GLPCI_GSCL_1_P\t\t\t\t0x0009E9B4 /* Reset Source: PCIR */\n+#define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_S\t\t0\n+#define GLPCI_GSCL_1_P_GIO_COUNT_EN_0_M\t\tBIT(0)\n+#define GLPCI_GSCL_1_P_GIO_COUNT_EN_1_S\t\t1\n+#define GLPCI_GSCL_1_P_GIO_COUNT_EN_1_M\t\tBIT(1)\n+#define GLPCI_GSCL_1_P_GIO_COUNT_EN_2_S\t\t2\n+#define GLPCI_GSCL_1_P_GIO_COUNT_EN_2_M\t\tBIT(2)\n+#define GLPCI_GSCL_1_P_GIO_COUNT_EN_3_S\t\t3\n+#define GLPCI_GSCL_1_P_GIO_COUNT_EN_3_M\t\tBIT(3)\n+#define GLPCI_GSCL_1_P_LBC_ENABLE_0_S\t\t4\n+#define GLPCI_GSCL_1_P_LBC_ENABLE_0_M\t\tBIT(4)\n+#define GLPCI_GSCL_1_P_LBC_ENABLE_1_S\t\t5\n+#define GLPCI_GSCL_1_P_LBC_ENABLE_1_M\t\tBIT(5)\n+#define GLPCI_GSCL_1_P_LBC_ENABLE_2_S\t\t6\n+#define GLPCI_GSCL_1_P_LBC_ENABLE_2_M\t\tBIT(6)\n+#define GLPCI_GSCL_1_P_LBC_ENABLE_3_S\t\t7\n+#define GLPCI_GSCL_1_P_LBC_ENABLE_3_M\t\tBIT(7)\n+#define GLPCI_GSCL_1_P_PCI_COUNT_BW_EN_S\t14\n+#define GLPCI_GSCL_1_P_PCI_COUNT_BW_EN_M\tBIT(14)\n+#define GLPCI_GSCL_1_P_GIO_64_BIT_EN_S\t\t28\n+#define GLPCI_GSCL_1_P_GIO_64_BIT_EN_M\t\tBIT(28)\n+#define GLPCI_GSCL_1_P_GIO_COUNT_RESET_S\t29\n+#define GLPCI_GSCL_1_P_GIO_COUNT_RESET_M\tBIT(29)\n+#define GLPCI_GSCL_1_P_GIO_COUNT_STOP_S\t\t30\n+#define GLPCI_GSCL_1_P_GIO_COUNT_STOP_M\t\tBIT(30)\n+#define GLPCI_GSCL_1_P_GIO_COUNT_START_S\t31\n+#define GLPCI_GSCL_1_P_GIO_COUNT_START_M\tBIT(31)\n+#define GLPCI_GSCL_2\t\t\t\t0x0009E998 /* Reset Source: PCIR */\n+#define GLPCI_GSCL_2_GIO_EVENT_NUM_0_S\t\t0\n+#define GLPCI_GSCL_2_GIO_EVENT_NUM_0_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPCI_GSCL_2_GIO_EVENT_NUM_1_S\t\t8\n+#define GLPCI_GSCL_2_GIO_EVENT_NUM_1_M\t\tMAKEMASK(0xFF, 8)\n+#define GLPCI_GSCL_2_GIO_EVENT_NUM_2_S\t\t16\n+#define GLPCI_GSCL_2_GIO_EVENT_NUM_2_M\t\tMAKEMASK(0xFF, 16)\n+#define GLPCI_GSCL_2_GIO_EVENT_NUM_3_S\t\t24\n+#define GLPCI_GSCL_2_GIO_EVENT_NUM_3_M\t\tMAKEMASK(0xFF, 24)\n+#define GLPCI_GSCL_5_8(_i)\t\t\t(0x0009E954 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */\n+#define GLPCI_GSCL_5_8_MAX_INDEX\t\t3\n+#define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_S\t0\n+#define GLPCI_GSCL_5_8_LBC_THRESHOLD_N_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPCI_GSCL_5_8_LBC_TIMER_N_S\t\t16\n+#define GLPCI_GSCL_5_8_LBC_TIMER_N_M\t\tMAKEMASK(0xFFFF, 16)\n+#define GLPCI_GSCN_0_3(_i)\t\t\t(0x0009E99C + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: PCIR */\n+#define GLPCI_GSCN_0_3_MAX_INDEX\t\t3\n+#define GLPCI_GSCN_0_3_EVENT_COUNTER_S\t\t0\n+#define GLPCI_GSCN_0_3_EVENT_COUNTER_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPCI_LATCT_NP_C\t\t\t0x000BFDA0 /* Reset Source: PCIR */\n+#define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_S\t0\n+#define GLPCI_LATCT_NP_C_PCI_LATENCY_COUNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPCI_LBARCTRL\t\t\t\t0x0009DE74 /* Reset Source: POR */\n+#define GLPCI_LBARCTRL_PREFBAR_S\t\t0\n+#define GLPCI_LBARCTRL_PREFBAR_M\t\tBIT(0)\n+#define GLPCI_LBARCTRL_BAR32_S\t\t\t1\n+#define GLPCI_LBARCTRL_BAR32_M\t\t\tBIT(1)\n+#define GLPCI_LBARCTRL_PAGES_SPACE_EN_PF_S\t2\n+#define GLPCI_LBARCTRL_PAGES_SPACE_EN_PF_M\tBIT(2)\n+#define GLPCI_LBARCTRL_FLASH_EXPOSE_S\t\t3\n+#define GLPCI_LBARCTRL_FLASH_EXPOSE_M\t\tBIT(3)\n+#define GLPCI_LBARCTRL_PE_DB_SIZE_S\t\t4\n+#define GLPCI_LBARCTRL_PE_DB_SIZE_M\t\tMAKEMASK(0x3, 4)\n+#define GLPCI_LBARCTRL_PAGES_SPACE_EN_VF_S\t9\n+#define GLPCI_LBARCTRL_PAGES_SPACE_EN_VF_M\tBIT(9)\n+#define GLPCI_LBARCTRL_EXROM_SIZE_S\t\t11\n+#define GLPCI_LBARCTRL_EXROM_SIZE_M\t\tMAKEMASK(0x7, 11)\n+#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_S\t\t14\n+#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_M\t\tMAKEMASK(0x3, 14)\n+#define GLPCI_LINKCAP\t\t\t\t0x0009DE90 /* Reset Source: PCIR */\n+#define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_S\t0\n+#define GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_M\tMAKEMASK(0x3F, 0)\n+#define GLPCI_LINKCAP_MAX_LINK_WIDTH_S\t\t9\n+#define GLPCI_LINKCAP_MAX_LINK_WIDTH_M\t\tMAKEMASK(0xF, 9)\n+#define GLPCI_NPQ_CFG\t\t\t\t0x000BFD80 /* Reset Source: PCIR */\n+#define GLPCI_NPQ_CFG_EXTEND_TO_S\t\t0\n+#define GLPCI_NPQ_CFG_EXTEND_TO_M\t\tBIT(0)\n+#define GLPCI_NPQ_CFG_SMALL_TO_S\t\t1\n+#define GLPCI_NPQ_CFG_SMALL_TO_M\t\tBIT(1)\n+#define GLPCI_NPQ_CFG_WEIGHT_AVG_S\t\t2\n+#define GLPCI_NPQ_CFG_WEIGHT_AVG_M\t\tMAKEMASK(0xF, 2)\n+#define GLPCI_NPQ_CFG_NPQ_SPARE_S\t\t6\n+#define GLPCI_NPQ_CFG_NPQ_SPARE_M\t\tMAKEMASK(0x3FF, 6)\n+#define GLPCI_NPQ_CFG_NPQ_ERR_STAT_S\t\t16\n+#define GLPCI_NPQ_CFG_NPQ_ERR_STAT_M\t\tMAKEMASK(0xF, 16)\n+#define GLPCI_PKTCT_NP_C\t\t\t0x000BFD9C /* Reset Source: PCIR */\n+#define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_S\t0\n+#define GLPCI_PKTCT_NP_C_PCI_COUNT_BW_PCT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPCI_PKTCT_P\t\t\t\t0x0009E9B0 /* Reset Source: PCIR */\n+#define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_S\t0\n+#define GLPCI_PKTCT_P_PCI_COUNT_BW_PCT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPCI_PMSUP\t\t\t\t0x0009DE94 /* Reset Source: PCIR */\n+#define GLPCI_PMSUP_RESERVED_0_S\t\t0\n+#define GLPCI_PMSUP_RESERVED_0_M\t\tMAKEMASK(0x3, 0)\n+#define GLPCI_PMSUP_RESERVED_1_S\t\t2\n+#define GLPCI_PMSUP_RESERVED_1_M\t\tMAKEMASK(0x7, 2)\n+#define GLPCI_PMSUP_RESERVED_2_S\t\t5\n+#define GLPCI_PMSUP_RESERVED_2_M\t\tMAKEMASK(0x7, 5)\n+#define GLPCI_PMSUP_L0S_ACC_LAT_S\t\t8\n+#define GLPCI_PMSUP_L0S_ACC_LAT_M\t\tMAKEMASK(0x7, 8)\n+#define GLPCI_PMSUP_L1_ACC_LAT_S\t\t11\n+#define GLPCI_PMSUP_L1_ACC_LAT_M\t\tMAKEMASK(0x7, 11)\n+#define GLPCI_PMSUP_RESERVED_3_S\t\t14\n+#define GLPCI_PMSUP_RESERVED_3_M\t\tBIT(14)\n+#define GLPCI_PMSUP_OBFF_SUP_S\t\t\t15\n+#define GLPCI_PMSUP_OBFF_SUP_M\t\t\tMAKEMASK(0x3, 15)\n+#define GLPCI_PUSH_PE_IF_TO_STATUS\t\t0x0009DF44 /* Reset Source: PCIR */\n+#define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_S 0\n+#define GLPCI_PUSH_PE_IF_TO_STATUS_GLPCI_PUSH_PE_IF_TO_STATUS_M BIT(0)\n+#define GLPCI_PWRDATA\t\t\t\t0x0009DE7C /* Reset Source: PCIR */\n+#define GLPCI_PWRDATA_D0_POWER_S\t\t0\n+#define GLPCI_PWRDATA_D0_POWER_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPCI_PWRDATA_COMM_POWER_S\t\t8\n+#define GLPCI_PWRDATA_COMM_POWER_M\t\tMAKEMASK(0xFF, 8)\n+#define GLPCI_PWRDATA_D3_POWER_S\t\t16\n+#define GLPCI_PWRDATA_D3_POWER_M\t\tMAKEMASK(0xFF, 16)\n+#define GLPCI_PWRDATA_DATA_SCALE_S\t\t24\n+#define GLPCI_PWRDATA_DATA_SCALE_M\t\tMAKEMASK(0x3, 24)\n+#define GLPCI_REVID\t\t\t\t0x0009DE98 /* Reset Source: PCIR */\n+#define GLPCI_REVID_NVM_REVID_S\t\t\t0\n+#define GLPCI_REVID_NVM_REVID_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPCI_SERH\t\t\t\t0x0009DE84 /* Reset Source: PCIR */\n+#define GLPCI_SERH_SER_NUM_H_S\t\t\t0\n+#define GLPCI_SERH_SER_NUM_H_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define GLPCI_SERL\t\t\t\t0x0009DE80 /* Reset Source: PCIR */\n+#define GLPCI_SERL_SER_NUM_L_S\t\t\t0\n+#define GLPCI_SERL_SER_NUM_L_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPCI_SUBVENID\t\t\t\t0x0009DEE8 /* Reset Source: PCIR */\n+#define GLPCI_SUBVENID_SUB_VEN_ID_S\t\t0\n+#define GLPCI_SUBVENID_SUB_VEN_ID_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GLPCI_UPADD\t\t\t\t0x000BE0D4 /* Reset Source: PCIR */\n+#define GLPCI_UPADD_ADDRESS_S\t\t\t1\n+#define GLPCI_UPADD_ADDRESS_M\t\t\tMAKEMASK(0x7FFFFFFF, 1)\n+#define GLPCI_VENDORID\t\t\t\t0x0009DEC8 /* Reset Source: PCIR */\n+#define GLPCI_VENDORID_VENDORID_S\t\t0\n+#define GLPCI_VENDORID_VENDORID_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GLPCI_VFSUP\t\t\t\t0x0009DE9C /* Reset Source: PCIR */\n+#define GLPCI_VFSUP_VF_PREFETCH_S\t\t0\n+#define GLPCI_VFSUP_VF_PREFETCH_M\t\tBIT(0)\n+#define GLPCI_VFSUP_VR_BAR_TYPE_S\t\t1\n+#define GLPCI_VFSUP_VR_BAR_TYPE_M\t\tBIT(1)\n+#define GLPCI_WATMK_CLNT_PIPEMON\t\t0x000BFD90 /* Reset Source: PCIR */\n+#define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_S\t0\n+#define GLPCI_WATMK_CLNT_PIPEMON_DATA_LINES_M\tMAKEMASK(0xFFFF, 0)\n+#define PF_FUNC_RID\t\t\t\t0x0009E880 /* Reset Source: PCIR */\n+#define PF_FUNC_RID_FUNCTION_NUMBER_S\t\t0\n+#define PF_FUNC_RID_FUNCTION_NUMBER_M\t\tMAKEMASK(0x7, 0)\n+#define PF_FUNC_RID_DEVICE_NUMBER_S\t\t3\n+#define PF_FUNC_RID_DEVICE_NUMBER_M\t\tMAKEMASK(0x1F, 3)\n+#define PF_FUNC_RID_BUS_NUMBER_S\t\t8\n+#define PF_FUNC_RID_BUS_NUMBER_M\t\tMAKEMASK(0xFF, 8)\n+#define PF_PCI_CIAA\t\t\t\t0x0009E580 /* Reset Source: FLR */\n+#define PF_PCI_CIAA_ADDRESS_S\t\t\t0\n+#define PF_PCI_CIAA_ADDRESS_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define PF_PCI_CIAA_VF_NUM_S\t\t\t12\n+#define PF_PCI_CIAA_VF_NUM_M\t\t\tMAKEMASK(0xFF, 12)\n+#define PF_PCI_CIAD\t\t\t\t0x0009E500 /* Reset Source: FLR */\n+#define PF_PCI_CIAD_DATA_S\t\t\t0\n+#define PF_PCI_CIAD_DATA_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFPCI_CLASS\t\t\t\t0x0009DB00 /* Reset Source: PCIR */\n+#define PFPCI_CLASS_STORAGE_CLASS_S\t\t0\n+#define PFPCI_CLASS_STORAGE_CLASS_M\t\tBIT(0)\n+#define PFPCI_CLASS_PF_IS_LAN_S\t\t\t2\n+#define PFPCI_CLASS_PF_IS_LAN_M\t\t\tBIT(2)\n+#define PFPCI_CNF\t\t\t\t0x0009DF00 /* Reset Source: PCIR */\n+#define PFPCI_CNF_MSI_EN_S\t\t\t2\n+#define PFPCI_CNF_MSI_EN_M\t\t\tBIT(2)\n+#define PFPCI_CNF_EXROM_DIS_S\t\t\t3\n+#define PFPCI_CNF_EXROM_DIS_M\t\t\tBIT(3)\n+#define PFPCI_CNF_IO_BAR_S\t\t\t4\n+#define PFPCI_CNF_IO_BAR_M\t\t\tBIT(4)\n+#define PFPCI_CNF_INT_PIN_S\t\t\t5\n+#define PFPCI_CNF_INT_PIN_M\t\t\tMAKEMASK(0x3, 5)\n+#define PFPCI_DEVID\t\t\t\t0x0009DE00 /* Reset Source: PCIR */\n+#define PFPCI_DEVID_PF_DEV_ID_S\t\t\t0\n+#define PFPCI_DEVID_PF_DEV_ID_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define PFPCI_DEVID_VF_DEV_ID_S\t\t\t16\n+#define PFPCI_DEVID_VF_DEV_ID_M\t\t\tMAKEMASK(0xFFFF, 16)\n+#define PFPCI_FACTPS\t\t\t\t0x0009E900 /* Reset Source: FLR */\n+#define PFPCI_FACTPS_FUNC_POWER_STATE_S\t\t0\n+#define PFPCI_FACTPS_FUNC_POWER_STATE_M\t\tMAKEMASK(0x3, 0)\n+#define PFPCI_FACTPS_FUNC_AUX_EN_S\t\t3\n+#define PFPCI_FACTPS_FUNC_AUX_EN_M\t\tBIT(3)\n+#define PFPCI_FUNC\t\t\t\t0x0009D980 /* Reset Source: POR */\n+#define PFPCI_FUNC_FUNC_DIS_S\t\t\t0\n+#define PFPCI_FUNC_FUNC_DIS_M\t\t\tBIT(0)\n+#define PFPCI_FUNC_ALLOW_FUNC_DIS_S\t\t1\n+#define PFPCI_FUNC_ALLOW_FUNC_DIS_M\t\tBIT(1)\n+#define PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_S\t2\n+#define PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_M\tBIT(2)\n+#define PFPCI_PF_FLUSH_DONE\t\t\t0x0009E400 /* Reset Source: PCIR */\n+#define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_S\t0\n+#define PFPCI_PF_FLUSH_DONE_FLUSH_DONE_M\tBIT(0)\n+#define PFPCI_PM\t\t\t\t0x0009DA80 /* Reset Source: POR */\n+#define PFPCI_PM_PME_EN_S\t\t\t0\n+#define PFPCI_PM_PME_EN_M\t\t\tBIT(0)\n+#define PFPCI_STATUS1\t\t\t\t0x0009DA00 /* Reset Source: POR */\n+#define PFPCI_STATUS1_FUNC_VALID_S\t\t0\n+#define PFPCI_STATUS1_FUNC_VALID_M\t\tBIT(0)\n+#define PFPCI_SUBSYSID\t\t\t\t0x0009D880 /* Reset Source: PCIR */\n+#define PFPCI_SUBSYSID_PF_SUBSYS_ID_S\t\t0\n+#define PFPCI_SUBSYSID_PF_SUBSYS_ID_M\t\tMAKEMASK(0xFFFF, 0)\n+#define PFPCI_SUBSYSID_VF_SUBSYS_ID_S\t\t16\n+#define PFPCI_SUBSYSID_VF_SUBSYS_ID_M\t\tMAKEMASK(0xFFFF, 16)\n+#define PFPCI_VF_FLUSH_DONE(_VF)\t\t(0x0009E000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PCIR */\n+#define PFPCI_VF_FLUSH_DONE_MAX_INDEX\t\t255\n+#define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_S\t0\n+#define PFPCI_VF_FLUSH_DONE_FLUSH_DONE_M\tBIT(0)\n+#define PFPCI_VM_FLUSH_DONE\t\t\t0x0009E480 /* Reset Source: PCIR */\n+#define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_S\t0\n+#define PFPCI_VM_FLUSH_DONE_FLUSH_DONE_M\tBIT(0)\n+#define PFPCI_VMINDEX\t\t\t\t0x0009E600 /* Reset Source: PCIR */\n+#define PFPCI_VMINDEX_VMINDEX_S\t\t\t0\n+#define PFPCI_VMINDEX_VMINDEX_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PFPCI_VMPEND\t\t\t\t0x0009E800 /* Reset Source: PCIR */\n+#define PFPCI_VMPEND_PENDING_S\t\t\t0\n+#define PFPCI_VMPEND_PENDING_M\t\t\tBIT(0)\n+#define PQ_FIFO_STATUS\t\t\t\t0x0009DF40 /* Reset Source: PCIR */\n+#define PQ_FIFO_STATUS_PQ_FIFO_COUNT_S\t\t0\n+#define PQ_FIFO_STATUS_PQ_FIFO_COUNT_M\t\tMAKEMASK(0x7FFFFFFF, 0)\n+#define PQ_FIFO_STATUS_PQ_FIFO_EMPTY_S\t\t31\n+#define PQ_FIFO_STATUS_PQ_FIFO_EMPTY_M\t\tBIT(31)\n+#define GLPE_CPUSTATUS0\t\t\t\t0x0050BA5C /* Reset Source: CORER */\n+#define GLPE_CPUSTATUS0_PECPUSTATUS0_S\t\t0\n+#define GLPE_CPUSTATUS0_PECPUSTATUS0_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPE_CPUSTATUS1\t\t\t\t0x0050BA60 /* Reset Source: CORER */\n+#define GLPE_CPUSTATUS1_PECPUSTATUS1_S\t\t0\n+#define GLPE_CPUSTATUS1_PECPUSTATUS1_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPE_CPUSTATUS2\t\t\t\t0x0050BA64 /* Reset Source: CORER */\n+#define GLPE_CPUSTATUS2_PECPUSTATUS2_S\t\t0\n+#define GLPE_CPUSTATUS2_PECPUSTATUS2_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPE_MDQ_BASE(_i)\t\t\t(0x00536000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLPE_MDQ_BASE_MAX_INDEX\t\t\t511\n+#define GLPE_MDQ_BASE_MDOC_INDEX_S\t\t0\n+#define GLPE_MDQ_BASE_MDOC_INDEX_M\t\tMAKEMASK(0xFFFFFFF, 0)\n+#define GLPE_MDQ_PTR(_i)\t\t\t(0x00537000 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLPE_MDQ_PTR_MAX_INDEX\t\t\t511\n+#define GLPE_MDQ_PTR_MDQ_HEAD_S\t\t\t0\n+#define GLPE_MDQ_PTR_MDQ_HEAD_M\t\t\tMAKEMASK(0x3FFF, 0)\n+#define GLPE_MDQ_PTR_MDQ_TAIL_S\t\t\t16\n+#define GLPE_MDQ_PTR_MDQ_TAIL_M\t\t\tMAKEMASK(0x3FFF, 16)\n+#define GLPE_MDQ_SIZE(_i)\t\t\t(0x00536800 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLPE_MDQ_SIZE_MAX_INDEX\t\t\t511\n+#define GLPE_MDQ_SIZE_MDQ_SIZE_S\t\t0\n+#define GLPE_MDQ_SIZE_MDQ_SIZE_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLPE_PEPM_CTRL\t\t\t\t0x0050C000 /* Reset Source: PERST */\n+#define GLPE_PEPM_CTRL_PEPM_ENABLE_S\t\t0\n+#define GLPE_PEPM_CTRL_PEPM_ENABLE_M\t\tBIT(0)\n+#define GLPE_PEPM_CTRL_PEPM_HALT_S\t\t8\n+#define GLPE_PEPM_CTRL_PEPM_HALT_M\t\tBIT(8)\n+#define GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_S\t16\n+#define GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_M\tMAKEMASK(0xFF, 16)\n+#define GLPE_PEPM_DEALLOC\t\t\t0x0050C004 /* Reset Source: PERST */\n+#define GLPE_PEPM_DEALLOC_MDQ_CREDITS_S\t\t0\n+#define GLPE_PEPM_DEALLOC_MDQ_CREDITS_M\t\tMAKEMASK(0x3FFF, 0)\n+#define GLPE_PEPM_DEALLOC_PSQ_CREDITS_S\t\t14\n+#define GLPE_PEPM_DEALLOC_PSQ_CREDITS_M\t\tMAKEMASK(0x1F, 14)\n+#define GLPE_PEPM_DEALLOC_PQID_S\t\t19\n+#define GLPE_PEPM_DEALLOC_PQID_M\t\tMAKEMASK(0x1FF, 19)\n+#define GLPE_PEPM_DEALLOC_PORT_S\t\t28\n+#define GLPE_PEPM_DEALLOC_PORT_M\t\tMAKEMASK(0x7, 28)\n+#define GLPE_PEPM_DEALLOC_DEALLOC_RDY_S\t\t31\n+#define GLPE_PEPM_DEALLOC_DEALLOC_RDY_M\t\tBIT(31)\n+#define GLPE_PEPM_PSQ_COUNT\t\t\t0x0050C020 /* Reset Source: PERST */\n+#define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_S\t0\n+#define GLPE_PEPM_PSQ_COUNT_PEPM_PSQ_COUNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_PEPM_THRESH(_i)\t\t\t(0x0050C840 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */\n+#define GLPE_PEPM_THRESH_MAX_INDEX\t\t511\n+#define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_S\t0\n+#define GLPE_PEPM_THRESH_PEPM_PSQ_THRESH_M\tMAKEMASK(0x1F, 0)\n+#define GLPE_PEPM_THRESH_PEPM_MDQ_THRESH_S\t16\n+#define GLPE_PEPM_THRESH_PEPM_MDQ_THRESH_M\tMAKEMASK(0x3FFF, 16)\n+#define GLPE_PFAEQEDROPCNT(_i)\t\t\t(0x00503240 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPE_PFAEQEDROPCNT_MAX_INDEX\t\t7\n+#define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_S\t0\n+#define GLPE_PFAEQEDROPCNT_AEQEDROPCNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_PFCEQEDROPCNT(_i)\t\t\t(0x00503220 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPE_PFCEQEDROPCNT_MAX_INDEX\t\t7\n+#define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_S\t0\n+#define GLPE_PFCEQEDROPCNT_CEQEDROPCNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_PFCQEDROPCNT(_i)\t\t\t(0x00503200 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPE_PFCQEDROPCNT_MAX_INDEX\t\t7\n+#define GLPE_PFCQEDROPCNT_CQEDROPCNT_S\t\t0\n+#define GLPE_PFCQEDROPCNT_CQEDROPCNT_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_PFFLMOOISCALLOCERR(_i)\t\t(0x0050B960 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPE_PFFLMOOISCALLOCERR_MAX_INDEX\t7\n+#define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_S\t0\n+#define GLPE_PFFLMOOISCALLOCERR_ERROR_COUNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_PFFLMQ1ALLOCERR(_i)\t\t(0x0050B920 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPE_PFFLMQ1ALLOCERR_MAX_INDEX\t\t7\n+#define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_S\t0\n+#define GLPE_PFFLMQ1ALLOCERR_ERROR_COUNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_PFFLMRRFALLOCERR(_i)\t\t(0x0050B940 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPE_PFFLMRRFALLOCERR_MAX_INDEX\t\t7\n+#define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_S\t0\n+#define GLPE_PFFLMRRFALLOCERR_ERROR_COUNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_PFFLMXMITALLOCERR(_i)\t\t(0x0050B900 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPE_PFFLMXMITALLOCERR_MAX_INDEX\t7\n+#define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_S\t0\n+#define GLPE_PFFLMXMITALLOCERR_ERROR_COUNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_PFTCPNOW50USCNT(_i)\t\t(0x0050B8C0 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPE_PFTCPNOW50USCNT_MAX_INDEX\t\t7\n+#define GLPE_PFTCPNOW50USCNT_CNT_S\t\t0\n+#define GLPE_PFTCPNOW50USCNT_CNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPE_PUSH_PEPM\t\t\t\t0x0053241C /* Reset Source: CORER */\n+#define GLPE_PUSH_PEPM_MDQ_CREDITS_S\t\t0\n+#define GLPE_PUSH_PEPM_MDQ_CREDITS_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPE_VFAEQEDROPCNT(_i)\t\t\t(0x00503100 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLPE_VFAEQEDROPCNT_MAX_INDEX\t\t31\n+#define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_S\t0\n+#define GLPE_VFAEQEDROPCNT_AEQEDROPCNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_VFCEQEDROPCNT(_i)\t\t\t(0x00503080 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLPE_VFCEQEDROPCNT_MAX_INDEX\t\t31\n+#define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_S\t0\n+#define GLPE_VFCEQEDROPCNT_CEQEDROPCNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_VFCQEDROPCNT(_i)\t\t\t(0x00503000 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLPE_VFCQEDROPCNT_MAX_INDEX\t\t31\n+#define GLPE_VFCQEDROPCNT_CQEDROPCNT_S\t\t0\n+#define GLPE_VFCQEDROPCNT_CQEDROPCNT_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_VFFLMOOISCALLOCERR(_i)\t\t(0x0050B580 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLPE_VFFLMOOISCALLOCERR_MAX_INDEX\t31\n+#define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_S\t0\n+#define GLPE_VFFLMOOISCALLOCERR_ERROR_COUNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_VFFLMQ1ALLOCERR(_i)\t\t(0x0050B480 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLPE_VFFLMQ1ALLOCERR_MAX_INDEX\t\t31\n+#define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_S\t0\n+#define GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_VFFLMRRFALLOCERR(_i)\t\t(0x0050B500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLPE_VFFLMRRFALLOCERR_MAX_INDEX\t\t31\n+#define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_S\t0\n+#define GLPE_VFFLMRRFALLOCERR_ERROR_COUNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_VFFLMXMITALLOCERR(_i)\t\t(0x0050B400 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLPE_VFFLMXMITALLOCERR_MAX_INDEX\t31\n+#define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_S\t0\n+#define GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPE_VFTCPNOW50USCNT(_i)\t\t(0x0050B300 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: PE_CORER */\n+#define GLPE_VFTCPNOW50USCNT_MAX_INDEX\t\t31\n+#define GLPE_VFTCPNOW50USCNT_CNT_S\t\t0\n+#define GLPE_VFTCPNOW50USCNT_CNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFPE_AEQALLOC\t\t\t\t0x00502D00 /* Reset Source: PFR */\n+#define PFPE_AEQALLOC_AECOUNT_S\t\t\t0\n+#define PFPE_AEQALLOC_AECOUNT_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFPE_CCQPHIGH\t\t\t\t0x0050A100 /* Reset Source: PFR */\n+#define PFPE_CCQPHIGH_PECCQPHIGH_S\t\t0\n+#define PFPE_CCQPHIGH_PECCQPHIGH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFPE_CCQPLOW\t\t\t\t0x0050A080 /* Reset Source: PFR */\n+#define PFPE_CCQPLOW_PECCQPLOW_S\t\t0\n+#define PFPE_CCQPLOW_PECCQPLOW_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFPE_CCQPSTATUS\t\t\t\t0x0050A000 /* Reset Source: PFR */\n+#define PFPE_CCQPSTATUS_CCQP_DONE_S\t\t0\n+#define PFPE_CCQPSTATUS_CCQP_DONE_M\t\tBIT(0)\n+#define PFPE_CCQPSTATUS_HMC_PROFILE_S\t\t4\n+#define PFPE_CCQPSTATUS_HMC_PROFILE_M\t\tMAKEMASK(0x7, 4)\n+#define PFPE_CCQPSTATUS_RDMA_EN_VFS_S\t\t16\n+#define PFPE_CCQPSTATUS_RDMA_EN_VFS_M\t\tMAKEMASK(0x3F, 16)\n+#define PFPE_CCQPSTATUS_CCQP_ERR_S\t\t31\n+#define PFPE_CCQPSTATUS_CCQP_ERR_M\t\tBIT(31)\n+#define PFPE_CQACK\t\t\t\t0x00502C80 /* Reset Source: PFR */\n+#define PFPE_CQACK_PECQID_S\t\t\t0\n+#define PFPE_CQACK_PECQID_M\t\t\tMAKEMASK(0x7FFFF, 0)\n+#define PFPE_CQARM\t\t\t\t0x00502C00 /* Reset Source: PFR */\n+#define PFPE_CQARM_PECQID_S\t\t\t0\n+#define PFPE_CQARM_PECQID_M\t\t\tMAKEMASK(0x7FFFF, 0)\n+#define PFPE_CQPDB\t\t\t\t0x00500800 /* Reset Source: PFR */\n+#define PFPE_CQPDB_WQHEAD_S\t\t\t0\n+#define PFPE_CQPDB_WQHEAD_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define PFPE_CQPERRCODES\t\t\t0x0050A200 /* Reset Source: PFR */\n+#define PFPE_CQPERRCODES_CQP_MINOR_CODE_S\t0\n+#define PFPE_CQPERRCODES_CQP_MINOR_CODE_M\tMAKEMASK(0xFFFF, 0)\n+#define PFPE_CQPERRCODES_CQP_MAJOR_CODE_S\t16\n+#define PFPE_CQPERRCODES_CQP_MAJOR_CODE_M\tMAKEMASK(0xFFFF, 16)\n+#define PFPE_CQPTAIL\t\t\t\t0x00500880 /* Reset Source: PFR */\n+#define PFPE_CQPTAIL_WQTAIL_S\t\t\t0\n+#define PFPE_CQPTAIL_WQTAIL_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define PFPE_CQPTAIL_CQP_OP_ERR_S\t\t31\n+#define PFPE_CQPTAIL_CQP_OP_ERR_M\t\tBIT(31)\n+#define PFPE_IPCONFIG0\t\t\t\t0x0050A180 /* Reset Source: PFR */\n+#define PFPE_IPCONFIG0_PEIPID_S\t\t\t0\n+#define PFPE_IPCONFIG0_PEIPID_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define PFPE_IPCONFIG0_USEENTIREIDRANGE_S\t16\n+#define PFPE_IPCONFIG0_USEENTIREIDRANGE_M\tBIT(16)\n+#define PFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S\t17\n+#define PFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M\tBIT(17)\n+#define PFPE_MRTEIDXMASK\t\t\t0x0050A300 /* Reset Source: PFR */\n+#define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S\t0\n+#define PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M\tMAKEMASK(0x1F, 0)\n+#define PFPE_RCVUNEXPECTEDERROR\t\t\t0x0050A380 /* Reset Source: PFR */\n+#define PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0\n+#define PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)\n+#define PFPE_TCPNOWTIMER\t\t\t0x0050A280 /* Reset Source: PFR */\n+#define PFPE_TCPNOWTIMER_TCP_NOW_S\t\t0\n+#define PFPE_TCPNOWTIMER_TCP_NOW_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFPE_WQEALLOC\t\t\t\t0x00504400 /* Reset Source: PFR */\n+#define PFPE_WQEALLOC_PEQPID_S\t\t\t0\n+#define PFPE_WQEALLOC_PEQPID_M\t\t\tMAKEMASK(0x3FFFF, 0)\n+#define PFPE_WQEALLOC_WQE_DESC_INDEX_S\t\t20\n+#define PFPE_WQEALLOC_WQE_DESC_INDEX_M\t\tMAKEMASK(0xFFF, 20)\n+#define PRT_PEPM_COUNT(_i)\t\t\t(0x0050C040 + ((_i) * 4)) /* _i=0...511 */ /* Reset Source: PERST */\n+#define PRT_PEPM_COUNT_MAX_INDEX\t\t511\n+#define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_S\t\t0\n+#define PRT_PEPM_COUNT_PEPM_PSQ_COUNT_M\t\tMAKEMASK(0x1F, 0)\n+#define PRT_PEPM_COUNT_PEPM_MDQ_COUNT_S\t\t16\n+#define PRT_PEPM_COUNT_PEPM_MDQ_COUNT_M\t\tMAKEMASK(0x3FFF, 16)\n+#define VFPE_AEQALLOC(_VF)\t\t\t(0x00502800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_AEQALLOC_MAX_INDEX\t\t\t255\n+#define VFPE_AEQALLOC_AECOUNT_S\t\t\t0\n+#define VFPE_AEQALLOC_AECOUNT_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFPE_CCQPHIGH(_VF)\t\t\t(0x00508800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_CCQPHIGH_MAX_INDEX\t\t\t255\n+#define VFPE_CCQPHIGH_PECCQPHIGH_S\t\t0\n+#define VFPE_CCQPHIGH_PECCQPHIGH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFPE_CCQPLOW(_VF)\t\t\t(0x00508400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_CCQPLOW_MAX_INDEX\t\t\t255\n+#define VFPE_CCQPLOW_PECCQPLOW_S\t\t0\n+#define VFPE_CCQPLOW_PECCQPLOW_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFPE_CCQPSTATUS(_VF)\t\t\t(0x00508000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_CCQPSTATUS_MAX_INDEX\t\t255\n+#define VFPE_CCQPSTATUS_CCQP_DONE_S\t\t0\n+#define VFPE_CCQPSTATUS_CCQP_DONE_M\t\tBIT(0)\n+#define VFPE_CCQPSTATUS_HMC_PROFILE_S\t\t4\n+#define VFPE_CCQPSTATUS_HMC_PROFILE_M\t\tMAKEMASK(0x7, 4)\n+#define VFPE_CCQPSTATUS_RDMA_EN_VFS_S\t\t16\n+#define VFPE_CCQPSTATUS_RDMA_EN_VFS_M\t\tMAKEMASK(0x3F, 16)\n+#define VFPE_CCQPSTATUS_CCQP_ERR_S\t\t31\n+#define VFPE_CCQPSTATUS_CCQP_ERR_M\t\tBIT(31)\n+#define VFPE_CQACK(_VF)\t\t\t\t(0x00502400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_CQACK_MAX_INDEX\t\t\t255\n+#define VFPE_CQACK_PECQID_S\t\t\t0\n+#define VFPE_CQACK_PECQID_M\t\t\tMAKEMASK(0x7FFFF, 0)\n+#define VFPE_CQARM(_VF)\t\t\t\t(0x00502000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_CQARM_MAX_INDEX\t\t\t255\n+#define VFPE_CQARM_PECQID_S\t\t\t0\n+#define VFPE_CQARM_PECQID_M\t\t\tMAKEMASK(0x7FFFF, 0)\n+#define VFPE_CQPDB(_VF)\t\t\t\t(0x00500000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_CQPDB_MAX_INDEX\t\t\t255\n+#define VFPE_CQPDB_WQHEAD_S\t\t\t0\n+#define VFPE_CQPDB_WQHEAD_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define VFPE_CQPERRCODES(_VF)\t\t\t(0x00509000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_CQPERRCODES_MAX_INDEX\t\t255\n+#define VFPE_CQPERRCODES_CQP_MINOR_CODE_S\t0\n+#define VFPE_CQPERRCODES_CQP_MINOR_CODE_M\tMAKEMASK(0xFFFF, 0)\n+#define VFPE_CQPERRCODES_CQP_MAJOR_CODE_S\t16\n+#define VFPE_CQPERRCODES_CQP_MAJOR_CODE_M\tMAKEMASK(0xFFFF, 16)\n+#define VFPE_CQPTAIL(_VF)\t\t\t(0x00500400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_CQPTAIL_MAX_INDEX\t\t\t255\n+#define VFPE_CQPTAIL_WQTAIL_S\t\t\t0\n+#define VFPE_CQPTAIL_WQTAIL_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define VFPE_CQPTAIL_CQP_OP_ERR_S\t\t31\n+#define VFPE_CQPTAIL_CQP_OP_ERR_M\t\tBIT(31)\n+#define VFPE_IPCONFIG0(_VF)\t\t\t(0x00508C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_IPCONFIG0_MAX_INDEX\t\t255\n+#define VFPE_IPCONFIG0_PEIPID_S\t\t\t0\n+#define VFPE_IPCONFIG0_PEIPID_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define VFPE_IPCONFIG0_USEENTIREIDRANGE_S\t16\n+#define VFPE_IPCONFIG0_USEENTIREIDRANGE_M\tBIT(16)\n+#define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S\t17\n+#define VFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M\tBIT(17)\n+#define VFPE_RCVUNEXPECTEDERROR(_VF)\t\t(0x00509C00 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_RCVUNEXPECTEDERROR_MAX_INDEX\t255\n+#define VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_S 0\n+#define VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)\n+#define VFPE_TCPNOWTIMER(_VF)\t\t\t(0x00509400 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_TCPNOWTIMER_MAX_INDEX\t\t255\n+#define VFPE_TCPNOWTIMER_TCP_NOW_S\t\t0\n+#define VFPE_TCPNOWTIMER_TCP_NOW_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFPE_WQEALLOC(_VF)\t\t\t(0x00504000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_WQEALLOC_MAX_INDEX\t\t\t255\n+#define VFPE_WQEALLOC_PEQPID_S\t\t\t0\n+#define VFPE_WQEALLOC_PEQPID_M\t\t\tMAKEMASK(0x3FFFF, 0)\n+#define VFPE_WQEALLOC_WQE_DESC_INDEX_S\t\t20\n+#define VFPE_WQEALLOC_WQE_DESC_INDEX_M\t\tMAKEMASK(0xFFF, 20)\n+#define GLPES_PFIP4RXDISCARD(_i)\t\t(0x00541400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXDISCARD_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_S\t0\n+#define GLPES_PFIP4RXDISCARD_IP4RXDISCARD_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4RXFRAGSHI(_i)\t\t(0x00541C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXFRAGSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_S\t0\n+#define GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4RXFRAGSLO(_i)\t\t(0x00541C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXFRAGSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_S\t0\n+#define GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4RXMCOCTSHI(_i)\t\t(0x00542404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXMCOCTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_S\t0\n+#define GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4RXMCOCTSLO(_i)\t\t(0x00542400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXMCOCTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_S\t0\n+#define GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4RXMCPKTSHI(_i)\t\t(0x00542C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXMCPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_S\t0\n+#define GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4RXMCPKTSLO(_i)\t\t(0x00542C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXMCPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_S\t0\n+#define GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4RXOCTSHI(_i)\t\t\t(0x00540404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXOCTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_S\t0\n+#define GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4RXOCTSLO(_i)\t\t\t(0x00540400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXOCTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_S\t0\n+#define GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4RXPKTSHI(_i)\t\t\t(0x00540C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_S\t0\n+#define GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4RXPKTSLO(_i)\t\t\t(0x00540C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_S\t0\n+#define GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4RXTRUNC(_i)\t\t\t(0x00541800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4RXTRUNC_MAX_INDEX\t\t127\n+#define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_S\t\t0\n+#define GLPES_PFIP4RXTRUNC_IP4RXTRUNC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4TXFRAGSHI(_i)\t\t(0x00547404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXFRAGSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_S\t0\n+#define GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4TXFRAGSLO(_i)\t\t(0x00547400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXFRAGSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_S\t0\n+#define GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4TXMCOCTSHI(_i)\t\t(0x00547C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXMCOCTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_S\t0\n+#define GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4TXMCOCTSLO(_i)\t\t(0x00547C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXMCOCTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_S\t0\n+#define GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4TXMCPKTSHI(_i)\t\t(0x00548404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXMCPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_S\t0\n+#define GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4TXMCPKTSLO(_i)\t\t(0x00548400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXMCPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_S\t0\n+#define GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4TXNOROUTE(_i)\t\t(0x0054B400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXNOROUTE_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_S\t0\n+#define GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_PFIP4TXOCTSHI(_i)\t\t\t(0x00546404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXOCTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_S\t0\n+#define GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4TXOCTSLO(_i)\t\t\t(0x00546400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXOCTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_S\t0\n+#define GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP4TXPKTSHI(_i)\t\t\t(0x00546C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_S\t0\n+#define GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP4TXPKTSLO(_i)\t\t\t(0x00546C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP4TXPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_S\t0\n+#define GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6RXDISCARD(_i)\t\t(0x00544400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXDISCARD_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_S\t0\n+#define GLPES_PFIP6RXDISCARD_IP6RXDISCARD_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6RXFRAGSHI(_i)\t\t(0x00544C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXFRAGSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_S\t0\n+#define GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6RXFRAGSLO(_i)\t\t(0x00544C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXFRAGSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_S\t0\n+#define GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6RXMCOCTSHI(_i)\t\t(0x00545404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXMCOCTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_S\t0\n+#define GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6RXMCOCTSLO(_i)\t\t(0x00545400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXMCOCTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_S\t0\n+#define GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6RXMCPKTSHI(_i)\t\t(0x00545C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXMCPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_S\t0\n+#define GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6RXMCPKTSLO(_i)\t\t(0x00545C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXMCPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_S\t0\n+#define GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6RXOCTSHI(_i)\t\t\t(0x00543404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXOCTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_S\t0\n+#define GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6RXOCTSLO(_i)\t\t\t(0x00543400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXOCTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_S\t0\n+#define GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6RXPKTSHI(_i)\t\t\t(0x00543C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_S\t0\n+#define GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6RXPKTSLO(_i)\t\t\t(0x00543C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_S\t0\n+#define GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6RXTRUNC(_i)\t\t\t(0x00544800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6RXTRUNC_MAX_INDEX\t\t127\n+#define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_S\t\t0\n+#define GLPES_PFIP6RXTRUNC_IP6RXTRUNC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6TXFRAGSHI(_i)\t\t(0x00549C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXFRAGSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_S\t0\n+#define GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6TXFRAGSLO(_i)\t\t(0x00549C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXFRAGSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_S\t0\n+#define GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6TXMCOCTSHI(_i)\t\t(0x0054A404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXMCOCTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_S\t0\n+#define GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6TXMCOCTSLO(_i)\t\t(0x0054A400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXMCOCTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_S\t0\n+#define GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6TXMCPKTSHI(_i)\t\t(0x0054AC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXMCPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_S\t0\n+#define GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6TXMCPKTSLO(_i)\t\t(0x0054AC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXMCPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_S\t0\n+#define GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6TXNOROUTE(_i)\t\t(0x0054B800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXNOROUTE_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_S\t0\n+#define GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_PFIP6TXOCTSHI(_i)\t\t\t(0x00548C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXOCTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_S\t0\n+#define GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6TXOCTSLO(_i)\t\t\t(0x00548C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXOCTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_S\t0\n+#define GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFIP6TXPKTSHI(_i)\t\t\t(0x00549404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_S\t0\n+#define GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFIP6TXPKTSLO(_i)\t\t\t(0x00549400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFIP6TXPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_S\t0\n+#define GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFRDMARXRDSHI(_i)\t\t\t(0x0054EC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMARXRDSHI_MAX_INDEX\t\t127\n+#define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_S\t0\n+#define GLPES_PFRDMARXRDSHI_RDMARXRDSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFRDMARXRDSLO(_i)\t\t\t(0x0054EC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMARXRDSLO_MAX_INDEX\t\t127\n+#define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_S\t0\n+#define GLPES_PFRDMARXRDSLO_RDMARXRDSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFRDMARXSNDSHI(_i)\t\t(0x0054F404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMARXSNDSHI_MAX_INDEX\t\t127\n+#define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_S\t0\n+#define GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFRDMARXSNDSLO(_i)\t\t(0x0054F400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMARXSNDSLO_MAX_INDEX\t\t127\n+#define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_S\t0\n+#define GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFRDMARXWRSHI(_i)\t\t\t(0x0054E404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMARXWRSHI_MAX_INDEX\t\t127\n+#define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_S\t0\n+#define GLPES_PFRDMARXWRSHI_RDMARXWRSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFRDMARXWRSLO(_i)\t\t\t(0x0054E400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMARXWRSLO_MAX_INDEX\t\t127\n+#define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_S\t0\n+#define GLPES_PFRDMARXWRSLO_RDMARXWRSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFRDMATXRDSHI(_i)\t\t\t(0x00550404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMATXRDSHI_MAX_INDEX\t\t127\n+#define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_S\t0\n+#define GLPES_PFRDMATXRDSHI_RDMARXRDSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFRDMATXRDSLO(_i)\t\t\t(0x00550400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMATXRDSLO_MAX_INDEX\t\t127\n+#define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_S\t0\n+#define GLPES_PFRDMATXRDSLO_RDMARXRDSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFRDMATXSNDSHI(_i)\t\t(0x00550C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMATXSNDSHI_MAX_INDEX\t\t127\n+#define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_S\t0\n+#define GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFRDMATXSNDSLO(_i)\t\t(0x00550C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMATXSNDSLO_MAX_INDEX\t\t127\n+#define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_S\t0\n+#define GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFRDMATXWRSHI(_i)\t\t\t(0x0054FC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMATXWRSHI_MAX_INDEX\t\t127\n+#define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_S\t0\n+#define GLPES_PFRDMATXWRSHI_RDMARXWRSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFRDMATXWRSLO(_i)\t\t\t(0x0054FC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMATXWRSLO_MAX_INDEX\t\t127\n+#define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_S\t0\n+#define GLPES_PFRDMATXWRSLO_RDMARXWRSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFRDMAVBNDHI(_i)\t\t\t(0x00551404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMAVBNDHI_MAX_INDEX\t\t127\n+#define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_S\t\t0\n+#define GLPES_PFRDMAVBNDHI_RDMAVBNDHI_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFRDMAVBNDLO(_i)\t\t\t(0x00551400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMAVBNDLO_MAX_INDEX\t\t127\n+#define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_S\t\t0\n+#define GLPES_PFRDMAVBNDLO_RDMAVBNDLO_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFRDMAVINVHI(_i)\t\t\t(0x00551C04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMAVINVHI_MAX_INDEX\t\t127\n+#define GLPES_PFRDMAVINVHI_RDMAVINVHI_S\t\t0\n+#define GLPES_PFRDMAVINVHI_RDMAVINVHI_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFRDMAVINVLO(_i)\t\t\t(0x00551C00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRDMAVINVLO_MAX_INDEX\t\t127\n+#define GLPES_PFRDMAVINVLO_RDMAVINVLO_S\t\t0\n+#define GLPES_PFRDMAVINVLO_RDMAVINVLO_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFRXVLANERR(_i)\t\t\t(0x00540000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFRXVLANERR_MAX_INDEX\t\t127\n+#define GLPES_PFRXVLANERR_RXVLANERR_S\t\t0\n+#define GLPES_PFRXVLANERR_RXVLANERR_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_PFTCPRTXSEG(_i)\t\t\t(0x00552400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFTCPRTXSEG_MAX_INDEX\t\t127\n+#define GLPES_PFTCPRTXSEG_TCPRTXSEG_S\t\t0\n+#define GLPES_PFTCPRTXSEG_TCPRTXSEG_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFTCPRXOPTERR(_i)\t\t\t(0x0054C400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFTCPRXOPTERR_MAX_INDEX\t\t127\n+#define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_S\t0\n+#define GLPES_PFTCPRXOPTERR_TCPRXOPTERR_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_PFTCPRXPROTOERR(_i)\t\t(0x0054C800 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFTCPRXPROTOERR_MAX_INDEX\t\t127\n+#define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_S\t0\n+#define GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_PFTCPRXSEGSHI(_i)\t\t\t(0x0054BC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFTCPRXSEGSHI_MAX_INDEX\t\t127\n+#define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_S\t0\n+#define GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFTCPRXSEGSLO(_i)\t\t\t(0x0054BC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFTCPRXSEGSLO_MAX_INDEX\t\t127\n+#define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_S\t0\n+#define GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFTCPTXSEGHI(_i)\t\t\t(0x0054CC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFTCPTXSEGHI_MAX_INDEX\t\t127\n+#define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_S\t\t0\n+#define GLPES_PFTCPTXSEGHI_TCPTXSEGHI_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFTCPTXSEGLO(_i)\t\t\t(0x0054CC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFTCPTXSEGLO_MAX_INDEX\t\t127\n+#define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_S\t\t0\n+#define GLPES_PFTCPTXSEGLO_TCPTXSEGLO_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFUDPRXPKTSHI(_i)\t\t\t(0x0054D404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFUDPRXPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_S\t0\n+#define GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFUDPRXPKTSLO(_i)\t\t\t(0x0054D400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFUDPRXPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_S\t0\n+#define GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_PFUDPTXPKTSHI(_i)\t\t\t(0x0054DC04 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFUDPTXPKTSHI_MAX_INDEX\t\t127\n+#define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_S\t0\n+#define GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_M\tMAKEMASK(0xFFFF, 0)\n+#define GLPES_PFUDPTXPKTSLO(_i)\t\t\t(0x0054DC00 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLPES_PFUDPTXPKTSLO_MAX_INDEX\t\t127\n+#define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_S\t0\n+#define GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_RDMARXMULTFPDUSHI\t\t\t0x0055E00C /* Reset Source: CORER */\n+#define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_S 0\n+#define GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_M MAKEMASK(0xFFFFFF, 0)\n+#define GLPES_RDMARXMULTFPDUSLO\t\t\t0x0055E008 /* Reset Source: CORER */\n+#define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_S 0\n+#define GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_RDMARXOOODDPHI\t\t\t0x0055E014 /* Reset Source: CORER */\n+#define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_S\t0\n+#define GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_RDMARXOOODDPLO\t\t\t0x0055E010 /* Reset Source: CORER */\n+#define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_S\t0\n+#define GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_RDMARXOOONOMARK\t\t\t0x0055E004 /* Reset Source: CORER */\n+#define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_S\t0\n+#define GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_RDMARXUNALIGN\t\t\t0x0055E000 /* Reset Source: CORER */\n+#define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_S\t0\n+#define GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_TCPRXFOURHOLEHI\t\t\t0x0055E03C /* Reset Source: CORER */\n+#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0\n+#define GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M MAKEMASK(0xFFFFFF, 0)\n+#define GLPES_TCPRXFOURHOLELO\t\t\t0x0055E038 /* Reset Source: CORER */\n+#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0\n+#define GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_TCPRXONEHOLEHI\t\t\t0x0055E024 /* Reset Source: CORER */\n+#define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S\t0\n+#define GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_TCPRXONEHOLELO\t\t\t0x0055E020 /* Reset Source: CORER */\n+#define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_S\t0\n+#define GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_TCPRXPUREACKHI\t\t\t0x0055E01C /* Reset Source: CORER */\n+#define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_S\t0\n+#define GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_TCPRXPUREACKSLO\t\t\t0x0055E018 /* Reset Source: CORER */\n+#define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_S\t0\n+#define GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_TCPRXTHREEHOLEHI\t\t\t0x0055E034 /* Reset Source: CORER */\n+#define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_S 0\n+#define GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_M MAKEMASK(0xFFFFFF, 0)\n+#define GLPES_TCPRXTHREEHOLELO\t\t\t0x0055E030 /* Reset Source: CORER */\n+#define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_S 0\n+#define GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_TCPRXTWOHOLEHI\t\t\t0x0055E02C /* Reset Source: CORER */\n+#define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_S\t0\n+#define GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_TCPRXTWOHOLELO\t\t\t0x0055E028 /* Reset Source: CORER */\n+#define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_S\t0\n+#define GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_TCPTXRETRANSFASTHI\t\t0x0055E044 /* Reset Source: CORER */\n+#define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_S 0\n+#define GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_M MAKEMASK(0xFFFFFF, 0)\n+#define GLPES_TCPTXRETRANSFASTLO\t\t0x0055E040 /* Reset Source: CORER */\n+#define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_S 0\n+#define GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_TCPTXTOUTSFASTHI\t\t\t0x0055E04C /* Reset Source: CORER */\n+#define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_S 0\n+#define GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_M MAKEMASK(0xFFFFFF, 0)\n+#define GLPES_TCPTXTOUTSFASTLO\t\t\t0x0055E048 /* Reset Source: CORER */\n+#define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_S 0\n+#define GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_M MAKEMASK(0xFFFFFFFF, 0)\n+#define GLPES_TCPTXTOUTSHI\t\t\t0x0055E054 /* Reset Source: CORER */\n+#define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_S\t0\n+#define GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_M\tMAKEMASK(0xFFFFFF, 0)\n+#define GLPES_TCPTXTOUTSLO\t\t\t0x0055E050 /* Reset Source: CORER */\n+#define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_S\t0\n+#define GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_PWR_MODE_CTL\t\t\t\t0x000B820C /* Reset Source: POR */\n+#define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_S\t0\n+#define GL_PWR_MODE_CTL_SWITCH_PWR_MODE_EN_M\tBIT(0)\n+#define GL_PWR_MODE_CTL_NIC_PWR_MODE_EN_S\t1\n+#define GL_PWR_MODE_CTL_NIC_PWR_MODE_EN_M\tBIT(1)\n+#define GL_PWR_MODE_CTL_S5_PWR_MODE_EN_S\t2\n+#define GL_PWR_MODE_CTL_S5_PWR_MODE_EN_M\tBIT(2)\n+#define GL_PWR_MODE_CTL_CAR_MAX_SW_CONFIG_S\t3\n+#define GL_PWR_MODE_CTL_CAR_MAX_SW_CONFIG_M\tMAKEMASK(0x3, 3)\n+#define GL_PWR_MODE_CTL_CAR_MAX_BW_S\t\t30\n+#define GL_PWR_MODE_CTL_CAR_MAX_BW_M\t\tMAKEMASK(0x3, 30)\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT\t0x000B825C /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_S5_S 18\n+#define GL_PWR_MODE_DIVIDE_CTRL_H_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT\t0x000B8218 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_S5_S 18\n+#define GL_PWR_MODE_DIVIDE_CTRL_L_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT\t0x000B8260 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_S 0\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PECLK_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UCLK_S 3\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UCLK_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_LCLK_S 6\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_LCLK_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PSM_S 9\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_PSM_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_RXCTL_S 12\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_RXCTL_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UANA_S 15\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_UANA_M MAKEMASK(0x7, 15)\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_S5_S 18\n+#define GL_PWR_MODE_DIVIDE_CTRL_M_DEFAULT_DEFAULT_DIV_VAL_S5_M MAKEMASK(0x7, 18)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK\t0x000B8200 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_25G_H_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_10G_H_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_4G_H_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_A50G_H_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_LCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK\t0x000B81F0 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_25G_H_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_10G_H_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_4G_H_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_A50G_H_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PECLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM\t0x000B81FC /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_25G_H_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_10G_H_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_4G_H_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_A50G_H_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_PSM_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL\t0x000B81F8 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_25G_H_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_10G_H_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_4G_H_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_A50G_H_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_RXCTL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA\t0x000B8208 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_25G_H_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_10G_H_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_4G_H_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_A50G_H_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UANA_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK\t0x000B81F4 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_25G_H_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_10G_H_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_4G_H_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_A50G_H_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_H_UCLK_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK\t0x000B8244 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_25G_L_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_10G_L_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_4G_L_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_A50G_L_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_LCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK\t0x000B8220 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_25G_L_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_10G_L_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_4G_L_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_A50G_L_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PECLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM\t0x000B8240 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_25G_L_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_10G_L_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_4G_L_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_A50G_L_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_PSM_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL\t0x000B823C /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_25G_L_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_10G_L_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_4G_L_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_A50G_L_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_RXCTL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA\t0x000B8248 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_25G_L_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_10G_L_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_4G_L_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_A50G_L_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UANA_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK\t0x000B8238 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_25G_L_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_10G_L_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_4G_L_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_A50G_L_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_L_UCLK_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK\t0x000B8230 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_25G_M_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_10G_M_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_4G_M_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_A50G_M_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_LCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK\t0x000B821C /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_25G_M_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_10G_M_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_4G_M_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_A50G_M_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PECLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM\t0x000B822C /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_25G_M_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_10G_M_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_4G_M_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_A50G_M_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_PSM_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL\t0x000B8228 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_25G_M_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_10G_M_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_4G_M_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_A50G_M_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_RXCTL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA\t0x000B8234 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_25G_M_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_10G_M_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_4G_M_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_A50G_M_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UANA_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK\t0x000B8224 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_S 0\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_25G_M_S 3\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_10G_M_S 6\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_4G_M_S 9\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_A50G_M_S 12\n+#define GL_PWR_MODE_DIVIDE_S0_CTRL_M_UCLK_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL\t\t0x000B81EC /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_S 0\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_50G_H_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_25G_H_S 3\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_25G_H_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_10G_H_S 6\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_10G_H_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_4G_H_S 9\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_4G_H_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_A50G_H_S 12\n+#define GL_PWR_MODE_DIVIDE_S5_H_CTRL_DIV_VAL_TBW_A50G_H_M MAKEMASK(0xF, 12)\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL\t\t0x000B824C /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_S 0\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_50G_L_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_25G_L_S 3\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_25G_L_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_10G_L_S 6\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_10G_L_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_4G_L_S 9\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_4G_L_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_A50G_L_S 12\n+#define GL_PWR_MODE_DIVIDE_S5_L_CTRL_DIV_VAL_TBW_A50G_L_M MAKEMASK(0x7, 12)\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL\t\t0x000B8250 /* Reset Source: POR */\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_S 0\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_50G_M_M MAKEMASK(0x7, 0)\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_25G_M_S 3\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_25G_M_M MAKEMASK(0x7, 3)\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_10G_M_S 6\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_10G_M_M MAKEMASK(0x7, 6)\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_4G_M_S 9\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_4G_M_M MAKEMASK(0x7, 9)\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_A50G_M_S 12\n+#define GL_PWR_MODE_DIVIDE_S5_M_CTRL_DIV_VAL_TBW_A50G_M_M MAKEMASK(0x7, 12)\n+#define GL_S5_PWR_MODE_EXIT_CTL\t\t\t0x000B8270 /* Reset Source: POR */\n+#define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_S 0\n+#define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_AUTO_EXIT_M BIT(0)\n+#define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_FW_EXIT_S 1\n+#define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_FW_EXIT_M BIT(1)\n+#define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_PRST_FLOWS_ON_CORER_S 3\n+#define GL_S5_PWR_MODE_EXIT_CTL_S5_PWR_MODE_PRST_FLOWS_ON_CORER_M BIT(3)\n+#define GLGEN_PME_TO\t\t\t\t0x000B81BC /* Reset Source: POR */\n+#define GLGEN_PME_TO_PME_TO_FOR_PE_S\t\t0\n+#define GLGEN_PME_TO_PME_TO_FOR_PE_M\t\tBIT(0)\n+#define PRTPM_EEE_STAT\t\t\t\t0x001E4320 /* Reset Source: GLOBR */\n+#define PRTPM_EEE_STAT_EEE_NEG_S\t\t29\n+#define PRTPM_EEE_STAT_EEE_NEG_M\t\tBIT(29)\n+#define PRTPM_EEE_STAT_RX_LPI_STATUS_S\t\t30\n+#define PRTPM_EEE_STAT_RX_LPI_STATUS_M\t\tBIT(30)\n+#define PRTPM_EEE_STAT_TX_LPI_STATUS_S\t\t31\n+#define PRTPM_EEE_STAT_TX_LPI_STATUS_M\t\tBIT(31)\n+#define PRTPM_EEEC\t\t\t\t0x001E4380 /* Reset Source: GLOBR */\n+#define PRTPM_EEEC_TW_WAKE_MIN_S\t\t16\n+#define PRTPM_EEEC_TW_WAKE_MIN_M\t\tMAKEMASK(0x3F, 16)\n+#define PRTPM_EEEC_TX_LU_LPI_DLY_S\t\t24\n+#define PRTPM_EEEC_TX_LU_LPI_DLY_M\t\tMAKEMASK(0x3, 24)\n+#define PRTPM_EEEC_TEEE_DLY_S\t\t\t26\n+#define PRTPM_EEEC_TEEE_DLY_M\t\t\tMAKEMASK(0x3F, 26)\n+#define PRTPM_EEEFWD\t\t\t\t0x001E4400 /* Reset Source: GLOBR */\n+#define PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_S\t31\n+#define PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_M\tBIT(31)\n+#define PRTPM_EEER\t\t\t\t0x001E4360 /* Reset Source: GLOBR */\n+#define PRTPM_EEER_TW_SYSTEM_S\t\t\t0\n+#define PRTPM_EEER_TW_SYSTEM_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define PRTPM_EEER_TX_LPI_EN_S\t\t\t16\n+#define PRTPM_EEER_TX_LPI_EN_M\t\t\tBIT(16)\n+#define PRTPM_EEETXC\t\t\t\t0x001E43E0 /* Reset Source: GLOBR */\n+#define PRTPM_EEETXC_TW_PHY_S\t\t\t0\n+#define PRTPM_EEETXC_TW_PHY_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define PRTPM_RLPIC\t\t\t\t0x001E43A0 /* Reset Source: GLOBR */\n+#define PRTPM_RLPIC_ERLPIC_S\t\t\t0\n+#define PRTPM_RLPIC_ERLPIC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PRTPM_TLPIC\t\t\t\t0x001E43C0 /* Reset Source: GLOBR */\n+#define PRTPM_TLPIC_ETLPIC_S\t\t\t0\n+#define PRTPM_TLPIC_ETLPIC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLRPB_DHW(_i)\t\t\t\t(0x000AC000 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLRPB_DHW_MAX_INDEX\t\t\t15\n+#define GLRPB_DHW_DHW_TCN_S\t\t\t0\n+#define GLRPB_DHW_DHW_TCN_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPB_DLW(_i)\t\t\t\t(0x000AC044 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLRPB_DLW_MAX_INDEX\t\t\t15\n+#define GLRPB_DLW_DLW_TCN_S\t\t\t0\n+#define GLRPB_DLW_DLW_TCN_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPB_DPS(_i)\t\t\t\t(0x000AC084 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLRPB_DPS_MAX_INDEX\t\t\t15\n+#define GLRPB_DPS_DPS_TCN_S\t\t\t0\n+#define GLRPB_DPS_DPS_TCN_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPB_DSI_EN\t\t\t\t0x000AC324 /* Reset Source: CORER */\n+#define GLRPB_DSI_EN_DSI_EN_S\t\t\t0\n+#define GLRPB_DSI_EN_DSI_EN_M\t\t\tBIT(0)\n+#define GLRPB_DSI_EN_DSI_L2_MAC_ERR_DROP_EN_S\t1\n+#define GLRPB_DSI_EN_DSI_L2_MAC_ERR_DROP_EN_M\tBIT(1)\n+#define GLRPB_SHW(_i)\t\t\t\t(0x000AC120 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLRPB_SHW_MAX_INDEX\t\t\t7\n+#define GLRPB_SHW_SHW_S\t\t\t\t0\n+#define GLRPB_SHW_SHW_M\t\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPB_SLW(_i)\t\t\t\t(0x000AC140 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLRPB_SLW_MAX_INDEX\t\t\t7\n+#define GLRPB_SLW_SLW_S\t\t\t\t0\n+#define GLRPB_SLW_SLW_M\t\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPB_SPS(_i)\t\t\t\t(0x000AC0C4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLRPB_SPS_MAX_INDEX\t\t\t7\n+#define GLRPB_SPS_SPS_TCN_S\t\t\t0\n+#define GLRPB_SPS_SPS_TCN_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPB_TC_CFG(_i)\t\t\t(0x000AC2A4 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLRPB_TC_CFG_MAX_INDEX\t\t\t31\n+#define GLRPB_TC_CFG_D_POOL_S\t\t\t0\n+#define GLRPB_TC_CFG_D_POOL_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define GLRPB_TC_CFG_S_POOL_S\t\t\t16\n+#define GLRPB_TC_CFG_S_POOL_M\t\t\tMAKEMASK(0xFFFF, 16)\n+#define GLRPB_TCHW(_i)\t\t\t\t(0x000AC330 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLRPB_TCHW_MAX_INDEX\t\t\t31\n+#define GLRPB_TCHW_TCHW_S\t\t\t0\n+#define GLRPB_TCHW_TCHW_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPB_TCLW(_i)\t\t\t\t(0x000AC3B0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLRPB_TCLW_MAX_INDEX\t\t\t31\n+#define GLRPB_TCLW_TCLW_S\t\t\t0\n+#define GLRPB_TCLW_TCLW_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLQF_APBVT(_i)\t\t\t\t(0x00450000 + ((_i) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */\n+#define GLQF_APBVT_MAX_INDEX\t\t\t2047\n+#define GLQF_APBVT_APBVT_S\t\t\t0\n+#define GLQF_APBVT_APBVT_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQF_FD_CLSN_0\t\t\t\t0x00460028 /* Reset Source: CORER */\n+#define GLQF_FD_CLSN_0_HITSBCNT_S\t\t0\n+#define GLQF_FD_CLSN_0_HITSBCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQF_FD_CLSN1\t\t\t\t0x00460030 /* Reset Source: CORER */\n+#define GLQF_FD_CLSN1_HITLBCNT_S\t\t0\n+#define GLQF_FD_CLSN1_HITLBCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQF_FD_CNT\t\t\t\t0x00460018 /* Reset Source: CORER */\n+#define GLQF_FD_CNT_FD_GCNT_S\t\t\t0\n+#define GLQF_FD_CNT_FD_GCNT_M\t\t\tMAKEMASK(0x7FFF, 0)\n+#define GLQF_FD_CNT_FD_BCNT_S\t\t\t16\n+#define GLQF_FD_CNT_FD_BCNT_M\t\t\tMAKEMASK(0x7FFF, 16)\n+#define GLQF_FD_CTL\t\t\t\t0x00460000 /* Reset Source: CORER */\n+#define GLQF_FD_CTL_FDLONG_S\t\t\t0\n+#define GLQF_FD_CTL_FDLONG_M\t\t\tMAKEMASK(0xF, 0)\n+#define GLQF_FD_CTL_HASH_REPORT_S\t\t4\n+#define GLQF_FD_CTL_HASH_REPORT_M\t\tBIT(4)\n+#define GLQF_FD_CTL_FLT_ADDR_REPORT_S\t\t5\n+#define GLQF_FD_CTL_FLT_ADDR_REPORT_M\t\tBIT(5)\n+#define GLQF_FD_SIZE\t\t\t\t0x00460010 /* Reset Source: CORER */\n+#define GLQF_FD_SIZE_FD_GSIZE_S\t\t\t0\n+#define GLQF_FD_SIZE_FD_GSIZE_M\t\t\tMAKEMASK(0x7FFF, 0)\n+#define GLQF_FD_SIZE_FD_BSIZE_S\t\t\t16\n+#define GLQF_FD_SIZE_FD_BSIZE_M\t\t\tMAKEMASK(0x7FFF, 16)\n+#define GLQF_FDCNT_0\t\t\t\t0x00460020 /* Reset Source: CORER */\n+#define GLQF_FDCNT_0_BUCKETCNT_S\t\t0\n+#define GLQF_FDCNT_0_BUCKETCNT_M\t\tMAKEMASK(0x7FFF, 0)\n+#define GLQF_FDCNT_0_CNT_NOT_VLD_S\t\t31\n+#define GLQF_FDCNT_0_CNT_NOT_VLD_M\t\tBIT(31)\n+#define GLQF_FDEVICTENA(_i)\t\t\t(0x00452000 + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */\n+#define GLQF_FDEVICTENA_MAX_INDEX\t\t3\n+#define GLQF_FDEVICTENA_FDEVICTENA_S\t\t0\n+#define GLQF_FDEVICTENA_FDEVICTENA_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQF_FDINSET(_i, _j)\t\t\t(0x00412000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */\n+#define GLQF_FDINSET_MAX_INDEX\t\t\t127\n+#define GLQF_FDINSET_FV_WORD_INDX0_S\t\t0\n+#define GLQF_FDINSET_FV_WORD_INDX0_M\t\tMAKEMASK(0x1F, 0)\n+#define GLQF_FDINSET_FV_WORD_VAL0_S\t\t7\n+#define GLQF_FDINSET_FV_WORD_VAL0_M\t\tBIT(7)\n+#define GLQF_FDINSET_FV_WORD_INDX1_S\t\t8\n+#define GLQF_FDINSET_FV_WORD_INDX1_M\t\tMAKEMASK(0x1F, 8)\n+#define GLQF_FDINSET_FV_WORD_VAL1_S\t\t15\n+#define GLQF_FDINSET_FV_WORD_VAL1_M\t\tBIT(15)\n+#define GLQF_FDINSET_FV_WORD_INDX2_S\t\t16\n+#define GLQF_FDINSET_FV_WORD_INDX2_M\t\tMAKEMASK(0x1F, 16)\n+#define GLQF_FDINSET_FV_WORD_VAL2_S\t\t23\n+#define GLQF_FDINSET_FV_WORD_VAL2_M\t\tBIT(23)\n+#define GLQF_FDINSET_FV_WORD_INDX3_S\t\t24\n+#define GLQF_FDINSET_FV_WORD_INDX3_M\t\tMAKEMASK(0x1F, 24)\n+#define GLQF_FDINSET_FV_WORD_VAL3_S\t\t31\n+#define GLQF_FDINSET_FV_WORD_VAL3_M\t\tBIT(31)\n+#define GLQF_FDMASK(_i)\t\t\t\t(0x00410800 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLQF_FDMASK_MAX_INDEX\t\t\t31\n+#define GLQF_FDMASK_MSK_INDEX_S\t\t\t0\n+#define GLQF_FDMASK_MSK_INDEX_M\t\t\tMAKEMASK(0x1F, 0)\n+#define GLQF_FDMASK_MASK_S\t\t\t16\n+#define GLQF_FDMASK_MASK_M\t\t\tMAKEMASK(0xFFFF, 16)\n+#define GLQF_FDMASK_SEL(_i)\t\t\t(0x00410400 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLQF_FDMASK_SEL_MAX_INDEX\t\t127\n+#define GLQF_FDMASK_SEL_MASK_SEL_S\t\t0\n+#define GLQF_FDMASK_SEL_MASK_SEL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQF_FDSWAP(_i, _j)\t\t\t(0x00413000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */\n+#define GLQF_FDSWAP_MAX_INDEX\t\t\t127\n+#define GLQF_FDSWAP_FV_WORD_INDX0_S\t\t0\n+#define GLQF_FDSWAP_FV_WORD_INDX0_M\t\tMAKEMASK(0x1F, 0)\n+#define GLQF_FDSWAP_FV_WORD_VAL0_S\t\t7\n+#define GLQF_FDSWAP_FV_WORD_VAL0_M\t\tBIT(7)\n+#define GLQF_FDSWAP_FV_WORD_INDX1_S\t\t8\n+#define GLQF_FDSWAP_FV_WORD_INDX1_M\t\tMAKEMASK(0x1F, 8)\n+#define GLQF_FDSWAP_FV_WORD_VAL1_S\t\t15\n+#define GLQF_FDSWAP_FV_WORD_VAL1_M\t\tBIT(15)\n+#define GLQF_FDSWAP_FV_WORD_INDX2_S\t\t16\n+#define GLQF_FDSWAP_FV_WORD_INDX2_M\t\tMAKEMASK(0x1F, 16)\n+#define GLQF_FDSWAP_FV_WORD_VAL2_S\t\t23\n+#define GLQF_FDSWAP_FV_WORD_VAL2_M\t\tBIT(23)\n+#define GLQF_FDSWAP_FV_WORD_INDX3_S\t\t24\n+#define GLQF_FDSWAP_FV_WORD_INDX3_M\t\tMAKEMASK(0x1F, 24)\n+#define GLQF_FDSWAP_FV_WORD_VAL3_S\t\t31\n+#define GLQF_FDSWAP_FV_WORD_VAL3_M\t\tBIT(31)\n+#define GLQF_HINSET(_i, _j)\t\t\t(0x0040E000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */\n+#define GLQF_HINSET_MAX_INDEX\t\t\t127\n+#define GLQF_HINSET_FV_WORD_INDX0_S\t\t0\n+#define GLQF_HINSET_FV_WORD_INDX0_M\t\tMAKEMASK(0x1F, 0)\n+#define GLQF_HINSET_FV_WORD_VAL0_S\t\t7\n+#define GLQF_HINSET_FV_WORD_VAL0_M\t\tBIT(7)\n+#define GLQF_HINSET_FV_WORD_INDX1_S\t\t8\n+#define GLQF_HINSET_FV_WORD_INDX1_M\t\tMAKEMASK(0x1F, 8)\n+#define GLQF_HINSET_FV_WORD_VAL1_S\t\t15\n+#define GLQF_HINSET_FV_WORD_VAL1_M\t\tBIT(15)\n+#define GLQF_HINSET_FV_WORD_INDX2_S\t\t16\n+#define GLQF_HINSET_FV_WORD_INDX2_M\t\tMAKEMASK(0x1F, 16)\n+#define GLQF_HINSET_FV_WORD_VAL2_S\t\t23\n+#define GLQF_HINSET_FV_WORD_VAL2_M\t\tBIT(23)\n+#define GLQF_HINSET_FV_WORD_INDX3_S\t\t24\n+#define GLQF_HINSET_FV_WORD_INDX3_M\t\tMAKEMASK(0x1F, 24)\n+#define GLQF_HINSET_FV_WORD_VAL3_S\t\t31\n+#define GLQF_HINSET_FV_WORD_VAL3_M\t\tBIT(31)\n+#define GLQF_HKEY(_i)\t\t\t\t(0x00456000 + ((_i) * 4)) /* _i=0...12 */ /* Reset Source: CORER */\n+#define GLQF_HKEY_MAX_INDEX\t\t\t12\n+#define GLQF_HKEY_KEY_0_S\t\t\t0\n+#define GLQF_HKEY_KEY_0_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLQF_HKEY_KEY_1_S\t\t\t8\n+#define GLQF_HKEY_KEY_1_M\t\t\tMAKEMASK(0xFF, 8)\n+#define GLQF_HKEY_KEY_2_S\t\t\t16\n+#define GLQF_HKEY_KEY_2_M\t\t\tMAKEMASK(0xFF, 16)\n+#define GLQF_HKEY_KEY_3_S\t\t\t24\n+#define GLQF_HKEY_KEY_3_M\t\t\tMAKEMASK(0xFF, 24)\n+#define GLQF_HLUT(_i, _j)\t\t\t(0x00438000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...15 */ /* Reset Source: CORER */\n+#define GLQF_HLUT_MAX_INDEX\t\t\t127\n+#define GLQF_HLUT_LUT0_S\t\t\t0\n+#define GLQF_HLUT_LUT0_M\t\t\tMAKEMASK(0x3F, 0)\n+#define GLQF_HLUT_LUT1_S\t\t\t8\n+#define GLQF_HLUT_LUT1_M\t\t\tMAKEMASK(0x3F, 8)\n+#define GLQF_HLUT_LUT2_S\t\t\t16\n+#define GLQF_HLUT_LUT2_M\t\t\tMAKEMASK(0x3F, 16)\n+#define GLQF_HLUT_LUT3_S\t\t\t24\n+#define GLQF_HLUT_LUT3_M\t\t\tMAKEMASK(0x3F, 24)\n+#define GLQF_HLUT_SIZE(_i)\t\t\t(0x00455400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLQF_HLUT_SIZE_MAX_INDEX\t\t15\n+#define GLQF_HLUT_SIZE_HSIZE_S\t\t\t0\n+#define GLQF_HLUT_SIZE_HSIZE_M\t\t\tBIT(0)\n+#define GLQF_HMASK(_i)\t\t\t\t(0x0040FC00 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLQF_HMASK_MAX_INDEX\t\t\t31\n+#define GLQF_HMASK_MSK_INDEX_S\t\t\t0\n+#define GLQF_HMASK_MSK_INDEX_M\t\t\tMAKEMASK(0x1F, 0)\n+#define GLQF_HMASK_MASK_S\t\t\t16\n+#define GLQF_HMASK_MASK_M\t\t\tMAKEMASK(0xFFFF, 16)\n+#define GLQF_HMASK_SEL(_i)\t\t\t(0x00410000 + ((_i) * 4)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GLQF_HMASK_SEL_MAX_INDEX\t\t127\n+#define GLQF_HMASK_SEL_MASK_SEL_S\t\t0\n+#define GLQF_HMASK_SEL_MASK_SEL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQF_HSYMM(_i, _j)\t\t\t(0x0040F000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...5 */ /* Reset Source: CORER */\n+#define GLQF_HSYMM_MAX_INDEX\t\t\t127\n+#define GLQF_HSYMM_FV_SYMM_INDX0_S\t\t0\n+#define GLQF_HSYMM_FV_SYMM_INDX0_M\t\tMAKEMASK(0x1F, 0)\n+#define GLQF_HSYMM_SYMM0_ENA_S\t\t\t7\n+#define GLQF_HSYMM_SYMM0_ENA_M\t\t\tBIT(7)\n+#define GLQF_HSYMM_FV_SYMM_INDX1_S\t\t8\n+#define GLQF_HSYMM_FV_SYMM_INDX1_M\t\tMAKEMASK(0x1F, 8)\n+#define GLQF_HSYMM_SYMM1_ENA_S\t\t\t15\n+#define GLQF_HSYMM_SYMM1_ENA_M\t\t\tBIT(15)\n+#define GLQF_HSYMM_FV_SYMM_INDX2_S\t\t16\n+#define GLQF_HSYMM_FV_SYMM_INDX2_M\t\tMAKEMASK(0x1F, 16)\n+#define GLQF_HSYMM_SYMM2_ENA_S\t\t\t23\n+#define GLQF_HSYMM_SYMM2_ENA_M\t\t\tBIT(23)\n+#define GLQF_HSYMM_FV_SYMM_INDX3_S\t\t24\n+#define GLQF_HSYMM_FV_SYMM_INDX3_M\t\tMAKEMASK(0x1F, 24)\n+#define GLQF_HSYMM_SYMM3_ENA_S\t\t\t31\n+#define GLQF_HSYMM_SYMM3_ENA_M\t\t\tBIT(31)\n+#define GLQF_PE_APBVT_CNT\t\t\t0x00455500 /* Reset Source: CORER */\n+#define GLQF_PE_APBVT_CNT_APBVT_LAN_S\t\t0\n+#define GLQF_PE_APBVT_CNT_APBVT_LAN_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLQF_PE_CMD\t\t\t\t0x00471080 /* Reset Source: CORER */\n+#define GLQF_PE_CMD_ADDREM_STS_S\t\t0\n+#define GLQF_PE_CMD_ADDREM_STS_M\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLQF_PE_CMD_ADDREM_ID_S\t\t\t28\n+#define GLQF_PE_CMD_ADDREM_ID_M\t\t\tMAKEMASK(0xF, 28)\n+#define GLQF_PE_CTL\t\t\t\t0x004710C0 /* Reset Source: CORER */\n+#define GLQF_PE_CTL_PELONG_S\t\t\t0\n+#define GLQF_PE_CTL_PELONG_M\t\t\tMAKEMASK(0xF, 0)\n+#define GLQF_PE_CTL2(_i)\t\t\t(0x00455200 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLQF_PE_CTL2_MAX_INDEX\t\t\t31\n+#define GLQF_PE_CTL2_TO_QH_S\t\t\t0\n+#define GLQF_PE_CTL2_TO_QH_M\t\t\tMAKEMASK(0x3, 0)\n+#define GLQF_PE_CTL2_APBVT_ENA_S\t\t2\n+#define GLQF_PE_CTL2_APBVT_ENA_M\t\tBIT(2)\n+#define GLQF_PE_FVE\t\t\t\t0x0020E514 /* Reset Source: CORER */\n+#define GLQF_PE_FVE_W_ENA_S\t\t\t0\n+#define GLQF_PE_FVE_W_ENA_M\t\t\tMAKEMASK(0xFFFFFF, 0)\n+#define GLQF_PE_OSR_STS\t\t\t\t0x00471040 /* Reset Source: CORER */\n+#define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_S\t0\n+#define GLQF_PE_OSR_STS_QH_SRCH_MAXOSR_M\tMAKEMASK(0x3FF, 0)\n+#define GLQF_PE_OSR_STS_QH_CMD_MAXOSR_S\t\t16\n+#define GLQF_PE_OSR_STS_QH_CMD_MAXOSR_M\t\tMAKEMASK(0x3FF, 16)\n+#define GLQF_PEINSET(_i, _j)\t\t\t(0x00415000 + ((_i) * 4 + (_j) * 128)) /* _i=0...31, _j=0...5 */ /* Reset Source: CORER */\n+#define GLQF_PEINSET_MAX_INDEX\t\t\t31\n+#define GLQF_PEINSET_FV_WORD_INDX0_S\t\t0\n+#define GLQF_PEINSET_FV_WORD_INDX0_M\t\tMAKEMASK(0x1F, 0)\n+#define GLQF_PEINSET_FV_WORD_VAL0_S\t\t7\n+#define GLQF_PEINSET_FV_WORD_VAL0_M\t\tBIT(7)\n+#define GLQF_PEINSET_FV_WORD_INDX1_S\t\t8\n+#define GLQF_PEINSET_FV_WORD_INDX1_M\t\tMAKEMASK(0x1F, 8)\n+#define GLQF_PEINSET_FV_WORD_VAL1_S\t\t15\n+#define GLQF_PEINSET_FV_WORD_VAL1_M\t\tBIT(15)\n+#define GLQF_PEINSET_FV_WORD_INDX2_S\t\t16\n+#define GLQF_PEINSET_FV_WORD_INDX2_M\t\tMAKEMASK(0x1F, 16)\n+#define GLQF_PEINSET_FV_WORD_VAL2_S\t\t23\n+#define GLQF_PEINSET_FV_WORD_VAL2_M\t\tBIT(23)\n+#define GLQF_PEINSET_FV_WORD_INDX3_S\t\t24\n+#define GLQF_PEINSET_FV_WORD_INDX3_M\t\tMAKEMASK(0x1F, 24)\n+#define GLQF_PEINSET_FV_WORD_VAL3_S\t\t31\n+#define GLQF_PEINSET_FV_WORD_VAL3_M\t\tBIT(31)\n+#define GLQF_PEMASK(_i)\t\t\t\t(0x00415400 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLQF_PEMASK_MAX_INDEX\t\t\t15\n+#define GLQF_PEMASK_MSK_INDEX_S\t\t\t0\n+#define GLQF_PEMASK_MSK_INDEX_M\t\t\tMAKEMASK(0x1F, 0)\n+#define GLQF_PEMASK_MASK_S\t\t\t16\n+#define GLQF_PEMASK_MASK_M\t\t\tMAKEMASK(0xFFFF, 16)\n+#define GLQF_PEMASK_SEL(_i)\t\t\t(0x00415500 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLQF_PEMASK_SEL_MAX_INDEX\t\t31\n+#define GLQF_PEMASK_SEL_MASK_SEL_S\t\t0\n+#define GLQF_PEMASK_SEL_MASK_SEL_M\t\tMAKEMASK(0xFFFF, 0)\n+#define GLQF_PETABLE_CLR(_i)\t\t\t(0x000AA078 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLQF_PETABLE_CLR_MAX_INDEX\t\t1\n+#define GLQF_PETABLE_CLR_VM_VF_NUM_S\t\t0\n+#define GLQF_PETABLE_CLR_VM_VF_NUM_M\t\tMAKEMASK(0x3FF, 0)\n+#define GLQF_PETABLE_CLR_VM_VF_TYPE_S\t\t10\n+#define GLQF_PETABLE_CLR_VM_VF_TYPE_M\t\tMAKEMASK(0x3, 10)\n+#define GLQF_PETABLE_CLR_PF_NUM_S\t\t12\n+#define GLQF_PETABLE_CLR_PF_NUM_M\t\tMAKEMASK(0x7, 12)\n+#define GLQF_PETABLE_CLR_PE_BUSY_S\t\t16\n+#define GLQF_PETABLE_CLR_PE_BUSY_M\t\tBIT(16)\n+#define GLQF_PETABLE_CLR_PE_CLEAR_S\t\t17\n+#define GLQF_PETABLE_CLR_PE_CLEAR_M\t\tBIT(17)\n+#define GLQF_PROF2TC(_i, _j)\t\t\t(0x0044D000 + ((_i) * 4 + (_j) * 512)) /* _i=0...127, _j=0...3 */ /* Reset Source: CORER */\n+#define GLQF_PROF2TC_MAX_INDEX\t\t\t127\n+#define GLQF_PROF2TC_OVERRIDE_ENA_0_S\t\t0\n+#define GLQF_PROF2TC_OVERRIDE_ENA_0_M\t\tBIT(0)\n+#define GLQF_PROF2TC_REGION_0_S\t\t\t1\n+#define GLQF_PROF2TC_REGION_0_M\t\t\tMAKEMASK(0x7, 1)\n+#define GLQF_PROF2TC_OVERRIDE_ENA_1_S\t\t4\n+#define GLQF_PROF2TC_OVERRIDE_ENA_1_M\t\tBIT(4)\n+#define GLQF_PROF2TC_REGION_1_S\t\t\t5\n+#define GLQF_PROF2TC_REGION_1_M\t\t\tMAKEMASK(0x7, 5)\n+#define GLQF_PROF2TC_OVERRIDE_ENA_2_S\t\t8\n+#define GLQF_PROF2TC_OVERRIDE_ENA_2_M\t\tBIT(8)\n+#define GLQF_PROF2TC_REGION_2_S\t\t\t9\n+#define GLQF_PROF2TC_REGION_2_M\t\t\tMAKEMASK(0x7, 9)\n+#define GLQF_PROF2TC_OVERRIDE_ENA_3_S\t\t12\n+#define GLQF_PROF2TC_OVERRIDE_ENA_3_M\t\tBIT(12)\n+#define GLQF_PROF2TC_REGION_3_S\t\t\t13\n+#define GLQF_PROF2TC_REGION_3_M\t\t\tMAKEMASK(0x7, 13)\n+#define GLQF_PROF2TC_OVERRIDE_ENA_4_S\t\t16\n+#define GLQF_PROF2TC_OVERRIDE_ENA_4_M\t\tBIT(16)\n+#define GLQF_PROF2TC_REGION_4_S\t\t\t17\n+#define GLQF_PROF2TC_REGION_4_M\t\t\tMAKEMASK(0x7, 17)\n+#define GLQF_PROF2TC_OVERRIDE_ENA_5_S\t\t20\n+#define GLQF_PROF2TC_OVERRIDE_ENA_5_M\t\tBIT(20)\n+#define GLQF_PROF2TC_REGION_5_S\t\t\t21\n+#define GLQF_PROF2TC_REGION_5_M\t\t\tMAKEMASK(0x7, 21)\n+#define GLQF_PROF2TC_OVERRIDE_ENA_6_S\t\t24\n+#define GLQF_PROF2TC_OVERRIDE_ENA_6_M\t\tBIT(24)\n+#define GLQF_PROF2TC_REGION_6_S\t\t\t25\n+#define GLQF_PROF2TC_REGION_6_M\t\t\tMAKEMASK(0x7, 25)\n+#define GLQF_PROF2TC_OVERRIDE_ENA_7_S\t\t28\n+#define GLQF_PROF2TC_OVERRIDE_ENA_7_M\t\tBIT(28)\n+#define GLQF_PROF2TC_REGION_7_S\t\t\t29\n+#define GLQF_PROF2TC_REGION_7_M\t\t\tMAKEMASK(0x7, 29)\n+#define PFQF_FD_CNT\t\t\t\t0x00460180 /* Reset Source: CORER */\n+#define PFQF_FD_CNT_FD_GCNT_S\t\t\t0\n+#define PFQF_FD_CNT_FD_GCNT_M\t\t\tMAKEMASK(0x7FFF, 0)\n+#define PFQF_FD_CNT_FD_BCNT_S\t\t\t16\n+#define PFQF_FD_CNT_FD_BCNT_M\t\t\tMAKEMASK(0x7FFF, 16)\n+#define PFQF_FD_ENA\t\t\t\t0x0043A000 /* Reset Source: CORER */\n+#define PFQF_FD_ENA_FD_ENA_S\t\t\t0\n+#define PFQF_FD_ENA_FD_ENA_M\t\t\tBIT(0)\n+#define PFQF_FD_SIZE\t\t\t\t0x00460100 /* Reset Source: CORER */\n+#define PFQF_FD_SIZE_FD_GSIZE_S\t\t\t0\n+#define PFQF_FD_SIZE_FD_GSIZE_M\t\t\tMAKEMASK(0x7FFF, 0)\n+#define PFQF_FD_SIZE_FD_BSIZE_S\t\t\t16\n+#define PFQF_FD_SIZE_FD_BSIZE_M\t\t\tMAKEMASK(0x7FFF, 16)\n+#define PFQF_FD_SUBTRACT\t\t\t0x00460200 /* Reset Source: CORER */\n+#define PFQF_FD_SUBTRACT_FD_GCNT_S\t\t0\n+#define PFQF_FD_SUBTRACT_FD_GCNT_M\t\tMAKEMASK(0x7FFF, 0)\n+#define PFQF_FD_SUBTRACT_FD_BCNT_S\t\t16\n+#define PFQF_FD_SUBTRACT_FD_BCNT_M\t\tMAKEMASK(0x7FFF, 16)\n+#define PFQF_HLUT(_i)\t\t\t\t(0x00430000 + ((_i) * 64)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define PFQF_HLUT_MAX_INDEX\t\t\t511\n+#define PFQF_HLUT_LUT0_S\t\t\t0\n+#define PFQF_HLUT_LUT0_M\t\t\tMAKEMASK(0xFF, 0)\n+#define PFQF_HLUT_LUT1_S\t\t\t8\n+#define PFQF_HLUT_LUT1_M\t\t\tMAKEMASK(0xFF, 8)\n+#define PFQF_HLUT_LUT2_S\t\t\t16\n+#define PFQF_HLUT_LUT2_M\t\t\tMAKEMASK(0xFF, 16)\n+#define PFQF_HLUT_LUT3_S\t\t\t24\n+#define PFQF_HLUT_LUT3_M\t\t\tMAKEMASK(0xFF, 24)\n+#define PFQF_HLUT_SIZE\t\t\t\t0x00455480 /* Reset Source: CORER */\n+#define PFQF_HLUT_SIZE_HSIZE_S\t\t\t0\n+#define PFQF_HLUT_SIZE_HSIZE_M\t\t\tMAKEMASK(0x3, 0)\n+#define PFQF_PE_CLSN0\t\t\t\t0x00470480 /* Reset Source: CORER */\n+#define PFQF_PE_CLSN0_HITSBCNT_S\t\t0\n+#define PFQF_PE_CLSN0_HITSBCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFQF_PE_CLSN1\t\t\t\t0x00470500 /* Reset Source: CORER */\n+#define PFQF_PE_CLSN1_HITLBCNT_S\t\t0\n+#define PFQF_PE_CLSN1_HITLBCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFQF_PE_CTL1\t\t\t\t0x00470000 /* Reset Source: CORER */\n+#define PFQF_PE_CTL1_PEHSIZE_S\t\t\t0\n+#define PFQF_PE_CTL1_PEHSIZE_M\t\t\tMAKEMASK(0xF, 0)\n+#define PFQF_PE_CTL2\t\t\t\t0x00470040 /* Reset Source: CORER */\n+#define PFQF_PE_CTL2_PEDSIZE_S\t\t\t0\n+#define PFQF_PE_CTL2_PEDSIZE_M\t\t\tMAKEMASK(0xF, 0)\n+#define PFQF_PE_FILTERING_ENA\t\t\t0x0043A080 /* Reset Source: CORER */\n+#define PFQF_PE_FILTERING_ENA_PE_ENA_S\t\t0\n+#define PFQF_PE_FILTERING_ENA_PE_ENA_M\t\tBIT(0)\n+#define PFQF_PE_FLHD\t\t\t\t0x00470100 /* Reset Source: CORER */\n+#define PFQF_PE_FLHD_FLHD_S\t\t\t0\n+#define PFQF_PE_FLHD_FLHD_M\t\t\tMAKEMASK(0xFFFFFF, 0)\n+#define PFQF_PE_ST_CTL\t\t\t\t0x00470400 /* Reset Source: CORER */\n+#define PFQF_PE_ST_CTL_PF_CNT_EN_S\t\t0\n+#define PFQF_PE_ST_CTL_PF_CNT_EN_M\t\tBIT(0)\n+#define PFQF_PE_ST_CTL_VFS_CNT_EN_S\t\t1\n+#define PFQF_PE_ST_CTL_VFS_CNT_EN_M\t\tBIT(1)\n+#define PFQF_PE_ST_CTL_VF_CNT_EN_S\t\t2\n+#define PFQF_PE_ST_CTL_VF_CNT_EN_M\t\tBIT(2)\n+#define PFQF_PE_ST_CTL_VF_NUM_S\t\t\t16\n+#define PFQF_PE_ST_CTL_VF_NUM_M\t\t\tMAKEMASK(0xFF, 16)\n+#define PFQF_PE_TC_CTL\t\t\t\t0x00452080 /* Reset Source: CORER */\n+#define PFQF_PE_TC_CTL_TC_EN_PF_S\t\t0\n+#define PFQF_PE_TC_CTL_TC_EN_PF_M\t\tMAKEMASK(0xFF, 0)\n+#define PFQF_PE_TC_CTL_TC_EN_VF_S\t\t16\n+#define PFQF_PE_TC_CTL_TC_EN_VF_M\t\tMAKEMASK(0xFF, 16)\n+#define PFQF_PECNT_0\t\t\t\t0x00470200 /* Reset Source: CORER */\n+#define PFQF_PECNT_0_BUCKETCNT_S\t\t0\n+#define PFQF_PECNT_0_BUCKETCNT_M\t\tMAKEMASK(0x3FFFF, 0)\n+#define PFQF_PECNT_1\t\t\t\t0x00470300 /* Reset Source: CORER */\n+#define PFQF_PECNT_1_FLTCNT_S\t\t\t0\n+#define PFQF_PECNT_1_FLTCNT_M\t\t\tMAKEMASK(0x3FFFF, 0)\n+#define VPQF_PE_CTL1(_VF)\t\t\t(0x00474000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPQF_PE_CTL1_MAX_INDEX\t\t\t255\n+#define VPQF_PE_CTL1_PEHSIZE_S\t\t\t0\n+#define VPQF_PE_CTL1_PEHSIZE_M\t\t\tMAKEMASK(0xF, 0)\n+#define VPQF_PE_CTL2(_VF)\t\t\t(0x00474800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPQF_PE_CTL2_MAX_INDEX\t\t\t255\n+#define VPQF_PE_CTL2_PEDSIZE_S\t\t\t0\n+#define VPQF_PE_CTL2_PEDSIZE_M\t\t\tMAKEMASK(0xF, 0)\n+#define VPQF_PE_FILTERING_ENA(_VF)\t\t(0x00455800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPQF_PE_FILTERING_ENA_MAX_INDEX\t\t255\n+#define VPQF_PE_FILTERING_ENA_PE_ENA_S\t\t0\n+#define VPQF_PE_FILTERING_ENA_PE_ENA_M\t\tBIT(0)\n+#define VPQF_PE_FLHD(_VF)\t\t\t(0x00472000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPQF_PE_FLHD_MAX_INDEX\t\t\t255\n+#define VPQF_PE_FLHD_FLHD_S\t\t\t0\n+#define VPQF_PE_FLHD_FLHD_M\t\t\tMAKEMASK(0xFFFFFF, 0)\n+#define VPQF_PECNT_0(_VF)\t\t\t(0x00472800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPQF_PECNT_0_MAX_INDEX\t\t\t255\n+#define VPQF_PECNT_0_BUCKETCNT_S\t\t0\n+#define VPQF_PECNT_0_BUCKETCNT_M\t\tMAKEMASK(0x3FFFF, 0)\n+#define VPQF_PECNT_1(_VF)\t\t\t(0x00473000 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VPQF_PECNT_1_MAX_INDEX\t\t\t255\n+#define VPQF_PECNT_1_FLTCNT_S\t\t\t0\n+#define VPQF_PECNT_1_FLTCNT_M\t\t\tMAKEMASK(0x3FFFF, 0)\n+#define GLDCB_RMPMC\t\t\t\t0x001223C8 /* Reset Source: CORER */\n+#define GLDCB_RMPMC_RSPM_S\t\t\t0\n+#define GLDCB_RMPMC_RSPM_M\t\t\tMAKEMASK(0x3F, 0)\n+#define GLDCB_RMPMC_MIQ_NODROP_MODE_S\t\t6\n+#define GLDCB_RMPMC_MIQ_NODROP_MODE_M\t\tMAKEMASK(0x1F, 6)\n+#define GLDCB_RMPMC_RPM_DIS_S\t\t\t31\n+#define GLDCB_RMPMC_RPM_DIS_M\t\t\tBIT(31)\n+#define GLDCB_RMPMS\t\t\t\t0x001223CC /* Reset Source: CORER */\n+#define GLDCB_RMPMS_RMPM_S\t\t\t0\n+#define GLDCB_RMPMS_RMPM_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define GLDCB_RPCC\t\t\t\t0x00122260 /* Reset Source: CORER */\n+#define GLDCB_RPCC_EN_S\t\t\t\t0\n+#define GLDCB_RPCC_EN_M\t\t\t\tBIT(0)\n+#define GLDCB_RPCC_SCL_FACT_S\t\t\t4\n+#define GLDCB_RPCC_SCL_FACT_M\t\t\tMAKEMASK(0x1F, 4)\n+#define GLDCB_RPCC_THRSH_S\t\t\t16\n+#define GLDCB_RPCC_THRSH_M\t\t\tMAKEMASK(0xFFF, 16)\n+#define GLDCB_RSPMC\t\t\t\t0x001223C4 /* Reset Source: CORER */\n+#define GLDCB_RSPMC_RSPM_S\t\t\t0\n+#define GLDCB_RSPMC_RSPM_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLDCB_RSPMC_RPM_MODE_S\t\t\t8\n+#define GLDCB_RSPMC_RPM_MODE_M\t\t\tMAKEMASK(0x3, 8)\n+#define GLDCB_RSPMC_PRR_MAX_EXP_S\t\t10\n+#define GLDCB_RSPMC_PRR_MAX_EXP_M\t\tMAKEMASK(0xF, 10)\n+#define GLDCB_RSPMC_PFCTIMER_S\t\t\t14\n+#define GLDCB_RSPMC_PFCTIMER_M\t\t\tMAKEMASK(0x3FFF, 14)\n+#define GLDCB_RSPMC_RPM_DIS_S\t\t\t31\n+#define GLDCB_RSPMC_RPM_DIS_M\t\t\tBIT(31)\n+#define GLDCB_RSPMS\t\t\t\t0x001223C0 /* Reset Source: CORER */\n+#define GLDCB_RSPMS_RSPM_S\t\t\t0\n+#define GLDCB_RSPMS_RSPM_M\t\t\tMAKEMASK(0x3FFFF, 0)\n+#define GLDCB_RTCTI\t\t\t\t0x001223D0 /* Reset Source: CORER */\n+#define GLDCB_RTCTI_PFCTIMEOUT_TC_S\t\t0\n+#define GLDCB_RTCTI_PFCTIMEOUT_TC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLDCB_RTCTQ(_i)\t\t\t\t(0x001222C0 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLDCB_RTCTQ_MAX_INDEX\t\t\t31\n+#define GLDCB_RTCTQ_RXQNUM_S\t\t\t0\n+#define GLDCB_RTCTQ_RXQNUM_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define GLDCB_RTCTQ_IS_PF_Q_S\t\t\t16\n+#define GLDCB_RTCTQ_IS_PF_Q_M\t\t\tBIT(16)\n+#define GLDCB_RTCTS(_i)\t\t\t\t(0x00122340 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLDCB_RTCTS_MAX_INDEX\t\t\t31\n+#define GLDCB_RTCTS_PFCTIMER_S\t\t\t0\n+#define GLDCB_RTCTS_PFCTIMER_M\t\t\tMAKEMASK(0x3FFF, 0)\n+#define GLRCB_CFG_COTF_CNT(_i)\t\t\t(0x001223D4 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLRCB_CFG_COTF_CNT_MAX_INDEX\t\t7\n+#define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_S\t0\n+#define GLRCB_CFG_COTF_CNT_MRKR_COTF_CNT_M\tMAKEMASK(0x3F, 0)\n+#define GLRCB_CFG_COTF_ST\t\t\t0x001223F4 /* Reset Source: CORER */\n+#define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_S\t0\n+#define GLRCB_CFG_COTF_ST_MRKR_COTF_ST_M\tMAKEMASK(0xFF, 0)\n+#define GLRPRS_PMCFG_DHW(_i)\t\t\t(0x00200388 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLRPRS_PMCFG_DHW_MAX_INDEX\t\t15\n+#define GLRPRS_PMCFG_DHW_DHW_S\t\t\t0\n+#define GLRPRS_PMCFG_DHW_DHW_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPRS_PMCFG_DLW(_i)\t\t\t(0x002003C8 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLRPRS_PMCFG_DLW_MAX_INDEX\t\t15\n+#define GLRPRS_PMCFG_DLW_DLW_S\t\t\t0\n+#define GLRPRS_PMCFG_DLW_DLW_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPRS_PMCFG_DPS(_i)\t\t\t(0x00200308 + ((_i) * 4)) /* _i=0...15 */ /* Reset Source: CORER */\n+#define GLRPRS_PMCFG_DPS_MAX_INDEX\t\t15\n+#define GLRPRS_PMCFG_DPS_DPS_S\t\t\t0\n+#define GLRPRS_PMCFG_DPS_DPS_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPRS_PMCFG_SHW(_i)\t\t\t(0x00200448 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLRPRS_PMCFG_SHW_MAX_INDEX\t\t7\n+#define GLRPRS_PMCFG_SHW_SHW_S\t\t\t0\n+#define GLRPRS_PMCFG_SHW_SHW_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPRS_PMCFG_SLW(_i)\t\t\t(0x00200468 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLRPRS_PMCFG_SLW_MAX_INDEX\t\t7\n+#define GLRPRS_PMCFG_SLW_SLW_S\t\t\t0\n+#define GLRPRS_PMCFG_SLW_SLW_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPRS_PMCFG_SPS(_i)\t\t\t(0x00200408 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLRPRS_PMCFG_SPS_MAX_INDEX\t\t7\n+#define GLRPRS_PMCFG_SPS_SPS_S\t\t\t0\n+#define GLRPRS_PMCFG_SPS_SPS_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPRS_PMCFG_TC_CFG(_i)\t\t\t(0x00200488 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLRPRS_PMCFG_TC_CFG_MAX_INDEX\t\t31\n+#define GLRPRS_PMCFG_TC_CFG_D_POOL_S\t\t0\n+#define GLRPRS_PMCFG_TC_CFG_D_POOL_M\t\tMAKEMASK(0xF, 0)\n+#define GLRPRS_PMCFG_TC_CFG_S_POOL_S\t\t16\n+#define GLRPRS_PMCFG_TC_CFG_S_POOL_M\t\tMAKEMASK(0x7, 16)\n+#define GLRPRS_PMCFG_TCHW(_i)\t\t\t(0x00200588 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLRPRS_PMCFG_TCHW_MAX_INDEX\t\t31\n+#define GLRPRS_PMCFG_TCHW_TCHW_S\t\t0\n+#define GLRPRS_PMCFG_TCHW_TCHW_M\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLRPRS_PMCFG_TCLW(_i)\t\t\t(0x00200608 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLRPRS_PMCFG_TCLW_MAX_INDEX\t\t31\n+#define GLRPRS_PMCFG_TCLW_TCLW_S\t\t0\n+#define GLRPRS_PMCFG_TCLW_TCLW_M\t\tMAKEMASK(0xFFFFF, 0)\n+#define GLSWT_PMCFG_TC_CFG(_i)\t\t\t(0x00204900 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSWT_PMCFG_TC_CFG_MAX_INDEX\t\t31\n+#define GLSWT_PMCFG_TC_CFG_D_POOL_S\t\t0\n+#define GLSWT_PMCFG_TC_CFG_D_POOL_M\t\tMAKEMASK(0xF, 0)\n+#define GLSWT_PMCFG_TC_CFG_S_POOL_S\t\t16\n+#define GLSWT_PMCFG_TC_CFG_S_POOL_M\t\tMAKEMASK(0x7, 16)\n+#define PRTDCB_RLANPMS\t\t\t\t0x00122280 /* Reset Source: CORER */\n+#define PRTDCB_RLANPMS_LANRPPM_S\t\t0\n+#define PRTDCB_RLANPMS_LANRPPM_M\t\tMAKEMASK(0x3FFFF, 0)\n+#define PRTDCB_RPPMC\t\t\t\t0x00122240 /* Reset Source: CORER */\n+#define PRTDCB_RPPMC_LANRPPM_S\t\t\t0\n+#define PRTDCB_RPPMC_LANRPPM_M\t\t\tMAKEMASK(0xFF, 0)\n+#define PRTDCB_RPPMC_RDMARPPM_S\t\t\t8\n+#define PRTDCB_RPPMC_RDMARPPM_M\t\t\tMAKEMASK(0xFF, 8)\n+#define PRTDCB_RRDMAPMS\t\t\t\t0x00122120 /* Reset Source: CORER */\n+#define PRTDCB_RRDMAPMS_RDMARPPM_S\t\t0\n+#define PRTDCB_RRDMAPMS_RDMARPPM_M\t\tMAKEMASK(0x3FFFF, 0)\n+#define GL_STAT_SWR_BPCH(_i)\t\t\t(0x00347804 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_BPCH_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_BPCH_VLBPCH_S\t\t0\n+#define GL_STAT_SWR_BPCH_VLBPCH_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_STAT_SWR_BPCL(_i)\t\t\t(0x00347800 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_BPCL_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_BPCL_VLBPCL_S\t\t0\n+#define GL_STAT_SWR_BPCL_VLBPCL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_STAT_SWR_GORCH(_i)\t\t\t(0x00342004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_GORCH_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_GORCH_VLBCH_S\t\t0\n+#define GL_STAT_SWR_GORCH_VLBCH_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_STAT_SWR_GORCL(_i)\t\t\t(0x00342000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_GORCL_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_GORCL_VLBCL_S\t\t0\n+#define GL_STAT_SWR_GORCL_VLBCL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_STAT_SWR_GOTCH(_i)\t\t\t(0x00304004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_GOTCH_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_GOTCH_VLBCH_S\t\t0\n+#define GL_STAT_SWR_GOTCH_VLBCH_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_STAT_SWR_GOTCL(_i)\t\t\t(0x00304000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_GOTCL_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_GOTCL_VLBCL_S\t\t0\n+#define GL_STAT_SWR_GOTCL_VLBCL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_STAT_SWR_MPCH(_i)\t\t\t(0x00347404 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_MPCH_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_MPCH_VLMPCH_S\t\t0\n+#define GL_STAT_SWR_MPCH_VLMPCH_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_STAT_SWR_MPCL(_i)\t\t\t(0x00347400 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_MPCL_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_MPCL_VLMPCL_S\t\t0\n+#define GL_STAT_SWR_MPCL_VLMPCL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_STAT_SWR_UPCH(_i)\t\t\t(0x00347004 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_UPCH_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_UPCH_VLUPCH_S\t\t0\n+#define GL_STAT_SWR_UPCH_VLUPCH_M\t\tMAKEMASK(0xFF, 0)\n+#define GL_STAT_SWR_UPCL(_i)\t\t\t(0x00347000 + ((_i) * 8)) /* _i=0...127 */ /* Reset Source: CORER */\n+#define GL_STAT_SWR_UPCL_MAX_INDEX\t\t127\n+#define GL_STAT_SWR_UPCL_VLUPCL_S\t\t0\n+#define GL_STAT_SWR_UPCL_VLUPCL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_AORCL(_i)\t\t\t\t(0x003812C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_AORCL_MAX_INDEX\t\t\t7\n+#define GLPRT_AORCL_AORCL_S\t\t\t0\n+#define GLPRT_AORCL_AORCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_BPRCH(_i)\t\t\t\t(0x00381384 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_BPRCH_MAX_INDEX\t\t\t7\n+#define GLPRT_BPRCH_UPRCH_S\t\t\t0\n+#define GLPRT_BPRCH_UPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_BPRCL(_i)\t\t\t\t(0x00381380 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_BPRCL_MAX_INDEX\t\t\t7\n+#define GLPRT_BPRCL_UPRCH_S\t\t\t0\n+#define GLPRT_BPRCL_UPRCH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_BPTCH(_i)\t\t\t\t(0x00381244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_BPTCH_MAX_INDEX\t\t\t7\n+#define GLPRT_BPTCH_UPRCH_S\t\t\t0\n+#define GLPRT_BPTCH_UPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_BPTCL(_i)\t\t\t\t(0x00381240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_BPTCL_MAX_INDEX\t\t\t7\n+#define GLPRT_BPTCL_UPRCH_S\t\t\t0\n+#define GLPRT_BPTCL_UPRCH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_CRCERRS(_i)\t\t\t(0x00380100 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_CRCERRS_MAX_INDEX\t\t\t7\n+#define GLPRT_CRCERRS_CRCERRS_S\t\t\t0\n+#define GLPRT_CRCERRS_CRCERRS_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_CRCERRS_H(_i)\t\t\t(0x00380104 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_CRCERRS_H_MAX_INDEX\t\t7\n+#define GLPRT_CRCERRS_H_CRCERRS_S\t\t0\n+#define GLPRT_CRCERRS_H_CRCERRS_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_GORCH(_i)\t\t\t\t(0x00380004 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_GORCH_MAX_INDEX\t\t\t7\n+#define GLPRT_GORCH_GORCH_S\t\t\t0\n+#define GLPRT_GORCH_GORCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_GORCL(_i)\t\t\t\t(0x00380000 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_GORCL_MAX_INDEX\t\t\t7\n+#define GLPRT_GORCL_GORCL_S\t\t\t0\n+#define GLPRT_GORCL_GORCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_GOTCH(_i)\t\t\t\t(0x00380B44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_GOTCH_MAX_INDEX\t\t\t7\n+#define GLPRT_GOTCH_GOTCH_S\t\t\t0\n+#define GLPRT_GOTCH_GOTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_GOTCL(_i)\t\t\t\t(0x00380B40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_GOTCL_MAX_INDEX\t\t\t7\n+#define GLPRT_GOTCL_GOTCL_S\t\t\t0\n+#define GLPRT_GOTCL_GOTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_ILLERRC(_i)\t\t\t(0x003801C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_ILLERRC_MAX_INDEX\t\t\t7\n+#define GLPRT_ILLERRC_ILLERRC_S\t\t\t0\n+#define GLPRT_ILLERRC_ILLERRC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_ILLERRC_H(_i)\t\t\t(0x003801C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_ILLERRC_H_MAX_INDEX\t\t7\n+#define GLPRT_ILLERRC_H_ILLERRC_S\t\t0\n+#define GLPRT_ILLERRC_H_ILLERRC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_LXOFFRXC(_i)\t\t\t(0x003802C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_LXOFFRXC_MAX_INDEX\t\t7\n+#define GLPRT_LXOFFRXC_LXOFFRXCNT_S\t\t0\n+#define GLPRT_LXOFFRXC_LXOFFRXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_LXOFFRXC_H(_i)\t\t\t(0x003802C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_LXOFFRXC_H_MAX_INDEX\t\t7\n+#define GLPRT_LXOFFRXC_H_LXOFFRXCNT_S\t\t0\n+#define GLPRT_LXOFFRXC_H_LXOFFRXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_LXOFFTXC(_i)\t\t\t(0x00381180 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_LXOFFTXC_MAX_INDEX\t\t7\n+#define GLPRT_LXOFFTXC_LXOFFTXC_S\t\t0\n+#define GLPRT_LXOFFTXC_LXOFFTXC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_LXOFFTXC_H(_i)\t\t\t(0x00381184 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_LXOFFTXC_H_MAX_INDEX\t\t7\n+#define GLPRT_LXOFFTXC_H_LXOFFTXC_S\t\t0\n+#define GLPRT_LXOFFTXC_H_LXOFFTXC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_LXONRXC(_i)\t\t\t(0x00380280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_LXONRXC_MAX_INDEX\t\t\t7\n+#define GLPRT_LXONRXC_LXONRXCNT_S\t\t0\n+#define GLPRT_LXONRXC_LXONRXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_LXONRXC_H(_i)\t\t\t(0x00380284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_LXONRXC_H_MAX_INDEX\t\t7\n+#define GLPRT_LXONRXC_H_LXONRXCNT_S\t\t0\n+#define GLPRT_LXONRXC_H_LXONRXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_LXONTXC(_i)\t\t\t(0x00381140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_LXONTXC_MAX_INDEX\t\t\t7\n+#define GLPRT_LXONTXC_LXONTXC_S\t\t\t0\n+#define GLPRT_LXONTXC_LXONTXC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_LXONTXC_H(_i)\t\t\t(0x00381144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_LXONTXC_H_MAX_INDEX\t\t7\n+#define GLPRT_LXONTXC_H_LXONTXC_S\t\t0\n+#define GLPRT_LXONTXC_H_LXONTXC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_MLFC(_i)\t\t\t\t(0x00380040 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_MLFC_MAX_INDEX\t\t\t7\n+#define GLPRT_MLFC_MLFC_S\t\t\t0\n+#define GLPRT_MLFC_MLFC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_MLFC_H(_i)\t\t\t(0x00380044 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_MLFC_H_MAX_INDEX\t\t\t7\n+#define GLPRT_MLFC_H_MLFC_S\t\t\t0\n+#define GLPRT_MLFC_H_MLFC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_MPRCH(_i)\t\t\t\t(0x00381344 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_MPRCH_MAX_INDEX\t\t\t7\n+#define GLPRT_MPRCH_MPRCH_S\t\t\t0\n+#define GLPRT_MPRCH_MPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_MPRCL(_i)\t\t\t\t(0x00381340 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_MPRCL_MAX_INDEX\t\t\t7\n+#define GLPRT_MPRCL_MPRCL_S\t\t\t0\n+#define GLPRT_MPRCL_MPRCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_MPTCH(_i)\t\t\t\t(0x00381204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_MPTCH_MAX_INDEX\t\t\t7\n+#define GLPRT_MPTCH_MPTCH_S\t\t\t0\n+#define GLPRT_MPTCH_MPTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_MPTCL(_i)\t\t\t\t(0x00381200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_MPTCL_MAX_INDEX\t\t\t7\n+#define GLPRT_MPTCL_MPTCL_S\t\t\t0\n+#define GLPRT_MPTCL_MPTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_MRFC(_i)\t\t\t\t(0x00380080 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_MRFC_MAX_INDEX\t\t\t7\n+#define GLPRT_MRFC_MRFC_S\t\t\t0\n+#define GLPRT_MRFC_MRFC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_MRFC_H(_i)\t\t\t(0x00380084 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_MRFC_H_MAX_INDEX\t\t\t7\n+#define GLPRT_MRFC_H_MRFC_S\t\t\t0\n+#define GLPRT_MRFC_H_MRFC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PRC1023H(_i)\t\t\t(0x00380A04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC1023H_MAX_INDEX\t\t7\n+#define GLPRT_PRC1023H_PRC1023H_S\t\t0\n+#define GLPRT_PRC1023H_PRC1023H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PRC1023L(_i)\t\t\t(0x00380A00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC1023L_MAX_INDEX\t\t7\n+#define GLPRT_PRC1023L_PRC1023L_S\t\t0\n+#define GLPRT_PRC1023L_PRC1023L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PRC127H(_i)\t\t\t(0x00380944 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC127H_MAX_INDEX\t\t\t7\n+#define GLPRT_PRC127H_PRC127H_S\t\t\t0\n+#define GLPRT_PRC127H_PRC127H_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PRC127L(_i)\t\t\t(0x00380940 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC127L_MAX_INDEX\t\t\t7\n+#define GLPRT_PRC127L_PRC127L_S\t\t\t0\n+#define GLPRT_PRC127L_PRC127L_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PRC1522H(_i)\t\t\t(0x00380A44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC1522H_MAX_INDEX\t\t7\n+#define GLPRT_PRC1522H_PRC1522H_S\t\t0\n+#define GLPRT_PRC1522H_PRC1522H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PRC1522L(_i)\t\t\t(0x00380A40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC1522L_MAX_INDEX\t\t7\n+#define GLPRT_PRC1522L_PRC1522L_S\t\t0\n+#define GLPRT_PRC1522L_PRC1522L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PRC255H(_i)\t\t\t(0x00380984 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC255H_MAX_INDEX\t\t\t7\n+#define GLPRT_PRC255H_PRTPRC255H_S\t\t0\n+#define GLPRT_PRC255H_PRTPRC255H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PRC255L(_i)\t\t\t(0x00380980 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC255L_MAX_INDEX\t\t\t7\n+#define GLPRT_PRC255L_PRC255L_S\t\t\t0\n+#define GLPRT_PRC255L_PRC255L_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PRC511H(_i)\t\t\t(0x003809C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC511H_MAX_INDEX\t\t\t7\n+#define GLPRT_PRC511H_PRC511H_S\t\t\t0\n+#define GLPRT_PRC511H_PRC511H_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PRC511L(_i)\t\t\t(0x003809C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC511L_MAX_INDEX\t\t\t7\n+#define GLPRT_PRC511L_PRC511L_S\t\t\t0\n+#define GLPRT_PRC511L_PRC511L_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PRC64H(_i)\t\t\t(0x00380904 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC64H_MAX_INDEX\t\t\t7\n+#define GLPRT_PRC64H_PRC64H_S\t\t\t0\n+#define GLPRT_PRC64H_PRC64H_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PRC64L(_i)\t\t\t(0x00380900 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC64L_MAX_INDEX\t\t\t7\n+#define GLPRT_PRC64L_PRC64L_S\t\t\t0\n+#define GLPRT_PRC64L_PRC64L_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PRC9522H(_i)\t\t\t(0x00380A84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC9522H_MAX_INDEX\t\t7\n+#define GLPRT_PRC9522H_PRC1522H_S\t\t0\n+#define GLPRT_PRC9522H_PRC1522H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PRC9522L(_i)\t\t\t(0x00380A80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PRC9522L_MAX_INDEX\t\t7\n+#define GLPRT_PRC9522L_PRC1522L_S\t\t0\n+#define GLPRT_PRC9522L_PRC1522L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PTC1023H(_i)\t\t\t(0x00380C84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC1023H_MAX_INDEX\t\t7\n+#define GLPRT_PTC1023H_PTC1023H_S\t\t0\n+#define GLPRT_PTC1023H_PTC1023H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PTC1023L(_i)\t\t\t(0x00380C80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC1023L_MAX_INDEX\t\t7\n+#define GLPRT_PTC1023L_PTC1023L_S\t\t0\n+#define GLPRT_PTC1023L_PTC1023L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PTC127H(_i)\t\t\t(0x00380BC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC127H_MAX_INDEX\t\t\t7\n+#define GLPRT_PTC127H_PTC127H_S\t\t\t0\n+#define GLPRT_PTC127H_PTC127H_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PTC127L(_i)\t\t\t(0x00380BC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC127L_MAX_INDEX\t\t\t7\n+#define GLPRT_PTC127L_PTC127L_S\t\t\t0\n+#define GLPRT_PTC127L_PTC127L_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PTC1522H(_i)\t\t\t(0x00380CC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC1522H_MAX_INDEX\t\t7\n+#define GLPRT_PTC1522H_PTC1522H_S\t\t0\n+#define GLPRT_PTC1522H_PTC1522H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PTC1522L(_i)\t\t\t(0x00380CC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC1522L_MAX_INDEX\t\t7\n+#define GLPRT_PTC1522L_PTC1522L_S\t\t0\n+#define GLPRT_PTC1522L_PTC1522L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PTC255H(_i)\t\t\t(0x00380C04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC255H_MAX_INDEX\t\t\t7\n+#define GLPRT_PTC255H_PTC255H_S\t\t\t0\n+#define GLPRT_PTC255H_PTC255H_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PTC255L(_i)\t\t\t(0x00380C00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC255L_MAX_INDEX\t\t\t7\n+#define GLPRT_PTC255L_PTC255L_S\t\t\t0\n+#define GLPRT_PTC255L_PTC255L_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PTC511H(_i)\t\t\t(0x00380C44 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC511H_MAX_INDEX\t\t\t7\n+#define GLPRT_PTC511H_PTC511H_S\t\t\t0\n+#define GLPRT_PTC511H_PTC511H_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PTC511L(_i)\t\t\t(0x00380C40 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC511L_MAX_INDEX\t\t\t7\n+#define GLPRT_PTC511L_PTC511L_S\t\t\t0\n+#define GLPRT_PTC511L_PTC511L_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PTC64H(_i)\t\t\t(0x00380B84 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC64H_MAX_INDEX\t\t\t7\n+#define GLPRT_PTC64H_PTC64H_S\t\t\t0\n+#define GLPRT_PTC64H_PTC64H_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PTC64L(_i)\t\t\t(0x00380B80 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC64L_MAX_INDEX\t\t\t7\n+#define GLPRT_PTC64L_PTC64L_S\t\t\t0\n+#define GLPRT_PTC64L_PTC64L_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PTC9522H(_i)\t\t\t(0x00380D04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC9522H_MAX_INDEX\t\t7\n+#define GLPRT_PTC9522H_PTC9522H_S\t\t0\n+#define GLPRT_PTC9522H_PTC9522H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_PTC9522L(_i)\t\t\t(0x00380D00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PTC9522L_MAX_INDEX\t\t7\n+#define GLPRT_PTC9522L_PTC9522L_S\t\t0\n+#define GLPRT_PTC9522L_PTC9522L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PXOFFRXC(_i, _j)\t\t\t(0x00380500 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PXOFFRXC_MAX_INDEX\t\t7\n+#define GLPRT_PXOFFRXC_PRPXOFFRXCNT_S\t\t0\n+#define GLPRT_PXOFFRXC_PRPXOFFRXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PXOFFRXC_H(_i, _j)\t\t(0x00380504 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PXOFFRXC_H_MAX_INDEX\t\t7\n+#define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_S\t\t0\n+#define GLPRT_PXOFFRXC_H_PRPXOFFRXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PXOFFTXC(_i, _j)\t\t\t(0x00380F40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PXOFFTXC_MAX_INDEX\t\t7\n+#define GLPRT_PXOFFTXC_PRPXOFFTXCNT_S\t\t0\n+#define GLPRT_PXOFFTXC_PRPXOFFTXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PXOFFTXC_H(_i, _j)\t\t(0x00380F44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PXOFFTXC_H_MAX_INDEX\t\t7\n+#define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_S\t\t0\n+#define GLPRT_PXOFFTXC_H_PRPXOFFTXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PXONRXC(_i, _j)\t\t\t(0x00380300 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PXONRXC_MAX_INDEX\t\t\t7\n+#define GLPRT_PXONRXC_PRPXONRXCNT_S\t\t0\n+#define GLPRT_PXONRXC_PRPXONRXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PXONRXC_H(_i, _j)\t\t\t(0x00380304 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PXONRXC_H_MAX_INDEX\t\t7\n+#define GLPRT_PXONRXC_H_PRPXONRXCNT_S\t\t0\n+#define GLPRT_PXONRXC_H_PRPXONRXCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PXONTXC(_i, _j)\t\t\t(0x00380D40 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PXONTXC_MAX_INDEX\t\t\t7\n+#define GLPRT_PXONTXC_PRPXONTXC_S\t\t0\n+#define GLPRT_PXONTXC_PRPXONTXC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_PXONTXC_H(_i, _j)\t\t\t(0x00380D44 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_PXONTXC_H_MAX_INDEX\t\t7\n+#define GLPRT_PXONTXC_H_PRPXONTXC_S\t\t0\n+#define GLPRT_PXONTXC_H_PRPXONTXC_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RFC(_i)\t\t\t\t(0x00380AC0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RFC_MAX_INDEX\t\t\t7\n+#define GLPRT_RFC_RFC_S\t\t\t\t0\n+#define GLPRT_RFC_RFC_M\t\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RFC_H(_i)\t\t\t\t(0x00380AC4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RFC_H_MAX_INDEX\t\t\t7\n+#define GLPRT_RFC_H_RFC_S\t\t\t0\n+#define GLPRT_RFC_H_RFC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RJC(_i)\t\t\t\t(0x00380B00 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RJC_MAX_INDEX\t\t\t7\n+#define GLPRT_RJC_RJC_S\t\t\t\t0\n+#define GLPRT_RJC_RJC_M\t\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RJC_H(_i)\t\t\t\t(0x00380B04 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RJC_H_MAX_INDEX\t\t\t7\n+#define GLPRT_RJC_H_RJC_S\t\t\t0\n+#define GLPRT_RJC_H_RJC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RLEC(_i)\t\t\t\t(0x00380140 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RLEC_MAX_INDEX\t\t\t7\n+#define GLPRT_RLEC_RLEC_S\t\t\t0\n+#define GLPRT_RLEC_RLEC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RLEC_H(_i)\t\t\t(0x00380144 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RLEC_H_MAX_INDEX\t\t\t7\n+#define GLPRT_RLEC_H_RLEC_S\t\t\t0\n+#define GLPRT_RLEC_H_RLEC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_ROC(_i)\t\t\t\t(0x00380240 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_ROC_MAX_INDEX\t\t\t7\n+#define GLPRT_ROC_ROC_S\t\t\t\t0\n+#define GLPRT_ROC_ROC_M\t\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_ROC_H(_i)\t\t\t\t(0x00380244 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_ROC_H_MAX_INDEX\t\t\t7\n+#define GLPRT_ROC_H_ROC_S\t\t\t0\n+#define GLPRT_ROC_H_ROC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RUC(_i)\t\t\t\t(0x00380200 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RUC_MAX_INDEX\t\t\t7\n+#define GLPRT_RUC_RUC_S\t\t\t\t0\n+#define GLPRT_RUC_RUC_M\t\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RUC_H(_i)\t\t\t\t(0x00380204 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RUC_H_MAX_INDEX\t\t\t7\n+#define GLPRT_RUC_H_RUC_S\t\t\t0\n+#define GLPRT_RUC_H_RUC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RXON2OFFCNT(_i, _j)\t\t(0x00380700 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RXON2OFFCNT_MAX_INDEX\t\t7\n+#define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_S\t0\n+#define GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_RXON2OFFCNT_H(_i, _j)\t\t(0x00380704 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_RXON2OFFCNT_H_MAX_INDEX\t\t7\n+#define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_S\t0\n+#define GLPRT_RXON2OFFCNT_H_PRRXON2OFFCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_STDC(_i)\t\t\t\t(0x00340000 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_STDC_MAX_INDEX\t\t\t7\n+#define GLPRT_STDC_STDC_S\t\t\t0\n+#define GLPRT_STDC_STDC_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_TDOLD(_i)\t\t\t\t(0x00381280 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_TDOLD_MAX_INDEX\t\t\t7\n+#define GLPRT_TDOLD_GLPRT_TDOLD_S\t\t0\n+#define GLPRT_TDOLD_GLPRT_TDOLD_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_TDOLD_H(_i)\t\t\t(0x00381284 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_TDOLD_H_MAX_INDEX\t\t\t7\n+#define GLPRT_TDOLD_H_GLPRT_TDOLD_S\t\t0\n+#define GLPRT_TDOLD_H_GLPRT_TDOLD_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_UPRCH(_i)\t\t\t\t(0x00381304 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_UPRCH_MAX_INDEX\t\t\t7\n+#define GLPRT_UPRCH_UPRCH_S\t\t\t0\n+#define GLPRT_UPRCH_UPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_UPRCL(_i)\t\t\t\t(0x00381300 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_UPRCL_MAX_INDEX\t\t\t7\n+#define GLPRT_UPRCL_UPRCL_S\t\t\t0\n+#define GLPRT_UPRCL_UPRCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPRT_UPTCH(_i)\t\t\t\t(0x003811C4 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_UPTCH_MAX_INDEX\t\t\t7\n+#define GLPRT_UPTCH_UPTCH_S\t\t\t0\n+#define GLPRT_UPTCH_UPTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLPRT_UPTCL(_i)\t\t\t\t(0x003811C0 + ((_i) * 8)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define GLPRT_UPTCL_MAX_INDEX\t\t\t7\n+#define GLPRT_UPTCL_VUPTCH_S\t\t\t0\n+#define GLPRT_UPTCL_VUPTCH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSTAT_ACL_CNT_0_H(_i)\t\t\t(0x00388004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLSTAT_ACL_CNT_0_H_MAX_INDEX\t\t511\n+#define GLSTAT_ACL_CNT_0_H_CNT_MSB_S\t\t0\n+#define GLSTAT_ACL_CNT_0_H_CNT_MSB_M\t\tMAKEMASK(0xFF, 0)\n+#define GLSTAT_ACL_CNT_0_L(_i)\t\t\t(0x00388000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLSTAT_ACL_CNT_0_L_MAX_INDEX\t\t511\n+#define GLSTAT_ACL_CNT_0_L_CNT_LSB_S\t\t0\n+#define GLSTAT_ACL_CNT_0_L_CNT_LSB_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSTAT_ACL_CNT_1_H(_i)\t\t\t(0x00389004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLSTAT_ACL_CNT_1_H_MAX_INDEX\t\t511\n+#define GLSTAT_ACL_CNT_1_H_CNT_MSB_S\t\t0\n+#define GLSTAT_ACL_CNT_1_H_CNT_MSB_M\t\tMAKEMASK(0xFF, 0)\n+#define GLSTAT_ACL_CNT_1_L(_i)\t\t\t(0x00389000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLSTAT_ACL_CNT_1_L_MAX_INDEX\t\t511\n+#define GLSTAT_ACL_CNT_1_L_CNT_LSB_S\t\t0\n+#define GLSTAT_ACL_CNT_1_L_CNT_LSB_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSTAT_ACL_CNT_2_H(_i)\t\t\t(0x0038A004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLSTAT_ACL_CNT_2_H_MAX_INDEX\t\t511\n+#define GLSTAT_ACL_CNT_2_H_CNT_MSB_S\t\t0\n+#define GLSTAT_ACL_CNT_2_H_CNT_MSB_M\t\tMAKEMASK(0xFF, 0)\n+#define GLSTAT_ACL_CNT_2_L(_i)\t\t\t(0x0038A000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLSTAT_ACL_CNT_2_L_MAX_INDEX\t\t511\n+#define GLSTAT_ACL_CNT_2_L_CNT_LSB_S\t\t0\n+#define GLSTAT_ACL_CNT_2_L_CNT_LSB_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSTAT_ACL_CNT_3_H(_i)\t\t\t(0x0038B004 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLSTAT_ACL_CNT_3_H_MAX_INDEX\t\t511\n+#define GLSTAT_ACL_CNT_3_H_CNT_MSB_S\t\t0\n+#define GLSTAT_ACL_CNT_3_H_CNT_MSB_M\t\tMAKEMASK(0xFF, 0)\n+#define GLSTAT_ACL_CNT_3_L(_i)\t\t\t(0x0038B000 + ((_i) * 8)) /* _i=0...511 */ /* Reset Source: CORER */\n+#define GLSTAT_ACL_CNT_3_L_MAX_INDEX\t\t511\n+#define GLSTAT_ACL_CNT_3_L_CNT_LSB_S\t\t0\n+#define GLSTAT_ACL_CNT_3_L_CNT_LSB_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSTAT_FD_CNT0H(_i)\t\t\t(0x003A0004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */\n+#define GLSTAT_FD_CNT0H_MAX_INDEX\t\t4095\n+#define GLSTAT_FD_CNT0H_FD0_CNT_H_S\t\t0\n+#define GLSTAT_FD_CNT0H_FD0_CNT_H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLSTAT_FD_CNT0L(_i)\t\t\t(0x003A0000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */\n+#define GLSTAT_FD_CNT0L_MAX_INDEX\t\t4095\n+#define GLSTAT_FD_CNT0L_FD0_CNT_L_S\t\t0\n+#define GLSTAT_FD_CNT0L_FD0_CNT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSTAT_FD_CNT1H(_i)\t\t\t(0x003A8004 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */\n+#define GLSTAT_FD_CNT1H_MAX_INDEX\t\t4095\n+#define GLSTAT_FD_CNT1H_FD0_CNT_H_S\t\t0\n+#define GLSTAT_FD_CNT1H_FD0_CNT_H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLSTAT_FD_CNT1L(_i)\t\t\t(0x003A8000 + ((_i) * 8)) /* _i=0...4095 */ /* Reset Source: CORER */\n+#define GLSTAT_FD_CNT1L_MAX_INDEX\t\t4095\n+#define GLSTAT_FD_CNT1L_FD0_CNT_L_S\t\t0\n+#define GLSTAT_FD_CNT1L_FD0_CNT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSW_BPRCH(_i)\t\t\t\t(0x00346204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_BPRCH_MAX_INDEX\t\t\t31\n+#define GLSW_BPRCH_BPRCH_S\t\t\t0\n+#define GLSW_BPRCH_BPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLSW_BPRCL(_i)\t\t\t\t(0x00346200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_BPRCL_MAX_INDEX\t\t\t31\n+#define GLSW_BPRCL_BPRCL_S\t\t\t0\n+#define GLSW_BPRCL_BPRCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSW_BPTCH(_i)\t\t\t\t(0x00310204 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_BPTCH_MAX_INDEX\t\t\t31\n+#define GLSW_BPTCH_BPTCH_S\t\t\t0\n+#define GLSW_BPTCH_BPTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLSW_BPTCL(_i)\t\t\t\t(0x00310200 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_BPTCL_MAX_INDEX\t\t\t31\n+#define GLSW_BPTCL_BPTCL_S\t\t\t0\n+#define GLSW_BPTCL_BPTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSW_GORCH(_i)\t\t\t\t(0x00341004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_GORCH_MAX_INDEX\t\t\t31\n+#define GLSW_GORCH_GORCH_S\t\t\t0\n+#define GLSW_GORCH_GORCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLSW_GORCL(_i)\t\t\t\t(0x00341000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_GORCL_MAX_INDEX\t\t\t31\n+#define GLSW_GORCL_GORCL_S\t\t\t0\n+#define GLSW_GORCL_GORCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSW_GOTCH(_i)\t\t\t\t(0x00302004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_GOTCH_MAX_INDEX\t\t\t31\n+#define GLSW_GOTCH_GOTCH_S\t\t\t0\n+#define GLSW_GOTCH_GOTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLSW_GOTCL(_i)\t\t\t\t(0x00302000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_GOTCL_MAX_INDEX\t\t\t31\n+#define GLSW_GOTCL_GOTCL_S\t\t\t0\n+#define GLSW_GOTCL_GOTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSW_MPRCH(_i)\t\t\t\t(0x00346104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_MPRCH_MAX_INDEX\t\t\t31\n+#define GLSW_MPRCH_MPRCH_S\t\t\t0\n+#define GLSW_MPRCH_MPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLSW_MPRCL(_i)\t\t\t\t(0x00346100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_MPRCL_MAX_INDEX\t\t\t31\n+#define GLSW_MPRCL_MPRCL_S\t\t\t0\n+#define GLSW_MPRCL_MPRCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSW_MPTCH(_i)\t\t\t\t(0x00310104 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_MPTCH_MAX_INDEX\t\t\t31\n+#define GLSW_MPTCH_MPTCH_S\t\t\t0\n+#define GLSW_MPTCH_MPTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLSW_MPTCL(_i)\t\t\t\t(0x00310100 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_MPTCL_MAX_INDEX\t\t\t31\n+#define GLSW_MPTCL_MPTCL_S\t\t\t0\n+#define GLSW_MPTCL_MPTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSW_UPRCH(_i)\t\t\t\t(0x00346004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_UPRCH_MAX_INDEX\t\t\t31\n+#define GLSW_UPRCH_UPRCH_S\t\t\t0\n+#define GLSW_UPRCH_UPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLSW_UPRCL(_i)\t\t\t\t(0x00346000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_UPRCL_MAX_INDEX\t\t\t31\n+#define GLSW_UPRCL_UPRCL_S\t\t\t0\n+#define GLSW_UPRCL_UPRCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSW_UPTCH(_i)\t\t\t\t(0x00310004 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_UPTCH_MAX_INDEX\t\t\t31\n+#define GLSW_UPTCH_UPTCH_S\t\t\t0\n+#define GLSW_UPTCH_UPTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLSW_UPTCL(_i)\t\t\t\t(0x00310000 + ((_i) * 8)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GLSW_UPTCL_MAX_INDEX\t\t\t31\n+#define GLSW_UPTCL_UPTCL_S\t\t\t0\n+#define GLSW_UPTCL_UPTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSWID_RUPP(_i)\t\t\t\t(0x00345000 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define GLSWID_RUPP_MAX_INDEX\t\t\t255\n+#define GLSWID_RUPP_RUPP_S\t\t\t0\n+#define GLSWID_RUPP_RUPP_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_BPRCH(_i)\t\t\t\t(0x003B6004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_BPRCH_MAX_INDEX\t\t\t767\n+#define GLV_BPRCH_BPRCH_S\t\t\t0\n+#define GLV_BPRCH_BPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLV_BPRCL(_i)\t\t\t\t(0x003B6000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_BPRCL_MAX_INDEX\t\t\t767\n+#define GLV_BPRCL_BPRCL_S\t\t\t0\n+#define GLV_BPRCL_BPRCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_BPTCH(_i)\t\t\t\t(0x0030E004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_BPTCH_MAX_INDEX\t\t\t767\n+#define GLV_BPTCH_BPTCH_S\t\t\t0\n+#define GLV_BPTCH_BPTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLV_BPTCL(_i)\t\t\t\t(0x0030E000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_BPTCL_MAX_INDEX\t\t\t767\n+#define GLV_BPTCL_BPTCL_S\t\t\t0\n+#define GLV_BPTCL_BPTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_GORCH(_i)\t\t\t\t(0x003B0004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_GORCH_MAX_INDEX\t\t\t767\n+#define GLV_GORCH_GORCH_S\t\t\t0\n+#define GLV_GORCH_GORCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLV_GORCL(_i)\t\t\t\t(0x003B0000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_GORCL_MAX_INDEX\t\t\t767\n+#define GLV_GORCL_GORCL_S\t\t\t0\n+#define GLV_GORCL_GORCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_GOTCH(_i)\t\t\t\t(0x00300004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_GOTCH_MAX_INDEX\t\t\t767\n+#define GLV_GOTCH_GOTCH_S\t\t\t0\n+#define GLV_GOTCH_GOTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLV_GOTCL(_i)\t\t\t\t(0x00300000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_GOTCL_MAX_INDEX\t\t\t767\n+#define GLV_GOTCL_GOTCL_S\t\t\t0\n+#define GLV_GOTCL_GOTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_MPRCH(_i)\t\t\t\t(0x003B4004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_MPRCH_MAX_INDEX\t\t\t767\n+#define GLV_MPRCH_MPRCH_S\t\t\t0\n+#define GLV_MPRCH_MPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLV_MPRCL(_i)\t\t\t\t(0x003B4000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_MPRCL_MAX_INDEX\t\t\t767\n+#define GLV_MPRCL_MPRCL_S\t\t\t0\n+#define GLV_MPRCL_MPRCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_MPTCH(_i)\t\t\t\t(0x0030C004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_MPTCH_MAX_INDEX\t\t\t767\n+#define GLV_MPTCH_MPTCH_S\t\t\t0\n+#define GLV_MPTCH_MPTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLV_MPTCL(_i)\t\t\t\t(0x0030C000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_MPTCL_MAX_INDEX\t\t\t767\n+#define GLV_MPTCL_MPTCL_S\t\t\t0\n+#define GLV_MPTCL_MPTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_RDPC(_i)\t\t\t\t(0x00294C04 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_RDPC_MAX_INDEX\t\t\t767\n+#define GLV_RDPC_RDPC_S\t\t\t\t0\n+#define GLV_RDPC_RDPC_M\t\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_REPC(_i)\t\t\t\t(0x00295804 + ((_i) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_REPC_MAX_INDEX\t\t\t767\n+#define GLV_REPC_NO_DESC_CNT_S\t\t\t0\n+#define GLV_REPC_NO_DESC_CNT_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define GLV_REPC_ERROR_CNT_S\t\t\t16\n+#define GLV_REPC_ERROR_CNT_M\t\t\tMAKEMASK(0xFFFF, 16)\n+#define GLV_TEPC(_VSI)\t\t\t\t(0x00312000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_TEPC_MAX_INDEX\t\t\t767\n+#define GLV_TEPC_TEPC_S\t\t\t\t0\n+#define GLV_TEPC_TEPC_M\t\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_UPRCH(_i)\t\t\t\t(0x003B2004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_UPRCH_MAX_INDEX\t\t\t767\n+#define GLV_UPRCH_UPRCH_S\t\t\t0\n+#define GLV_UPRCH_UPRCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLV_UPRCL(_i)\t\t\t\t(0x003B2000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_UPRCL_MAX_INDEX\t\t\t767\n+#define GLV_UPRCL_UPRCL_S\t\t\t0\n+#define GLV_UPRCL_UPRCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLV_UPTCH(_i)\t\t\t\t(0x0030A004 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_UPTCH_MAX_INDEX\t\t\t767\n+#define GLV_UPTCH_GLVUPTCH_S\t\t\t0\n+#define GLV_UPTCH_GLVUPTCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLV_UPTCL(_i)\t\t\t\t(0x0030A000 + ((_i) * 8)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define GLV_UPTCL_MAX_INDEX\t\t\t767\n+#define GLV_UPTCL_UPTCL_S\t\t\t0\n+#define GLV_UPTCL_UPTCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLVEBUP_RBCH(_i, _j)\t\t\t(0x00343004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */\n+#define GLVEBUP_RBCH_MAX_INDEX\t\t\t7\n+#define GLVEBUP_RBCH_UPBCH_S\t\t\t0\n+#define GLVEBUP_RBCH_UPBCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLVEBUP_RBCL(_i, _j)\t\t\t(0x00343000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */\n+#define GLVEBUP_RBCL_MAX_INDEX\t\t\t7\n+#define GLVEBUP_RBCL_UPBCL_S\t\t\t0\n+#define GLVEBUP_RBCL_UPBCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLVEBUP_RPCH(_i, _j)\t\t\t(0x00344004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */\n+#define GLVEBUP_RPCH_MAX_INDEX\t\t\t7\n+#define GLVEBUP_RPCH_UPPCH_S\t\t\t0\n+#define GLVEBUP_RPCH_UPPCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLVEBUP_RPCL(_i, _j)\t\t\t(0x00344000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */\n+#define GLVEBUP_RPCL_MAX_INDEX\t\t\t7\n+#define GLVEBUP_RPCL_UPPCL_S\t\t\t0\n+#define GLVEBUP_RPCL_UPPCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLVEBUP_TBCH(_i, _j)\t\t\t(0x00306004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */\n+#define GLVEBUP_TBCH_MAX_INDEX\t\t\t7\n+#define GLVEBUP_TBCH_UPBCH_S\t\t\t0\n+#define GLVEBUP_TBCH_UPBCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLVEBUP_TBCL(_i, _j)\t\t\t(0x00306000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */\n+#define GLVEBUP_TBCL_MAX_INDEX\t\t\t7\n+#define GLVEBUP_TBCL_UPBCL_S\t\t\t0\n+#define GLVEBUP_TBCL_UPBCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLVEBUP_TPCH(_i, _j)\t\t\t(0x00308004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */\n+#define GLVEBUP_TPCH_MAX_INDEX\t\t\t7\n+#define GLVEBUP_TPCH_UPPCH_S\t\t\t0\n+#define GLVEBUP_TPCH_UPPCH_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLVEBUP_TPCL(_i, _j)\t\t\t(0x00308000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...31 */ /* Reset Source: CORER */\n+#define GLVEBUP_TPCL_MAX_INDEX\t\t\t7\n+#define GLVEBUP_TPCL_UPPCL_S\t\t\t0\n+#define GLVEBUP_TPCL_UPPCL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PRTRPB_LDPC\t\t\t\t0x000AC280 /* Reset Source: CORER */\n+#define PRTRPB_LDPC_CRCERRS_S\t\t\t0\n+#define PRTRPB_LDPC_CRCERRS_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PRTRPB_RDPC\t\t\t\t0x000AC260 /* Reset Source: CORER */\n+#define PRTRPB_RDPC_CRCERRS_S\t\t\t0\n+#define PRTRPB_RDPC_CRCERRS_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PRTTPB_STAT_TC_BYTES_SENTL(_i)\t\t(0x00098200 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define PRTTPB_STAT_TC_BYTES_SENTL_MAX_INDEX\t63\n+#define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_S\t0\n+#define PRTTPB_STAT_TC_BYTES_SENTL_TCCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define TPB_PRTTPB_STAT_PKT_SENT(_i)\t\t(0x00099470 + ((_i) * 4)) /* _i=0...7 */ /* Reset Source: CORER */\n+#define TPB_PRTTPB_STAT_PKT_SENT_MAX_INDEX\t7\n+#define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_S\t0\n+#define TPB_PRTTPB_STAT_PKT_SENT_PKTCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define TPB_PRTTPB_STAT_TC_BYTES_SENT(_i)\t(0x00099094 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define TPB_PRTTPB_STAT_TC_BYTES_SENT_MAX_INDEX 63\n+#define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_S\t0\n+#define TPB_PRTTPB_STAT_TC_BYTES_SENT_TCCNT_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define EMP_SWT_PRUNIND\t\t\t\t0x00204020 /* Reset Source: CORER */\n+#define EMP_SWT_PRUNIND_OPCODE_S\t\t0\n+#define EMP_SWT_PRUNIND_OPCODE_M\t\tMAKEMASK(0xF, 0)\n+#define EMP_SWT_PRUNIND_LIST_INDEX_NUM_S\t4\n+#define EMP_SWT_PRUNIND_LIST_INDEX_NUM_M\tMAKEMASK(0x3FF, 4)\n+#define EMP_SWT_PRUNIND_VSI_NUM_S\t\t16\n+#define EMP_SWT_PRUNIND_VSI_NUM_M\t\tMAKEMASK(0x3FF, 16)\n+#define EMP_SWT_PRUNIND_BIT_VALUE_S\t\t31\n+#define EMP_SWT_PRUNIND_BIT_VALUE_M\t\tBIT(31)\n+#define EMP_SWT_REPIND\t\t\t\t0x0020401c /* Reset Source: CORER */\n+#define EMP_SWT_REPIND_OPCODE_S\t\t\t0\n+#define EMP_SWT_REPIND_OPCODE_M\t\t\tMAKEMASK(0xF, 0)\n+#define EMP_SWT_REPIND_LIST_INDEX_NUMBER_S\t4\n+#define EMP_SWT_REPIND_LIST_INDEX_NUMBER_M\tMAKEMASK(0x3FF, 4)\n+#define EMP_SWT_REPIND_VSI_NUM_S\t\t16\n+#define EMP_SWT_REPIND_VSI_NUM_M\t\tMAKEMASK(0x3FF, 16)\n+#define EMP_SWT_REPIND_BIT_VALUE_S\t\t31\n+#define EMP_SWT_REPIND_BIT_VALUE_M\t\tBIT(31)\n+#define GL_OVERRIDEC\t\t\t\t0x002040a4 /* Reset Source: CORER */\n+#define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_S\t0\n+#define GL_OVERRIDEC_OVERRIDE_ATTEMPTC_M\tMAKEMASK(0xFFFF, 0)\n+#define GL_OVERRIDEC_LAST_VSI_S\t\t\t16\n+#define GL_OVERRIDEC_LAST_VSI_M\t\t\tMAKEMASK(0x3FF, 16)\n+#define GL_PLG_AVG_CALC_CFG\t\t\t0x0020A5AC /* Reset Source: CORER */\n+#define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_S\t\t0\n+#define GL_PLG_AVG_CALC_CFG_CYCLE_LEN_M\t\tMAKEMASK(0x7FFFFFFF, 0)\n+#define GL_PLG_AVG_CALC_CFG_MODE_S\t\t31\n+#define GL_PLG_AVG_CALC_CFG_MODE_M\t\tBIT(31)\n+#define GL_PLG_AVG_CALC_ST\t\t\t0x0020A5B0 /* Reset Source: CORER */\n+#define GL_PLG_AVG_CALC_ST_IN_DATA_S\t\t0\n+#define GL_PLG_AVG_CALC_ST_IN_DATA_M\t\tMAKEMASK(0x7FFF, 0)\n+#define GL_PLG_AVG_CALC_ST_OUT_DATA_S\t\t16\n+#define GL_PLG_AVG_CALC_ST_OUT_DATA_M\t\tMAKEMASK(0x7FFF, 16)\n+#define GL_PLG_AVG_CALC_ST_VALID_S\t\t31\n+#define GL_PLG_AVG_CALC_ST_VALID_M\t\tBIT(31)\n+#define GL_PRE_CFG_CMD\t\t\t\t0x00214090 /* Reset Source: CORER */\n+#define GL_PRE_CFG_CMD_ADDR_S\t\t\t0\n+#define GL_PRE_CFG_CMD_ADDR_M\t\t\tMAKEMASK(0x1FFF, 0)\n+#define GL_PRE_CFG_CMD_TBLIDX_S\t\t\t16\n+#define GL_PRE_CFG_CMD_TBLIDX_M\t\t\tMAKEMASK(0x7, 16)\n+#define GL_PRE_CFG_CMD_CMD_S\t\t\t29\n+#define GL_PRE_CFG_CMD_CMD_M\t\t\tBIT(29)\n+#define GL_PRE_CFG_CMD_DONE_S\t\t\t31\n+#define GL_PRE_CFG_CMD_DONE_M\t\t\tBIT(31)\n+#define GL_PRE_CFG_DATA(_i)\t\t\t(0x00214074 + ((_i) * 4)) /* _i=0...6 */ /* Reset Source: CORER */\n+#define GL_PRE_CFG_DATA_MAX_INDEX\t\t6\n+#define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_S\t0\n+#define GL_PRE_CFG_DATA_GL_PRE_RCP_DATA_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_SWT_FUNCFILT\t\t\t\t0x001D2698 /* Reset Source: CORER */\n+#define GL_SWT_FUNCFILT_FUNCFILT_S\t\t0\n+#define GL_SWT_FUNCFILT_FUNCFILT_M\t\tBIT(0)\n+#define GL_SWT_FW_STS(_i)\t\t\t(0x00216000 + ((_i) * 4)) /* _i=0...5 */ /* Reset Source: CORER */\n+#define GL_SWT_FW_STS_MAX_INDEX\t\t\t5\n+#define GL_SWT_FW_STS_GL_SWT_FW_STS_S\t\t0\n+#define GL_SWT_FW_STS_GL_SWT_FW_STS_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_SWT_LAT_DOUBLE\t\t\t0x00204004 /* Reset Source: CORER */\n+#define GL_SWT_LAT_DOUBLE_BASE_S\t\t0\n+#define GL_SWT_LAT_DOUBLE_BASE_M\t\tMAKEMASK(0x7FF, 0)\n+#define GL_SWT_LAT_DOUBLE_SIZE_S\t\t16\n+#define GL_SWT_LAT_DOUBLE_SIZE_M\t\tMAKEMASK(0x7FF, 16)\n+#define GL_SWT_LAT_QUAD\t\t\t\t0x00204008 /* Reset Source: CORER */\n+#define GL_SWT_LAT_QUAD_BASE_S\t\t\t0\n+#define GL_SWT_LAT_QUAD_BASE_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define GL_SWT_LAT_QUAD_SIZE_S\t\t\t16\n+#define GL_SWT_LAT_QUAD_SIZE_M\t\t\tMAKEMASK(0x7FF, 16)\n+#define GL_SWT_LAT_SINGLE\t\t\t0x00204000 /* Reset Source: CORER */\n+#define GL_SWT_LAT_SINGLE_BASE_S\t\t0\n+#define GL_SWT_LAT_SINGLE_BASE_M\t\tMAKEMASK(0x7FF, 0)\n+#define GL_SWT_LAT_SINGLE_SIZE_S\t\t16\n+#define GL_SWT_LAT_SINGLE_SIZE_M\t\tMAKEMASK(0x7FF, 16)\n+#define GL_SWT_MD_PRI\t\t\t\t0x002040ac /* Reset Source: CORER */\n+#define GL_SWT_MD_PRI_VSI_PRI_S\t\t\t0\n+#define GL_SWT_MD_PRI_VSI_PRI_M\t\t\tMAKEMASK(0x7, 0)\n+#define GL_SWT_MD_PRI_LB_PRI_S\t\t\t4\n+#define GL_SWT_MD_PRI_LB_PRI_M\t\t\tMAKEMASK(0x7, 4)\n+#define GL_SWT_MD_PRI_LAN_EN_PRI_S\t\t8\n+#define GL_SWT_MD_PRI_LAN_EN_PRI_M\t\tMAKEMASK(0x7, 8)\n+#define GL_SWT_MD_PRI_QH_PRI_S\t\t\t12\n+#define GL_SWT_MD_PRI_QH_PRI_M\t\t\tMAKEMASK(0x7, 12)\n+#define GL_SWT_MD_PRI_QL_PRI_S\t\t\t16\n+#define GL_SWT_MD_PRI_QL_PRI_M\t\t\tMAKEMASK(0x7, 16)\n+#define GL_SWT_MIRTARVSI(_i)\t\t\t(0x00204500 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: CORER */\n+#define GL_SWT_MIRTARVSI_MAX_INDEX\t\t63\n+#define GL_SWT_MIRTARVSI_VFVMNUMBER_S\t\t0\n+#define GL_SWT_MIRTARVSI_VFVMNUMBER_M\t\tMAKEMASK(0x3FF, 0)\n+#define GL_SWT_MIRTARVSI_FUNCTIONTYPE_S\t\t10\n+#define GL_SWT_MIRTARVSI_FUNCTIONTYPE_M\t\tMAKEMASK(0x3, 10)\n+#define GL_SWT_MIRTARVSI_PFNUMBER_S\t\t12\n+#define GL_SWT_MIRTARVSI_PFNUMBER_M\t\tMAKEMASK(0x7, 12)\n+#define GL_SWT_MIRTARVSI_TARGETVSI_S\t\t20\n+#define GL_SWT_MIRTARVSI_TARGETVSI_M\t\tMAKEMASK(0x3FF, 20)\n+#define GL_SWT_MIRTARVSI_RULEENABLE_S\t\t31\n+#define GL_SWT_MIRTARVSI_RULEENABLE_M\t\tBIT(31)\n+#define GL_SWT_NOMDEF_FLGS_H\t\t\t0x0021411C /* Reset Source: CORER */\n+#define GL_SWT_NOMDEF_FLGS_H_FLGS_S\t\t0\n+#define GL_SWT_NOMDEF_FLGS_H_FLGS_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_SWT_NOMDEF_FLGS_L\t\t\t0x00214118 /* Reset Source: CORER */\n+#define GL_SWT_NOMDEF_FLGS_L_FLGS_S\t\t0\n+#define GL_SWT_NOMDEF_FLGS_L_FLGS_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GL_SWT_SWIDFVIDX\t\t\t0x00214114 /* Reset Source: CORER */\n+#define GL_SWT_SWIDFVIDX_SWIDFVIDX_S\t\t0\n+#define GL_SWT_SWIDFVIDX_SWIDFVIDX_M\t\tMAKEMASK(0x3F, 0)\n+#define GL_SWT_SWIDFVIDX_PORT_TYPE_S\t\t31\n+#define GL_SWT_SWIDFVIDX_PORT_TYPE_M\t\tBIT(31)\n+#define GL_VP_SWITCHID(_i)\t\t\t(0x00214094 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define GL_VP_SWITCHID_MAX_INDEX\t\t31\n+#define GL_VP_SWITCHID_SWITCHID_S\t\t0\n+#define GL_VP_SWITCHID_SWITCHID_M\t\tMAKEMASK(0xFF, 0)\n+#define GLSWID_STAT_BLOCK(_i)\t\t\t(0x0020A1A4 + ((_i) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define GLSWID_STAT_BLOCK_MAX_INDEX\t\t255\n+#define GLSWID_STAT_BLOCK_VEBID_S\t\t0\n+#define GLSWID_STAT_BLOCK_VEBID_M\t\tMAKEMASK(0x1F, 0)\n+#define GLSWID_STAT_BLOCK_VEBID_VALID_S\t\t31\n+#define GLSWID_STAT_BLOCK_VEBID_VALID_M\t\tBIT(31)\n+#define GLSWT_ACT_RESP_0\t\t\t0x0020A5A4 /* Reset Source: CORER */\n+#define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_S\t0\n+#define GLSWT_ACT_RESP_0_GLSWT_ACT_RESP_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSWT_ACT_RESP_1\t\t\t0x0020A5A8 /* Reset Source: CORER */\n+#define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_S\t0\n+#define GLSWT_ACT_RESP_1_GLSWT_ACT_RESP_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLSWT_ARB_MODE\t\t\t\t0x0020A674 /* Reset Source: CORER */\n+#define GLSWT_ARB_MODE_FLU_PRI_SHM_S\t\t0\n+#define GLSWT_ARB_MODE_FLU_PRI_SHM_M\t\tBIT(0)\n+#define GLSWT_ARB_MODE_TX_RX_FWD_PRI_S\t\t1\n+#define GLSWT_ARB_MODE_TX_RX_FWD_PRI_M\t\tBIT(1)\n+#define PRT_SBPVSI\t\t\t\t0x00204120 /* Reset Source: CORER */\n+#define PRT_SBPVSI_BAD_FRAMES_VSI_S\t\t0\n+#define PRT_SBPVSI_BAD_FRAMES_VSI_M\t\tMAKEMASK(0x3FF, 0)\n+#define PRT_SBPVSI_SBP_S\t\t\t31\n+#define PRT_SBPVSI_SBP_M\t\t\tBIT(31)\n+#define PRT_SCSTS\t\t\t\t0x00204140 /* Reset Source: CORER */\n+#define PRT_SCSTS_BSCA_S\t\t\t0\n+#define PRT_SCSTS_BSCA_M\t\t\tBIT(0)\n+#define PRT_SCSTS_BSCAP_S\t\t\t1\n+#define PRT_SCSTS_BSCAP_M\t\t\tBIT(1)\n+#define PRT_SCSTS_MSCA_S\t\t\t2\n+#define PRT_SCSTS_MSCA_M\t\t\tBIT(2)\n+#define PRT_SCSTS_MSCAP_S\t\t\t3\n+#define PRT_SCSTS_MSCAP_M\t\t\tBIT(3)\n+#define PRT_SWT_BSCCNT\t\t\t\t0x00204160 /* Reset Source: CORER */\n+#define PRT_SWT_BSCCNT_CCOUNT_S\t\t\t0\n+#define PRT_SWT_BSCCNT_CCOUNT_M\t\t\tMAKEMASK(0x1FFFFFF, 0)\n+#define PRT_SWT_BSCTRH\t\t\t\t0x00204180 /* Reset Source: CORER */\n+#define PRT_SWT_BSCTRH_UTRESH_S\t\t\t0\n+#define PRT_SWT_BSCTRH_UTRESH_M\t\t\tMAKEMASK(0x7FFFF, 0)\n+#define PRT_SWT_MIREG\t\t\t\t0x002042A0 /* Reset Source: CORER */\n+#define PRT_SWT_MIREG_MIRRULE_S\t\t\t0\n+#define PRT_SWT_MIREG_MIRRULE_M\t\t\tMAKEMASK(0x3F, 0)\n+#define PRT_SWT_MIREG_MIRENA_S\t\t\t7\n+#define PRT_SWT_MIREG_MIRENA_M\t\t\tBIT(7)\n+#define PRT_SWT_MIRIG\t\t\t\t0x00204280 /* Reset Source: CORER */\n+#define PRT_SWT_MIRIG_MIRRULE_S\t\t\t0\n+#define PRT_SWT_MIRIG_MIRRULE_M\t\t\tMAKEMASK(0x3F, 0)\n+#define PRT_SWT_MIRIG_MIRENA_S\t\t\t7\n+#define PRT_SWT_MIRIG_MIRENA_M\t\t\tBIT(7)\n+#define PRT_SWT_MSCCNT\t\t\t\t0x00204100 /* Reset Source: CORER */\n+#define PRT_SWT_MSCCNT_CCOUNT_S\t\t\t0\n+#define PRT_SWT_MSCCNT_CCOUNT_M\t\t\tMAKEMASK(0x1FFFFFF, 0)\n+#define PRT_SWT_MSCTRH\t\t\t\t0x002041c0 /* Reset Source: CORER */\n+#define PRT_SWT_MSCTRH_UTRESH_S\t\t\t0\n+#define PRT_SWT_MSCTRH_UTRESH_M\t\t\tMAKEMASK(0x7FFFF, 0)\n+#define PRT_SWT_SCBI\t\t\t\t0x002041e0 /* Reset Source: CORER */\n+#define PRT_SWT_SCBI_BI_S\t\t\t0\n+#define PRT_SWT_SCBI_BI_M\t\t\tMAKEMASK(0x1FFFFFF, 0)\n+#define PRT_SWT_SCCRL\t\t\t\t0x00204200 /* Reset Source: CORER */\n+#define PRT_SWT_SCCRL_MDIPW_S\t\t\t0\n+#define PRT_SWT_SCCRL_MDIPW_M\t\t\tBIT(0)\n+#define PRT_SWT_SCCRL_MDICW_S\t\t\t1\n+#define PRT_SWT_SCCRL_MDICW_M\t\t\tBIT(1)\n+#define PRT_SWT_SCCRL_BDIPW_S\t\t\t2\n+#define PRT_SWT_SCCRL_BDIPW_M\t\t\tBIT(2)\n+#define PRT_SWT_SCCRL_BDICW_S\t\t\t3\n+#define PRT_SWT_SCCRL_BDICW_M\t\t\tBIT(3)\n+#define PRT_SWT_SCCRL_INTERVAL_S\t\t8\n+#define PRT_SWT_SCCRL_INTERVAL_M\t\tMAKEMASK(0xFFFFF, 8)\n+#define PRT_TCTUPR(_i)\t\t\t\t(0x00040840 + ((_i) * 4)) /* _i=0...31 */ /* Reset Source: CORER */\n+#define PRT_TCTUPR_MAX_INDEX\t\t\t31\n+#define PRT_TCTUPR_UP0_S\t\t\t0\n+#define PRT_TCTUPR_UP0_M\t\t\tMAKEMASK(0x7, 0)\n+#define PRT_TCTUPR_UP1_S\t\t\t4\n+#define PRT_TCTUPR_UP1_M\t\t\tMAKEMASK(0x7, 4)\n+#define PRT_TCTUPR_UP2_S\t\t\t8\n+#define PRT_TCTUPR_UP2_M\t\t\tMAKEMASK(0x7, 8)\n+#define PRT_TCTUPR_UP3_S\t\t\t12\n+#define PRT_TCTUPR_UP3_M\t\t\tMAKEMASK(0x7, 12)\n+#define PRT_TCTUPR_UP4_S\t\t\t16\n+#define PRT_TCTUPR_UP4_M\t\t\tMAKEMASK(0x7, 16)\n+#define PRT_TCTUPR_UP5_S\t\t\t20\n+#define PRT_TCTUPR_UP5_M\t\t\tMAKEMASK(0x7, 20)\n+#define PRT_TCTUPR_UP6_S\t\t\t24\n+#define PRT_TCTUPR_UP6_M\t\t\tMAKEMASK(0x7, 24)\n+#define PRT_TCTUPR_UP7_S\t\t\t28\n+#define PRT_TCTUPR_UP7_M\t\t\tMAKEMASK(0x7, 28)\n+#define GLHH_ART_CTL\t\t\t\t0x000A41D4 /* Reset Source: POR */\n+#define GLHH_ART_CTL_ACTIVE_S\t\t\t0\n+#define GLHH_ART_CTL_ACTIVE_M\t\t\tBIT(0)\n+#define GLHH_ART_CTL_TIME_OUT1_S\t\t1\n+#define GLHH_ART_CTL_TIME_OUT1_M\t\tBIT(1)\n+#define GLHH_ART_CTL_TIME_OUT2_S\t\t2\n+#define GLHH_ART_CTL_TIME_OUT2_M\t\tBIT(2)\n+#define GLHH_ART_CTL_RESET_HH_S\t\t\t31\n+#define GLHH_ART_CTL_RESET_HH_M\t\t\tBIT(31)\n+#define GLHH_ART_DATA\t\t\t\t0x000A41E0 /* Reset Source: POR */\n+#define GLHH_ART_DATA_AGENT_TYPE_S\t\t0\n+#define GLHH_ART_DATA_AGENT_TYPE_M\t\tMAKEMASK(0x7, 0)\n+#define GLHH_ART_DATA_SYNC_TYPE_S\t\t3\n+#define GLHH_ART_DATA_SYNC_TYPE_M\t\tBIT(3)\n+#define GLHH_ART_DATA_MAX_DELAY_S\t\t4\n+#define GLHH_ART_DATA_MAX_DELAY_M\t\tMAKEMASK(0xF, 4)\n+#define GLHH_ART_DATA_TIME_BASE_S\t\t8\n+#define GLHH_ART_DATA_TIME_BASE_M\t\tMAKEMASK(0xF, 8)\n+#define GLHH_ART_DATA_RSV_DATA_S\t\t12\n+#define GLHH_ART_DATA_RSV_DATA_M\t\tMAKEMASK(0xFFFFF, 12)\n+#define GLHH_ART_TIME_H\t\t\t\t0x000A41D8 /* Reset Source: POR */\n+#define GLHH_ART_TIME_H_ART_TIME_H_S\t\t0\n+#define GLHH_ART_TIME_H_ART_TIME_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLHH_ART_TIME_L\t\t\t\t0x000A41DC /* Reset Source: POR */\n+#define GLHH_ART_TIME_L_ART_TIME_L_S\t\t0\n+#define GLHH_ART_TIME_L_ART_TIME_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_AUX_IN_0(_i)\t\t\t(0x000889D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_AUX_IN_0_MAX_INDEX\t\t1\n+#define GLTSYN_AUX_IN_0_EVNTLVL_S\t\t0\n+#define GLTSYN_AUX_IN_0_EVNTLVL_M\t\tMAKEMASK(0x3, 0)\n+#define GLTSYN_AUX_IN_0_INT_ENA_S\t\t4\n+#define GLTSYN_AUX_IN_0_INT_ENA_M\t\tBIT(4)\n+#define GLTSYN_AUX_IN_1(_i)\t\t\t(0x000889E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_AUX_IN_1_MAX_INDEX\t\t1\n+#define GLTSYN_AUX_IN_1_EVNTLVL_S\t\t0\n+#define GLTSYN_AUX_IN_1_EVNTLVL_M\t\tMAKEMASK(0x3, 0)\n+#define GLTSYN_AUX_IN_1_INT_ENA_S\t\t4\n+#define GLTSYN_AUX_IN_1_INT_ENA_M\t\tBIT(4)\n+#define GLTSYN_AUX_IN_2(_i)\t\t\t(0x000889E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_AUX_IN_2_MAX_INDEX\t\t1\n+#define GLTSYN_AUX_IN_2_EVNTLVL_S\t\t0\n+#define GLTSYN_AUX_IN_2_EVNTLVL_M\t\tMAKEMASK(0x3, 0)\n+#define GLTSYN_AUX_IN_2_INT_ENA_S\t\t4\n+#define GLTSYN_AUX_IN_2_INT_ENA_M\t\tBIT(4)\n+#define GLTSYN_AUX_OUT_0(_i)\t\t\t(0x00088998 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_AUX_OUT_0_MAX_INDEX\t\t1\n+#define GLTSYN_AUX_OUT_0_OUT_ENA_S\t\t0\n+#define GLTSYN_AUX_OUT_0_OUT_ENA_M\t\tBIT(0)\n+#define GLTSYN_AUX_OUT_0_OUTMOD_S\t\t1\n+#define GLTSYN_AUX_OUT_0_OUTMOD_M\t\tMAKEMASK(0x3, 1)\n+#define GLTSYN_AUX_OUT_0_OUTLVL_S\t\t3\n+#define GLTSYN_AUX_OUT_0_OUTLVL_M\t\tBIT(3)\n+#define GLTSYN_AUX_OUT_0_INT_ENA_S\t\t4\n+#define GLTSYN_AUX_OUT_0_INT_ENA_M\t\tBIT(4)\n+#define GLTSYN_AUX_OUT_0_PULSEW_S\t\t8\n+#define GLTSYN_AUX_OUT_0_PULSEW_M\t\tMAKEMASK(0xF, 8)\n+#define GLTSYN_AUX_OUT_1(_i)\t\t\t(0x000889A0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_AUX_OUT_1_MAX_INDEX\t\t1\n+#define GLTSYN_AUX_OUT_1_OUT_ENA_S\t\t0\n+#define GLTSYN_AUX_OUT_1_OUT_ENA_M\t\tBIT(0)\n+#define GLTSYN_AUX_OUT_1_OUTMOD_S\t\t1\n+#define GLTSYN_AUX_OUT_1_OUTMOD_M\t\tMAKEMASK(0x3, 1)\n+#define GLTSYN_AUX_OUT_1_OUTLVL_S\t\t3\n+#define GLTSYN_AUX_OUT_1_OUTLVL_M\t\tBIT(3)\n+#define GLTSYN_AUX_OUT_1_INT_ENA_S\t\t4\n+#define GLTSYN_AUX_OUT_1_INT_ENA_M\t\tBIT(4)\n+#define GLTSYN_AUX_OUT_1_PULSEW_S\t\t8\n+#define GLTSYN_AUX_OUT_1_PULSEW_M\t\tMAKEMASK(0xF, 8)\n+#define GLTSYN_AUX_OUT_2(_i)\t\t\t(0x000889A8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_AUX_OUT_2_MAX_INDEX\t\t1\n+#define GLTSYN_AUX_OUT_2_OUT_ENA_S\t\t0\n+#define GLTSYN_AUX_OUT_2_OUT_ENA_M\t\tBIT(0)\n+#define GLTSYN_AUX_OUT_2_OUTMOD_S\t\t1\n+#define GLTSYN_AUX_OUT_2_OUTMOD_M\t\tMAKEMASK(0x3, 1)\n+#define GLTSYN_AUX_OUT_2_OUTLVL_S\t\t3\n+#define GLTSYN_AUX_OUT_2_OUTLVL_M\t\tBIT(3)\n+#define GLTSYN_AUX_OUT_2_INT_ENA_S\t\t4\n+#define GLTSYN_AUX_OUT_2_INT_ENA_M\t\tBIT(4)\n+#define GLTSYN_AUX_OUT_2_PULSEW_S\t\t8\n+#define GLTSYN_AUX_OUT_2_PULSEW_M\t\tMAKEMASK(0xF, 8)\n+#define GLTSYN_AUX_OUT_3(_i)\t\t\t(0x000889B0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_AUX_OUT_3_MAX_INDEX\t\t1\n+#define GLTSYN_AUX_OUT_3_OUT_ENA_S\t\t0\n+#define GLTSYN_AUX_OUT_3_OUT_ENA_M\t\tBIT(0)\n+#define GLTSYN_AUX_OUT_3_OUTMOD_S\t\t1\n+#define GLTSYN_AUX_OUT_3_OUTMOD_M\t\tMAKEMASK(0x3, 1)\n+#define GLTSYN_AUX_OUT_3_OUTLVL_S\t\t3\n+#define GLTSYN_AUX_OUT_3_OUTLVL_M\t\tBIT(3)\n+#define GLTSYN_AUX_OUT_3_INT_ENA_S\t\t4\n+#define GLTSYN_AUX_OUT_3_INT_ENA_M\t\tBIT(4)\n+#define GLTSYN_AUX_OUT_3_PULSEW_S\t\t8\n+#define GLTSYN_AUX_OUT_3_PULSEW_M\t\tMAKEMASK(0xF, 8)\n+#define GLTSYN_CLKO_0(_i)\t\t\t(0x000889B8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_CLKO_0_MAX_INDEX\t\t\t1\n+#define GLTSYN_CLKO_0_TSYNCLKO_S\t\t0\n+#define GLTSYN_CLKO_0_TSYNCLKO_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_CLKO_1(_i)\t\t\t(0x000889C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_CLKO_1_MAX_INDEX\t\t\t1\n+#define GLTSYN_CLKO_1_TSYNCLKO_S\t\t0\n+#define GLTSYN_CLKO_1_TSYNCLKO_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_CLKO_2(_i)\t\t\t(0x000889C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_CLKO_2_MAX_INDEX\t\t\t1\n+#define GLTSYN_CLKO_2_TSYNCLKO_S\t\t0\n+#define GLTSYN_CLKO_2_TSYNCLKO_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_CLKO_3(_i)\t\t\t(0x000889D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_CLKO_3_MAX_INDEX\t\t\t1\n+#define GLTSYN_CLKO_3_TSYNCLKO_S\t\t0\n+#define GLTSYN_CLKO_3_TSYNCLKO_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_CMD\t\t\t\t0x00088810 /* Reset Source: CORER */\n+#define GLTSYN_CMD_CMD_S\t\t\t0\n+#define GLTSYN_CMD_CMD_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GLTSYN_CMD_SEL_MASTER_S\t\t\t8\n+#define GLTSYN_CMD_SEL_MASTER_M\t\t\tBIT(8)\n+#define GLTSYN_CMD_SYNC\t\t\t\t0x00088814 /* Reset Source: CORER */\n+#define GLTSYN_CMD_SYNC_SYNC_S\t\t\t0\n+#define GLTSYN_CMD_SYNC_SYNC_M\t\t\tMAKEMASK(0x3, 0)\n+#define GLTSYN_ENA(_i)\t\t\t\t(0x00088808 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_ENA_MAX_INDEX\t\t\t1\n+#define GLTSYN_ENA_TSYN_ENA_S\t\t\t0\n+#define GLTSYN_ENA_TSYN_ENA_M\t\t\tBIT(0)\n+#define GLTSYN_EVNT_H_0(_i)\t\t\t(0x00088970 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_EVNT_H_0_MAX_INDEX\t\t1\n+#define GLTSYN_EVNT_H_0_TSYNEVNT_H_S\t\t0\n+#define GLTSYN_EVNT_H_0_TSYNEVNT_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_EVNT_H_1(_i)\t\t\t(0x00088980 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_EVNT_H_1_MAX_INDEX\t\t1\n+#define GLTSYN_EVNT_H_1_TSYNEVNT_H_S\t\t0\n+#define GLTSYN_EVNT_H_1_TSYNEVNT_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_EVNT_H_2(_i)\t\t\t(0x00088990 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_EVNT_H_2_MAX_INDEX\t\t1\n+#define GLTSYN_EVNT_H_2_TSYNEVNT_H_S\t\t0\n+#define GLTSYN_EVNT_H_2_TSYNEVNT_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_EVNT_L_0(_i)\t\t\t(0x00088968 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_EVNT_L_0_MAX_INDEX\t\t1\n+#define GLTSYN_EVNT_L_0_TSYNEVNT_L_S\t\t0\n+#define GLTSYN_EVNT_L_0_TSYNEVNT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_EVNT_L_1(_i)\t\t\t(0x00088978 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_EVNT_L_1_MAX_INDEX\t\t1\n+#define GLTSYN_EVNT_L_1_TSYNEVNT_L_S\t\t0\n+#define GLTSYN_EVNT_L_1_TSYNEVNT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_EVNT_L_2(_i)\t\t\t(0x00088988 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_EVNT_L_2_MAX_INDEX\t\t1\n+#define GLTSYN_EVNT_L_2_TSYNEVNT_L_S\t\t0\n+#define GLTSYN_EVNT_L_2_TSYNEVNT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_HHTIME_H(_i)\t\t\t(0x00088900 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_HHTIME_H_MAX_INDEX\t\t1\n+#define GLTSYN_HHTIME_H_TSYNEVNT_H_S\t\t0\n+#define GLTSYN_HHTIME_H_TSYNEVNT_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_HHTIME_L(_i)\t\t\t(0x000888F8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_HHTIME_L_MAX_INDEX\t\t1\n+#define GLTSYN_HHTIME_L_TSYNEVNT_L_S\t\t0\n+#define GLTSYN_HHTIME_L_TSYNEVNT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_INCVAL_H(_i)\t\t\t(0x00088920 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_INCVAL_H_MAX_INDEX\t\t1\n+#define GLTSYN_INCVAL_H_INCVAL_H_S\t\t0\n+#define GLTSYN_INCVAL_H_INCVAL_H_M\t\tMAKEMASK(0xFF, 0)\n+#define GLTSYN_INCVAL_L(_i)\t\t\t(0x00088918 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_INCVAL_L_MAX_INDEX\t\t1\n+#define GLTSYN_INCVAL_L_INCVAL_L_S\t\t0\n+#define GLTSYN_INCVAL_L_INCVAL_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_SHADJ_H(_i)\t\t\t(0x00088910 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_SHADJ_H_MAX_INDEX\t\t1\n+#define GLTSYN_SHADJ_H_ADJUST_H_S\t\t0\n+#define GLTSYN_SHADJ_H_ADJUST_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_SHADJ_L(_i)\t\t\t(0x00088908 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_SHADJ_L_MAX_INDEX\t\t1\n+#define GLTSYN_SHADJ_L_ADJUST_L_S\t\t0\n+#define GLTSYN_SHADJ_L_ADJUST_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_SHTIME_0(_i)\t\t\t(0x000888E0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_SHTIME_0_MAX_INDEX\t\t1\n+#define GLTSYN_SHTIME_0_TSYNTIME_0_S\t\t0\n+#define GLTSYN_SHTIME_0_TSYNTIME_0_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_SHTIME_H(_i)\t\t\t(0x000888F0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_SHTIME_H_MAX_INDEX\t\t1\n+#define GLTSYN_SHTIME_H_TSYNTIME_H_S\t\t0\n+#define GLTSYN_SHTIME_H_TSYNTIME_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_SHTIME_L(_i)\t\t\t(0x000888E8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_SHTIME_L_MAX_INDEX\t\t1\n+#define GLTSYN_SHTIME_L_TSYNTIME_L_S\t\t0\n+#define GLTSYN_SHTIME_L_TSYNTIME_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_STAT(_i)\t\t\t\t(0x000888C0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_STAT_MAX_INDEX\t\t\t1\n+#define GLTSYN_STAT_EVENT0_S\t\t\t0\n+#define GLTSYN_STAT_EVENT0_M\t\t\tBIT(0)\n+#define GLTSYN_STAT_EVENT1_S\t\t\t1\n+#define GLTSYN_STAT_EVENT1_M\t\t\tBIT(1)\n+#define GLTSYN_STAT_EVENT2_S\t\t\t2\n+#define GLTSYN_STAT_EVENT2_M\t\t\tBIT(2)\n+#define GLTSYN_STAT_TGT0_S\t\t\t4\n+#define GLTSYN_STAT_TGT0_M\t\t\tBIT(4)\n+#define GLTSYN_STAT_TGT1_S\t\t\t5\n+#define GLTSYN_STAT_TGT1_M\t\t\tBIT(5)\n+#define GLTSYN_STAT_TGT2_S\t\t\t6\n+#define GLTSYN_STAT_TGT2_M\t\t\tBIT(6)\n+#define GLTSYN_STAT_TGT3_S\t\t\t7\n+#define GLTSYN_STAT_TGT3_M\t\t\tBIT(7)\n+#define GLTSYN_SYNC_DLAY\t\t\t0x00088818 /* Reset Source: CORER */\n+#define GLTSYN_SYNC_DLAY_SYNC_DELAY_S\t\t0\n+#define GLTSYN_SYNC_DLAY_SYNC_DELAY_M\t\tMAKEMASK(0x1F, 0)\n+#define GLTSYN_TGT_H_0(_i)\t\t\t(0x00088930 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TGT_H_0_MAX_INDEX\t\t1\n+#define GLTSYN_TGT_H_0_TSYNTGTT_H_S\t\t0\n+#define GLTSYN_TGT_H_0_TSYNTGTT_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TGT_H_1(_i)\t\t\t(0x00088940 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TGT_H_1_MAX_INDEX\t\t1\n+#define GLTSYN_TGT_H_1_TSYNTGTT_H_S\t\t0\n+#define GLTSYN_TGT_H_1_TSYNTGTT_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TGT_H_2(_i)\t\t\t(0x00088950 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TGT_H_2_MAX_INDEX\t\t1\n+#define GLTSYN_TGT_H_2_TSYNTGTT_H_S\t\t0\n+#define GLTSYN_TGT_H_2_TSYNTGTT_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TGT_H_3(_i)\t\t\t(0x00088960 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TGT_H_3_MAX_INDEX\t\t1\n+#define GLTSYN_TGT_H_3_TSYNTGTT_H_S\t\t0\n+#define GLTSYN_TGT_H_3_TSYNTGTT_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TGT_L_0(_i)\t\t\t(0x00088928 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TGT_L_0_MAX_INDEX\t\t1\n+#define GLTSYN_TGT_L_0_TSYNTGTT_L_S\t\t0\n+#define GLTSYN_TGT_L_0_TSYNTGTT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TGT_L_1(_i)\t\t\t(0x00088938 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TGT_L_1_MAX_INDEX\t\t1\n+#define GLTSYN_TGT_L_1_TSYNTGTT_L_S\t\t0\n+#define GLTSYN_TGT_L_1_TSYNTGTT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TGT_L_2(_i)\t\t\t(0x00088948 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TGT_L_2_MAX_INDEX\t\t1\n+#define GLTSYN_TGT_L_2_TSYNTGTT_L_S\t\t0\n+#define GLTSYN_TGT_L_2_TSYNTGTT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TGT_L_3(_i)\t\t\t(0x00088958 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TGT_L_3_MAX_INDEX\t\t1\n+#define GLTSYN_TGT_L_3_TSYNTGTT_L_S\t\t0\n+#define GLTSYN_TGT_L_3_TSYNTGTT_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TIME_0(_i)\t\t\t(0x000888C8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TIME_0_MAX_INDEX\t\t\t1\n+#define GLTSYN_TIME_0_TSYNTIME_0_S\t\t0\n+#define GLTSYN_TIME_0_TSYNTIME_0_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TIME_H(_i)\t\t\t(0x000888D8 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TIME_H_MAX_INDEX\t\t\t1\n+#define GLTSYN_TIME_H_TSYNTIME_H_S\t\t0\n+#define GLTSYN_TIME_H_TSYNTIME_H_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLTSYN_TIME_L(_i)\t\t\t(0x000888D0 + ((_i) * 4)) /* _i=0...1 */ /* Reset Source: CORER */\n+#define GLTSYN_TIME_L_MAX_INDEX\t\t\t1\n+#define GLTSYN_TIME_L_TSYNTIME_L_S\t\t0\n+#define GLTSYN_TIME_L_TSYNTIME_L_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define PFHH_SEM\t\t\t\t0x000A4200 /* Reset Source: PFR */\n+#define PFHH_SEM_BUSY_S\t\t\t\t0\n+#define PFHH_SEM_BUSY_M\t\t\t\tBIT(0)\n+#define PFHH_SEM_PF_OWNER_S\t\t\t4\n+#define PFHH_SEM_PF_OWNER_M\t\t\tMAKEMASK(0x7, 4)\n+#define PFTSYN_SEM\t\t\t\t0x00088880 /* Reset Source: PFR */\n+#define PFTSYN_SEM_BUSY_S\t\t\t0\n+#define PFTSYN_SEM_BUSY_M\t\t\tBIT(0)\n+#define PFTSYN_SEM_PF_OWNER_S\t\t\t4\n+#define PFTSYN_SEM_PF_OWNER_M\t\t\tMAKEMASK(0x7, 4)\n+#define GLPE_TSCD_FLR(_i)\t\t\t(0x0051E24c + ((_i) * 4)) /* _i=0...3 */ /* Reset Source: CORER */\n+#define GLPE_TSCD_FLR_MAX_INDEX\t\t\t3\n+#define GLPE_TSCD_FLR_DRAIN_VCTR_ID_S\t\t0\n+#define GLPE_TSCD_FLR_DRAIN_VCTR_ID_M\t\tMAKEMASK(0x3, 0)\n+#define GLPE_TSCD_FLR_PORT_S\t\t\t2\n+#define GLPE_TSCD_FLR_PORT_M\t\t\tMAKEMASK(0x7, 2)\n+#define GLPE_TSCD_FLR_PF_NUM_S\t\t\t5\n+#define GLPE_TSCD_FLR_PF_NUM_M\t\t\tMAKEMASK(0x7, 5)\n+#define GLPE_TSCD_FLR_VM_VF_TYPE_S\t\t8\n+#define GLPE_TSCD_FLR_VM_VF_TYPE_M\t\tMAKEMASK(0x3, 8)\n+#define GLPE_TSCD_FLR_VM_VF_NUM_S\t\t16\n+#define GLPE_TSCD_FLR_VM_VF_NUM_M\t\tMAKEMASK(0x3FF, 16)\n+#define GLPE_TSCD_FLR_VLD_S\t\t\t31\n+#define GLPE_TSCD_FLR_VLD_M\t\t\tBIT(31)\n+#define GLPE_TSCD_PEPM\t\t\t\t0x0051E228 /* Reset Source: CORER */\n+#define GLPE_TSCD_PEPM_MDQ_CREDITS_S\t\t0\n+#define GLPE_TSCD_PEPM_MDQ_CREDITS_M\t\tMAKEMASK(0xFF, 0)\n+#define PF_VIRT_VSTATUS\t\t\t\t0x0009E680 /* Reset Source: PFR */\n+#define PF_VIRT_VSTATUS_NUM_VFS_S\t\t0\n+#define PF_VIRT_VSTATUS_NUM_VFS_M\t\tMAKEMASK(0xFF, 0)\n+#define PF_VIRT_VSTATUS_TOTAL_VFS_S\t\t8\n+#define PF_VIRT_VSTATUS_TOTAL_VFS_M\t\tMAKEMASK(0xFF, 8)\n+#define PF_VIRT_VSTATUS_IOV_ACTIVE_S\t\t16\n+#define PF_VIRT_VSTATUS_IOV_ACTIVE_M\t\tBIT(16)\n+#define PF_VT_PFALLOC\t\t\t\t0x001D2480 /* Reset Source: CORER */\n+#define PF_VT_PFALLOC_FIRSTVF_S\t\t\t0\n+#define PF_VT_PFALLOC_FIRSTVF_M\t\t\tMAKEMASK(0xFF, 0)\n+#define PF_VT_PFALLOC_LASTVF_S\t\t\t8\n+#define PF_VT_PFALLOC_LASTVF_M\t\t\tMAKEMASK(0xFF, 8)\n+#define PF_VT_PFALLOC_VALID_S\t\t\t31\n+#define PF_VT_PFALLOC_VALID_M\t\t\tBIT(31)\n+#define PF_VT_PFALLOC_HIF\t\t\t0x0009DD80 /* Reset Source: PCIR */\n+#define PF_VT_PFALLOC_HIF_FIRSTVF_S\t\t0\n+#define PF_VT_PFALLOC_HIF_FIRSTVF_M\t\tMAKEMASK(0xFF, 0)\n+#define PF_VT_PFALLOC_HIF_LASTVF_S\t\t8\n+#define PF_VT_PFALLOC_HIF_LASTVF_M\t\tMAKEMASK(0xFF, 8)\n+#define PF_VT_PFALLOC_HIF_VALID_S\t\t31\n+#define PF_VT_PFALLOC_HIF_VALID_M\t\tBIT(31)\n+#define PF_VT_PFALLOC_PCIE\t\t\t0x000BE080 /* Reset Source: PCIR */\n+#define PF_VT_PFALLOC_PCIE_FIRSTVF_S\t\t0\n+#define PF_VT_PFALLOC_PCIE_FIRSTVF_M\t\tMAKEMASK(0xFF, 0)\n+#define PF_VT_PFALLOC_PCIE_LASTVF_S\t\t8\n+#define PF_VT_PFALLOC_PCIE_LASTVF_M\t\tMAKEMASK(0xFF, 8)\n+#define PF_VT_PFALLOC_PCIE_VALID_S\t\t31\n+#define PF_VT_PFALLOC_PCIE_VALID_M\t\tBIT(31)\n+#define VSI_L2TAGSTXVALID(_VSI)\t\t\t(0x00046000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_L2TAGSTXVALID_MAX_INDEX\t\t767\n+#define VSI_L2TAGSTXVALID_L2TAG1INSERTID_S\t0\n+#define VSI_L2TAGSTXVALID_L2TAG1INSERTID_M\tMAKEMASK(0x7, 0)\n+#define VSI_L2TAGSTXVALID_L2TAG1INSERTID_VALID_S 3\n+#define VSI_L2TAGSTXVALID_L2TAG1INSERTID_VALID_M BIT(3)\n+#define VSI_L2TAGSTXVALID_L2TAG2INSERTID_S\t4\n+#define VSI_L2TAGSTXVALID_L2TAG2INSERTID_M\tMAKEMASK(0x7, 4)\n+#define VSI_L2TAGSTXVALID_L2TAG2INSERTID_VALID_S 7\n+#define VSI_L2TAGSTXVALID_L2TAG2INSERTID_VALID_M BIT(7)\n+#define VSI_L2TAGSTXVALID_TIR0INSERTID_S\t16\n+#define VSI_L2TAGSTXVALID_TIR0INSERTID_M\tMAKEMASK(0x7, 16)\n+#define VSI_L2TAGSTXVALID_TIR0_INSERT_S\t\t19\n+#define VSI_L2TAGSTXVALID_TIR0_INSERT_M\t\tBIT(19)\n+#define VSI_L2TAGSTXVALID_TIR1INSERTID_S\t20\n+#define VSI_L2TAGSTXVALID_TIR1INSERTID_M\tMAKEMASK(0x7, 20)\n+#define VSI_L2TAGSTXVALID_TIR1_INSERT_S\t\t23\n+#define VSI_L2TAGSTXVALID_TIR1_INSERT_M\t\tBIT(23)\n+#define VSI_L2TAGSTXVALID_TIR2INSERTID_S\t24\n+#define VSI_L2TAGSTXVALID_TIR2INSERTID_M\tMAKEMASK(0x7, 24)\n+#define VSI_L2TAGSTXVALID_TIR2_INSERT_S\t\t27\n+#define VSI_L2TAGSTXVALID_TIR2_INSERT_M\t\tBIT(27)\n+#define VSI_PASID(_VSI)\t\t\t\t(0x0009C000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_PASID_MAX_INDEX\t\t\t767\n+#define VSI_PASID_PASID_S\t\t\t0\n+#define VSI_PASID_PASID_M\t\t\tMAKEMASK(0xFFFFF, 0)\n+#define VSI_PASID_EN_S\t\t\t\t31\n+#define VSI_PASID_EN_M\t\t\t\tBIT(31)\n+#define VSI_RUPR(_VSI)\t\t\t\t(0x00050000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_RUPR_MAX_INDEX\t\t\t767\n+#define VSI_RUPR_UP0_S\t\t\t\t0\n+#define VSI_RUPR_UP0_M\t\t\t\tMAKEMASK(0x7, 0)\n+#define VSI_RUPR_UP1_S\t\t\t\t3\n+#define VSI_RUPR_UP1_M\t\t\t\tMAKEMASK(0x7, 3)\n+#define VSI_RUPR_UP2_S\t\t\t\t6\n+#define VSI_RUPR_UP2_M\t\t\t\tMAKEMASK(0x7, 6)\n+#define VSI_RUPR_UP3_S\t\t\t\t9\n+#define VSI_RUPR_UP3_M\t\t\t\tMAKEMASK(0x7, 9)\n+#define VSI_RUPR_UP4_S\t\t\t\t12\n+#define VSI_RUPR_UP4_M\t\t\t\tMAKEMASK(0x7, 12)\n+#define VSI_RUPR_UP5_S\t\t\t\t15\n+#define VSI_RUPR_UP5_M\t\t\t\tMAKEMASK(0x7, 15)\n+#define VSI_RUPR_UP6_S\t\t\t\t18\n+#define VSI_RUPR_UP6_M\t\t\t\tMAKEMASK(0x7, 18)\n+#define VSI_RUPR_UP7_S\t\t\t\t21\n+#define VSI_RUPR_UP7_M\t\t\t\tMAKEMASK(0x7, 21)\n+#define VSI_RXSWCTRL(_VSI)\t\t\t(0x00205000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_RXSWCTRL_MAX_INDEX\t\t\t767\n+#define VSI_RXSWCTRL_MACVSIPRUNEENABLE_S\t8\n+#define VSI_RXSWCTRL_MACVSIPRUNEENABLE_M\tBIT(8)\n+#define VSI_RXSWCTRL_PRUNEENABLE_S\t\t9\n+#define VSI_RXSWCTRL_PRUNEENABLE_M\t\tMAKEMASK(0xF, 9)\n+#define VSI_RXSWCTRL_SRCPRUNEENABLE_S\t\t13\n+#define VSI_RXSWCTRL_SRCPRUNEENABLE_M\t\tBIT(13)\n+#define VSI_SRCSWCTRL(_VSI)\t\t\t(0x00209000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_SRCSWCTRL_MAX_INDEX\t\t\t767\n+#define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_S\t0\n+#define VSI_SRCSWCTRL_ALLOWDESTOVERRIDE_M\tBIT(0)\n+#define VSI_SRCSWCTRL_ALLOWLOOPBACK_S\t\t1\n+#define VSI_SRCSWCTRL_ALLOWLOOPBACK_M\t\tBIT(1)\n+#define VSI_SRCSWCTRL_LANENABLE_S\t\t2\n+#define VSI_SRCSWCTRL_LANENABLE_M\t\tBIT(2)\n+#define VSI_SRCSWCTRL_MACAS_S\t\t\t3\n+#define VSI_SRCSWCTRL_MACAS_M\t\t\tBIT(3)\n+#define VSI_SRCSWCTRL_PRUNEENABLE_S\t\t4\n+#define VSI_SRCSWCTRL_PRUNEENABLE_M\t\tMAKEMASK(0xF, 4)\n+#define VSI_SWITCHID(_VSI)\t\t\t(0x00215000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_SWITCHID_MAX_INDEX\t\t\t767\n+#define VSI_SWITCHID_SWITCHID_S\t\t\t0\n+#define VSI_SWITCHID_SWITCHID_M\t\t\tMAKEMASK(0xFF, 0)\n+#define VSI_SWT_MIREG(_VSI)\t\t\t(0x00207000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_SWT_MIREG_MAX_INDEX\t\t\t767\n+#define VSI_SWT_MIREG_MIRRULE_S\t\t\t0\n+#define VSI_SWT_MIREG_MIRRULE_M\t\t\tMAKEMASK(0x3F, 0)\n+#define VSI_SWT_MIREG_MIRENA_S\t\t\t7\n+#define VSI_SWT_MIREG_MIRENA_M\t\t\tBIT(7)\n+#define VSI_SWT_MIRIG(_VSI)\t\t\t(0x00208000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSI_SWT_MIRIG_MAX_INDEX\t\t\t767\n+#define VSI_SWT_MIRIG_MIRRULE_S\t\t\t0\n+#define VSI_SWT_MIRIG_MIRRULE_M\t\t\tMAKEMASK(0x3F, 0)\n+#define VSI_SWT_MIRIG_MIRENA_S\t\t\t7\n+#define VSI_SWT_MIRIG_MIRENA_M\t\t\tBIT(7)\n+#define VSI_TAIR(_VSI)\t\t\t\t(0x00044000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_TAIR_MAX_INDEX\t\t\t767\n+#define VSI_TAIR_PORT_TAG_ID_S\t\t\t0\n+#define VSI_TAIR_PORT_TAG_ID_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define VSI_TAR(_VSI)\t\t\t\t(0x00045000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_TAR_MAX_INDEX\t\t\t767\n+#define VSI_TAR_ACCEPTTAGGED_S\t\t\t0\n+#define VSI_TAR_ACCEPTTAGGED_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VSI_TAR_ACCEPTUNTAGGED_S\t\t16\n+#define VSI_TAR_ACCEPTUNTAGGED_M\t\tMAKEMASK(0x3FF, 16)\n+#define VSI_TIR_0(_VSI)\t\t\t\t(0x00041000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_TIR_0_MAX_INDEX\t\t\t767\n+#define VSI_TIR_0_PORT_TAG_ID_S\t\t\t0\n+#define VSI_TIR_0_PORT_TAG_ID_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define VSI_TIR_1(_VSI)\t\t\t\t(0x00042000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_TIR_1_MAX_INDEX\t\t\t767\n+#define VSI_TIR_1_PORT_TAG_ID_S\t\t\t0\n+#define VSI_TIR_1_PORT_TAG_ID_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VSI_TIR_2(_VSI)\t\t\t\t(0x00043000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_TIR_2_MAX_INDEX\t\t\t767\n+#define VSI_TIR_2_PORT_TAG_ID_S\t\t\t0\n+#define VSI_TIR_2_PORT_TAG_ID_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define VSI_TSR(_VSI)\t\t\t\t(0x00051000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_TSR_MAX_INDEX\t\t\t767\n+#define VSI_TSR_STRIPTAG_S\t\t\t0\n+#define VSI_TSR_STRIPTAG_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VSI_TSR_SHOWTAG_S\t\t\t10\n+#define VSI_TSR_SHOWTAG_M\t\t\tMAKEMASK(0x3FF, 10)\n+#define VSI_TSR_SHOWPRIONLY_S\t\t\t20\n+#define VSI_TSR_SHOWPRIONLY_M\t\t\tMAKEMASK(0x3FF, 20)\n+#define VSI_TUPIOM(_VSI)\t\t\t(0x00048000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_TUPIOM_MAX_INDEX\t\t\t767\n+#define VSI_TUPIOM_UP0_S\t\t\t0\n+#define VSI_TUPIOM_UP0_M\t\t\tMAKEMASK(0x7, 0)\n+#define VSI_TUPIOM_UP1_S\t\t\t3\n+#define VSI_TUPIOM_UP1_M\t\t\tMAKEMASK(0x7, 3)\n+#define VSI_TUPIOM_UP2_S\t\t\t6\n+#define VSI_TUPIOM_UP2_M\t\t\tMAKEMASK(0x7, 6)\n+#define VSI_TUPIOM_UP3_S\t\t\t9\n+#define VSI_TUPIOM_UP3_M\t\t\tMAKEMASK(0x7, 9)\n+#define VSI_TUPIOM_UP4_S\t\t\t12\n+#define VSI_TUPIOM_UP4_M\t\t\tMAKEMASK(0x7, 12)\n+#define VSI_TUPIOM_UP5_S\t\t\t15\n+#define VSI_TUPIOM_UP5_M\t\t\tMAKEMASK(0x7, 15)\n+#define VSI_TUPIOM_UP6_S\t\t\t18\n+#define VSI_TUPIOM_UP6_M\t\t\tMAKEMASK(0x7, 18)\n+#define VSI_TUPIOM_UP7_S\t\t\t21\n+#define VSI_TUPIOM_UP7_M\t\t\tMAKEMASK(0x7, 21)\n+#define VSI_TUPR(_VSI)\t\t\t\t(0x00047000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_TUPR_MAX_INDEX\t\t\t767\n+#define VSI_TUPR_UP0_S\t\t\t\t0\n+#define VSI_TUPR_UP0_M\t\t\t\tMAKEMASK(0x7, 0)\n+#define VSI_TUPR_UP1_S\t\t\t\t3\n+#define VSI_TUPR_UP1_M\t\t\t\tMAKEMASK(0x7, 3)\n+#define VSI_TUPR_UP2_S\t\t\t\t6\n+#define VSI_TUPR_UP2_M\t\t\t\tMAKEMASK(0x7, 6)\n+#define VSI_TUPR_UP3_S\t\t\t\t9\n+#define VSI_TUPR_UP3_M\t\t\t\tMAKEMASK(0x7, 9)\n+#define VSI_TUPR_UP4_S\t\t\t\t12\n+#define VSI_TUPR_UP4_M\t\t\t\tMAKEMASK(0x7, 12)\n+#define VSI_TUPR_UP5_S\t\t\t\t15\n+#define VSI_TUPR_UP5_M\t\t\t\tMAKEMASK(0x7, 15)\n+#define VSI_TUPR_UP6_S\t\t\t\t18\n+#define VSI_TUPR_UP6_M\t\t\t\tMAKEMASK(0x7, 18)\n+#define VSI_TUPR_UP7_S\t\t\t\t21\n+#define VSI_TUPR_UP7_M\t\t\t\tMAKEMASK(0x7, 21)\n+#define VSI_VSI2F(_VSI)\t\t\t\t(0x001D0000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_VSI2F_MAX_INDEX\t\t\t767\n+#define VSI_VSI2F_VFVMNUMBER_S\t\t\t0\n+#define VSI_VSI2F_VFVMNUMBER_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VSI_VSI2F_FUNCTIONTYPE_S\t\t10\n+#define VSI_VSI2F_FUNCTIONTYPE_M\t\tMAKEMASK(0x3, 10)\n+#define VSI_VSI2F_PFNUMBER_S\t\t\t12\n+#define VSI_VSI2F_PFNUMBER_M\t\t\tMAKEMASK(0x7, 12)\n+#define VSI_VSI2F_BUFFERNUMBER_S\t\t16\n+#define VSI_VSI2F_BUFFERNUMBER_M\t\tMAKEMASK(0x7, 16)\n+#define VSI_VSI2F_VSI_NUMBER_S\t\t\t20\n+#define VSI_VSI2F_VSI_NUMBER_M\t\t\tMAKEMASK(0x3FF, 20)\n+#define VSI_VSI2F_VSI_ENABLE_S\t\t\t31\n+#define VSI_VSI2F_VSI_ENABLE_M\t\t\tBIT(31)\n+#define VSI_VSI2F_MBX(_VSI)\t\t\t(0x00232000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSI_VSI2F_MBX_MAX_INDEX\t\t\t767\n+#define VSI_VSI2F_MBX_VFVMNUMBER_S\t\t0\n+#define VSI_VSI2F_MBX_VFVMNUMBER_M\t\tMAKEMASK(0x3FF, 0)\n+#define VSI_VSI2F_MBX_FUNCTIONTYPE_S\t\t10\n+#define VSI_VSI2F_MBX_FUNCTIONTYPE_M\t\tMAKEMASK(0x3, 10)\n+#define VSI_VSI2F_MBX_PFNUMBER_S\t\t12\n+#define VSI_VSI2F_MBX_PFNUMBER_M\t\tMAKEMASK(0x7, 12)\n+#define VSI_VSI2F_MBX_BUFFERNUMBER_S\t\t16\n+#define VSI_VSI2F_MBX_BUFFERNUMBER_M\t\tMAKEMASK(0x7, 16)\n+#define VSI_VSI2F_MBX_VSI_NUMBER_S\t\t20\n+#define VSI_VSI2F_MBX_VSI_NUMBER_M\t\tMAKEMASK(0x3FF, 20)\n+#define VSI_VSI2F_MBX_VSI_ENABLE_S\t\t31\n+#define VSI_VSI2F_MBX_VSI_ENABLE_M\t\tBIT(31)\n+#define VSIQF_FD_CNT(_VSI)\t\t\t(0x00464000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSIQF_FD_CNT_MAX_INDEX\t\t\t767\n+#define VSIQF_FD_CNT_FD_GCNT_S\t\t\t0\n+#define VSIQF_FD_CNT_FD_GCNT_M\t\t\tMAKEMASK(0x3FFF, 0)\n+#define VSIQF_FD_CNT_FD_BCNT_S\t\t\t16\n+#define VSIQF_FD_CNT_FD_BCNT_M\t\t\tMAKEMASK(0x3FFF, 16)\n+#define VSIQF_FD_CTL1(_VSI)\t\t\t(0x00411000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSIQF_FD_CTL1_MAX_INDEX\t\t\t767\n+#define VSIQF_FD_CTL1_FLT_ENA_S\t\t\t0\n+#define VSIQF_FD_CTL1_FLT_ENA_M\t\t\tBIT(0)\n+#define VSIQF_FD_CTL1_CFG_ENA_S\t\t\t1\n+#define VSIQF_FD_CTL1_CFG_ENA_M\t\t\tBIT(1)\n+#define VSIQF_FD_CTL1_EVICT_ENA_S\t\t2\n+#define VSIQF_FD_CTL1_EVICT_ENA_M\t\tBIT(2)\n+#define VSIQF_FD_DFLT(_VSI)\t\t\t(0x00457000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSIQF_FD_DFLT_MAX_INDEX\t\t\t767\n+#define VSIQF_FD_DFLT_DEFLT_QINDX_S\t\t0\n+#define VSIQF_FD_DFLT_DEFLT_QINDX_M\t\tMAKEMASK(0x7FF, 0)\n+#define VSIQF_FD_DFLT_DEFLT_TOQUEUE_S\t\t12\n+#define VSIQF_FD_DFLT_DEFLT_TOQUEUE_M\t\tMAKEMASK(0x7, 12)\n+#define VSIQF_FD_DFLT_COMP_QINDX_S\t\t16\n+#define VSIQF_FD_DFLT_COMP_QINDX_M\t\tMAKEMASK(0x7FF, 16)\n+#define VSIQF_FD_DFLT_DEFLT_QINDX_PRIO_S\t28\n+#define VSIQF_FD_DFLT_DEFLT_QINDX_PRIO_M\tMAKEMASK(0x7, 28)\n+#define VSIQF_FD_DFLT_DEFLT_DROP_S\t\t31\n+#define VSIQF_FD_DFLT_DEFLT_DROP_M\t\tBIT(31)\n+#define VSIQF_FD_SIZE(_VSI)\t\t\t(0x00462000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: CORER */\n+#define VSIQF_FD_SIZE_MAX_INDEX\t\t\t767\n+#define VSIQF_FD_SIZE_FD_GSIZE_S\t\t0\n+#define VSIQF_FD_SIZE_FD_GSIZE_M\t\tMAKEMASK(0x3FFF, 0)\n+#define VSIQF_FD_SIZE_FD_BSIZE_S\t\t16\n+#define VSIQF_FD_SIZE_FD_BSIZE_M\t\tMAKEMASK(0x3FFF, 16)\n+#define VSIQF_HASH_CTL(_VSI)\t\t\t(0x0040D000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSIQF_HASH_CTL_MAX_INDEX\t\t767\n+#define VSIQF_HASH_CTL_HASH_LUT_SEL_S\t\t0\n+#define VSIQF_HASH_CTL_HASH_LUT_SEL_M\t\tMAKEMASK(0x3, 0)\n+#define VSIQF_HASH_CTL_GLOB_LUT_S\t\t2\n+#define VSIQF_HASH_CTL_GLOB_LUT_M\t\tMAKEMASK(0xF, 2)\n+#define VSIQF_HASH_CTL_HASH_SCHEME_S\t\t6\n+#define VSIQF_HASH_CTL_HASH_SCHEME_M\t\tMAKEMASK(0x3, 6)\n+#define VSIQF_HASH_CTL_TC_OVER_SEL_S\t\t8\n+#define VSIQF_HASH_CTL_TC_OVER_SEL_M\t\tMAKEMASK(0x1F, 8)\n+#define VSIQF_HASH_CTL_TC_OVER_ENA_S\t\t15\n+#define VSIQF_HASH_CTL_TC_OVER_ENA_M\t\tBIT(15)\n+#define VSIQF_HKEY(_i, _VSI)\t\t\t(0x00400000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...12, _VSI=0...767 */ /* Reset Source: PFR */\n+#define VSIQF_HKEY_MAX_INDEX\t\t\t12\n+#define VSIQF_HKEY_KEY_0_S\t\t\t0\n+#define VSIQF_HKEY_KEY_0_M\t\t\tMAKEMASK(0xFF, 0)\n+#define VSIQF_HKEY_KEY_1_S\t\t\t8\n+#define VSIQF_HKEY_KEY_1_M\t\t\tMAKEMASK(0xFF, 8)\n+#define VSIQF_HKEY_KEY_2_S\t\t\t16\n+#define VSIQF_HKEY_KEY_2_M\t\t\tMAKEMASK(0xFF, 16)\n+#define VSIQF_HKEY_KEY_3_S\t\t\t24\n+#define VSIQF_HKEY_KEY_3_M\t\t\tMAKEMASK(0xFF, 24)\n+#define VSIQF_HLUT(_i, _VSI)\t\t\t(0x00420000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...15, _VSI=0...767 */ /* Reset Source: PFR */\n+#define VSIQF_HLUT_MAX_INDEX\t\t\t15\n+#define VSIQF_HLUT_LUT0_S\t\t\t0\n+#define VSIQF_HLUT_LUT0_M\t\t\tMAKEMASK(0xF, 0)\n+#define VSIQF_HLUT_LUT1_S\t\t\t8\n+#define VSIQF_HLUT_LUT1_M\t\t\tMAKEMASK(0xF, 8)\n+#define VSIQF_HLUT_LUT2_S\t\t\t16\n+#define VSIQF_HLUT_LUT2_M\t\t\tMAKEMASK(0xF, 16)\n+#define VSIQF_HLUT_LUT3_S\t\t\t24\n+#define VSIQF_HLUT_LUT3_M\t\t\tMAKEMASK(0xF, 24)\n+#define VSIQF_PE_CTL1(_VSI)\t\t\t(0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ /* Reset Source: PFR */\n+#define VSIQF_PE_CTL1_MAX_INDEX\t\t\t767\n+#define VSIQF_PE_CTL1_PE_FLTENA_S\t\t0\n+#define VSIQF_PE_CTL1_PE_FLTENA_M\t\tBIT(0)\n+#define VSIQF_TC_REGION(_i, _VSI)\t\t(0x00448000 + ((_i) * 4096 + (_VSI) * 4)) /* _i=0...3, _VSI=0...767 */ /* Reset Source: PFR */\n+#define VSIQF_TC_REGION_MAX_INDEX\t\t3\n+#define VSIQF_TC_REGION_TC_BASE0_S\t\t0\n+#define VSIQF_TC_REGION_TC_BASE0_M\t\tMAKEMASK(0x7FF, 0)\n+#define VSIQF_TC_REGION_TC_SIZE0_S\t\t11\n+#define VSIQF_TC_REGION_TC_SIZE0_M\t\tMAKEMASK(0xF, 11)\n+#define VSIQF_TC_REGION_TC_BASE1_S\t\t16\n+#define VSIQF_TC_REGION_TC_BASE1_M\t\tMAKEMASK(0x7FF, 16)\n+#define VSIQF_TC_REGION_TC_SIZE1_S\t\t27\n+#define VSIQF_TC_REGION_TC_SIZE1_M\t\tMAKEMASK(0xF, 27)\n+#define GLPM_WUMC\t\t\t\t0x0009DEE4 /* Reset Source: POR */\n+#define GLPM_WUMC_MNG_WU_PF_S\t\t\t16\n+#define GLPM_WUMC_MNG_WU_PF_M\t\t\tMAKEMASK(0xFF, 16)\n+#define PFPM_APM\t\t\t\t0x000B8080 /* Reset Source: POR */\n+#define PFPM_APM_APME_S\t\t\t\t0\n+#define PFPM_APM_APME_M\t\t\t\tBIT(0)\n+#define PFPM_WUC\t\t\t\t0x0009DC80 /* Reset Source: POR */\n+#define PFPM_WUC_EN_APM_D0_S\t\t\t5\n+#define PFPM_WUC_EN_APM_D0_M\t\t\tBIT(5)\n+#define PFPM_WUFC\t\t\t\t0x0009DC00 /* Reset Source: POR */\n+#define PFPM_WUFC_LNKC_S\t\t\t0\n+#define PFPM_WUFC_LNKC_M\t\t\tBIT(0)\n+#define PFPM_WUFC_MAG_S\t\t\t\t1\n+#define PFPM_WUFC_MAG_M\t\t\t\tBIT(1)\n+#define PFPM_WUFC_MNG_S\t\t\t\t3\n+#define PFPM_WUFC_MNG_M\t\t\t\tBIT(3)\n+#define PFPM_WUFC_FLX0_ACT_S\t\t\t4\n+#define PFPM_WUFC_FLX0_ACT_M\t\t\tBIT(4)\n+#define PFPM_WUFC_FLX1_ACT_S\t\t\t5\n+#define PFPM_WUFC_FLX1_ACT_M\t\t\tBIT(5)\n+#define PFPM_WUFC_FLX2_ACT_S\t\t\t6\n+#define PFPM_WUFC_FLX2_ACT_M\t\t\tBIT(6)\n+#define PFPM_WUFC_FLX3_ACT_S\t\t\t7\n+#define PFPM_WUFC_FLX3_ACT_M\t\t\tBIT(7)\n+#define PFPM_WUFC_FLX4_ACT_S\t\t\t8\n+#define PFPM_WUFC_FLX4_ACT_M\t\t\tBIT(8)\n+#define PFPM_WUFC_FLX5_ACT_S\t\t\t9\n+#define PFPM_WUFC_FLX5_ACT_M\t\t\tBIT(9)\n+#define PFPM_WUFC_FLX6_ACT_S\t\t\t10\n+#define PFPM_WUFC_FLX6_ACT_M\t\t\tBIT(10)\n+#define PFPM_WUFC_FLX7_ACT_S\t\t\t11\n+#define PFPM_WUFC_FLX7_ACT_M\t\t\tBIT(11)\n+#define PFPM_WUFC_FLX0_S\t\t\t16\n+#define PFPM_WUFC_FLX0_M\t\t\tBIT(16)\n+#define PFPM_WUFC_FLX1_S\t\t\t17\n+#define PFPM_WUFC_FLX1_M\t\t\tBIT(17)\n+#define PFPM_WUFC_FLX2_S\t\t\t18\n+#define PFPM_WUFC_FLX2_M\t\t\tBIT(18)\n+#define PFPM_WUFC_FLX3_S\t\t\t19\n+#define PFPM_WUFC_FLX3_M\t\t\tBIT(19)\n+#define PFPM_WUFC_FLX4_S\t\t\t20\n+#define PFPM_WUFC_FLX4_M\t\t\tBIT(20)\n+#define PFPM_WUFC_FLX5_S\t\t\t21\n+#define PFPM_WUFC_FLX5_M\t\t\tBIT(21)\n+#define PFPM_WUFC_FLX6_S\t\t\t22\n+#define PFPM_WUFC_FLX6_M\t\t\tBIT(22)\n+#define PFPM_WUFC_FLX7_S\t\t\t23\n+#define PFPM_WUFC_FLX7_M\t\t\tBIT(23)\n+#define PFPM_WUFC_FW_RST_WK_S\t\t\t31\n+#define PFPM_WUFC_FW_RST_WK_M\t\t\tBIT(31)\n+#define PFPM_WUS\t\t\t\t0x0009DB80 /* Reset Source: POR */\n+#define PFPM_WUS_LNKC_S\t\t\t\t0\n+#define PFPM_WUS_LNKC_M\t\t\t\tBIT(0)\n+#define PFPM_WUS_MAG_S\t\t\t\t1\n+#define PFPM_WUS_MAG_M\t\t\t\tBIT(1)\n+#define PFPM_WUS_PME_STATUS_S\t\t\t2\n+#define PFPM_WUS_PME_STATUS_M\t\t\tBIT(2)\n+#define PFPM_WUS_MNG_S\t\t\t\t3\n+#define PFPM_WUS_MNG_M\t\t\t\tBIT(3)\n+#define PFPM_WUS_FLX0_S\t\t\t\t16\n+#define PFPM_WUS_FLX0_M\t\t\t\tBIT(16)\n+#define PFPM_WUS_FLX1_S\t\t\t\t17\n+#define PFPM_WUS_FLX1_M\t\t\t\tBIT(17)\n+#define PFPM_WUS_FLX2_S\t\t\t\t18\n+#define PFPM_WUS_FLX2_M\t\t\t\tBIT(18)\n+#define PFPM_WUS_FLX3_S\t\t\t\t19\n+#define PFPM_WUS_FLX3_M\t\t\t\tBIT(19)\n+#define PFPM_WUS_FLX4_S\t\t\t\t20\n+#define PFPM_WUS_FLX4_M\t\t\t\tBIT(20)\n+#define PFPM_WUS_FLX5_S\t\t\t\t21\n+#define PFPM_WUS_FLX5_M\t\t\t\tBIT(21)\n+#define PFPM_WUS_FLX6_S\t\t\t\t22\n+#define PFPM_WUS_FLX6_M\t\t\t\tBIT(22)\n+#define PFPM_WUS_FLX7_S\t\t\t\t23\n+#define PFPM_WUS_FLX7_M\t\t\t\tBIT(23)\n+#define PFPM_WUS_FW_RST_WK_S\t\t\t31\n+#define PFPM_WUS_FW_RST_WK_M\t\t\tBIT(31)\n+#define PRTPM_SAH(_i)\t\t\t\t(0x001E3BA0 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */\n+#define PRTPM_SAH_MAX_INDEX\t\t\t3\n+#define PRTPM_SAH_PFPM_SAH_S\t\t\t0\n+#define PRTPM_SAH_PFPM_SAH_M\t\t\tMAKEMASK(0xFFFF, 0)\n+#define PRTPM_SAH_PF_NUM_S\t\t\t26\n+#define PRTPM_SAH_PF_NUM_M\t\t\tMAKEMASK(0xF, 26)\n+#define PRTPM_SAH_MC_MAG_EN_S\t\t\t30\n+#define PRTPM_SAH_MC_MAG_EN_M\t\t\tBIT(30)\n+#define PRTPM_SAH_AV_S\t\t\t\t31\n+#define PRTPM_SAH_AV_M\t\t\t\tBIT(31)\n+#define PRTPM_SAL(_i)\t\t\t\t(0x001E3B20 + ((_i) * 32)) /* _i=0...3 */ /* Reset Source: PFR */\n+#define PRTPM_SAL_MAX_INDEX\t\t\t3\n+#define PRTPM_SAL_PFPM_SAL_S\t\t\t0\n+#define PRTPM_SAL_PFPM_SAL_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define GLPE_CQM_FUNC_INVALIDATE\t\t0x00503300 /* Reset Source: CORER */\n+#define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_S\t0\n+#define GLPE_CQM_FUNC_INVALIDATE_PF_NUM_M\tMAKEMASK(0x7, 0)\n+#define GLPE_CQM_FUNC_INVALIDATE_VM_VF_NUM_S\t3\n+#define GLPE_CQM_FUNC_INVALIDATE_VM_VF_NUM_M\tMAKEMASK(0x3FF, 3)\n+#define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_S\t13\n+#define GLPE_CQM_FUNC_INVALIDATE_VM_VF_TYPE_M\tMAKEMASK(0x3, 13)\n+#define GLPE_CQM_FUNC_INVALIDATE_ENABLE_S\t31\n+#define GLPE_CQM_FUNC_INVALIDATE_ENABLE_M\tBIT(31)\n+#define VFPE_MRTEIDXMASK\t\t\t0x00009000 /* Reset Source: PFR */\n+#define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_S\t0\n+#define VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_M\tMAKEMASK(0x1F, 0)\n+#define GLTSYN_HH_DLAY\t\t\t\t0x0008881C /* Reset Source: CORER */\n+#define GLTSYN_HH_DLAY_SYNC_DELAY_S\t\t0\n+#define GLTSYN_HH_DLAY_SYNC_DELAY_M\t\tMAKEMASK(0xF, 0)\n+#define VF_MBX_ARQBAH1\t\t\t\t0x00006000 /* Reset Source: CORER */\n+#define VF_MBX_ARQBAH1_ARQBAH_S\t\t\t0\n+#define VF_MBX_ARQBAH1_ARQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_ARQBAL1\t\t\t\t0x00006C00 /* Reset Source: CORER */\n+#define VF_MBX_ARQBAL1_ARQBAL_LSB_S\t\t0\n+#define VF_MBX_ARQBAL1_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_MBX_ARQBAL1_ARQBAL_S\t\t\t6\n+#define VF_MBX_ARQBAL1_ARQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_ARQH1\t\t\t\t0x00007400 /* Reset Source: CORER */\n+#define VF_MBX_ARQH1_ARQH_S\t\t\t0\n+#define VF_MBX_ARQH1_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ARQLEN1\t\t\t\t0x00008000 /* Reset Source: CORER */\n+#define VF_MBX_ARQLEN1_ARQLEN_S\t\t\t0\n+#define VF_MBX_ARQLEN1_ARQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ARQLEN1_ARQVFE_S\t\t\t28\n+#define VF_MBX_ARQLEN1_ARQVFE_M\t\t\tBIT(28)\n+#define VF_MBX_ARQLEN1_ARQOVFL_S\t\t29\n+#define VF_MBX_ARQLEN1_ARQOVFL_M\t\tBIT(29)\n+#define VF_MBX_ARQLEN1_ARQCRIT_S\t\t30\n+#define VF_MBX_ARQLEN1_ARQCRIT_M\t\tBIT(30)\n+#define VF_MBX_ARQLEN1_ARQENABLE_S\t\t31\n+#define VF_MBX_ARQLEN1_ARQENABLE_M\t\tBIT(31)\n+#define VF_MBX_ARQT1\t\t\t\t0x00007000 /* Reset Source: CORER */\n+#define VF_MBX_ARQT1_ARQT_S\t\t\t0\n+#define VF_MBX_ARQT1_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ATQBAH1\t\t\t\t0x00007800 /* Reset Source: CORER */\n+#define VF_MBX_ATQBAH1_ATQBAH_S\t\t\t0\n+#define VF_MBX_ATQBAH1_ATQBAH_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_ATQBAL1\t\t\t\t0x00007C00 /* Reset Source: CORER */\n+#define VF_MBX_ATQBAL1_ATQBAL_S\t\t\t6\n+#define VF_MBX_ATQBAL1_ATQBAL_M\t\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_ATQH1\t\t\t\t0x00006400 /* Reset Source: CORER */\n+#define VF_MBX_ATQH1_ATQH_S\t\t\t0\n+#define VF_MBX_ATQH1_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ATQLEN1\t\t\t\t0x00006800 /* Reset Source: CORER */\n+#define VF_MBX_ATQLEN1_ATQLEN_S\t\t\t0\n+#define VF_MBX_ATQLEN1_ATQLEN_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_ATQLEN1_ATQVFE_S\t\t\t28\n+#define VF_MBX_ATQLEN1_ATQVFE_M\t\t\tBIT(28)\n+#define VF_MBX_ATQLEN1_ATQOVFL_S\t\t29\n+#define VF_MBX_ATQLEN1_ATQOVFL_M\t\tBIT(29)\n+#define VF_MBX_ATQLEN1_ATQCRIT_S\t\t30\n+#define VF_MBX_ATQLEN1_ATQCRIT_M\t\tBIT(30)\n+#define VF_MBX_ATQLEN1_ATQENABLE_S\t\t31\n+#define VF_MBX_ATQLEN1_ATQENABLE_M\t\tBIT(31)\n+#define VF_MBX_ATQT1\t\t\t\t0x00008400 /* Reset Source: CORER */\n+#define VF_MBX_ATQT1_ATQT_S\t\t\t0\n+#define VF_MBX_ATQT1_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define PFPCI_VF_FLUSH_DONE1\t\t\t0x0000E400 /* Reset Source: PCIR */\n+#define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_S\t0\n+#define PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_M\tBIT(0)\n+#define VFGEN_RSTAT1\t\t\t\t0x00008800 /* Reset Source: VFR */\n+#define VFGEN_RSTAT1_VFR_STATE_S\t\t0\n+#define VFGEN_RSTAT1_VFR_STATE_M\t\tMAKEMASK(0x3, 0)\n+#define VFINT_DYN_CTL0\t\t\t\t0x00005C00 /* Reset Source: PFR */\n+#define VFINT_DYN_CTL0_INTENA_S\t\t\t0\n+#define VFINT_DYN_CTL0_INTENA_M\t\t\tBIT(0)\n+#define VFINT_DYN_CTL0_CLEARPBA_S\t\t1\n+#define VFINT_DYN_CTL0_CLEARPBA_M\t\tBIT(1)\n+#define VFINT_DYN_CTL0_SWINT_TRIG_S\t\t2\n+#define VFINT_DYN_CTL0_SWINT_TRIG_M\t\tBIT(2)\n+#define VFINT_DYN_CTL0_ITR_INDX_S\t\t3\n+#define VFINT_DYN_CTL0_ITR_INDX_M\t\tMAKEMASK(0x3, 3)\n+#define VFINT_DYN_CTL0_INTERVAL_S\t\t5\n+#define VFINT_DYN_CTL0_INTERVAL_M\t\tMAKEMASK(0xFFF, 5)\n+#define VFINT_DYN_CTL0_SW_ITR_INDX_ENA_S\t24\n+#define VFINT_DYN_CTL0_SW_ITR_INDX_ENA_M\tBIT(24)\n+#define VFINT_DYN_CTL0_SW_ITR_INDX_S\t\t25\n+#define VFINT_DYN_CTL0_SW_ITR_INDX_M\t\tMAKEMASK(0x3, 25)\n+#define VFINT_DYN_CTL0_WB_ON_ITR_S\t\t30\n+#define VFINT_DYN_CTL0_WB_ON_ITR_M\t\tBIT(30)\n+#define VFINT_DYN_CTL0_INTENA_MSK_S\t\t31\n+#define VFINT_DYN_CTL0_INTENA_MSK_M\t\tBIT(31)\n+#define VFINT_DYN_CTLN(_i)\t\t\t(0x00003800 + ((_i) * 4)) /* _i=0...63 */ /* Reset Source: PFR */\n+#define VFINT_DYN_CTLN_MAX_INDEX\t\t63\n+#define VFINT_DYN_CTLN_INTENA_S\t\t\t0\n+#define VFINT_DYN_CTLN_INTENA_M\t\t\tBIT(0)\n+#define VFINT_DYN_CTLN_CLEARPBA_S\t\t1\n+#define VFINT_DYN_CTLN_CLEARPBA_M\t\tBIT(1)\n+#define VFINT_DYN_CTLN_SWINT_TRIG_S\t\t2\n+#define VFINT_DYN_CTLN_SWINT_TRIG_M\t\tBIT(2)\n+#define VFINT_DYN_CTLN_ITR_INDX_S\t\t3\n+#define VFINT_DYN_CTLN_ITR_INDX_M\t\tMAKEMASK(0x3, 3)\n+#define VFINT_DYN_CTLN_INTERVAL_S\t\t5\n+#define VFINT_DYN_CTLN_INTERVAL_M\t\tMAKEMASK(0xFFF, 5)\n+#define VFINT_DYN_CTLN_SW_ITR_INDX_ENA_S\t24\n+#define VFINT_DYN_CTLN_SW_ITR_INDX_ENA_M\tBIT(24)\n+#define VFINT_DYN_CTLN_SW_ITR_INDX_S\t\t25\n+#define VFINT_DYN_CTLN_SW_ITR_INDX_M\t\tMAKEMASK(0x3, 25)\n+#define VFINT_DYN_CTLN_WB_ON_ITR_S\t\t30\n+#define VFINT_DYN_CTLN_WB_ON_ITR_M\t\tBIT(30)\n+#define VFINT_DYN_CTLN_INTENA_MSK_S\t\t31\n+#define VFINT_DYN_CTLN_INTENA_MSK_M\t\tBIT(31)\n+#define VFINT_ITR0(_i)\t\t\t\t(0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset Source: PFR */\n+#define VFINT_ITR0_MAX_INDEX\t\t\t2\n+#define VFINT_ITR0_INTERVAL_S\t\t\t0\n+#define VFINT_ITR0_INTERVAL_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define VFINT_ITRN(_i, _j)\t\t\t(0x00002800 + ((_i) * 4 + (_j) * 12)) /* _i=0...2, _j=0...63 */ /* Reset Source: PFR */\n+#define VFINT_ITRN_MAX_INDEX\t\t\t2\n+#define VFINT_ITRN_INTERVAL_S\t\t\t0\n+#define VFINT_ITRN_INTERVAL_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define QRX_TAIL1(_QRX)\t\t\t\t(0x00002000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define QRX_TAIL1_MAX_INDEX\t\t\t255\n+#define QRX_TAIL1_TAIL_S\t\t\t0\n+#define QRX_TAIL1_TAIL_M\t\t\tMAKEMASK(0x1FFF, 0)\n+#define QTX_TAIL(_DBQM)\t\t\t\t(0x00000000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define QTX_TAIL_MAX_INDEX\t\t\t255\n+#define QTX_TAIL_QTX_COMM_DBELL_S\t\t0\n+#define QTX_TAIL_QTX_COMM_DBELL_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define MSIX_TMSG1(_i)\t\t\t\t(0x00000008 + ((_i) * 16)) /* _i=0...64 */ /* Reset Source: FLR */\n+#define MSIX_TMSG1_MAX_INDEX\t\t\t64\n+#define MSIX_TMSG1_MSIXTMSG_S\t\t\t0\n+#define MSIX_TMSG1_MSIXTMSG_M\t\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFPE_AEQALLOC1\t\t\t\t0x0000A400 /* Reset Source: VFR */\n+#define VFPE_AEQALLOC1_AECOUNT_S\t\t0\n+#define VFPE_AEQALLOC1_AECOUNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFPE_CCQPHIGH1\t\t\t\t0x00009800 /* Reset Source: VFR */\n+#define VFPE_CCQPHIGH1_PECCQPHIGH_S\t\t0\n+#define VFPE_CCQPHIGH1_PECCQPHIGH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFPE_CCQPLOW1\t\t\t\t0x0000AC00 /* Reset Source: VFR */\n+#define VFPE_CCQPLOW1_PECCQPLOW_S\t\t0\n+#define VFPE_CCQPLOW1_PECCQPLOW_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFPE_CCQPSTATUS1\t\t\t0x0000B800 /* Reset Source: VFR */\n+#define VFPE_CCQPSTATUS1_CCQP_DONE_S\t\t0\n+#define VFPE_CCQPSTATUS1_CCQP_DONE_M\t\tBIT(0)\n+#define VFPE_CCQPSTATUS1_HMC_PROFILE_S\t\t4\n+#define VFPE_CCQPSTATUS1_HMC_PROFILE_M\t\tMAKEMASK(0x7, 4)\n+#define VFPE_CCQPSTATUS1_RDMA_EN_VFS_S\t\t16\n+#define VFPE_CCQPSTATUS1_RDMA_EN_VFS_M\t\tMAKEMASK(0x3F, 16)\n+#define VFPE_CCQPSTATUS1_CCQP_ERR_S\t\t31\n+#define VFPE_CCQPSTATUS1_CCQP_ERR_M\t\tBIT(31)\n+#define VFPE_CQACK1\t\t\t\t0x0000B000 /* Reset Source: VFR */\n+#define VFPE_CQACK1_PECQID_S\t\t\t0\n+#define VFPE_CQACK1_PECQID_M\t\t\tMAKEMASK(0x7FFFF, 0)\n+#define VFPE_CQARM1\t\t\t\t0x0000B400 /* Reset Source: VFR */\n+#define VFPE_CQARM1_PECQID_S\t\t\t0\n+#define VFPE_CQARM1_PECQID_M\t\t\tMAKEMASK(0x7FFFF, 0)\n+#define VFPE_CQPDB1\t\t\t\t0x0000BC00 /* Reset Source: VFR */\n+#define VFPE_CQPDB1_WQHEAD_S\t\t\t0\n+#define VFPE_CQPDB1_WQHEAD_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define VFPE_CQPERRCODES1\t\t\t0x00009C00 /* Reset Source: VFR */\n+#define VFPE_CQPERRCODES1_CQP_MINOR_CODE_S\t0\n+#define VFPE_CQPERRCODES1_CQP_MINOR_CODE_M\tMAKEMASK(0xFFFF, 0)\n+#define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_S\t16\n+#define VFPE_CQPERRCODES1_CQP_MAJOR_CODE_M\tMAKEMASK(0xFFFF, 16)\n+#define VFPE_CQPTAIL1\t\t\t\t0x0000A000 /* Reset Source: VFR */\n+#define VFPE_CQPTAIL1_WQTAIL_S\t\t\t0\n+#define VFPE_CQPTAIL1_WQTAIL_M\t\t\tMAKEMASK(0x7FF, 0)\n+#define VFPE_CQPTAIL1_CQP_OP_ERR_S\t\t31\n+#define VFPE_CQPTAIL1_CQP_OP_ERR_M\t\tBIT(31)\n+#define VFPE_IPCONFIG01\t\t\t\t0x00008C00 /* Reset Source: VFR */\n+#define VFPE_IPCONFIG01_PEIPID_S\t\t0\n+#define VFPE_IPCONFIG01_PEIPID_M\t\tMAKEMASK(0xFFFF, 0)\n+#define VFPE_IPCONFIG01_USEENTIREIDRANGE_S\t16\n+#define VFPE_IPCONFIG01_USEENTIREIDRANGE_M\tBIT(16)\n+#define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_S\t17\n+#define VFPE_IPCONFIG01_UDP_SRC_PORT_MASK_EN_M\tBIT(17)\n+#define VFPE_MRTEIDXMASK1(_VF)\t\t\t(0x00509800 + ((_VF) * 4)) /* _i=0...255 */ /* Reset Source: PFR */\n+#define VFPE_MRTEIDXMASK1_MAX_INDEX\t\t255\n+#define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_S\t0\n+#define VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_M\tMAKEMASK(0x1F, 0)\n+#define VFPE_RCVUNEXPECTEDERROR1\t\t0x00009400 /* Reset Source: VFR */\n+#define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_S 0\n+#define VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_M MAKEMASK(0xFFFFFF, 0)\n+#define VFPE_TCPNOWTIMER1\t\t\t0x0000A800 /* Reset Source: VFR */\n+#define VFPE_TCPNOWTIMER1_TCP_NOW_S\t\t0\n+#define VFPE_TCPNOWTIMER1_TCP_NOW_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFPE_WQEALLOC1\t\t\t\t0x0000C000 /* Reset Source: VFR */\n+#define VFPE_WQEALLOC1_PEQPID_S\t\t\t0\n+#define VFPE_WQEALLOC1_PEQPID_M\t\t\tMAKEMASK(0x3FFFF, 0)\n+#define VFPE_WQEALLOC1_WQE_DESC_INDEX_S\t\t20\n+#define VFPE_WQEALLOC1_WQE_DESC_INDEX_M\t\tMAKEMASK(0xFFF, 20)\n+#define VF_MBX_CPM_ARQBAH1\t\t\t0x0000F060 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQBAH1_ARQBAH_S\t\t0\n+#define VF_MBX_CPM_ARQBAH1_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_CPM_ARQBAL1\t\t\t0x0000F050 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_S\t\t0\n+#define VF_MBX_CPM_ARQBAL1_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_MBX_CPM_ARQBAL1_ARQBAL_S\t\t6\n+#define VF_MBX_CPM_ARQBAL1_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_CPM_ARQH1\t\t\t0x0000F080 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQH1_ARQH_S\t\t\t0\n+#define VF_MBX_CPM_ARQH1_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ARQLEN1\t\t\t0x0000F070 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQLEN1_ARQLEN_S\t\t0\n+#define VF_MBX_CPM_ARQLEN1_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ARQLEN1_ARQVFE_S\t\t28\n+#define VF_MBX_CPM_ARQLEN1_ARQVFE_M\t\tBIT(28)\n+#define VF_MBX_CPM_ARQLEN1_ARQOVFL_S\t\t29\n+#define VF_MBX_CPM_ARQLEN1_ARQOVFL_M\t\tBIT(29)\n+#define VF_MBX_CPM_ARQLEN1_ARQCRIT_S\t\t30\n+#define VF_MBX_CPM_ARQLEN1_ARQCRIT_M\t\tBIT(30)\n+#define VF_MBX_CPM_ARQLEN1_ARQENABLE_S\t\t31\n+#define VF_MBX_CPM_ARQLEN1_ARQENABLE_M\t\tBIT(31)\n+#define VF_MBX_CPM_ARQT1\t\t\t0x0000F090 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ARQT1_ARQT_S\t\t\t0\n+#define VF_MBX_CPM_ARQT1_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ATQBAH1\t\t\t0x0000F010 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQBAH1_ATQBAH_S\t\t0\n+#define VF_MBX_CPM_ATQBAH1_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_CPM_ATQBAL1\t\t\t0x0000F000 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQBAL1_ATQBAL_S\t\t6\n+#define VF_MBX_CPM_ATQBAL1_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_CPM_ATQH1\t\t\t0x0000F030 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQH1_ATQH_S\t\t\t0\n+#define VF_MBX_CPM_ATQH1_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ATQLEN1\t\t\t0x0000F020 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQLEN1_ATQLEN_S\t\t0\n+#define VF_MBX_CPM_ATQLEN1_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_CPM_ATQLEN1_ATQVFE_S\t\t28\n+#define VF_MBX_CPM_ATQLEN1_ATQVFE_M\t\tBIT(28)\n+#define VF_MBX_CPM_ATQLEN1_ATQOVFL_S\t\t29\n+#define VF_MBX_CPM_ATQLEN1_ATQOVFL_M\t\tBIT(29)\n+#define VF_MBX_CPM_ATQLEN1_ATQCRIT_S\t\t30\n+#define VF_MBX_CPM_ATQLEN1_ATQCRIT_M\t\tBIT(30)\n+#define VF_MBX_CPM_ATQLEN1_ATQENABLE_S\t\t31\n+#define VF_MBX_CPM_ATQLEN1_ATQENABLE_M\t\tBIT(31)\n+#define VF_MBX_CPM_ATQT1\t\t\t0x0000F040 /* Reset Source: CORER */\n+#define VF_MBX_CPM_ATQT1_ATQT_S\t\t\t0\n+#define VF_MBX_CPM_ATQT1_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ARQBAH1\t\t\t0x00020060 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQBAH1_ARQBAH_S\t\t0\n+#define VF_MBX_HLP_ARQBAH1_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_HLP_ARQBAL1\t\t\t0x00020050 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_S\t\t0\n+#define VF_MBX_HLP_ARQBAL1_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_MBX_HLP_ARQBAL1_ARQBAL_S\t\t6\n+#define VF_MBX_HLP_ARQBAL1_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_HLP_ARQH1\t\t\t0x00020080 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQH1_ARQH_S\t\t\t0\n+#define VF_MBX_HLP_ARQH1_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ARQLEN1\t\t\t0x00020070 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQLEN1_ARQLEN_S\t\t0\n+#define VF_MBX_HLP_ARQLEN1_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ARQLEN1_ARQVFE_S\t\t28\n+#define VF_MBX_HLP_ARQLEN1_ARQVFE_M\t\tBIT(28)\n+#define VF_MBX_HLP_ARQLEN1_ARQOVFL_S\t\t29\n+#define VF_MBX_HLP_ARQLEN1_ARQOVFL_M\t\tBIT(29)\n+#define VF_MBX_HLP_ARQLEN1_ARQCRIT_S\t\t30\n+#define VF_MBX_HLP_ARQLEN1_ARQCRIT_M\t\tBIT(30)\n+#define VF_MBX_HLP_ARQLEN1_ARQENABLE_S\t\t31\n+#define VF_MBX_HLP_ARQLEN1_ARQENABLE_M\t\tBIT(31)\n+#define VF_MBX_HLP_ARQT1\t\t\t0x00020090 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ARQT1_ARQT_S\t\t\t0\n+#define VF_MBX_HLP_ARQT1_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ATQBAH1\t\t\t0x00020010 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQBAH1_ATQBAH_S\t\t0\n+#define VF_MBX_HLP_ATQBAH1_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_HLP_ATQBAL1\t\t\t0x00020000 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQBAL1_ATQBAL_S\t\t6\n+#define VF_MBX_HLP_ATQBAL1_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_HLP_ATQH1\t\t\t0x00020030 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQH1_ATQH_S\t\t\t0\n+#define VF_MBX_HLP_ATQH1_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ATQLEN1\t\t\t0x00020020 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQLEN1_ATQLEN_S\t\t0\n+#define VF_MBX_HLP_ATQLEN1_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_HLP_ATQLEN1_ATQVFE_S\t\t28\n+#define VF_MBX_HLP_ATQLEN1_ATQVFE_M\t\tBIT(28)\n+#define VF_MBX_HLP_ATQLEN1_ATQOVFL_S\t\t29\n+#define VF_MBX_HLP_ATQLEN1_ATQOVFL_M\t\tBIT(29)\n+#define VF_MBX_HLP_ATQLEN1_ATQCRIT_S\t\t30\n+#define VF_MBX_HLP_ATQLEN1_ATQCRIT_M\t\tBIT(30)\n+#define VF_MBX_HLP_ATQLEN1_ATQENABLE_S\t\t31\n+#define VF_MBX_HLP_ATQLEN1_ATQENABLE_M\t\tBIT(31)\n+#define VF_MBX_HLP_ATQT1\t\t\t0x00020040 /* Reset Source: CORER */\n+#define VF_MBX_HLP_ATQT1_ATQT_S\t\t\t0\n+#define VF_MBX_HLP_ATQT1_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ARQBAH1\t\t\t0x00021060 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQBAH1_ARQBAH_S\t\t0\n+#define VF_MBX_PSM_ARQBAH1_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_PSM_ARQBAL1\t\t\t0x00021050 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_S\t\t0\n+#define VF_MBX_PSM_ARQBAL1_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_MBX_PSM_ARQBAL1_ARQBAL_S\t\t6\n+#define VF_MBX_PSM_ARQBAL1_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_PSM_ARQH1\t\t\t0x00021080 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQH1_ARQH_S\t\t\t0\n+#define VF_MBX_PSM_ARQH1_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ARQLEN1\t\t\t0x00021070 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQLEN1_ARQLEN_S\t\t0\n+#define VF_MBX_PSM_ARQLEN1_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ARQLEN1_ARQVFE_S\t\t28\n+#define VF_MBX_PSM_ARQLEN1_ARQVFE_M\t\tBIT(28)\n+#define VF_MBX_PSM_ARQLEN1_ARQOVFL_S\t\t29\n+#define VF_MBX_PSM_ARQLEN1_ARQOVFL_M\t\tBIT(29)\n+#define VF_MBX_PSM_ARQLEN1_ARQCRIT_S\t\t30\n+#define VF_MBX_PSM_ARQLEN1_ARQCRIT_M\t\tBIT(30)\n+#define VF_MBX_PSM_ARQLEN1_ARQENABLE_S\t\t31\n+#define VF_MBX_PSM_ARQLEN1_ARQENABLE_M\t\tBIT(31)\n+#define VF_MBX_PSM_ARQT1\t\t\t0x00021090 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ARQT1_ARQT_S\t\t\t0\n+#define VF_MBX_PSM_ARQT1_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ATQBAH1\t\t\t0x00021010 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQBAH1_ATQBAH_S\t\t0\n+#define VF_MBX_PSM_ATQBAH1_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_MBX_PSM_ATQBAL1\t\t\t0x00021000 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQBAL1_ATQBAL_S\t\t6\n+#define VF_MBX_PSM_ATQBAL1_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_MBX_PSM_ATQH1\t\t\t0x00021030 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQH1_ATQH_S\t\t\t0\n+#define VF_MBX_PSM_ATQH1_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ATQLEN1\t\t\t0x00021020 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQLEN1_ATQLEN_S\t\t0\n+#define VF_MBX_PSM_ATQLEN1_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_MBX_PSM_ATQLEN1_ATQVFE_S\t\t28\n+#define VF_MBX_PSM_ATQLEN1_ATQVFE_M\t\tBIT(28)\n+#define VF_MBX_PSM_ATQLEN1_ATQOVFL_S\t\t29\n+#define VF_MBX_PSM_ATQLEN1_ATQOVFL_M\t\tBIT(29)\n+#define VF_MBX_PSM_ATQLEN1_ATQCRIT_S\t\t30\n+#define VF_MBX_PSM_ATQLEN1_ATQCRIT_M\t\tBIT(30)\n+#define VF_MBX_PSM_ATQLEN1_ATQENABLE_S\t\t31\n+#define VF_MBX_PSM_ATQLEN1_ATQENABLE_M\t\tBIT(31)\n+#define VF_MBX_PSM_ATQT1\t\t\t0x00021040 /* Reset Source: CORER */\n+#define VF_MBX_PSM_ATQT1_ATQT_S\t\t\t0\n+#define VF_MBX_PSM_ATQT1_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ARQBAH1\t\t\t0x0000F160 /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQBAH1_ARQBAH_S\t\t0\n+#define VF_SB_CPM_ARQBAH1_ARQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_SB_CPM_ARQBAL1\t\t\t0x0000F150 /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_S\t\t0\n+#define VF_SB_CPM_ARQBAL1_ARQBAL_LSB_M\t\tMAKEMASK(0x3F, 0)\n+#define VF_SB_CPM_ARQBAL1_ARQBAL_S\t\t6\n+#define VF_SB_CPM_ARQBAL1_ARQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_SB_CPM_ARQH1\t\t\t\t0x0000F180 /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQH1_ARQH_S\t\t\t0\n+#define VF_SB_CPM_ARQH1_ARQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ARQLEN1\t\t\t0x0000F170 /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQLEN1_ARQLEN_S\t\t0\n+#define VF_SB_CPM_ARQLEN1_ARQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ARQLEN1_ARQVFE_S\t\t28\n+#define VF_SB_CPM_ARQLEN1_ARQVFE_M\t\tBIT(28)\n+#define VF_SB_CPM_ARQLEN1_ARQOVFL_S\t\t29\n+#define VF_SB_CPM_ARQLEN1_ARQOVFL_M\t\tBIT(29)\n+#define VF_SB_CPM_ARQLEN1_ARQCRIT_S\t\t30\n+#define VF_SB_CPM_ARQLEN1_ARQCRIT_M\t\tBIT(30)\n+#define VF_SB_CPM_ARQLEN1_ARQENABLE_S\t\t31\n+#define VF_SB_CPM_ARQLEN1_ARQENABLE_M\t\tBIT(31)\n+#define VF_SB_CPM_ARQT1\t\t\t\t0x0000F190 /* Reset Source: CORER */\n+#define VF_SB_CPM_ARQT1_ARQT_S\t\t\t0\n+#define VF_SB_CPM_ARQT1_ARQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ATQBAH1\t\t\t0x0000F110 /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQBAH1_ATQBAH_S\t\t0\n+#define VF_SB_CPM_ATQBAH1_ATQBAH_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VF_SB_CPM_ATQBAL1\t\t\t0x0000F100 /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQBAL1_ATQBAL_S\t\t6\n+#define VF_SB_CPM_ATQBAL1_ATQBAL_M\t\tMAKEMASK(0x3FFFFFF, 6)\n+#define VF_SB_CPM_ATQH1\t\t\t\t0x0000F130 /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQH1_ATQH_S\t\t\t0\n+#define VF_SB_CPM_ATQH1_ATQH_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ATQLEN1\t\t\t0x0000F120 /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQLEN1_ATQLEN_S\t\t0\n+#define VF_SB_CPM_ATQLEN1_ATQLEN_M\t\tMAKEMASK(0x3FF, 0)\n+#define VF_SB_CPM_ATQLEN1_ATQVFE_S\t\t28\n+#define VF_SB_CPM_ATQLEN1_ATQVFE_M\t\tBIT(28)\n+#define VF_SB_CPM_ATQLEN1_ATQOVFL_S\t\t29\n+#define VF_SB_CPM_ATQLEN1_ATQOVFL_M\t\tBIT(29)\n+#define VF_SB_CPM_ATQLEN1_ATQCRIT_S\t\t30\n+#define VF_SB_CPM_ATQLEN1_ATQCRIT_M\t\tBIT(30)\n+#define VF_SB_CPM_ATQLEN1_ATQENABLE_S\t\t31\n+#define VF_SB_CPM_ATQLEN1_ATQENABLE_M\t\tBIT(31)\n+#define VF_SB_CPM_ATQT1\t\t\t\t0x0000F140 /* Reset Source: CORER */\n+#define VF_SB_CPM_ATQT1_ATQT_S\t\t\t0\n+#define VF_SB_CPM_ATQT1_ATQT_M\t\t\tMAKEMASK(0x3FF, 0)\n+#define VFINT_DYN_CTL(_i)\t\t\t(0x00023000 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: PFR */\n+#define VFINT_DYN_CTL_MAX_INDEX\t\t\t7\n+#define VFINT_DYN_CTL_INTENA_S\t\t\t0\n+#define VFINT_DYN_CTL_INTENA_M\t\t\tBIT(0)\n+#define VFINT_DYN_CTL_CLEARPBA_S\t\t1\n+#define VFINT_DYN_CTL_CLEARPBA_M\t\tBIT(1)\n+#define VFINT_DYN_CTL_SWINT_TRIG_S\t\t2\n+#define VFINT_DYN_CTL_SWINT_TRIG_M\t\tBIT(2)\n+#define VFINT_DYN_CTL_ITR_INDX_S\t\t3\n+#define VFINT_DYN_CTL_ITR_INDX_M\t\tMAKEMASK(0x3, 3)\n+#define VFINT_DYN_CTL_INTERVAL_S\t\t5\n+#define VFINT_DYN_CTL_INTERVAL_M\t\tMAKEMASK(0xFFF, 5)\n+#define VFINT_DYN_CTL_SW_ITR_INDX_ENA_S\t\t24\n+#define VFINT_DYN_CTL_SW_ITR_INDX_ENA_M\t\tBIT(24)\n+#define VFINT_DYN_CTL_SW_ITR_INDX_S\t\t25\n+#define VFINT_DYN_CTL_SW_ITR_INDX_M\t\tMAKEMASK(0x3, 25)\n+#define VFINT_DYN_CTL_WB_ON_ITR_S\t\t30\n+#define VFINT_DYN_CTL_WB_ON_ITR_M\t\tBIT(30)\n+#define VFINT_DYN_CTL_INTENA_MSK_S\t\t31\n+#define VFINT_DYN_CTL_INTENA_MSK_M\t\tBIT(31)\n+#define VFINT_ITR_0(_i)\t\t\t\t(0x00023004 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: PFR */\n+#define VFINT_ITR_0_MAX_INDEX\t\t\t7\n+#define VFINT_ITR_0_INTERVAL_S\t\t\t0\n+#define VFINT_ITR_0_INTERVAL_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define VFINT_ITR_1(_i)\t\t\t\t(0x00023008 + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: PFR */\n+#define VFINT_ITR_1_MAX_INDEX\t\t\t7\n+#define VFINT_ITR_1_INTERVAL_S\t\t\t0\n+#define VFINT_ITR_1_INTERVAL_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define VFINT_ITR_2(_i)\t\t\t\t(0x0002300C + ((_i) * 4096)) /* _i=0...7 */ /* Reset Source: PFR */\n+#define VFINT_ITR_2_MAX_INDEX\t\t\t7\n+#define VFINT_ITR_2_INTERVAL_S\t\t\t0\n+#define VFINT_ITR_2_INTERVAL_M\t\t\tMAKEMASK(0xFFF, 0)\n+#define VFQRX_TAIL(_QRX)\t\t\t(0x0002E000 + ((_QRX) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VFQRX_TAIL_MAX_INDEX\t\t\t255\n+#define VFQRX_TAIL_TAIL_S\t\t\t0\n+#define VFQRX_TAIL_TAIL_M\t\t\tMAKEMASK(0x1FFF, 0)\n+#define VFQTX_COMM_DBELL(_DBQM)\t\t\t(0x00030000 + ((_DBQM) * 4)) /* _i=0...255 */ /* Reset Source: CORER */\n+#define VFQTX_COMM_DBELL_MAX_INDEX\t\t255\n+#define VFQTX_COMM_DBELL_QTX_COMM_DBELL_S\t0\n+#define VFQTX_COMM_DBELL_QTX_COMM_DBELL_M\tMAKEMASK(0xFFFFFFFF, 0)\n+#define VFQTX_COMM_DBLQ_DBELL(_DBLQ)\t\t(0x00022000 + ((_DBLQ) * 4)) /* _i=0...3 */ /* Reset Source: CORER */\n+#define VFQTX_COMM_DBLQ_DBELL_MAX_INDEX\t\t3\n+#define VFQTX_COMM_DBLQ_DBELL_TAIL_S\t\t0\n+#define VFQTX_COMM_DBLQ_DBELL_TAIL_M\t\tMAKEMASK(0x1FFF, 0)\n+\n+#endif\ndiff --git a/drivers/net/ice/base/ice_impl_guide.c b/drivers/net/ice/base/ice_impl_guide.c\nnew file mode 100644\nindex 0000000..853cf52\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_impl_guide.c\n@@ -0,0 +1,167 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+/*! \\mainpage Intel FIXME Shared Code Implementation Guide\n+ *\n+ *\\section secA  Operating System Interface\n+ * The Shared Code is common code designed to coordinate, and\n+ * make common, the initialization and other hardware tasks.\n+ *\n+ * \\section sec2 Operating System Dependent Files\n+ * Each driver is required to implement one or two files, ice_osdep.c and\n+ * ice_osdep.h for the operating system dependent portions of the shared code.\n+ * The following are required in the osdep file(s) (in header file if\n+ * implemented as a macro/inline-function or in the C file if implemented as a\n+ * function with a prototype in the header file).\n+ *\n+ * \\section sec3 Data Types/structures\n+ * \\htmlonly <br>\n+ * __le16<br>\n+ * __le32<br>\n+ * __le64<br>\n+ * <br>\n+ * struct ice_dma_mem {<br>\n+ * &emsp;void *va;<br>\n+ * &emsp;&lt;os-specific physical address type&gt; pa;<br>\n+ * &emsp;&lt;os-specific size type&gt; size;<br>\n+ * &emsp;&lt;other OS-specific data...&gt;<br>\n+ * }<br>\n+ * <br>\n+ * struct ice_lock {<br>\n+ * &emsp;&lt;os specific lock type&gt; lock;<br>\n+ * }<br>\n+ * <br>\n+ * LIST_ENTRY_TYPE\t(list entry, e.g. list_head on Linux, _LIST_ENTRY on Windows)<br>\n+ * LIST_HEAD_TYPE\t(list head, e.g. list_head on Linux, _LIST_ENTRY on Windows)<br>\n+ * \\endhtmlonly\n+ *\n+ * \\section sec4 Functions/macros\n+ * \\htmlonly <br>\n+ * <bold>See ice_common.c:ice_init_hw() for some examples</bold><br>\n+ * <br>\n+ * STATIC<br>\n+ * CPU_TO_BE64(a)<br>\n+ * CPU_TO_BE32(a)<br>\n+ * CPU_TO_BE16(a)<br>\n+ * CPU_TO_LE64(a)<br>\n+ * CPU_TO_LE32(a)<br>\n+ * CPU_TO_LE16(a)<br>\n+ * LE64_TO_CPU(a)<br>\n+ * LE32_TO_CPU(a)<br>\n+ * LE16_TO_CPU(a)<br>\n+ * offsetof(_type, _field)<br>\n+ * FIELD_SIZEOF(_type, _field)<br>\n+ * ARRAY_SIZE(_array)<br>\n+ * NTOHL(a)<br>\n+ * NTOHS(a)<br>\n+ * HTONL(a)<br>\n+ * HTONS(a)<br>\n+ * SNPRINTF(buf, size, fmt, ...)<br>\n+ * <br>\n+ * u32 rd32(struct ice_hw *, reg_offset)<br>\n+ * void wr32(struct ice_hw *, reg_offset, u32 value)<br>\n+ * u64 rd64(struct ice_hw *, reg_offset)<br>\n+ * void wr64(struct ice_hw *, reg_offset, u64 value)<br>\n+ * <br>\n+ * void ice_flush(struct ice_hw *)<br>\n+ * <br>\n+ * void ice_debug(struct ice_hw *hw, u32 mask, char *format, ...)<br>\n+ * void ice_debug_array(struct ice_hw *hw, u32 mask, u32 rowsize, u32 groupsize, char *buf, size_t len)<br>\n+ * <br>\n+ * void ice_info(struct ice_hw *hw, char *format, ...)<br>\n+ * <br>\n+ * void ice_warn(struct ice_hw *hw, char *format, ...)<br>\n+ * Like ice_info but may log the message at a higher warning level<br>\n+ * <br>\n+ * Delay functions - bool sleep indicates sleep (true) or busy-wait (false)<br>\n+ * void ice_usec_delay(unsigned long usecs, bool sleep)<br>\n+ * void ice_msec_delay(unsigned long msecs, bool sleep)<br>\n+ * <br>\n+ * void *ice_memset(void *addr, int c, size_t n, ice_memset_type direction)<br>\n+ * void *ice_memcpy(void *d, const void *s, size_t n, ice_memcpy_type dir)<br>\n+ * void *ice_memdup(struct ice_hw *hw, const void *s, size_t n, ice_memcpy_type dir)<br>\n+ * <br>\n+ * Memory allocation functions - expected to provide zero'ed memory<br>\n+ * void *ice_alloc_dma_mem(struct ice_hw *hw, struct ice_dma_mem *m, u64 size)<br>\n+ * void *ice_malloc(struct ice_hw *hw, size)<br>\n+ * void *ice_calloc(struct ice_hw *hw, cnt, size)<br>\n+ * <br>\n+ * void ice_free_dma_mem(struct ice_hw *hw, struct ice_dma_mem *m)<br>\n+ * void ice_free(struct ice_hw *, void *) - should not fail if void pointer is NULL<br>\n+ * <br>\n+ * void ice_init_lock(struct ice_lock *lock);<br>\n+ * void ice_acquire_lock(struct ice_lock *lock);<br>\n+ * void ice_release_lock(struct ice_lock *lock);<br>\n+ * void ice_destroy_lock(struct ice_lock *lock);<br>\n+ * <br>\n+ * void ice_declare_bitmap(name, u16 size);<br>\n+ * void ice_set_bit(unsigned int bit, unsigned long *name);<br>\n+ * <br>\n+ * u8 ice_hweight8(u8 weight) - determine hamming weight of an 8-bit value<br>\n+ * <br>\n+ * <bold>doubly-linked list management macros:</bold><br>\n+ * INIT_LIST_HEAD(struct LIST_HEAD_TYPE *head)<br>\n+ * LIST_EMPTY(const struct LIST_HEAD_TYPE *head)<br>\n+ * LIST_ADD(struct LIST_ENTRY_TYPE *entry, struct LIST_HEAD_TYPE *head)<br>\n+ * LIST_ADD_AFTER(struct LIST_ENTRY_TYPE *entry, struct LIST_ENTRY_TYPE *elem)<br>\n+ * LIST_FIRST_ENTRY(struct LIST_HEAD_TYPE *head, &lt;name of struct&gt;, &lt;name of LIST_ENTRY_TYPE member in struct&gt;)<br>\n+ * LIST_DEL(struct LIST_ENTRY_TYPE *entry)<br>\n+ * LIST_FOR_EACH_ENTRY(&lt;&amp;struct used as iterator&gt;, struct LIST_HEAD_TYPE *head, &lt;name of struct&gt;, &lt;name of LIST_ENTRY_TYPE member in struct&gt;)<br>\n+ * Note: it is not safe to remove list entries in a LIST_FOR_EACH_ENTRY() loop<br>\n+ * LIST_FOR_EACH_ENTRY_SAFE(&lt;&amp;struct used as iterator&gt;, &lt;&amp;struct used as iterator&gt;struct LIST_ENTRY_TYPE *entry;, struct LIST_HEAD_TYPE *head, &lt;name of struct&gt;, &lt;name of LIST_ENTRY_TYPE member in struct&gt;)<br>\n+ * LIST_REPLACE_INIT(struct LIST_HEAD_TYPE *old_head, struct LIST_HEAD_TYPE *new_head)<br>\n+ *\n+ * \\section sec5 List implementation details\n+ * The LIST macros are defined to implement a doubly-linked list which embeds\n+ * the LIST_ENTRY structures as elements of the items linked to the list. The\n+ * macros assume that pointer arithmetic can be used to extract the container\n+ * structure from the LIST_ENTRY element and the structure type.\n+ * <br>\n+ * INIT_LIST_HEAD is expected to be able to initialize a pointer to a new\n+ * list.\n+ * <br>\n+ * LIST_EMPTY is called to determine if a list pointed to by a given list head\n+ * contains any elements. Calling LIST_EMPTY on an uninitialized list head\n+ * results in undefined implementation specific behavior.\n+ * <br>\n+ * LIST_ADD is called to add an element to the front of a list pointed to by\n+ * a given list head. It is assumed that LIST_ADD will perform any required\n+ * initialization for the LIST_ENTRY_TYPE structure.\n+ * <br>\n+ * LIST_ADD_AFTER is called to insert a new element into the list after the\n+ * given element. It is assumed that LIST_ADD_AFTER will perform any required\n+ * initialization for the LIST_ENTRY_TYPE structure.\n+ * <br>\n+ * LIST_FIRST_ENTRY is called to obtain a pointer to the structure containing\n+ * the first LIST_ENTRY_TYPE element of a list pointed to by the given list\n+ * head. Calling LIST_FIRST_ENTRY with an empty or uninitialized list results\n+ * in undefined implementation specific behavior.\n+ * <br>\n+ * LIST_NEXT_ENTRY is called to obtain a pointer to the structure containing\n+ * the next LIST_ENTRY_TYPE element in the list, given a pointer to the current\n+ * structure.\n+ * <br>\n+ * LIST_DEL is called to remove an element from its associated list.\n+ * <br>\n+ * LIST_FOR_EACH_ENTRY is used to loop through every element of a list, using\n+ * a pointer of the containing type as an iterator. It is expected to have\n+ * semantics similar to for loops, and can take either a single or block\n+ * statement following it. Calling LIST_DEL on the iterator is not safe and\n+ * results in undefined implementation specific behavior. If deleting elements\n+ * from the list while iterating is required, use LIST_FOR_EACH_ENTRY_SAFE\n+ * instead.\n+ * <br>\n+ * LIST_FOR_EACH_ENTRY_SAFE is used to loop through every element of a list\n+ * guaranteeing safety to delete the iterator element even during the\n+ * iteration. It requires two temporary pointers both of the struct type used\n+ * as the iterator. If the ability to remove the iterated element from the\n+ * list is required, then LIST_FOR_EACH_ENTRY_SAFE must be used instead of\n+ * LIST_FOR_EACH_ENTRY.\n+ * <br>\n+ * LIST_REPLACE_INIT is used to replace old head by a new head. This will also\n+ * reinitialize the old head to make it a empty list head. The new list does\n+ * not have to be initialized for this function.\n+ * <br>\n+ * \\endhtmlonly\n+ */\ndiff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h\nnew file mode 100644\nindex 0000000..30671a5\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_lan_tx_rx.h\n@@ -0,0 +1,2290 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_LAN_TX_RX_H_\n+#define _ICE_LAN_TX_RX_H_\n+#include \"ice_osdep.h\"\n+\n+/* RX Descriptors */\n+union ice_16byte_rx_desc {\n+\tstruct {\n+\t\t__le64 pkt_addr; /* Packet buffer address */\n+\t\t__le64 hdr_addr; /* Header buffer address */\n+\t} read;\n+\tstruct {\n+\t\tstruct {\n+\t\t\tstruct {\n+\t\t\t\t__le16 mirroring_status;\n+\t\t\t\t__le16 l2tag1;\n+\t\t\t} lo_dword;\n+\t\t\tunion {\n+\t\t\t\t__le32 rss; /* RSS Hash */\n+\t\t\t\t__le32 fd_id; /* Flow Director filter id */\n+\t\t\t} hi_dword;\n+\t\t} qword0;\n+\t\tstruct {\n+\t\t\t/* ext status/error/PTYPE/length */\n+\t\t\t__le64 status_error_len;\n+\t\t} qword1;\n+\t} wb;  /* writeback */\n+};\n+\n+union ice_32byte_rx_desc {\n+\tstruct {\n+\t\t__le64 pkt_addr; /* Packet buffer address */\n+\t\t__le64 hdr_addr; /* Header buffer address */\n+\t\t\t/* bit 0 of hdr_addr is DD bit */\n+\t\t__le64 rsvd1;\n+\t\t__le64 rsvd2;\n+\t} read;\n+\tstruct {\n+\t\tstruct {\n+\t\t\tstruct {\n+\t\t\t\t__le16 mirroring_status;\n+\t\t\t\t__le16 l2tag1;\n+\t\t\t} lo_dword;\n+\t\t\tunion {\n+\t\t\t\t__le32 rss; /* RSS Hash */\n+\t\t\t\t__le32 fd_id; /* Flow Director filter id */\n+\t\t\t} hi_dword;\n+\t\t} qword0;\n+\t\tstruct {\n+\t\t\t/* status/error/PTYPE/length */\n+\t\t\t__le64 status_error_len;\n+\t\t} qword1;\n+\t\tstruct {\n+\t\t\t__le16 ext_status; /* extended status */\n+\t\t\t__le16 rsvd;\n+\t\t\t__le16 l2tag2_1;\n+\t\t\t__le16 l2tag2_2;\n+\t\t} qword2;\n+\t\tstruct {\n+\t\t\t__le32 reserved;\n+\t\t\t__le32 fd_id;\n+\t\t} qword3;\n+\t} wb; /* writeback */\n+};\n+\n+struct ice_fltr_desc {\n+\t__le64 qidx_compq_space_stat;\n+\t__le64 dtype_cmd_vsi_fdid;\n+};\n+\n+#define ICE_FXD_FLTR_QW0_QINDEX_S\t0\n+#define ICE_FXD_FLTR_QW0_QINDEX_M\t(0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S)\n+#define ICE_FXD_FLTR_QW0_COMP_Q_S\t11\n+#define ICE_FXD_FLTR_QW0_COMP_Q_M\tBIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S)\n+#define ICE_FXD_FLTR_QW0_COMP_Q_ZERO\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_COMP_Q_QINDX\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_S\t12\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_M\t\\\n+\t\t\t\t(0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S)\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_NONE\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL\t0x1ULL\n+#define ICE_FXD_FLTR_QW0_COMP_REPORT_SW\t\t0x2ULL\n+\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_S\t14\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_M\t(0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S)\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR\t\t\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_BEST_EFFORT\t\t0x1ULL\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST\t\t0x2ULL\n+#define ICE_FXD_FLTR_QW0_FD_SPACE_BEST_GUAR\t\t0x3ULL\n+\n+#define ICE_FXD_FLTR_QW0_STAT_CNT_S\t16\n+#define ICE_FXD_FLTR_QW0_STAT_CNT_M\t\\\n+\t\t\t\t(0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S)\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_S\t29\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_M\t(0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S)\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_NONE\t\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS\t\t0x1ULL\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_BYTES\t\t0x2ULL\n+#define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS_BYTES\t0x3ULL\n+\n+#define ICE_FXD_FLTR_QW0_EVICT_ENA_S\t31\n+#define ICE_FXD_FLTR_QW0_EVICT_ENA_M\tBIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S)\n+#define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE\t\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW0_TO_Q_S\t\t32\n+#define ICE_FXD_FLTR_QW0_TO_Q_M\t\t(0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S)\n+#define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW0_TO_Q_PRI_S\t35\n+#define ICE_FXD_FLTR_QW0_TO_Q_PRI_M\t(0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S)\n+#define ICE_FXD_FLTR_QW0_TO_Q_PRIO1\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW0_DPU_RECIPE_S\t38\n+#define ICE_FXD_FLTR_QW0_DPU_RECIPE_M\t\\\n+\t\t\t(0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S)\n+#define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW0_DROP_S\t\t40\n+#define ICE_FXD_FLTR_QW0_DROP_M\t\tBIT_ULL(ICE_FXD_FLTR_QW0_DROP_S)\n+#define ICE_FXD_FLTR_QW0_DROP_NO\t0x0ULL\n+#define ICE_FXD_FLTR_QW0_DROP_YES\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW0_FLEX_PRI_S\t41\n+#define ICE_FXD_FLTR_QW0_FLEX_PRI_M\t(0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S)\n+#define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW0_FLEX_MDID_S\t44\n+#define ICE_FXD_FLTR_QW0_FLEX_MDID_M\t(0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S)\n+#define ICE_FXD_FLTR_QW0_FLEX_MDID0\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW0_FLEX_VAL_S\t48\n+#define ICE_FXD_FLTR_QW0_FLEX_VAL_M\t\\\n+\t\t\t\t(0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S)\n+#define ICE_FXD_FLTR_QW0_FLEX_VAL0\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW1_DTYPE_S\t0\n+#define ICE_FXD_FLTR_QW1_DTYPE_M\t(0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S)\n+#define ICE_FXD_FLTR_QW1_PCMD_S\t\t4\n+#define ICE_FXD_FLTR_QW1_PCMD_M\t\tBIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S)\n+#define ICE_FXD_FLTR_QW1_PCMD_ADD\t0x0ULL\n+#define ICE_FXD_FLTR_QW1_PCMD_REMOVE\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW1_PROF_PRI_S\t5\n+#define ICE_FXD_FLTR_QW1_PROF_PRI_M\t(0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S)\n+#define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW1_PROF_S\t\t8\n+#define ICE_FXD_FLTR_QW1_PROF_M\t\t(0x3FULL << ICE_FXD_FLTR_QW1_PROF_S)\n+#define ICE_FXD_FLTR_QW1_PROF_ZERO\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW1_FD_VSI_S\t14\n+#define ICE_FXD_FLTR_QW1_FD_VSI_M\t(0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S)\n+#define ICE_FXD_FLTR_QW1_SWAP_S\t\t24\n+#define ICE_FXD_FLTR_QW1_SWAP_M\t\tBIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S)\n+#define ICE_FXD_FLTR_QW1_SWAP_NOT_SET\t0x0ULL\n+#define ICE_FXD_FLTR_QW1_SWAP_SET\t0x1ULL\n+\n+#define ICE_FXD_FLTR_QW1_FDID_PRI_S\t25\n+#define ICE_FXD_FLTR_QW1_FDID_PRI_M\t(0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)\n+#define ICE_FXD_FLTR_QW1_FDID_PRI_ZERO\t0x0ULL\n+\n+#define ICE_FXD_FLTR_QW1_FDID_MDID_S\t28\n+#define ICE_FXD_FLTR_QW1_FDID_MDID_M\t(0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)\n+#define ICE_FXD_FLTR_QW1_FDID_MDID_FD\t0x05ULL\n+\n+#define ICE_FXD_FLTR_QW1_FDID_S\t\t32\n+#define ICE_FXD_FLTR_QW1_FDID_M\t\t\\\n+\t\t\t(0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)\n+#define ICE_FXD_FLTR_QW1_FDID_ZERO\t0x0ULL\n+\n+\n+enum ice_rx_desc_status_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_DESC_STATUS_DD_S\t\t\t= 0,\n+\tICE_RX_DESC_STATUS_EOF_S\t\t= 1,\n+\tICE_RX_DESC_STATUS_L2TAG1P_S\t\t= 2,\n+\tICE_RX_DESC_STATUS_L3L4P_S\t\t= 3,\n+\tICE_RX_DESC_STATUS_CRCP_S\t\t= 4,\n+\tICE_RX_DESC_STATUS_TSYNINDX_S\t\t= 5, /* 2 BITS */\n+\tICE_RX_DESC_STATUS_TSYNVALID_S\t\t= 7,\n+\tICE_RX_DESC_STATUS_EXT_UDP_0_S\t\t= 8,\n+\tICE_RX_DESC_STATUS_UMBCAST_S\t\t= 9, /* 2 BITS */\n+\tICE_RX_DESC_STATUS_FLM_S\t\t= 11,\n+\tICE_RX_DESC_STATUS_FLTSTAT_S\t\t= 12, /* 2 BITS */\n+\tICE_RX_DESC_STATUS_LPBK_S\t\t= 14,\n+\tICE_RX_DESC_STATUS_IPV6EXADD_S\t\t= 15,\n+\tICE_RX_DESC_STATUS_RESERVED2_S\t\t= 16, /* 2 BITS */\n+\tICE_RX_DESC_STATUS_INT_UDP_0_S\t\t= 18,\n+\tICE_RX_DESC_STATUS_LAST /* this entry must be last!!! */\n+};\n+\n+#define ICE_RXD_QW1_STATUS_S\t0\n+#define ICE_RXD_QW1_STATUS_M\t((BIT(ICE_RX_DESC_STATUS_LAST) - 1) << \\\n+\t\t\t\t ICE_RXD_QW1_STATUS_S)\n+\n+#define ICE_RXD_QW1_STATUS_TSYNINDX_S ICE_RX_DESC_STATUS_TSYNINDX_S\n+#define ICE_RXD_QW1_STATUS_TSYNINDX_M (0x3UL << ICE_RXD_QW1_STATUS_TSYNINDX_S)\n+\n+#define ICE_RXD_QW1_STATUS_TSYNVALID_S ICE_RX_DESC_STATUS_TSYNVALID_S\n+#define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S)\n+\n+\n+enum ice_rx_desc_fltstat_values {\n+\tICE_RX_DESC_FLTSTAT_NO_DATA\t= 0,\n+\tICE_RX_DESC_FLTSTAT_RSV_FD_ID\t= 1, /* 16byte desc? FD_ID : RSV */\n+\tICE_RX_DESC_FLTSTAT_RSV\t\t= 2,\n+\tICE_RX_DESC_FLTSTAT_RSS_HASH\t= 3,\n+};\n+\n+\n+#define ICE_RXD_QW1_ERROR_S\t19\n+#define ICE_RXD_QW1_ERROR_M\t\t(0xFFUL << ICE_RXD_QW1_ERROR_S)\n+\n+enum ice_rx_desc_error_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_DESC_ERROR_RXE_S\t\t\t= 0,\n+\tICE_RX_DESC_ERROR_RECIPE_S\t\t= 1,\n+\tICE_RX_DESC_ERROR_HBO_S\t\t\t= 2,\n+\tICE_RX_DESC_ERROR_L3L4E_S\t\t= 3, /* 3 BITS */\n+\tICE_RX_DESC_ERROR_IPE_S\t\t\t= 3,\n+\tICE_RX_DESC_ERROR_L4E_S\t\t\t= 4,\n+\tICE_RX_DESC_ERROR_EIPE_S\t\t= 5,\n+\tICE_RX_DESC_ERROR_OVERSIZE_S\t\t= 6,\n+\tICE_RX_DESC_ERROR_PPRS_S\t\t= 7\n+};\n+\n+enum ice_rx_desc_error_l3l4e_masks {\n+\tICE_RX_DESC_ERROR_L3L4E_NONE\t\t= 0,\n+\tICE_RX_DESC_ERROR_L3L4E_PROT\t\t= 1,\n+};\n+\n+#define ICE_RXD_QW1_PTYPE_S\t30\n+#define ICE_RXD_QW1_PTYPE_M\t(0xFFULL << ICE_RXD_QW1_PTYPE_S)\n+\n+/* Packet type non-ip values */\n+enum ice_rx_l2_ptype {\n+\tICE_RX_PTYPE_L2_RESERVED\t= 0,\n+\tICE_RX_PTYPE_L2_MAC_PAY2\t= 1,\n+\tICE_RX_PTYPE_L2_FIP_PAY2\t= 3,\n+\tICE_RX_PTYPE_L2_OUI_PAY2\t= 4,\n+\tICE_RX_PTYPE_L2_MACCNTRL_PAY2\t= 5,\n+\tICE_RX_PTYPE_L2_LLDP_PAY2\t= 6,\n+\tICE_RX_PTYPE_L2_ECP_PAY2\t= 7,\n+\tICE_RX_PTYPE_L2_EVB_PAY2\t= 8,\n+\tICE_RX_PTYPE_L2_QCN_PAY2\t= 9,\n+\tICE_RX_PTYPE_L2_EAPOL_PAY2\t= 10,\n+\tICE_RX_PTYPE_L2_ARP\t\t= 11,\n+};\n+\n+struct ice_rx_ptype_decoded {\n+\tu32 ptype:10;\n+\tu32 known:1;\n+\tu32 outer_ip:1;\n+\tu32 outer_ip_ver:2;\n+\tu32 outer_frag:1;\n+\tu32 tunnel_type:3;\n+\tu32 tunnel_end_prot:2;\n+\tu32 tunnel_end_frag:1;\n+\tu32 inner_prot:4;\n+\tu32 payload_layer:3;\n+};\n+\n+enum ice_rx_ptype_outer_ip {\n+\tICE_RX_PTYPE_OUTER_L2\t= 0,\n+\tICE_RX_PTYPE_OUTER_IP\t= 1,\n+};\n+\n+enum ice_rx_ptype_outer_ip_ver {\n+\tICE_RX_PTYPE_OUTER_NONE\t= 0,\n+\tICE_RX_PTYPE_OUTER_IPV4\t= 1,\n+\tICE_RX_PTYPE_OUTER_IPV6\t= 2,\n+};\n+\n+enum ice_rx_ptype_outer_fragmented {\n+\tICE_RX_PTYPE_NOT_FRAG\t= 0,\n+\tICE_RX_PTYPE_FRAG\t= 1,\n+};\n+\n+enum ice_rx_ptype_tunnel_type {\n+\tICE_RX_PTYPE_TUNNEL_NONE\t\t= 0,\n+\tICE_RX_PTYPE_TUNNEL_IP_IP\t\t= 1,\n+\tICE_RX_PTYPE_TUNNEL_IP_GRENAT\t\t= 2,\n+\tICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC\t= 3,\n+\tICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN\t= 4,\n+};\n+\n+enum ice_rx_ptype_tunnel_end_prot {\n+\tICE_RX_PTYPE_TUNNEL_END_NONE\t= 0,\n+\tICE_RX_PTYPE_TUNNEL_END_IPV4\t= 1,\n+\tICE_RX_PTYPE_TUNNEL_END_IPV6\t= 2,\n+};\n+\n+enum ice_rx_ptype_inner_prot {\n+\tICE_RX_PTYPE_INNER_PROT_NONE\t\t= 0,\n+\tICE_RX_PTYPE_INNER_PROT_UDP\t\t= 1,\n+\tICE_RX_PTYPE_INNER_PROT_TCP\t\t= 2,\n+\tICE_RX_PTYPE_INNER_PROT_SCTP\t\t= 3,\n+\tICE_RX_PTYPE_INNER_PROT_ICMP\t\t= 4,\n+};\n+\n+enum ice_rx_ptype_payload_layer {\n+\tICE_RX_PTYPE_PAYLOAD_LAYER_NONE\t= 0,\n+\tICE_RX_PTYPE_PAYLOAD_LAYER_PAY2\t= 1,\n+\tICE_RX_PTYPE_PAYLOAD_LAYER_PAY3\t= 2,\n+\tICE_RX_PTYPE_PAYLOAD_LAYER_PAY4\t= 3,\n+};\n+\n+\n+#define ICE_RXD_QW1_LEN_PBUF_S\t38\n+#define ICE_RXD_QW1_LEN_PBUF_M\t(0x3FFFULL << ICE_RXD_QW1_LEN_PBUF_S)\n+\n+#define ICE_RXD_QW1_LEN_HBUF_S\t52\n+#define ICE_RXD_QW1_LEN_HBUF_M\t(0x7FFULL << ICE_RXD_QW1_LEN_HBUF_S)\n+\n+#define ICE_RXD_QW1_LEN_SPH_S\t63\n+#define ICE_RXD_QW1_LEN_SPH_M\tBIT_ULL(ICE_RXD_QW1_LEN_SPH_S)\n+\n+\n+enum ice_rx_desc_ext_status_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_DESC_EXT_STATUS_L2TAG2P_S\t= 0,\n+\tICE_RX_DESC_EXT_STATUS_L2TAG3P_S\t= 1,\n+\tICE_RX_DESC_EXT_STATUS_FLEXBL_S\t\t= 2, /* 2 BITS */\n+\tICE_RX_DESC_EXT_STATUS_FLEXBH_S\t\t= 4, /* 2 BITS */\n+\tICE_RX_DESC_EXT_STATUS_FDLONGB_S\t= 9,\n+\tICE_RX_DESC_EXT_STATUS_PELONGB_S\t= 11,\n+};\n+\n+\n+enum ice_rx_desc_pe_status_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_DESC_PE_STATUS_QPID_S\t\t= 0, /* 18 BITS */\n+\tICE_RX_DESC_PE_STATUS_L4PORT_S\t\t= 0, /* 16 BITS */\n+\tICE_RX_DESC_PE_STATUS_IPINDEX_S\t\t= 16, /* 8 BITS */\n+\tICE_RX_DESC_PE_STATUS_QPIDHIT_S\t\t= 24,\n+\tICE_RX_DESC_PE_STATUS_APBVTHIT_S\t= 25,\n+\tICE_RX_DESC_PE_STATUS_PORTV_S\t\t= 26,\n+\tICE_RX_DESC_PE_STATUS_URG_S\t\t= 27,\n+\tICE_RX_DESC_PE_STATUS_IPFRAG_S\t\t= 28,\n+\tICE_RX_DESC_PE_STATUS_IPOPT_S\t\t= 29\n+};\n+\n+#define ICE_RX_PROG_STATUS_DESC_LEN_S\t38\n+#define ICE_RX_PROG_STATUS_DESC_LEN\t0x2000000\n+\n+#define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S\t2\n+#define ICE_RX_PROG_STATUS_DESC_QW1_PROGID_M\t\\\n+\t\t\t(0x7UL << ICE_RX_PROG_STATUS_DESC_QW1_PROGID_S)\n+\n+\n+#define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S\t19\n+#define ICE_RX_PROG_STATUS_DESC_QW1_ERROR_M\t\\\n+\t\t\t(0x3FUL << ICE_RX_PROG_STATUS_DESC_QW1_ERROR_S)\n+\n+enum ice_rx_prog_status_desc_status_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_PROG_STATUS_DESC_DD_S\t\t= 0,\n+\tICE_RX_PROG_STATUS_DESC_PROG_ID_S\t= 2 /* 3 BITS */\n+};\n+\n+enum ice_rx_prog_status_desc_prog_id_masks {\n+\tICE_RX_PROG_STATUS_DESC_FD_FLTR_STATUS\t= 1,\n+};\n+\n+enum ice_rx_prog_status_desc_error_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_PROG_STATUS_DESC_FD_TBL_FULL_S\t= 0,\n+\tICE_RX_PROG_STATUS_DESC_NO_FD_ENTRY_S\t= 1,\n+};\n+\n+/* RX Flex Descriptor\n+ * This descriptor is used instead of the legacy version descriptor when\n+ * ice_rlan_ctx.adv_desc is set\n+ */\n+union ice_32b_rx_flex_desc {\n+\tstruct {\n+\t\t__le64 pkt_addr; /* Packet buffer address */\n+\t\t__le64 hdr_addr; /* Header buffer address */\n+\t\t\t\t /* bit 0 of hdr_addr is DD bit */\n+\t\t__le64 rsvd1;\n+\t\t__le64 rsvd2;\n+\t} read;\n+\tstruct {\n+\t\t/* Qword 0 */\n+\t\tu8 rxdid; /* descriptor builder profile id */\n+\t\tu8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */\n+\t\t__le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */\n+\t\t__le16 pkt_len; /* [15:14] are reserved */\n+\t\t__le16 hdr_len_sph_flex_flags1; /* header=[10:0] */\n+\t\t\t\t\t\t/* sph=[11:11] */\n+\t\t\t\t\t\t/* ff1/ext=[15:12] */\n+\n+\t\t/* Qword 1 */\n+\t\t__le16 status_error0;\n+\t\t__le16 l2tag1;\n+\t\t__le16 flex_meta0;\n+\t\t__le16 flex_meta1;\n+\n+\t\t/* Qword 2 */\n+\t\t__le16 status_error1;\n+\t\tu8 flex_flags2;\n+\t\tu8 time_stamp_low;\n+\t\t__le16 l2tag2_1st;\n+\t\t__le16 l2tag2_2nd;\n+\n+\t\t/* Qword 3 */\n+\t\t__le16 flex_meta2;\n+\t\t__le16 flex_meta3;\n+\t\tunion {\n+\t\t\tstruct {\n+\t\t\t\t__le16 flex_meta4;\n+\t\t\t\t__le16 flex_meta5;\n+\t\t\t} flex;\n+\t\t\t__le32 ts_high;\n+\t\t} flex_ts;\n+\t} wb; /* writeback */\n+};\n+\n+/* Rx Flex Descriptor NIC Profile\n+ * RxDID Profile Id 2\n+ * Flex-field 0: RSS hash lower 16-bits\n+ * Flex-field 1: RSS hash upper 16-bits\n+ * Flex-field 2: Flow Id lower 16-bits\n+ * Flex-field 3: Flow Id higher 16-bits\n+ * Flex-field 4: reserved, Vlan id taken from L2Tag\n+ */\n+struct ice_32b_rx_flex_desc_nic {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le32 rss_hash;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flexi_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le32 flow_id;\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le16 rsvd;\n+\t\t\t__le16 flow_id_ipv6;\n+\t\t} flex;\n+\t\t__le32 ts_high;\n+\t} flex_ts;\n+};\n+\n+/* Rx Flex Descriptor Switch Profile\n+ * RxDID Profile Id 3\n+ * Flex-field 0: Source Vsi\n+ */\n+struct ice_32b_rx_flex_desc_sw {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le16 src_vsi; /* [10:15] are reserved */\n+\t__le16 flex_md1_rsvd;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flex_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le32 rsvd; /* flex words 2-3 are reserved */\n+\t__le32 ts_high;\n+};\n+\n+/* Rx Flex Descriptor NIC VEB Profile\n+ * RxDID Profile Id 4\n+ * Flex-field 0: Destination Vsi\n+ */\n+struct ice_32b_rx_flex_desc_nic_veb_dbg {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le16 dst_vsi; /* [0:12]: destination vsi */\n+\t\t\t/* 13: vsi valid bit */\n+\t\t\t/* [14:15] are reserved */\n+\t__le16 flex_field_1;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flex_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le32 rsvd; /* flex words 2-3 are reserved */\n+\t__le32 ts_high;\n+};\n+\n+/* Rx Flex Descriptor NIC ACL Profile\n+ * RxDID Profile Id 5\n+ * Flex-field 0: ACL Counter 0\n+ * Flex-field 1: ACL Counter 1\n+ * Flex-field 2: ACL Counter 2\n+ */\n+struct ice_32b_rx_flex_desc_nic_acl_dbg {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le16 acl_ctr0;\n+\t__le16 acl_ctr1;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flex_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le16 acl_ctr2;\n+\t__le16 rsvd; /* flex words 2-3 are reserved */\n+\t__le32 ts_high;\n+};\n+\n+/* Rx Flex Descriptor NIC Profile\n+ * RxDID Profile Id 6\n+ * Flex-field 0: RSS hash lower 16-bits\n+ * Flex-field 1: RSS hash upper 16-bits\n+ * Flex-field 2: Flow Id lower 16-bits\n+ * Flex-field 3: Source Vsi\n+ * Flex-field 4: reserved, Vlan id taken from L2Tag\n+ */\n+struct ice_32b_rx_flex_desc_nic_2 {\n+\t/* Qword 0 */\n+\tu8 rxdid;\n+\tu8 mir_id_umb_cast;\n+\t__le16 ptype_flexi_flags0;\n+\t__le16 pkt_len;\n+\t__le16 hdr_len_sph_flex_flags1;\n+\n+\t/* Qword 1 */\n+\t__le16 status_error0;\n+\t__le16 l2tag1;\n+\t__le32 rss_hash;\n+\n+\t/* Qword 2 */\n+\t__le16 status_error1;\n+\tu8 flexi_flags2;\n+\tu8 ts_low;\n+\t__le16 l2tag2_1st;\n+\t__le16 l2tag2_2nd;\n+\n+\t/* Qword 3 */\n+\t__le16 flow_id;\n+\t__le16 src_vsi;\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le16 rsvd;\n+\t\t\t__le16 flow_id_ipv6;\n+\t\t} flex;\n+\t\t__le32 ts_high;\n+\t} flex_ts;\n+};\n+\n+/* Receive Flex Descriptor profile IDs: There are a total\n+ * of 64 profiles where profile IDs 0/1 are for legacy; and\n+ * profiles 2-63 are flex profiles that can be programmed\n+ * with a specific metadata (profile 7 reserved for HW)\n+ */\n+enum ice_rxdid {\n+\tICE_RXDID_LEGACY_0\t\t= 0,\n+\tICE_RXDID_LEGACY_1\t\t= 1,\n+\tICE_RXDID_FLEX_NIC\t\t= 2,\n+\tICE_RXDID_FLEX_NIC_2\t\t= 6,\n+\tICE_RXDID_HW\t\t\t= 7,\n+\tICE_RXDID_LAST\t\t\t= 63,\n+};\n+\n+/* Recceive Flex descriptor Dword Index */\n+enum ice_flex_word {\n+\tICE_RX_FLEX_DWORD_0 = 0,\n+\tICE_RX_FLEX_DWORD_1,\n+\tICE_RX_FLEX_DWORD_2,\n+\tICE_RX_FLEX_DWORD_3,\n+\tICE_RX_FLEX_DWORD_4,\n+\tICE_RX_FLEX_DWORD_5\n+};\n+\n+/* Receive Flex Descriptor Rx opcode values */\n+enum ice_flex_opcode {\n+\tICE_RX_OPC_DEBUG = 0,\n+\tICE_RX_OPC_MDID,\n+\tICE_RX_OPC_EXTRACT,\n+\tICE_RX_OPC_PROTID\n+};\n+\n+/* Receive Descriptor MDID values */\n+enum ice_flex_rx_mdid {\n+\tICE_RX_MDID_FLOW_ID_LOWER\t= 5,\n+\tICE_RX_MDID_FLOW_ID_HIGH,\n+\tICE_RX_MDID_DST_VSI\t\t= 13,\n+\tICE_RX_MDID_SRC_VSI\t\t= 19,\n+\tICE_RX_MDID_HASH_LOW\t\t= 56,\n+\tICE_RX_MDID_HASH_HIGH,\n+\tICE_RX_MDID_ACL_CTR0\t\t= ICE_RX_MDID_HASH_LOW,\n+\tICE_RX_MDID_ACL_CTR1\t\t= ICE_RX_MDID_HASH_HIGH,\n+\tICE_RX_MDID_ACL_CTR2\t\t= 59\n+};\n+\n+/* for ice_32byte_rx_flex_desc.mir_id_umb_cast member */\n+#define ICE_RX_FLEX_DESC_MIRROR_M\t(0x3F) /* 6-bits */\n+\n+/* Rx Flag64 packet flag bits */\n+enum ice_rx_flg64_bits {\n+\tICE_RXFLG_PKT_DSI\t= 0,\n+\tICE_RXFLG_EVLAN_x8100\t= 15,\n+\tICE_RXFLG_EVLAN_x9100,\n+\tICE_RXFLG_VLAN_x8100,\n+\tICE_RXFLG_TNL_MAC\t= 22,\n+\tICE_RXFLG_TNL_VLAN,\n+\tICE_RXFLG_PKT_FRG,\n+\tICE_RXFLG_FIN\t\t= 32,\n+\tICE_RXFLG_SYN,\n+\tICE_RXFLG_RST,\n+\tICE_RXFLG_TNL0\t\t= 38,\n+\tICE_RXFLG_TNL1,\n+\tICE_RXFLG_TNL2,\n+\tICE_RXFLG_UDP_GRE,\n+\tICE_RXFLG_RSVD\t\t= 63\n+};\n+\n+enum ice_rx_flex_desc_umb_cast_bits { /* field is 2 bits long */\n+\tICE_RX_FLEX_DESC_UMB_CAST_S = 6,\n+\tICE_RX_FLEX_DESC_UMB_CAST_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_umbcast_dest_addr_types {\n+\tICE_DEST_UNICAST = 0,\n+\tICE_DEST_MULTICAST,\n+\tICE_DEST_BROADCAST,\n+\tICE_DEST_MIRRORED,\n+};\n+\n+/* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */\n+#define ICE_RX_FLEX_DESC_PTYPE_M\t(0x3FF) /* 10-bits */\n+\n+enum ice_rx_flex_desc_flexi_flags0_bits { /* field is 6 bits long */\n+\tICE_RX_FLEX_DESC_FLEXI_FLAGS0_S = 10,\n+\tICE_RX_FLEX_DESC_FLEXI_FLAGS0_LAST /* this entry must be last!!! */\n+};\n+\n+/* for ice_32byte_rx_flex_desc.pkt_length member */\n+#define ICE_RX_FLX_DESC_PKT_LEN_M\t(0x3FFF) /* 14-bits */\n+\n+/* for ice_32byte_rx_flex_desc.header_length_sph_flexi_flags1 member */\n+#define ICE_RX_FLEX_DESC_HEADER_LEN_M\t(0x7FF) /* 11-bits */\n+\n+enum ice_rx_flex_desc_sph_bits { /* field is 1 bit long */\n+\tICE_RX_FLEX_DESC_SPH_S = 11,\n+\tICE_RX_FLEX_DESC_SPH_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_flexi_flags1_bits { /* field is 4 bits long */\n+\tICE_RX_FLEX_DESC_FLEXI_FLAGS1_S = 12,\n+\tICE_RX_FLEX_DESC_FLEXI_FLAGS1_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_ext_status_bits { /* field is 4 bits long */\n+\tICE_RX_FLEX_DESC_EXT_STATUS_EXT_UDP_S = 12,\n+\tICE_RX_FLEX_DESC_EXT_STATUS_INT_UDP_S = 13,\n+\tICE_RX_FLEX_DESC_EXT_STATUS_RECIPE_S = 14,\n+\tICE_RX_FLEX_DESC_EXT_STATUS_OVERSIZE_S = 15,\n+\tICE_RX_FLEX_DESC_EXT_STATUS_LAST /* entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_status_error_0_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_FLEX_DESC_STATUS0_DD_S = 0,\n+\tICE_RX_FLEX_DESC_STATUS0_EOF_S,\n+\tICE_RX_FLEX_DESC_STATUS0_HBO_S,\n+\tICE_RX_FLEX_DESC_STATUS0_L3L4P_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,\n+\tICE_RX_FLEX_DESC_STATUS0_LPBK_S,\n+\tICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,\n+\tICE_RX_FLEX_DESC_STATUS0_RXE_S,\n+\tICE_RX_FLEX_DESC_STATUS0_CRCP_S,\n+\tICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S,\n+\tICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,\n+\tICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,\n+\tICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_status_error_1_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_FLEX_DESC_STATUS1_CPM_S = 0, /* 4 bits */\n+\tICE_RX_FLEX_DESC_STATUS1_NAT_S = 4,\n+\tICE_RX_FLEX_DESC_STATUS1_CRYPTO_S = 5,\n+\t/* [10:6] reserved */\n+\tICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,\n+\tICE_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12,\n+\tICE_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13,\n+\tICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14,\n+\tICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15,\n+\tICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */\n+};\n+\n+enum ice_rx_flex_desc_exstat_bits {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_RX_FLEX_DESC_EXSTAT_EXTUDP_S = 0,\n+\tICE_RX_FLEX_DESC_EXSTAT_INTUDP_S = 1,\n+\tICE_RX_FLEX_DESC_EXSTAT_RECIPE_S = 2,\n+\tICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,\n+};\n+\n+\n+#define ICE_RXQ_CTX_SIZE_DWORDS\t\t8\n+#define ICE_RXQ_CTX_SZ\t\t\t(ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))\n+#define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS\t22\n+#define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS\t5\n+#define GLTCLAN_CQ_CNTX(i, CQ)\t\t(GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))\n+\n+/* RLAN Rx queue context data\n+ *\n+ * The sizes of the variables may be larger than needed due to crossing byte\n+ * boundaries. If we do not have the width of the variable set to the correct\n+ * size then we could end up shifting bits off the top of the variable when the\n+ * variable is at the top of a byte and crosses over into the next byte.\n+ */\n+struct ice_rlan_ctx {\n+\tu16 head;\n+\tu16 cpuid; /* bigger than needed, see above for reason */\n+#define ICE_RLAN_BASE_S 7\n+\tu64 base;\n+\tu16 qlen;\n+#define ICE_RLAN_CTX_DBUF_S 7\n+\tu16 dbuf; /* bigger than needed, see above for reason */\n+#define ICE_RLAN_CTX_HBUF_S 6\n+\tu16 hbuf; /* bigger than needed, see above for reason */\n+\tu8 dtype;\n+\tu8 dsize;\n+\tu8 crcstrip;\n+\tu8 l2tsel;\n+\tu8 hsplit_0;\n+\tu8 hsplit_1;\n+\tu8 showiv;\n+\tu32 rxmax; /* bigger than needed, see above for reason */\n+\tu8 tphrdesc_ena;\n+\tu8 tphwdesc_ena;\n+\tu8 tphdata_ena;\n+\tu8 tphhead_ena;\n+\tu16 lrxqthresh; /* bigger than needed, see above for reason */\n+};\n+\n+struct ice_ctx_ele {\n+\tu16 offset;\n+\tu16 size_of;\n+\tu16 width;\n+\tu16 lsb;\n+};\n+\n+#define ICE_CTX_STORE(_struct, _ele, _width, _lsb) {\t\\\n+\t.offset = offsetof(struct _struct, _ele),\t\\\n+\t.size_of = FIELD_SIZEOF(struct _struct, _ele),\t\\\n+\t.width = _width,\t\t\t\t\\\n+\t.lsb = _lsb,\t\t\t\t\t\\\n+}\n+\n+/* for hsplit_0 field of Rx RLAN context */\n+enum ice_rlan_ctx_rx_hsplit_0 {\n+\tICE_RLAN_RX_HSPLIT_0_NO_SPLIT\t\t= 0,\n+\tICE_RLAN_RX_HSPLIT_0_SPLIT_L2\t\t= 1,\n+\tICE_RLAN_RX_HSPLIT_0_SPLIT_IP\t\t= 2,\n+\tICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP\t= 4,\n+\tICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP\t\t= 8,\n+};\n+\n+/* for hsplit_1 field of Rx RLAN context */\n+enum ice_rlan_ctx_rx_hsplit_1 {\n+\tICE_RLAN_RX_HSPLIT_1_NO_SPLIT\t\t= 0,\n+\tICE_RLAN_RX_HSPLIT_1_SPLIT_L2\t\t= 1,\n+\tICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS\t= 2,\n+};\n+\n+/* TX Descriptor */\n+struct ice_tx_desc {\n+\t__le64 buf_addr; /* Address of descriptor's data buf */\n+\t__le64 cmd_type_offset_bsz;\n+};\n+\n+#define ICE_TXD_QW1_DTYPE_S\t0\n+#define ICE_TXD_QW1_DTYPE_M\t(0xFUL << ICE_TXD_QW1_DTYPE_S)\n+\n+enum ice_tx_desc_dtype_value {\n+\tICE_TX_DESC_DTYPE_DATA\t\t= 0x0,\n+\tICE_TX_DESC_DTYPE_CTX\t\t= 0x1,\n+\tICE_TX_DESC_DTYPE_IPSEC\t\t= 0x3,\n+\tICE_TX_DESC_DTYPE_FLTR_PROG\t= 0x8,\n+\tICE_TX_DESC_DTYPE_HLP_META\t= 0x9,\n+\t/* DESC_DONE - HW has completed write-back of descriptor */\n+\tICE_TX_DESC_DTYPE_DESC_DONE\t= 0xF,\n+};\n+\n+#define ICE_TXD_QW1_CMD_S\t4\n+#define ICE_TXD_QW1_CMD_M\t(0xFFFUL << ICE_TXD_QW1_CMD_S)\n+\n+enum ice_tx_desc_cmd_bits {\n+\tICE_TX_DESC_CMD_EOP\t\t\t= 0x0001,\n+\tICE_TX_DESC_CMD_RS\t\t\t= 0x0002,\n+\tICE_TX_DESC_CMD_RSVD\t\t\t= 0x0004,\n+\tICE_TX_DESC_CMD_IL2TAG1\t\t\t= 0x0008,\n+\tICE_TX_DESC_CMD_DUMMY\t\t\t= 0x0010,\n+\tICE_TX_DESC_CMD_IIPT_NONIP\t\t= 0x0000, /* 2 BITS */\n+\tICE_TX_DESC_CMD_IIPT_IPV6\t\t= 0x0020, /* 2 BITS */\n+\tICE_TX_DESC_CMD_IIPT_IPV4\t\t= 0x0040, /* 2 BITS */\n+\tICE_TX_DESC_CMD_IIPT_IPV4_CSUM\t\t= 0x0060, /* 2 BITS */\n+\tICE_TX_DESC_CMD_RSVD2\t\t\t= 0x0080,\n+\tICE_TX_DESC_CMD_L4T_EOFT_UNK\t\t= 0x0000, /* 2 BITS */\n+\tICE_TX_DESC_CMD_L4T_EOFT_TCP\t\t= 0x0100, /* 2 BITS */\n+\tICE_TX_DESC_CMD_L4T_EOFT_SCTP\t\t= 0x0200, /* 2 BITS */\n+\tICE_TX_DESC_CMD_L4T_EOFT_UDP\t\t= 0x0300, /* 2 BITS */\n+\tICE_TX_DESC_CMD_RE\t\t\t= 0x0400,\n+\tICE_TX_DESC_CMD_RSVD3\t\t\t= 0x0800,\n+};\n+\n+#define ICE_TXD_QW1_OFFSET_S\t16\n+#define ICE_TXD_QW1_OFFSET_M\t(0x3FFFFULL << ICE_TXD_QW1_OFFSET_S)\n+\n+enum ice_tx_desc_len_fields {\n+\t/* Note: These are predefined bit offsets */\n+\tICE_TX_DESC_LEN_MACLEN_S\t= 0, /* 7 BITS */\n+\tICE_TX_DESC_LEN_IPLEN_S\t= 7, /* 7 BITS */\n+\tICE_TX_DESC_LEN_L4_LEN_S\t= 14 /* 4 BITS */\n+};\n+\n+#define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S)\n+#define ICE_TXD_QW1_IPLEN_M  (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S)\n+#define ICE_TXD_QW1_L4LEN_M  (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S)\n+\n+/* Tx descriptor field limits in bytes */\n+#define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \\\n+\t\t\t     ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD)\n+#define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \\\n+\t\t\t    ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD)\n+#define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \\\n+\t\t\t    ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD)\n+\n+#define ICE_TXD_QW1_TX_BUF_SZ_S\t34\n+#define ICE_TXD_QW1_TX_BUF_SZ_M\t(0x3FFFULL << ICE_TXD_QW1_TX_BUF_SZ_S)\n+\n+#define ICE_TXD_QW1_L2TAG1_S\t48\n+#define ICE_TXD_QW1_L2TAG1_M\t(0xFFFFULL << ICE_TXD_QW1_L2TAG1_S)\n+\n+/* Context descriptors */\n+struct ice_tx_ctx_desc {\n+\t__le32 tunneling_params;\n+\t__le16 l2tag2;\n+\t__le16 rsvd;\n+\t__le64 qw1;\n+};\n+\n+#define ICE_TXD_CTX_QW1_DTYPE_S\t0\n+#define ICE_TXD_CTX_QW1_DTYPE_M\t(0xFUL << ICE_TXD_CTX_QW1_DTYPE_S)\n+\n+#define ICE_TXD_CTX_QW1_CMD_S\t4\n+#define ICE_TXD_CTX_QW1_CMD_M\t(0x7FUL << ICE_TXD_CTX_QW1_CMD_S)\n+\n+#define ICE_TXD_CTX_QW1_IPSEC_S\t11\n+#define ICE_TXD_CTX_QW1_IPSEC_M\t(0x7FUL << ICE_TXD_CTX_QW1_IPSEC_S)\n+\n+#define ICE_TXD_CTX_QW1_TSO_LEN_S\t30\n+#define ICE_TXD_CTX_QW1_TSO_LEN_M\t\\\n+\t\t\t(0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S)\n+\n+#define ICE_TXD_CTX_QW1_TSYN_S\tICE_TXD_CTX_QW1_TSO_LEN_S\n+#define ICE_TXD_CTX_QW1_TSYN_M\tICE_TXD_CTX_QW1_TSO_LEN_M\n+\n+#define ICE_TXD_CTX_QW1_MSS_S\t50\n+#define ICE_TXD_CTX_QW1_MSS_M\t(0x3FFFULL << ICE_TXD_CTX_QW1_MSS_S)\n+#define ICE_TXD_CTX_MIN_MSS\t64\n+#define ICE_TXD_CTX_MAX_MSS\t9668\n+\n+#define ICE_TXD_CTX_QW1_VSI_S\t50\n+#define ICE_TXD_CTX_QW1_VSI_M\t(0x3FFULL << ICE_TXD_CTX_QW1_VSI_S)\n+\n+enum ice_tx_ctx_desc_cmd_bits {\n+\tICE_TX_CTX_DESC_TSO\t\t= 0x01,\n+\tICE_TX_CTX_DESC_TSYN\t\t= 0x02,\n+\tICE_TX_CTX_DESC_IL2TAG2\t\t= 0x04,\n+\tICE_TX_CTX_DESC_IL2TAG2_IL2H\t= 0x08,\n+\tICE_TX_CTX_DESC_SWTCH_NOTAG\t= 0x00,\n+\tICE_TX_CTX_DESC_SWTCH_UPLINK\t= 0x10,\n+\tICE_TX_CTX_DESC_SWTCH_LOCAL\t= 0x20,\n+\tICE_TX_CTX_DESC_SWTCH_VSI\t= 0x30,\n+\tICE_TX_CTX_DESC_RESERVED\t= 0x40\n+};\n+\n+enum ice_tx_ctx_desc_eipt_offload {\n+\tICE_TX_CTX_EIPT_NONE\t\t= 0x0,\n+\tICE_TX_CTX_EIPT_IPV6\t\t= 0x1,\n+\tICE_TX_CTX_EIPT_IPV4_NO_CSUM\t= 0x2,\n+\tICE_TX_CTX_EIPT_IPV4\t\t= 0x3\n+};\n+\n+#define ICE_TXD_CTX_QW0_EIPT_S\t0\n+#define ICE_TXD_CTX_QW0_EIPT_M\t(0x3ULL << ICE_TXD_CTX_QW0_EIPT_S)\n+\n+#define ICE_TXD_CTX_QW0_EIPLEN_S\t2\n+#define ICE_TXD_CTX_QW0_EIPLEN_M\t(0x7FUL << ICE_TXD_CTX_QW0_EIPLEN_S)\n+\n+#define ICE_TXD_CTX_QW0_L4TUNT_S\t9\n+#define ICE_TXD_CTX_QW0_L4TUNT_M\t(0x3ULL << ICE_TXD_CTX_QW0_L4TUNT_S)\n+\n+#define ICE_TXD_CTX_UDP_TUNNELING\tBIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S)\n+#define ICE_TXD_CTX_GRE_TUNNELING\t(0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S)\n+\n+#define ICE_TXD_CTX_QW0_EIP_NOINC_S\t11\n+#define ICE_TXD_CTX_QW0_EIP_NOINC_M\tBIT_ULL(ICE_TXD_CTX_QW0_EIP_NOINC_S)\n+\n+#define ICE_TXD_CTX_EIP_NOINC_IPID_CONST\tICE_TXD_CTX_QW0_EIP_NOINC_M\n+\n+#define ICE_TXD_CTX_QW0_NATLEN_S\t12\n+#define ICE_TXD_CTX_QW0_NATLEN_M\t(0X7FULL << ICE_TXD_CTX_QW0_NATLEN_S)\n+\n+#define ICE_TXD_CTX_QW0_DECTTL_S\t19\n+#define ICE_TXD_CTX_QW0_DECTTL_M\t(0xFULL << ICE_TXD_CTX_QW0_DECTTL_S)\n+\n+#define ICE_TXD_CTX_QW0_L4T_CS_S\t23\n+#define ICE_TXD_CTX_QW0_L4T_CS_M\tBIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)\n+\n+\n+#define ICE_LAN_TXQ_MAX_QGRPS\t127\n+#define ICE_LAN_TXQ_MAX_QDIS\t1023\n+\n+/* Tx queue context data\n+ *\n+ * The sizes of the variables may be larger than needed due to crossing byte\n+ * boundaries. If we do not have the width of the variable set to the correct\n+ * size then we could end up shifting bits off the top of the variable when the\n+ * variable is at the top of a byte and crosses over into the next byte.\n+ */\n+struct ice_tlan_ctx {\n+#define ICE_TLAN_CTX_BASE_S\t7\n+\tu64 base;\t\t/* base is defined in 128-byte units */\n+\tu8 port_num;\n+\tu16 cgd_num;\t\t/* bigger than needed, see above for reason */\n+\tu8 pf_num;\n+\tu16 vmvf_num;\n+\tu8 vmvf_type;\n+#define ICE_TLAN_CTX_VMVF_TYPE_VF\t0\n+#define ICE_TLAN_CTX_VMVF_TYPE_VMQ\t1\n+#define ICE_TLAN_CTX_VMVF_TYPE_PF\t2\n+\tu16 src_vsi;\n+\tu8 tsyn_ena;\n+\tu8 alt_vlan;\n+\tu16 cpuid;\t\t/* bigger than needed, see above for reason */\n+\tu8 wb_mode;\n+\tu8 tphrd_desc;\n+\tu8 tphrd;\n+\tu8 tphwr_desc;\n+\tu16 cmpq_id;\n+\tu16 qnum_in_func;\n+\tu8 itr_notification_mode;\n+\tu8 adjust_prof_id;\n+\tu32 qlen;\t\t/* bigger than needed, see above for reason */\n+\tu8 quanta_prof_idx;\n+\tu8 tso_ena;\n+\tu16 tso_qnum;\n+\tu8 legacy_int;\n+\tu8 drop_ena;\n+\tu8 cache_prof_idx;\n+\tu8 pkt_shaper_prof_idx;\n+\tu8 int_q_state;\t/* width not needed - internal do not write */\n+};\n+\n+/* LAN Tx Completion Queue data */\n+#pragma pack(1)\n+struct ice_tx_cmpltnq {\n+\tu16 txq_id;\n+\tu8 generation;\n+\tu16 tx_head;\n+\tu8 cmpl_type;\n+};\n+#pragma pack()\n+\n+\n+/* LAN Tx Completion Queue Context */\n+#pragma pack(1)\n+struct ice_tx_cmpltnq_ctx {\n+\tu64 base;\n+\tu32 q_len;\n+#define ICE_TX_CMPLTNQ_CTX_Q_LEN_S\t4\n+\tu8 generation;\n+\tu32 wrt_ptr;\n+\tu8 pf_num;\n+\tu16 vmvf_num;\n+\tu8 vmvf_type;\n+\tu8 tph_desc_wr;\n+\tu8 cpuid;\n+\tu32 cmpltn_cache[16];\n+};\n+#pragma pack()\n+\n+/* LAN Tx Doorbell Descriptor Format */\n+struct ice_tx_drbell_fmt {\n+\tu16 txq_id;\n+\tu8 dd;\n+\tu8 rs;\n+\tu32 db;\n+};\n+\n+\n+/* LAN Tx Doorbell Queue Context */\n+#pragma pack(1)\n+struct ice_tx_drbell_q_ctx {\n+\tu64 base;\n+\tu16 ring_len;\n+\tu8 pf_num;\n+\tu16 vf_num;\n+\tu8 vmvf_type;\n+\tu8 cpuid;\n+\tu8 tph_desc_rd;\n+\tu8 tph_desc_wr;\n+\tu8 db_q_en;\n+\tu16 rd_head;\n+\tu16 rd_tail;\n+};\n+#pragma pack()\n+\n+/* The ice_ptype_lkup table is used to convert from the 10-bit ptype in the\n+ * hardware to a bit-field that can be used by SW to more easily determine the\n+ * packet type.\n+ *\n+ * Macros are used to shorten the table lines and make this table human\n+ * readable.\n+ *\n+ * We store the PTYPE in the top byte of the bit field - this is just so that\n+ * we can check that the table doesn't have a row missing, as the index into\n+ * the table should be the PTYPE.\n+ *\n+ * Typical work flow:\n+ *\n+ * IF NOT ice_ptype_lkup[ptype].known\n+ * THEN\n+ *      Packet is unknown\n+ * ELSE IF ice_ptype_lkup[ptype].outer_ip == ICE_RX_PTYPE_OUTER_IP\n+ *      Use the rest of the fields to look at the tunnels, inner protocols, etc\n+ * ELSE\n+ *      Use the enum ice_rx_l2_ptype to decode the packet type\n+ * ENDIF\n+ */\n+\n+/* macro to make the table lines short */\n+#define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\\\n+\t{\tPTYPE, \\\n+\t\t1, \\\n+\t\tICE_RX_PTYPE_OUTER_##OUTER_IP, \\\n+\t\tICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \\\n+\t\tICE_RX_PTYPE_##OUTER_FRAG, \\\n+\t\tICE_RX_PTYPE_TUNNEL_##T, \\\n+\t\tICE_RX_PTYPE_TUNNEL_END_##TE, \\\n+\t\tICE_RX_PTYPE_##TEF, \\\n+\t\tICE_RX_PTYPE_INNER_PROT_##I, \\\n+\t\tICE_RX_PTYPE_PAYLOAD_LAYER_##PL }\n+\n+#define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }\n+\n+/* shorter macros makes the table fit but are terse */\n+#define ICE_RX_PTYPE_NOF\t\tICE_RX_PTYPE_NOT_FRAG\n+#define ICE_RX_PTYPE_FRG\t\tICE_RX_PTYPE_FRAG\n+\n+/* Lookup table mapping the HW PTYPE to the bit field for decoding */\n+static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = {\n+\t/* L2 Packet types */\n+\tICE_PTT_UNUSED_ENTRY(0),\n+\tICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),\n+\tICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT_UNUSED_ENTRY(3),\n+\tICE_PTT_UNUSED_ENTRY(4),\n+\tICE_PTT_UNUSED_ENTRY(5),\n+\tICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT_UNUSED_ENTRY(8),\n+\tICE_PTT_UNUSED_ENTRY(9),\n+\tICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),\n+\tICE_PTT_UNUSED_ENTRY(12),\n+\tICE_PTT_UNUSED_ENTRY(13),\n+\tICE_PTT_UNUSED_ENTRY(14),\n+\tICE_PTT_UNUSED_ENTRY(15),\n+\tICE_PTT_UNUSED_ENTRY(16),\n+\tICE_PTT_UNUSED_ENTRY(17),\n+\tICE_PTT_UNUSED_ENTRY(18),\n+\tICE_PTT_UNUSED_ENTRY(19),\n+\tICE_PTT_UNUSED_ENTRY(20),\n+\tICE_PTT_UNUSED_ENTRY(21),\n+\n+\t/* Non Tunneled IPv4 */\n+\tICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),\n+\tICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),\n+\tICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(25),\n+\tICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),\n+\tICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),\n+\tICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> IPv4 */\n+\tICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(32),\n+\tICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> IPv6 */\n+\tICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(39),\n+\tICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT */\n+\tICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv4 --> GRE/NAT --> IPv4 */\n+\tICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(47),\n+\tICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT --> IPv6 */\n+\tICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(54),\n+\tICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT --> MAC */\n+\tICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv4 --> GRE/NAT --> MAC --> IPv4 */\n+\tICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(62),\n+\tICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT -> MAC --> IPv6 */\n+\tICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(69),\n+\tICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 --> GRE/NAT --> MAC/VLAN */\n+\tICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */\n+\tICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(77),\n+\tICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */\n+\tICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(84),\n+\tICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* Non Tunneled IPv6 */\n+\tICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),\n+\tICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),\n+\tICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY3),\n+\tICE_PTT_UNUSED_ENTRY(91),\n+\tICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),\n+\tICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),\n+\tICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> IPv4 */\n+\tICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(98),\n+\tICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> IPv6 */\n+\tICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(105),\n+\tICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT */\n+\tICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv6 --> GRE/NAT -> IPv4 */\n+\tICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(113),\n+\tICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> IPv6 */\n+\tICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(120),\n+\tICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC */\n+\tICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC -> IPv4 */\n+\tICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(128),\n+\tICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC -> IPv6 */\n+\tICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(135),\n+\tICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC/VLAN */\n+\tICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */\n+\tICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),\n+\tICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),\n+\tICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(143),\n+\tICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),\n+\tICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),\n+\tICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),\n+\n+\t/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */\n+\tICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),\n+\tICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),\n+\tICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),\n+\tICE_PTT_UNUSED_ENTRY(150),\n+\tICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),\n+\tICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),\n+\tICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),\n+\n+\t/* unused entries */\n+\tICE_PTT_UNUSED_ENTRY(154),\n+\tICE_PTT_UNUSED_ENTRY(155),\n+\tICE_PTT_UNUSED_ENTRY(156),\n+\tICE_PTT_UNUSED_ENTRY(157),\n+\tICE_PTT_UNUSED_ENTRY(158),\n+\tICE_PTT_UNUSED_ENTRY(159),\n+\n+\tICE_PTT_UNUSED_ENTRY(160),\n+\tICE_PTT_UNUSED_ENTRY(161),\n+\tICE_PTT_UNUSED_ENTRY(162),\n+\tICE_PTT_UNUSED_ENTRY(163),\n+\tICE_PTT_UNUSED_ENTRY(164),\n+\tICE_PTT_UNUSED_ENTRY(165),\n+\tICE_PTT_UNUSED_ENTRY(166),\n+\tICE_PTT_UNUSED_ENTRY(167),\n+\tICE_PTT_UNUSED_ENTRY(168),\n+\tICE_PTT_UNUSED_ENTRY(169),\n+\n+\tICE_PTT_UNUSED_ENTRY(170),\n+\tICE_PTT_UNUSED_ENTRY(171),\n+\tICE_PTT_UNUSED_ENTRY(172),\n+\tICE_PTT_UNUSED_ENTRY(173),\n+\tICE_PTT_UNUSED_ENTRY(174),\n+\tICE_PTT_UNUSED_ENTRY(175),\n+\tICE_PTT_UNUSED_ENTRY(176),\n+\tICE_PTT_UNUSED_ENTRY(177),\n+\tICE_PTT_UNUSED_ENTRY(178),\n+\tICE_PTT_UNUSED_ENTRY(179),\n+\n+\tICE_PTT_UNUSED_ENTRY(180),\n+\tICE_PTT_UNUSED_ENTRY(181),\n+\tICE_PTT_UNUSED_ENTRY(182),\n+\tICE_PTT_UNUSED_ENTRY(183),\n+\tICE_PTT_UNUSED_ENTRY(184),\n+\tICE_PTT_UNUSED_ENTRY(185),\n+\tICE_PTT_UNUSED_ENTRY(186),\n+\tICE_PTT_UNUSED_ENTRY(187),\n+\tICE_PTT_UNUSED_ENTRY(188),\n+\tICE_PTT_UNUSED_ENTRY(189),\n+\n+\tICE_PTT_UNUSED_ENTRY(190),\n+\tICE_PTT_UNUSED_ENTRY(191),\n+\tICE_PTT_UNUSED_ENTRY(192),\n+\tICE_PTT_UNUSED_ENTRY(193),\n+\tICE_PTT_UNUSED_ENTRY(194),\n+\tICE_PTT_UNUSED_ENTRY(195),\n+\tICE_PTT_UNUSED_ENTRY(196),\n+\tICE_PTT_UNUSED_ENTRY(197),\n+\tICE_PTT_UNUSED_ENTRY(198),\n+\tICE_PTT_UNUSED_ENTRY(199),\n+\n+\tICE_PTT_UNUSED_ENTRY(200),\n+\tICE_PTT_UNUSED_ENTRY(201),\n+\tICE_PTT_UNUSED_ENTRY(202),\n+\tICE_PTT_UNUSED_ENTRY(203),\n+\tICE_PTT_UNUSED_ENTRY(204),\n+\tICE_PTT_UNUSED_ENTRY(205),\n+\tICE_PTT_UNUSED_ENTRY(206),\n+\tICE_PTT_UNUSED_ENTRY(207),\n+\tICE_PTT_UNUSED_ENTRY(208),\n+\tICE_PTT_UNUSED_ENTRY(209),\n+\n+\tICE_PTT_UNUSED_ENTRY(210),\n+\tICE_PTT_UNUSED_ENTRY(211),\n+\tICE_PTT_UNUSED_ENTRY(212),\n+\tICE_PTT_UNUSED_ENTRY(213),\n+\tICE_PTT_UNUSED_ENTRY(214),\n+\tICE_PTT_UNUSED_ENTRY(215),\n+\tICE_PTT_UNUSED_ENTRY(216),\n+\tICE_PTT_UNUSED_ENTRY(217),\n+\tICE_PTT_UNUSED_ENTRY(218),\n+\tICE_PTT_UNUSED_ENTRY(219),\n+\n+\tICE_PTT_UNUSED_ENTRY(220),\n+\tICE_PTT_UNUSED_ENTRY(221),\n+\tICE_PTT_UNUSED_ENTRY(222),\n+\tICE_PTT_UNUSED_ENTRY(223),\n+\tICE_PTT_UNUSED_ENTRY(224),\n+\tICE_PTT_UNUSED_ENTRY(225),\n+\tICE_PTT_UNUSED_ENTRY(226),\n+\tICE_PTT_UNUSED_ENTRY(227),\n+\tICE_PTT_UNUSED_ENTRY(228),\n+\tICE_PTT_UNUSED_ENTRY(229),\n+\n+\tICE_PTT_UNUSED_ENTRY(230),\n+\tICE_PTT_UNUSED_ENTRY(231),\n+\tICE_PTT_UNUSED_ENTRY(232),\n+\tICE_PTT_UNUSED_ENTRY(233),\n+\tICE_PTT_UNUSED_ENTRY(234),\n+\tICE_PTT_UNUSED_ENTRY(235),\n+\tICE_PTT_UNUSED_ENTRY(236),\n+\tICE_PTT_UNUSED_ENTRY(237),\n+\tICE_PTT_UNUSED_ENTRY(238),\n+\tICE_PTT_UNUSED_ENTRY(239),\n+\n+\tICE_PTT_UNUSED_ENTRY(240),\n+\tICE_PTT_UNUSED_ENTRY(241),\n+\tICE_PTT_UNUSED_ENTRY(242),\n+\tICE_PTT_UNUSED_ENTRY(243),\n+\tICE_PTT_UNUSED_ENTRY(244),\n+\tICE_PTT_UNUSED_ENTRY(245),\n+\tICE_PTT_UNUSED_ENTRY(246),\n+\tICE_PTT_UNUSED_ENTRY(247),\n+\tICE_PTT_UNUSED_ENTRY(248),\n+\tICE_PTT_UNUSED_ENTRY(249),\n+\n+\tICE_PTT_UNUSED_ENTRY(250),\n+\tICE_PTT_UNUSED_ENTRY(251),\n+\tICE_PTT_UNUSED_ENTRY(252),\n+\tICE_PTT_UNUSED_ENTRY(253),\n+\tICE_PTT_UNUSED_ENTRY(254),\n+\tICE_PTT_UNUSED_ENTRY(255),\n+\tICE_PTT_UNUSED_ENTRY(256),\n+\tICE_PTT_UNUSED_ENTRY(257),\n+\tICE_PTT_UNUSED_ENTRY(258),\n+\tICE_PTT_UNUSED_ENTRY(259),\n+\n+\tICE_PTT_UNUSED_ENTRY(260),\n+\tICE_PTT_UNUSED_ENTRY(261),\n+\tICE_PTT_UNUSED_ENTRY(262),\n+\tICE_PTT_UNUSED_ENTRY(263),\n+\tICE_PTT_UNUSED_ENTRY(264),\n+\tICE_PTT_UNUSED_ENTRY(265),\n+\tICE_PTT_UNUSED_ENTRY(266),\n+\tICE_PTT_UNUSED_ENTRY(267),\n+\tICE_PTT_UNUSED_ENTRY(268),\n+\tICE_PTT_UNUSED_ENTRY(269),\n+\n+\tICE_PTT_UNUSED_ENTRY(270),\n+\tICE_PTT_UNUSED_ENTRY(271),\n+\tICE_PTT_UNUSED_ENTRY(272),\n+\tICE_PTT_UNUSED_ENTRY(273),\n+\tICE_PTT_UNUSED_ENTRY(274),\n+\tICE_PTT_UNUSED_ENTRY(275),\n+\tICE_PTT_UNUSED_ENTRY(276),\n+\tICE_PTT_UNUSED_ENTRY(277),\n+\tICE_PTT_UNUSED_ENTRY(278),\n+\tICE_PTT_UNUSED_ENTRY(279),\n+\n+\tICE_PTT_UNUSED_ENTRY(280),\n+\tICE_PTT_UNUSED_ENTRY(281),\n+\tICE_PTT_UNUSED_ENTRY(282),\n+\tICE_PTT_UNUSED_ENTRY(283),\n+\tICE_PTT_UNUSED_ENTRY(284),\n+\tICE_PTT_UNUSED_ENTRY(285),\n+\tICE_PTT_UNUSED_ENTRY(286),\n+\tICE_PTT_UNUSED_ENTRY(287),\n+\tICE_PTT_UNUSED_ENTRY(288),\n+\tICE_PTT_UNUSED_ENTRY(289),\n+\n+\tICE_PTT_UNUSED_ENTRY(290),\n+\tICE_PTT_UNUSED_ENTRY(291),\n+\tICE_PTT_UNUSED_ENTRY(292),\n+\tICE_PTT_UNUSED_ENTRY(293),\n+\tICE_PTT_UNUSED_ENTRY(294),\n+\tICE_PTT_UNUSED_ENTRY(295),\n+\tICE_PTT_UNUSED_ENTRY(296),\n+\tICE_PTT_UNUSED_ENTRY(297),\n+\tICE_PTT_UNUSED_ENTRY(298),\n+\tICE_PTT_UNUSED_ENTRY(299),\n+\n+\tICE_PTT_UNUSED_ENTRY(300),\n+\tICE_PTT_UNUSED_ENTRY(301),\n+\tICE_PTT_UNUSED_ENTRY(302),\n+\tICE_PTT_UNUSED_ENTRY(303),\n+\tICE_PTT_UNUSED_ENTRY(304),\n+\tICE_PTT_UNUSED_ENTRY(305),\n+\tICE_PTT_UNUSED_ENTRY(306),\n+\tICE_PTT_UNUSED_ENTRY(307),\n+\tICE_PTT_UNUSED_ENTRY(308),\n+\tICE_PTT_UNUSED_ENTRY(309),\n+\n+\tICE_PTT_UNUSED_ENTRY(310),\n+\tICE_PTT_UNUSED_ENTRY(311),\n+\tICE_PTT_UNUSED_ENTRY(312),\n+\tICE_PTT_UNUSED_E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inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)\n+{\n+\treturn ice_ptype_lkup[ptype];\n+}\n+\n+#define ICE_LINK_SPEED_UNKNOWN\t\t0\n+#define ICE_LINK_SPEED_10MBPS\t\t10\n+#define ICE_LINK_SPEED_100MBPS\t\t100\n+#define ICE_LINK_SPEED_1000MBPS\t\t1000\n+#define ICE_LINK_SPEED_2500MBPS\t\t2500\n+#define ICE_LINK_SPEED_5000MBPS\t\t5000\n+#define ICE_LINK_SPEED_10000MBPS\t10000\n+#define ICE_LINK_SPEED_20000MBPS\t20000\n+#define ICE_LINK_SPEED_25000MBPS\t25000\n+#define ICE_LINK_SPEED_40000MBPS\t40000\n+\n+#endif /* _ICE_LAN_TX_RX_H_ */\ndiff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nnew file mode 100644\nindex 0000000..fc26531\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -0,0 +1,388 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_common.h\"\n+\n+\n+/**\n+ * ice_aq_read_nvm\n+ * @hw: pointer to the hw struct\n+ * @module_typeid: module pointer location in words from the NVM beginning\n+ * @offset: byte offset from the module beginning\n+ * @length: length of the section to be read (in bytes from the offset)\n+ * @data: command buffer (size [bytes] = length)\n+ * @last_command: tells if this is the last command in a series\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Read the NVM using the admin queue commands (0x0701)\n+ */\n+static enum ice_status\n+ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,\n+\t\tvoid *data, bool last_command, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc;\n+\tstruct ice_aqc_nvm *cmd;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_read_nvm\");\n+\n+\tcmd = &desc.params.nvm;\n+\n+\t/* In offset the highest byte must be zeroed. */\n+\tif (offset & 0xFF000000)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);\n+\n+\t/* If this is the last command in a series, set the proper flag. */\n+\tif (last_command)\n+\t\tcmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;\n+\tcmd->module_typeid = CPU_TO_LE16(module_typeid);\n+\tcmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);\n+\tcmd->offset_high = (offset >> 16) & 0xFF;\n+\tcmd->length = CPU_TO_LE16(length);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, data, length, cd);\n+}\n+\n+/**\n+ * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.\n+ * @hw: pointer to the HW structure\n+ * @offset: offset in words from module start\n+ * @words: number of words to access\n+ */\n+static enum ice_status\n+ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)\n+{\n+\tif ((offset + words) > hw->nvm.sr_words) {\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t  \"NVM error: offset beyond SR lmt.\\n\");\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {\n+\t\t/* We can access only up to 4KB (one sector), in one AQ write */\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t  \"NVM error: tried to access %d words, limit is %d.\\n\",\n+\t\t\t  words, ICE_SR_SECTOR_SIZE_IN_WORDS);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=\n+\t    (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {\n+\t\t/* A single access cannot spread over two sectors */\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t  \"NVM error: cannot spread over two sectors.\\n\");\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_read_sr_aq - Read Shadow RAM.\n+ * @hw: pointer to the HW structure\n+ * @offset: offset in words from module start\n+ * @words: number of words to read\n+ * @data: buffer for words reads from Shadow RAM\n+ * @last_command: tells the AdminQ that this is the last command\n+ *\n+ * Reads 16-bit word buffers from the Shadow RAM using the admin command.\n+ */\n+static enum ice_status\n+ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,\n+\t       bool last_command)\n+{\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_read_sr_aq\");\n+\n+\tstatus = ice_check_sr_access_params(hw, offset, words);\n+\n+\t/* values in \"offset\" and \"words\" parameters are sized as words\n+\t * (16 bits) but ice_aq_read_nvm expects these values in bytes.\n+\t * So do this conversion while calling ice_aq_read_nvm.\n+\t */\n+\tif (!status)\n+\t\tstatus = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,\n+\t\t\t\t\t last_command, NULL);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_read_sr_word_aq - Reads Shadow RAM via AQ\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.\n+ */\n+static enum ice_status\n+ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)\n+{\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_read_sr_word_aq\");\n+\n+\tstatus = ice_read_sr_aq(hw, offset, 1, data, true);\n+\tif (!status)\n+\t\t*data = LE16_TO_CPU(*(__le16 *)data);\n+\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @words: (in) number of words to read; (out) number of words actually read\n+ * @data: words read from the Shadow RAM\n+ *\n+ * Reads 16 bit words (data buf) from the SR using the ice_read_sr_aq\n+ * method. Ownership of the NVM is taken before reading the buffer and later\n+ * released.\n+ */\n+static enum ice_status\n+ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)\n+{\n+\tenum ice_status status;\n+\tbool last_cmd = false;\n+\tu16 words_read = 0;\n+\tu16 i = 0;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_read_sr_buf_aq\");\n+\n+\tdo {\n+\t\tu16 read_size, off_w;\n+\n+\t\t/* Calculate number of bytes we should read in this step.\n+\t\t * It's not allowed to read more than one page at a time or\n+\t\t * to cross page boundaries.\n+\t\t */\n+\t\toff_w = offset % ICE_SR_SECTOR_SIZE_IN_WORDS;\n+\t\tread_size = off_w ?\n+\t\t\tmin(*words,\n+\t\t\t    (u16)(ICE_SR_SECTOR_SIZE_IN_WORDS - off_w)) :\n+\t\t\tmin((*words - words_read), ICE_SR_SECTOR_SIZE_IN_WORDS);\n+\n+\t\t/* Check if this is last command, if so set proper flag */\n+\t\tif ((words_read + read_size) >= *words)\n+\t\t\tlast_cmd = true;\n+\n+\t\tstatus = ice_read_sr_aq(hw, offset, read_size,\n+\t\t\t\t\tdata + words_read, last_cmd);\n+\t\tif (status)\n+\t\t\tgoto read_nvm_buf_aq_exit;\n+\n+\t\t/* Increment counter for words already read and move offset to\n+\t\t * new read location\n+\t\t */\n+\t\twords_read += read_size;\n+\t\toffset += read_size;\n+\t} while (words_read < *words);\n+\n+\tfor (i = 0; i < *words; i++)\n+\t\tdata[i] = LE16_TO_CPU(((__le16 *)data)[i]);\n+\n+read_nvm_buf_aq_exit:\n+\t*words = words_read;\n+\treturn status;\n+}\n+\n+/**\n+ * ice_acquire_nvm - Generic request for acquiring the NVM ownership\n+ * @hw: pointer to the HW structure\n+ * @access: NVM access type (read or write)\n+ *\n+ * This function will request NVM ownership.\n+ */\n+static enum ice_status\n+ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)\n+{\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_acquire_nvm\");\n+\n+\tif (hw->nvm.blank_nvm_mode)\n+\t\treturn ICE_SUCCESS;\n+\n+\treturn ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);\n+}\n+\n+/**\n+ * ice_release_nvm - Generic request for releasing the NVM ownership\n+ * @hw: pointer to the HW structure\n+ *\n+ * This function will release NVM ownership.\n+ */\n+static void ice_release_nvm(struct ice_hw *hw)\n+{\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_release_nvm\");\n+\n+\tif (hw->nvm.blank_nvm_mode)\n+\t\treturn;\n+\n+\tice_release_res(hw, ICE_NVM_RES_ID);\n+}\n+\n+/**\n+ * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.\n+ */\n+enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_acquire_nvm(hw, ICE_RES_READ);\n+\tif (!status) {\n+\t\tstatus = ice_read_sr_word_aq(hw, offset, data);\n+\t\tice_release_nvm(hw);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_init_nvm - initializes NVM setting\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function reads and populates NVM settings such as Shadow RAM size,\n+ * max_timeout, and blank_nvm_mode\n+ */\n+enum ice_status ice_init_nvm(struct ice_hw *hw)\n+{\n+\tstruct ice_nvm_info *nvm = &hw->nvm;\n+\tu16 oem_hi, oem_lo, cfg_ptr;\n+\tu16 eetrack_lo, eetrack_hi;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu32 fla, gens_stat;\n+\tu8 sr_size;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_init_nvm\");\n+\n+\t/* The SR size is stored regardless of the nvm programming mode\n+\t * as the blank mode may be used in the factory line.\n+\t */\n+\tgens_stat = rd32(hw, GLNVM_GENS);\n+\tsr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;\n+\n+\t/* Switching to words (sr_size contains power of 2) */\n+\tnvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;\n+\n+\t/* Check if we are in the normal or blank NVM programming mode */\n+\tfla = rd32(hw, GLNVM_FLA);\n+\tif (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */\n+\t\tnvm->blank_nvm_mode = false;\n+\t} else { /* Blank programming mode */\n+\t\tnvm->blank_nvm_mode = true;\n+\t\tstatus = ICE_ERR_NVM_BLANK_MODE;\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t  \"NVM init error: unsupported blank mode.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t  \"Failed to read DEV starter version.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read EETRACK lo.\\n\");\n+\t\treturn status;\n+\t}\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read EETRACK hi.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\thw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;\n+\n+\tstatus = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read BOOT_CONFIG_PTR.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read OEM_VER hi.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),\n+\t\t\t\t  &oem_lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read OEM_VER lo.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\thw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @words: (in) number of words to read; (out) number of words actually read\n+ * @data: words read from the Shadow RAM\n+ *\n+ * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq\n+ * method. The buf read is preceded by the NVM ownership take\n+ * and followed by the release.\n+ */\n+enum ice_status\n+ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_acquire_nvm(hw, ICE_RES_READ);\n+\tif (!status) {\n+\t\tstatus = ice_read_sr_buf_aq(hw, offset, words, data);\n+\t\tice_release_nvm(hw);\n+\t}\n+\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_nvm_validate_checksum\n+ * @hw: pointer to the hw struct\n+ *\n+ * Verify NVM PFA checksum validity (0x0706)\n+ */\n+enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)\n+{\n+\tstruct ice_aqc_nvm_checksum *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tstatus = ice_acquire_nvm(hw, ICE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tcmd = &desc.params.nvm_checksum;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);\n+\tcmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+\tice_release_nvm(hw);\n+\n+\tif (!status)\n+\t\tif (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)\n+\t\t\tstatus = ICE_ERR_NVM_CHECKSUM;\n+\n+\treturn status;\n+}\n+\ndiff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h\nnew file mode 100644\nindex 0000000..e1f7581\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_osdep.h\n@@ -0,0 +1,491 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+#ifndef _ICE_OSDEP_H_\n+#define _ICE_OSDEP_H_\n+\n+#include <string.h>\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <stdarg.h>\n+#include <inttypes.h>\n+#include <sys/queue.h>\n+#include <stdbool.h>\n+\n+#include <rte_common.h>\n+#include <rte_memcpy.h>\n+#include <rte_malloc.h>\n+#include <rte_memzone.h>\n+#include <rte_byteorder.h>\n+#include <rte_cycles.h>\n+#include <rte_spinlock.h>\n+#include <rte_log.h>\n+#include <rte_random.h>\n+#include <rte_io.h>\n+\n+#include \"../ice_logs.h\"\n+\n+#define INLINE inline\n+#define STATIC static\n+\n+typedef uint8_t         u8;\n+typedef int8_t          s8;\n+typedef uint16_t        u16;\n+typedef int16_t         s16;\n+typedef uint32_t        u32;\n+typedef int32_t         s32;\n+typedef uint64_t        u64;\n+typedef uint64_t        s64;\n+\n+#define __iomem\n+#define hw_dbg(hw, S, A...) do {} while (0)\n+#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))\n+#define lower_32_bits(n) ((u32)(n))\n+#define low_16_bits(x)   ((x) & 0xFFFF)\n+#define high_16_bits(x)  (((x) & 0xFFFF0000) >> 16)\n+\n+#ifndef ETH_ADDR_LEN\n+#define ETH_ADDR_LEN                  6\n+#endif\n+\n+#ifndef __le16\n+#define __le16          uint16_t\n+#endif\n+#ifndef __le32\n+#define __le32          uint32_t\n+#endif\n+#ifndef __le64\n+#define __le64          uint64_t\n+#endif\n+#ifndef __be16\n+#define __be16          uint16_t\n+#endif\n+#ifndef __be32\n+#define __be32          uint32_t\n+#endif\n+#ifndef __be64\n+#define __be64          uint64_t\n+#endif\n+\n+#ifndef __always_unused\n+#define __always_unused  __attribute__((unused))\n+#endif\n+#ifndef __maybe_unused\n+#define __maybe_unused  __attribute__((unused))\n+#endif\n+#ifndef __packed\n+#define __packed  __attribute__((packed))\n+#endif\n+\n+#ifndef BIT_ULL\n+#define BIT_ULL(a) (1ULL << (a))\n+#endif\n+\n+#define FALSE           0\n+#define TRUE            1\n+#define false           0\n+#define true            1\n+\n+#define min(a, b) RTE_MIN(a, b)\n+#define max(a, b) RTE_MAX(a, b)\n+\n+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0]))\n+#define FIELD_SIZEOF(t, f) (sizeof(((t *)0)->f))\n+#define MAKEMASK(m, s) ((m) << (s))\n+\n+#define DEBUGOUT(S, A...) PMD_DRV_LOG_RAW(DEBUG, S, ##A)\n+#define DEBUGFUNC(F) PMD_DRV_LOG_RAW(DEBUG, F)\n+\n+#define ice_debug(h, m, s, ...)\t\t\t\t\t\\\n+do {\t\t\t\t\t\t\t\t\\\n+\tif (((m) & (h)->debug_mask))\t\t\t\t\\\n+\t\tPMD_DRV_LOG_RAW(DEBUG, \"ice %02x.%x \" s,\t\\\n+\t\t\t(h)->bus.device, (h)->bus.func,\t\t\\\n+\t\t\t\t\t##__VA_ARGS__);\t\t\\\n+} while (0)\n+\n+#define ice_info(hw, fmt, args...) ice_debug(hw, ICE_DBG_ALL, fmt, ##args)\n+#define ice_warn(hw, fmt, args...) ice_debug(hw, ICE_DBG_ALL, fmt, ##args)\n+#define ice_debug_array(hw, type, rowsize, groupsize, buf, len)\t\t\\\n+do {\t\t\t\t\t\t\t\t\t\\\n+\tstruct ice_hw *hw_l = hw;\t\t\t\t\t\\\n+\t\tu16 len_l = len;\t\t\t\t\t\\\n+\t\tu8 *buf_l = buf;\t\t\t\t\t\\\n+\t\tint i;\t\t\t\t\t\t\t\\\n+\t\tfor (i = 0; i < len_l; i += 8)\t\t\t\t\\\n+\t\t\tice_debug(hw_l, type,\t\t\t\t\\\n+\t\t\t\t  \"0x%04X  0x%016\"PRIx64\"\\n\",\t\t\\\n+\t\t\t\t  i, *((u64 *)((buf_l) + i)));\t\t\\\n+} while (0)\n+#define ice_snprintf snprintf\n+#ifndef SNPRINTF\n+#define SNPRINTF ice_snprintf\n+#endif\n+\n+#define ICE_PCI_REG(reg)     rte_read32(reg)\n+#define ICE_PCI_REG_ADDR(a, reg) \\\n+\t((volatile uint32_t *)((char *)(a)->hw_addr + (reg)))\n+static inline uint32_t ice_read_addr(volatile void *addr)\n+{\n+\treturn rte_le_to_cpu_32(ICE_PCI_REG(addr));\n+}\n+\n+#define ICE_PCI_REG_WRITE(reg, value) \\\n+\trte_write32((rte_cpu_to_le_32(value)), reg)\n+\n+#define ice_flush(a)   ICE_READ_REG((a), GLGEN_STAT)\n+#define icevf_flush(a) ICE_READ_REG((a), VFGEN_RSTAT)\n+#define ICE_READ_REG(hw, reg) ice_read_addr(ICE_PCI_REG_ADDR((hw), (reg)))\n+#define ICE_WRITE_REG(hw, reg, value) \\\n+\tICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((hw), (reg)), (value))\n+\n+#define rd32(a, reg) ice_read_addr(ICE_PCI_REG_ADDR((a), (reg)))\n+#define wr32(a, reg, value) \\\n+\tICE_PCI_REG_WRITE(ICE_PCI_REG_ADDR((a), (reg)), (value))\n+#define flush(a) ice_read_addr(ICE_PCI_REG_ADDR((a), (GLGEN_STAT)))\n+#define div64_long(n, d) ((n) / (d))\n+\n+typedef u8 ice_bitmap_t;\n+#define ice_declare_bitmap(name, bits) \\\n+\tunsigned long name[BITS_TO_LONGS(bits)]\n+\n+#define BITS_TO_LONGS(nr)   DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))\n+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n+#define BITS_PER_BYTE       8\n+#define BITS_CHUNK_MASK(nr)\t(((ice_bitmap_t)~0) >>\t\t\t\\\n+\t\t((BITS_PER_BYTE * sizeof(ice_bitmap_t)) -\t\t\\\n+\t\t(((nr) - 1) % (BITS_PER_BYTE * sizeof(ice_bitmap_t))\t\\\n+\t\t + 1)))\n+#define ice_is_bit_set(name, bits) \\\n+\t((name)[BITS_TO_LONGS(bits)] & 1)\n+#define ice_and_bitmap(d, b1, b2, sz) \\\n+\tice_intersect_bitmaps((u8 *)d, (u8 *)b1, (const u8 *)b2, (u16)sz)\n+static inline int\n+ice_intersect_bitmaps(u8 *dst, const u8 *bmp1, const u8 *bmp2, u16 sz)\n+{\n+\tu32 res = 0;\n+\tint cnt;\n+\tu16 i;\n+\n+\t/* Utilize 32-bit operations */\n+\tcnt = (sz % BITS_PER_BYTE) ?\n+\t\t(sz / BITS_PER_BYTE) + 1 : sz / BITS_PER_BYTE;\n+\tfor (i = 0; i < cnt / 4; i++) {\n+\t\t((u32 *)dst)[i] = ((const u32 *)bmp1)[i] &\n+\t\t((const u32 *)bmp2)[i];\n+\t\tres |= ((u32 *)dst)[i];\n+\t}\n+\n+\tfor (i *= 4; i < cnt; i++) {\n+\t\tif ((sz % 8 == 0) || (i + 1 < cnt)) {\n+\t\t\tdst[i] = bmp1[i] & bmp2[i];\n+\t\t} else {\n+\t\t\t/* Remaining bits that do not occupy the whole byte */\n+\t\t\tu8 mask = ~0u >> (8 - (sz % 8));\n+\n+\t\t\tdst[i] = bmp1[i] & bmp2[i] & mask;\n+\t\t}\n+\n+\t\tres |= dst[i];\n+\t}\n+\n+\treturn res != 0;\n+}\n+\n+static inline int ice_find_first_bit(unsigned long *name, u16 size)\n+{\n+\tu16 i;\n+\n+\tfor (i = 0; i < BITS_PER_BYTE * (size / BITS_PER_BYTE); i++)\n+\t\tif (ice_is_bit_set(name, i))\n+\t\t\treturn i;\n+\treturn size;\n+}\n+\n+static inline int ice_find_next_bit(unsigned long *name, u16 size, u16 bits)\n+{\n+\tu16 i;\n+\n+\tfor (i = bits; i < BITS_PER_BYTE * (size / BITS_PER_BYTE); i++)\n+\t\tif (ice_is_bit_set(name, i))\n+\t\t\treturn i;\n+\treturn bits;\n+}\n+\n+#define for_each_set_bit(bit, addr, size)\t\t\t\t\\\n+\tfor ((bit) = ice_find_first_bit((addr), (size));\t\t\\\n+\t(bit) < (size);\t\t\t\t\t\t\t\\\n+\t(bit) = ice_find_next_bit((addr), (size), (bit) + 1))\n+\n+#ifndef LINUX_SUPPORT\n+static inline bool ice_is_any_bit_set(u8 *bitmap, u32 bits)\n+#else\n+static inline bool ice_is_any_bit_set(unsigned long *bitmap, u32 bits)\n+#endif\n+{\n+#ifndef LINUX_SUPPORT\n+\tu32 max_index = (bits % 8) ? (bits / 8) + 1 : (bits / 8);\n+#else\n+\tu32 max_index = BITS_TO_LONGS(bits);\n+#endif\n+\tu32 i;\n+\n+\tfor (i = 0; i < max_index; i++) {\n+\t\tif (bitmap[i])\n+\t\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+/* memory allocation tracking */\n+struct ice_dma_mem {\n+\tvoid *va;\n+\tu64 pa;\n+\tu32 size;\n+\tconst void *zone;\n+} __attribute__((packed));\n+\n+struct ice_virt_mem {\n+\tvoid *va;\n+\tu32 size;\n+} __attribute__((packed));\n+\n+#define ice_malloc(h, s)    rte_zmalloc(\"ice\", s, 0)\n+#define ice_calloc(h, c, s) rte_zmalloc(\"ice\", c * s, 0)\n+#define ice_free(h, m)         rte_free(m)\n+\n+#define ice_memset(a, b, c, d) memset((a), (b), (c))\n+#define ice_memcpy(a, b, c, d) rte_memcpy((a), (b), (c))\n+#define ice_memdup(a, b, c, d) rte_memcpy(ice_malloc(a, c), b, c)\n+\n+#define CPU_TO_BE16(o) rte_cpu_to_be_16(o)\n+#define CPU_TO_BE32(o) rte_cpu_to_be_32(o)\n+#define CPU_TO_BE64(o) rte_cpu_to_be_64(o)\n+#define CPU_TO_LE16(o) rte_cpu_to_le_16(o)\n+#define CPU_TO_LE32(s) rte_cpu_to_le_32(s)\n+#define CPU_TO_LE64(h) rte_cpu_to_le_64(h)\n+#define LE16_TO_CPU(a) rte_le_to_cpu_16(a)\n+#define LE32_TO_CPU(c) rte_le_to_cpu_32(c)\n+#define LE64_TO_CPU(k) rte_le_to_cpu_64(k)\n+\n+#define NTOHS(a) rte_be_to_cpu_16(a)\n+#define NTOHL(a) rte_be_to_cpu_32(a)\n+#define HTONS(a) rte_cpu_to_be_16(a)\n+#define HTONL(a) rte_cpu_to_be_32(a)\n+\n+static inline void\n+ice_set_bit(unsigned int nr, volatile unsigned long *addr)\n+{\n+\t__sync_fetch_and_or(addr, (1UL << nr));\n+}\n+\n+static inline void\n+ice_clear_bit(unsigned int nr, volatile unsigned long *addr)\n+{\n+\t__sync_fetch_and_and(addr, (0UL << nr));\n+}\n+\n+static inline void\n+ice_zero_bitmap(unsigned long *bmp, u16 size)\n+{\n+\tunsigned long mask;\n+\tu16 i;\n+\n+\tfor (i = 0; i < BITS_TO_LONGS(size) - 1; i++)\n+\t\tbmp[i] = 0;\n+\tmask = BITS_CHUNK_MASK(size);\n+\tbmp[i] &= ~mask;\n+}\n+\n+static inline void\n+ice_or_bitmap(unsigned long *dst, const unsigned long *bmp1,\n+\t      const unsigned long *bmp2, u16 size)\n+{\n+\tunsigned long mask;\n+\tu16 i;\n+\n+\t/* Handle all but last chunk*/\n+\tfor (i = 0; i < BITS_TO_LONGS(size) - 1; i++)\n+\t\tdst[i] = bmp1[i] | bmp2[i];\n+\n+\t/* We want to only OR bits within the size. Furthermore, we also do\n+\t * not want to modify destination bits which are beyond the specified\n+\t * size. Use a bitmask to ensure that we only modify the bits that are\n+\t * within the specified size.\n+\t */\n+\tmask = BITS_CHUNK_MASK(size);\n+\tdst[i] &= ~mask;\n+\tdst[i] |= (bmp1[i] | bmp2[i]) & mask;\n+}\n+\n+/* SW spinlock */\n+struct ice_lock {\n+\trte_spinlock_t spinlock;\n+};\n+\n+static inline void\n+ice_init_lock(struct ice_lock *sp)\n+{\n+\trte_spinlock_init(&sp->spinlock);\n+}\n+\n+static inline void\n+ice_acquire_lock(struct ice_lock *sp)\n+{\n+\trte_spinlock_lock(&sp->spinlock);\n+}\n+\n+static inline void\n+ice_release_lock(struct ice_lock *sp)\n+{\n+\trte_spinlock_unlock(&sp->spinlock);\n+}\n+\n+static inline void\n+ice_destroy_lock(__attribute__((unused)) struct ice_lock *sp)\n+{\n+}\n+\n+struct ice_hw;\n+\n+static inline void *\n+ice_alloc_dma_mem(__attribute__((unused)) struct ice_hw *hw,\n+\t\t  struct ice_dma_mem *mem, u64 size)\n+{\n+\tconst struct rte_memzone *mz = NULL;\n+\tchar z_name[RTE_MEMZONE_NAMESIZE];\n+\n+\tif (!mem)\n+\t\treturn NULL;\n+\n+\tsnprintf(z_name, sizeof(z_name), \"ice_dma_%\"PRIu64, rte_rand());\n+\tmz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,\n+\t\t\t\t\t 0, RTE_PGSIZE_2M);\n+\tif (!mz)\n+\t\treturn NULL;\n+\n+\tmem->size = size;\n+\tmem->va = mz->addr;\n+\tmem->pa = mz->phys_addr;\n+\tmem->zone = (const void *)mz;\n+\tPMD_DRV_LOG(DEBUG, \"memzone %s allocated with physical address: \"\n+\t\t    \"%\"PRIu64, mz->name, mem->pa);\n+\n+\treturn mem->va;\n+}\n+\n+static inline void\n+ice_free_dma_mem(__attribute__((unused)) struct ice_hw *hw,\n+\t\t struct ice_dma_mem *mem)\n+{\n+\tPMD_DRV_LOG(DEBUG, \"memzone %s to be freed with physical address: \"\n+\t\t    \"%\"PRIu64, ((const struct rte_memzone *)mem->zone)->name,\n+\t\t    mem->pa);\n+\trte_memzone_free((const struct rte_memzone *)mem->zone);\n+\tmem->zone = NULL;\n+\tmem->va = NULL;\n+\tmem->pa = (u64)0;\n+}\n+\n+static inline u8\n+ice_hweight8(u32 num)\n+{\n+\tu8 bits = 0;\n+\tu32 i;\n+\n+\tfor (i = 0; i < 8; i++) {\n+\t\tbits += (u8)(num & 0x1);\n+\t\tnum >>= 1;\n+\t}\n+\n+\treturn bits;\n+}\n+\n+#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n+#define DELAY(x) rte_delay_us(x)\n+#define ice_usec_delay(x) rte_delay_us(x)\n+#define ice_msec_delay(x, y) rte_delay_us(1000 * (x))\n+#define udelay(x) DELAY(x)\n+#define msleep(x) DELAY(1000 * (x))\n+#define usleep_range(min, max) msleep(DIV_ROUND_UP(min, 1000))\n+\n+struct ice_list_entry {\n+\tLIST_ENTRY(ice_list_entry) next;\n+};\n+\n+LIST_HEAD(ice_list_head, ice_list_entry);\n+\n+#define LIST_ENTRY_TYPE    ice_list_entry\n+#define LIST_HEAD_TYPE     ice_list_head\n+#define INIT_LIST_HEAD(list_head)  LIST_INIT(list_head)\n+#define LIST_DEL(entry)            LIST_REMOVE(entry, next)\n+/* LIST_EMPTY(list_head)) the same in sys/queue.h */\n+\n+/*Note parameters are swapped*/\n+#define LIST_FIRST_ENTRY(head, type, field) (type *)((head)->lh_first)\n+#define LIST_ADD(entry, list_head)    LIST_INSERT_HEAD(list_head, entry, next)\n+#define LIST_ADD_AFTER(entry, list_entry) \\\n+\tLIST_INSERT_AFTER(list_entry, entry, next)\n+#define LIST_FOR_EACH_ENTRY(pos, head, type, member)\t\t\t       \\\n+\tfor ((pos) = (head)->lh_first ?\t\t\t\t\t       \\\n+\t\t     container_of((head)->lh_first, struct type, member) :     \\\n+\t\t     0;\t\t\t\t\t\t\t       \\\n+\t     (pos);\t\t\t\t\t\t\t       \\\n+\t     (pos) = (pos)->member.next.le_next ?\t\t\t       \\\n+\t\t     container_of((pos)->member.next.le_next, struct type,     \\\n+\t\t\t\t  member) :\t\t\t\t       \\\n+\t\t     0)\n+\n+#define LIST_REPLACE_INIT(list_head, head) do {\t\t\t\t\\\n+\t(head)->lh_first = (list_head)->lh_first;\t\t\t\\\n+\tINIT_LIST_HEAD(list_head);\t\t\t\t\t\\\n+} while (0)\n+\n+#define HLIST_NODE_TYPE         LIST_ENTRY_TYPE\n+#define HLIST_HEAD_TYPE         LIST_HEAD_TYPE\n+#define INIT_HLIST_HEAD(list_head)             INIT_LIST_HEAD(list_head)\n+#define HLIST_ADD_HEAD(entry, list_head)       LIST_ADD(entry, list_head)\n+#define HLIST_EMPTY(list_head)                 LIST_EMPTY(list_head)\n+#define HLIST_DEL(entry)                       LIST_DEL(entry)\n+#define HLIST_FOR_EACH_ENTRY(pos, head, type, member) \\\n+\tLIST_FOR_EACH_ENTRY(pos, head, type, member)\n+#define LIST_FOR_EACH_ENTRY_SAFE(pos, tmp, head, type, member) \\\n+\tLIST_FOR_EACH_ENTRY(pos, head, type, member)\n+\n+#ifndef ICE_DBG_TRACE\n+#define ICE_DBG_TRACE\t\tBIT_ULL(0)\n+#endif\n+\n+#ifndef DIVIDE_AND_ROUND_UP\n+#define DIVIDE_AND_ROUND_UP(a, b) (((a) + (b) - 1) / (b))\n+#endif\n+\n+#ifndef ICE_INTEL_VENDOR_ID\n+#define ICE_INTEL_VENDOR_ID\t\t0x8086\n+#endif\n+\n+#ifndef IS_UNICAST_ETHER_ADDR\n+#define IS_UNICAST_ETHER_ADDR(addr) \\\n+\t((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 0))\n+#endif\n+\n+#ifndef IS_MULTICAST_ETHER_ADDR\n+#define IS_MULTICAST_ETHER_ADDR(addr) \\\n+\t((bool)((((u8 *)(addr))[0] % ((u8)0x2)) == 1))\n+#endif\n+\n+#ifndef IS_BROADCAST_ETHER_ADDR\n+/* Check whether an address is broadcast. */\n+#define IS_BROADCAST_ETHER_ADDR(addr)\t\\\n+\t((bool)((((u16 *)(addr))[0] == ((u16)0xffff))))\n+#endif\n+\n+#ifndef IS_ZERO_ETHER_ADDR\n+#define IS_ZERO_ETHER_ADDR(addr) \\\n+\t(((bool)((((u16 *)(addr))[0] == ((u16)0x0)))) && \\\n+\t ((bool)((((u16 *)(addr))[1] == ((u16)0x0)))) && \\\n+\t ((bool)((((u16 *)(addr))[2] == ((u16)0x0)))))\n+#endif\n+\n+#endif /* _ICE_OSDEP_H_ */\ndiff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h\nnew file mode 100644\nindex 0000000..665856a\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_protocol_type.h\n@@ -0,0 +1,237 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_PROTOCOL_TYPE_H_\n+#define _ICE_PROTOCOL_TYPE_H_\n+#include \"ice_flex_type.h\"\n+#define ICE_IPV6_ADDR_LENGTH 16\n+\n+/* Each recipe can match up to 5 different fields. Fields to match can be meta-\n+ * data, values extracted from packet headers, or results from other recipes.\n+ * One of the 5 fields is reserved for matching the switch ID. So, up to 4\n+ * recipes can provide intermediate results to another one through chaining,\n+ * e.g. recipes 0, 1, 2, and 3 can provide intermediate results to recipe 4.\n+ */\n+#define ICE_NUM_WORDS_RECIPE 4\n+\n+/* Max recipes that can be chained */\n+#define ICE_MAX_CHAIN_RECIPE 5\n+\n+/* 1 word reserved for switch id from allowed 5 words.\n+ * So a recipe can have max 4 words. And you can chain 5 such recipes\n+ * together. So maximum words that can be programmed for look up is 5 * 4.\n+ */\n+#define ICE_MAX_CHAIN_WORDS (ICE_NUM_WORDS_RECIPE * ICE_MAX_CHAIN_RECIPE)\n+\n+/* Field vector index corresponding to chaining */\n+#define ICE_CHAIN_FV_INDEX_START 47\n+\n+enum ice_protocol_type {\n+\tICE_MAC_OFOS = 0,\n+\tICE_MAC_IL,\n+\tICE_IPV4_OFOS,\n+\tICE_IPV4_IL,\n+\tICE_IPV6_IL,\n+\tICE_IPV6_OFOS,\n+\tICE_TCP_IL,\n+\tICE_UDP_ILOS,\n+\tICE_SCTP_IL,\n+\tICE_VXLAN,\n+\tICE_GENEVE,\n+\tICE_VXLAN_GPE,\n+\tICE_NVGRE,\n+\tICE_PROTOCOL_LAST\n+};\n+\n+enum ice_sw_tunnel_type {\n+\tICE_NON_TUN,\n+\tICE_SW_TUN_VXLAN_GPE,\n+\tICE_SW_TUN_GENEVE,\n+\tICE_SW_TUN_VXLAN,\n+\tICE_SW_TUN_NVGRE,\n+\tICE_SW_TUN_UDP, /* This means all \"UDP\" tunnel types: VXLAN-GPE, VXLAN\n+\t\t\t * and GENEVE\n+\t\t\t */\n+\tICE_ALL_TUNNELS /* All tunnel types including NVGRE */\n+};\n+\n+/* Decoders for ice_prot_id:\n+ * - F: First\n+ * - I: Inner\n+ * - L: Last\n+ * - O: Outer\n+ * - S: Single\n+ */\n+enum ice_prot_id {\n+\tICE_PROT_ID_INVAL\t= 0,\n+\tICE_PROT_MAC_OF_OR_S\t= 1,\n+\tICE_PROT_MAC_O2\t\t= 2,\n+\tICE_PROT_MAC_IL\t\t= 4,\n+\tICE_PROT_MAC_IN_MAC\t= 7,\n+\tICE_PROT_ETYPE_OL\t= 9,\n+\tICE_PROT_ETYPE_IL\t= 10,\n+\tICE_PROT_PAY\t\t= 15,\n+\tICE_PROT_EVLAN_O\t= 16,\n+\tICE_PROT_VLAN_O\t\t= 17,\n+\tICE_PROT_VLAN_IF\t= 18,\n+\tICE_PROT_MPLS_OL_MINUS_1 = 27,\n+\tICE_PROT_MPLS_OL_OR_OS\t= 28,\n+\tICE_PROT_MPLS_IL\t= 29,\n+\tICE_PROT_IPV4_OF_OR_S\t= 32,\n+\tICE_PROT_IPV4_IL\t= 33,\n+\tICE_PROT_IPV6_OF_OR_S\t= 40,\n+\tICE_PROT_IPV6_IL\t= 41,\n+\tICE_PROT_IPV6_FRAG\t= 47,\n+\tICE_PROT_TCP_IL\t\t= 49,\n+\tICE_PROT_UDP_OF\t\t= 52,\n+\tICE_PROT_UDP_IL_OR_S\t= 53,\n+\tICE_PROT_GRE_OF\t\t= 64,\n+\tICE_PROT_NSH_F\t\t= 84,\n+\tICE_PROT_ESP_F\t\t= 88,\n+\tICE_PROT_ESP_2\t\t= 89,\n+\tICE_PROT_SCTP_IL\t= 96,\n+\tICE_PROT_ICMP_IL\t= 98,\n+\tICE_PROT_ICMPV6_IL\t= 100,\n+\tICE_PROT_VRRP_F\t\t= 101,\n+\tICE_PROT_OSPF\t\t= 102,\n+\tICE_PROT_ATAOE_OF\t= 114,\n+\tICE_PROT_CTRL_OF\t= 116,\n+\tICE_PROT_LLDP_OF\t= 117,\n+\tICE_PROT_ARP_OF\t\t= 118,\n+\tICE_PROT_EAPOL_OF\t= 120,\n+\tICE_PROT_META_ID\t= 255, /* when offset == metaddata */\n+\tICE_PROT_INVALID\t= 255  /* when offset == 0xFF */\n+};\n+\n+\n+#define ICE_MAC_OFOS_HW\t\t1\n+#define ICE_MAC_IL_HW\t\t4\n+#define ICE_IPV4_OFOS_HW\t32\n+#define ICE_IPV4_IL_HW\t\t33\n+#define ICE_IPV6_OFOS_HW\t40\n+#define ICE_IPV6_IL_HW\t\t41\n+#define ICE_TCP_IL_HW\t\t49\n+#define ICE_UDP_ILOS_HW\t\t53\n+#define ICE_SCTP_IL_HW\t\t96\n+\n+/* ICE_UDP_OF is used to identify all 3 tunnel types\n+ * VXLAN, GENEVE and VXLAN_GPE. To differentiate further\n+ * need to use flags from the field vector\n+ */\n+#define ICE_UDP_OF_HW\t52 /* UDP Tunnels */\n+#define ICE_GRE_OF_HW\t64 /* NVGRE */\n+#define ICE_META_DATA_ID_HW 255 /* this is used for tunnel type */\n+\n+#define ICE_TUN_FLAG_MASK 0xFF\n+#define ICE_TUN_FLAG_FV_IND 2\n+\n+#define ICE_PROTOCOL_MAX_ENTRIES 16\n+\n+/* Mapping of software defined protocol id to hardware defined protocol id */\n+struct ice_protocol_entry {\n+\tenum ice_protocol_type type;\n+\tu8 protocol_id;\n+};\n+\n+\n+struct ice_ether_hdr {\n+\tu8 dst_addr[ETH_ALEN];\n+\tu8 src_addr[ETH_ALEN];\n+\tu16 ethtype_id;\n+};\n+\n+struct ice_ether_vlan_hdr {\n+\tu8 dst_addr[ETH_ALEN];\n+\tu8 src_addr[ETH_ALEN];\n+\tu32 vlan_id;\n+};\n+\n+struct ice_ipv4_hdr {\n+\tu8 version;\n+\tu8 tos;\n+\tu16 total_length;\n+\tu16 id;\n+\tu16 frag_off;\n+\tu8 time_to_live;\n+\tu8 protocol;\n+\tu16 check;\n+\tu32 src_addr;\n+\tu32 dst_addr;\n+};\n+\n+struct ice_ipv6_hdr {\n+\tu8 version;\n+\tu8 tc;\n+\tu16 flow_label;\n+\tu8 src_addr[ICE_IPV6_ADDR_LENGTH];\n+\tu8 dst_addr[ICE_IPV6_ADDR_LENGTH];\n+};\n+\n+struct ice_l4_hdr {\n+\tu16 src_port;\n+\tu16 dst_port;\n+\tu16 len;\n+\tu16 check;\n+};\n+\n+struct ice_udp_tnl_hdr {\n+\tu16 field;\n+\tu16 proto_type;\n+\tu16 vni;\n+};\n+\n+struct ice_nvgre {\n+\tu16 tni;\n+\tu16 flow_id;\n+};\n+\n+union ice_prot_hdr {\n+\t\tstruct ice_ether_hdr eth_hdr;\n+\t\tstruct ice_ipv4_hdr ipv4_hdr;\n+\t\tstruct ice_ipv6_hdr ice_ipv6_ofos_hdr;\n+\t\tstruct ice_l4_hdr l4_hdr;\n+\t\tstruct ice_udp_tnl_hdr tnl_hdr;\n+\t\tstruct ice_nvgre nvgre_hdr;\n+};\n+\n+/* This is mapping table entry that maps every word within a given protocol\n+ * structure to the real byte offset as per the specification of that\n+ * protocol header.\n+ * for e.g. dst address is 3 words in ethertype header and corresponding bytes\n+ * are 0, 2, 3 in the actual packet header and src address is at 4, 6, 8\n+ */\n+struct ice_prot_ext_tbl_entry {\n+\tenum ice_protocol_type prot_type;\n+\t/* Byte offset into header of given protocol type */\n+\tu8 offs[sizeof(union ice_prot_hdr)];\n+};\n+\n+/* Extractions to be looked up for a given recipe */\n+struct ice_prot_lkup_ext {\n+\tu16 prot_type;\n+\tu8 n_val_words;\n+\t/* create a buffer to hold max words per recipe */\n+\tu8 field_off[ICE_MAX_CHAIN_WORDS];\n+\n+\tstruct ice_fv_word fv_words[ICE_MAX_CHAIN_WORDS];\n+\n+\t/* Indicate field offsets that have field vector indices assigned */\n+\tice_declare_bitmap(done, ICE_MAX_CHAIN_WORDS);\n+};\n+\n+struct ice_pref_recipe_group {\n+\tu8 n_val_pairs;\t\t/* Number of valid pairs */\n+\tstruct ice_fv_word pairs[ICE_NUM_WORDS_RECIPE];\n+};\n+\n+struct ice_recp_grp_entry {\n+\tstruct LIST_ENTRY_TYPE l_entry;\n+\n+#define ICE_INVAL_CHAIN_IND 0xFF\n+\tu16 rid;\n+\tu8 chain_idx;\n+\tu16 fv_idx[ICE_NUM_WORDS_RECIPE];\n+\tstruct ice_pref_recipe_group r_group;\n+};\n+#endif /* _ICE_PROTOCOL_TYPE_H_ */\ndiff --git a/drivers/net/ice/base/ice_sbq_cmd.h b/drivers/net/ice/base/ice_sbq_cmd.h\nnew file mode 100644\nindex 0000000..6dff378\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_sbq_cmd.h\n@@ -0,0 +1,93 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_SBQ_CMD_H_\n+#define _ICE_SBQ_CMD_H_\n+\n+/* This header file defines the Sideband Queue commands, error codes and\n+ * descriptor format. It is shared between Firmware and Software.\n+ */\n+\n+/* Sideband Queue command structure and opcodes */\n+enum ice_sbq_opc {\n+\t/* Sideband Queue commands */\n+\tice_sbq_opc_neigh_dev_req\t\t\t= 0x0C00,\n+\tice_sbq_opc_neigh_dev_ev\t\t\t= 0x0C01\n+};\n+\n+/* Sideband Queue descriptor. Indirect command\n+ * and non posted\n+ */\n+struct ice_sbq_cmd_desc {\n+\t__le16 flags;\n+\t__le16 opcode;\n+\t__le16 datalen;\n+\t__le16 cmd_retval;\n+\n+\t/* Opaque message data */\n+\t__le32 cookie_high;\n+\t__le32 cookie_low;\n+\n+\tunion {\n+\t\t__le16 cmd_len;\n+\t\t__le16 cmpl_len;\n+\t} param0;\n+\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+struct ice_sbq_evt_desc {\n+\t__le16 flags;\n+\t__le16 opcode;\n+\t__le16 datalen;\n+\t__le16 cmd_retval;\n+\tu8 data[24];\n+};\n+\n+enum ice_sbq_msg_dev {\n+\trmn_0\t= 0x02,\n+\trmn_1\t= 0x03,\n+\trmn_2\t= 0x04,\n+\tcgu\t= 0x06\n+};\n+\n+enum ice_sbq_msg_opcode {\n+\tice_sbq_msg_rd\t= 0x00,\n+\tice_sbq_msg_wr\t= 0x01\n+};\n+\n+#define ICE_SBQ_MSG_FLAGS\t0x40\n+#define ICE_SBQ_MSG_SBE_FBE\t0x0F\n+\n+struct ice_sbq_msg_req {\n+\tu8 dest_dev;\n+\tu8 src_dev;\n+\tu8 opcode;\n+\tu8 flags;\n+\tu8 sbe_fbe;\n+\tu8 func_id;\n+\t__le16 msg_addr_low;\n+\t__le32 msg_addr_high;\n+\t__le32 data;\n+};\n+\n+struct ice_sbq_msg_cmpl {\n+\tu8 dest_dev;\n+\tu8 src_dev;\n+\tu8 opcode;\n+\tu8 flags;\n+\t__le32 data;\n+};\n+\n+/* Internal struct */\n+struct ice_sbq_msg_input {\n+\tu8 dest_dev;\n+\tu8 opcode;\n+\tu16 msg_addr_low;\n+\tu32 msg_addr_high;\n+\tu32 data;\n+};\n+#endif /* _ICE_SBQ_CMD_H_ */\ndiff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nnew file mode 100644\nindex 0000000..662d136\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -0,0 +1,1715 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_sched.h\"\n+\n+\n+/**\n+ * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB\n+ * @pi: port information structure\n+ * @info: Scheduler element information from firmware\n+ *\n+ * This function inserts the root node of the scheduling tree topology\n+ * to the SW DB.\n+ */\n+static enum ice_status\n+ice_sched_add_root_node(struct ice_port_info *pi,\n+\t\t\tstruct ice_aqc_txsched_elem_data *info)\n+{\n+\tstruct ice_sched_node *root;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\thw = pi->hw;\n+\n+\troot = (struct ice_sched_node *)ice_malloc(hw, sizeof(*root));\n+\tif (!root)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t/* coverity[suspicious_sizeof] */\n+\troot->children = (struct ice_sched_node **)\n+\t\tice_calloc(hw, hw->max_children[0], sizeof(*root));\n+\tif (!root->children) {\n+\t\tice_free(hw, root);\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\t}\n+\n+\tice_memcpy(&root->info, info, sizeof(*info), ICE_DMA_TO_NONDMA);\n+\tpi->root = root;\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_find_node_by_teid - Find the Tx scheduler node in SW DB\n+ * @start_node: pointer to the starting ice_sched_node struct in a sub-tree\n+ * @teid: node teid to search\n+ *\n+ * This function searches for a node matching the teid in the scheduling tree\n+ * from the SW DB. The search is recursive and is restricted by the number of\n+ * layers it has searched through; stopping at the max supported layer.\n+ *\n+ * This function needs to be called when holding the port_info->sched_lock\n+ */\n+struct ice_sched_node *\n+ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid)\n+{\n+\tu16 i;\n+\n+\t/* The TEID is same as that of the start_node */\n+\tif (ICE_TXSCHED_GET_NODE_TEID(start_node) == teid)\n+\t\treturn start_node;\n+\n+\t/* The node has no children or is at the max layer */\n+\tif (!start_node->num_children ||\n+\t    start_node->tx_sched_layer >= ICE_AQC_TOPO_MAX_LEVEL_NUM ||\n+\t    start_node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF)\n+\t\treturn NULL;\n+\n+\t/* Check if teid matches to any of the children nodes */\n+\tfor (i = 0; i < start_node->num_children; i++)\n+\t\tif (ICE_TXSCHED_GET_NODE_TEID(start_node->children[i]) == teid)\n+\t\t\treturn start_node->children[i];\n+\n+\t/* Search within each child's sub-tree */\n+\tfor (i = 0; i < start_node->num_children; i++) {\n+\t\tstruct ice_sched_node *tmp;\n+\n+\t\ttmp = ice_sched_find_node_by_teid(start_node->children[i],\n+\t\t\t\t\t\t  teid);\n+\t\tif (tmp)\n+\t\t\treturn tmp;\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_aqc_send_sched_elem_cmd - send scheduling elements cmd\n+ * @hw: pointer to the hw struct\n+ * @cmd_opc: cmd opcode\n+ * @elems_req: number of elements to request\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @elems_resp: returns total number of elements response\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * This function sends a scheduling elements cmd (cmd_opc)\n+ */\n+static enum ice_status\n+ice_aqc_send_sched_elem_cmd(struct ice_hw *hw, enum ice_adminq_opc cmd_opc,\n+\t\t\t    u16 elems_req, void *buf, u16 buf_size,\n+\t\t\t    u16 *elems_resp, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_sched_elem_cmd *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.sched_elem_cmd;\n+\tice_fill_dflt_direct_cmd_desc(&desc, cmd_opc);\n+\tcmd->num_elem_req = CPU_TO_LE16(elems_req);\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (!status && elems_resp)\n+\t\t*elems_resp = LE16_TO_CPU(cmd->num_elem_resp);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_query_sched_elems - query scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @elems_req: number of elements to query\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @elems_ret: returns total number of elements returned\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Query scheduling elements (0x0404)\n+ */\n+static enum ice_status\n+ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,\n+\t\t\t struct ice_aqc_get_elem *buf, u16 buf_size,\n+\t\t\t u16 *elems_ret, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_get_sched_elems,\n+\t\t\t\t\t   elems_req, (void *)buf, buf_size,\n+\t\t\t\t\t   elems_ret, cd);\n+}\n+\n+/**\n+ * ice_sched_query_elem - query element information from hw\n+ * @hw: pointer to the hw struct\n+ * @node_teid: node teid to be queried\n+ * @buf: buffer to element information\n+ *\n+ * This function queries HW element information\n+ */\n+static enum ice_status\n+ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,\n+\t\t     struct ice_aqc_get_elem *buf)\n+{\n+\tu16 buf_size, num_elem_ret = 0;\n+\tenum ice_status status;\n+\n+\tbuf_size = sizeof(*buf);\n+\tice_memset(buf, 0, buf_size, ICE_NONDMA_MEM);\n+\tbuf->generic[0].node_teid = CPU_TO_LE32(node_teid);\n+\tstatus = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,\n+\t\t\t\t\t  NULL);\n+\tif (status != ICE_SUCCESS || num_elem_ret != 1)\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"query element failed\\n\");\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_add_node - Insert the Tx scheduler node in SW DB\n+ * @pi: port information structure\n+ * @layer: Scheduler layer of the node\n+ * @info: Scheduler element information from firmware\n+ *\n+ * This function inserts a scheduler node to the SW DB.\n+ */\n+enum ice_status\n+ice_sched_add_node(struct ice_port_info *pi, u8 layer,\n+\t\t   struct ice_aqc_txsched_elem_data *info)\n+{\n+\tstruct ice_sched_node *parent;\n+\tstruct ice_aqc_get_elem elem;\n+\tstruct ice_sched_node *node;\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\thw = pi->hw;\n+\n+\t/* A valid parent node should be there */\n+\tparent = ice_sched_find_node_by_teid(pi->root,\n+\t\t\t\t\t     LE32_TO_CPU(info->parent_teid));\n+\tif (!parent) {\n+\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t  \"Parent Node not found for parent_teid=0x%x\\n\",\n+\t\t\t  LE32_TO_CPU(info->parent_teid));\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\t/* query the current node information from FW  before additing it\n+\t * to the SW DB\n+\t */\n+\tstatus = ice_sched_query_elem(hw, LE32_TO_CPU(info->node_teid), &elem);\n+\tif (status)\n+\t\treturn status;\n+\tnode = (struct ice_sched_node *)ice_malloc(hw, sizeof(*node));\n+\tif (!node)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\tif (hw->max_children[layer]) {\n+\t\t/* coverity[suspicious_sizeof] */\n+\t\tnode->children = (struct ice_sched_node **)\n+\t\t\tice_calloc(hw, hw->max_children[layer], sizeof(*node));\n+\t\tif (!node->children) {\n+\t\t\tice_free(hw, node);\n+\t\t\treturn ICE_ERR_NO_MEMORY;\n+\t\t}\n+\t}\n+\n+\tnode->in_use = true;\n+\tnode->parent = parent;\n+\tnode->tx_sched_layer = layer;\n+\tparent->children[parent->num_children++] = node;\n+\tnode->info = elem.generic[0];\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_aq_delete_sched_elems - delete scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @grps_req: number of groups to delete\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @grps_del: returns total number of elements deleted\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Delete scheduling elements (0x040F)\n+ */\n+static enum ice_status\n+ice_aq_delete_sched_elems(struct ice_hw *hw, u16 grps_req,\n+\t\t\t  struct ice_aqc_delete_elem *buf, u16 buf_size,\n+\t\t\t  u16 *grps_del, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_delete_sched_elems,\n+\t\t\t\t\t   grps_req, (void *)buf, buf_size,\n+\t\t\t\t\t   grps_del, cd);\n+}\n+\n+/**\n+ * ice_sched_remove_elems - remove nodes from hw\n+ * @hw: pointer to the hw struct\n+ * @parent: pointer to the parent node\n+ * @num_nodes: number of nodes\n+ * @node_teids: array of node teids to be deleted\n+ *\n+ * This function remove nodes from hw\n+ */\n+static enum ice_status\n+ice_sched_remove_elems(struct ice_hw *hw, struct ice_sched_node *parent,\n+\t\t       u16 num_nodes, u32 *node_teids)\n+{\n+\tstruct ice_aqc_delete_elem *buf;\n+\tu16 i, num_groups_removed = 0;\n+\tenum ice_status status;\n+\tu16 buf_size;\n+\n+\tbuf_size = sizeof(*buf) + sizeof(u32) * (num_nodes - 1);\n+\tbuf = (struct ice_aqc_delete_elem *)ice_malloc(hw, buf_size);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tbuf->hdr.parent_teid = parent->info.node_teid;\n+\tbuf->hdr.num_elems = CPU_TO_LE16(num_nodes);\n+\tfor (i = 0; i < num_nodes; i++)\n+\t\tbuf->teid[i] = CPU_TO_LE32(node_teids[i]);\n+\n+\tstatus = ice_aq_delete_sched_elems(hw, 1, buf, buf_size,\n+\t\t\t\t\t   &num_groups_removed, NULL);\n+\tif (status != ICE_SUCCESS || num_groups_removed != 1)\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"remove elements failed\\n\");\n+\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_get_first_node - get the first node of the given layer\n+ * @hw: pointer to the hw struct\n+ * @parent: pointer the base node of the subtree\n+ * @layer: layer number\n+ *\n+ * This function retrieves the first node of the given layer from the subtree\n+ */\n+static struct ice_sched_node *\n+ice_sched_get_first_node(struct ice_hw *hw, struct ice_sched_node *parent,\n+\t\t\t u8 layer)\n+{\n+\tu8 i;\n+\n+\tif (layer < hw->sw_entry_point_layer)\n+\t\treturn NULL;\n+\tfor (i = 0; i < parent->num_children; i++) {\n+\t\tstruct ice_sched_node *node = parent->children[i];\n+\n+\t\tif (node) {\n+\t\t\tif (node->tx_sched_layer == layer)\n+\t\t\t\treturn node;\n+\t\t\t/* this recursion is intentional, and wouldn't\n+\t\t\t * go more than 9 calls\n+\t\t\t */\n+\t\t\treturn ice_sched_get_first_node(hw, node, layer);\n+\t\t}\n+\t}\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_sched_get_tc_node - get pointer to TC node\n+ * @pi: port information structure\n+ * @tc: TC number\n+ *\n+ * This function returns the TC node pointer\n+ */\n+struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc)\n+{\n+\tu8 i;\n+\n+\tif (!pi)\n+\t\treturn NULL;\n+\tfor (i = 0; i < pi->root->num_children; i++)\n+\t\tif (pi->root->children[i]->tc_num == tc)\n+\t\t\treturn pi->root->children[i];\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_free_sched_node - Free a Tx scheduler node from SW DB\n+ * @pi: port information structure\n+ * @node: pointer to the ice_sched_node struct\n+ *\n+ * This function frees up a node from SW DB as well as from HW\n+ *\n+ * This function needs to be called with the port_info->sched_lock held\n+ */\n+void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node)\n+{\n+\tstruct ice_sched_node *parent;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu8 i, j;\n+\n+\t/* Free the children before freeing up the parent node\n+\t * The parent array is updated below and that shifts the nodes\n+\t * in the array. So always pick the first child if num children > 0\n+\t */\n+\twhile (node->num_children)\n+\t\tice_free_sched_node(pi, node->children[0]);\n+\n+\t/* Leaf, TC and root nodes can't be deleted by SW */\n+\tif (node->tx_sched_layer >= hw->sw_entry_point_layer &&\n+\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC &&\n+\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT &&\n+\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_LEAF) {\n+\t\tu32 teid = LE32_TO_CPU(node->info.node_teid);\n+\t\tenum ice_status status;\n+\n+\t\tstatus = ice_sched_remove_elems(hw, node->parent, 1, &teid);\n+\t\tif (status != ICE_SUCCESS)\n+\t\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t\t  \"remove element failed %d\\n\", status);\n+\t}\n+\tparent = node->parent;\n+\t/* root has no parent */\n+\tif (parent) {\n+\t\tstruct ice_sched_node *p, *tc_node;\n+\n+\t\t/* update the parent */\n+\t\tfor (i = 0; i < parent->num_children; i++)\n+\t\t\tif (parent->children[i] == node) {\n+\t\t\t\tfor (j = i + 1; j < parent->num_children; j++)\n+\t\t\t\t\tparent->children[j - 1] =\n+\t\t\t\t\t\tparent->children[j];\n+\t\t\t\tparent->num_children--;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\n+\t\t/* search for previous sibling that points to this node and\n+\t\t * remove the reference\n+\t\t */\n+\t\ttc_node = ice_sched_get_tc_node(pi, node->tc_num);\n+\t\tif (!tc_node) {\n+\t\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t\t  \"Invalid TC number %d\\n\", node->tc_num);\n+\t\t\tgoto err_exit;\n+\t\t}\n+\t\tp = ice_sched_get_first_node(hw, tc_node, node->tx_sched_layer);\n+\t\twhile (p) {\n+\t\t\tif (p->sibling == node) {\n+\t\t\t\tp->sibling = node->sibling;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tp = p->sibling;\n+\t\t}\n+\t}\n+err_exit:\n+\t/* leaf nodes have no children */\n+\tif (node->children)\n+\t\tice_free(hw, node->children);\n+\tice_free(hw, node);\n+}\n+\n+/**\n+ * ice_aq_get_dflt_topo - gets default scheduler topology\n+ * @hw: pointer to the hw struct\n+ * @lport: logical port number\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @num_branches: returns total number of queue to port branches\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get default scheduler topology (0x400)\n+ */\n+static enum ice_status\n+ice_aq_get_dflt_topo(struct ice_hw *hw, u8 lport,\n+\t\t     struct ice_aqc_get_topo_elem *buf, u16 buf_size,\n+\t\t     u8 *num_branches, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_get_topo *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.get_topo;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_dflt_topo);\n+\tcmd->port_num = lport;\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (!status && num_branches)\n+\t\t*num_branches = cmd->num_branches;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_add_sched_elems - adds scheduling element\n+ * @hw: pointer to the hw struct\n+ * @grps_req: the number of groups that are requested to be added\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @grps_added: returns total number of groups added\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Add scheduling elements (0x0401)\n+ */\n+static enum ice_status\n+ice_aq_add_sched_elems(struct ice_hw *hw, u16 grps_req,\n+\t\t       struct ice_aqc_add_elem *buf, u16 buf_size,\n+\t\t       u16 *grps_added, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_add_sched_elems,\n+\t\t\t\t\t   grps_req, (void *)buf, buf_size,\n+\t\t\t\t\t   grps_added, cd);\n+}\n+\n+\n+\n+/**\n+ * ice_aq_suspend_sched_elems - suspend scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @elems_req: number of elements to suspend\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @elems_ret: returns total number of elements suspended\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Suspend scheduling elements (0x0409)\n+ */\n+static enum ice_status\n+ice_aq_suspend_sched_elems(struct ice_hw *hw, u16 elems_req,\n+\t\t\t   struct ice_aqc_suspend_resume_elem *buf,\n+\t\t\t   u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_suspend_sched_elems,\n+\t\t\t\t\t   elems_req, (void *)buf, buf_size,\n+\t\t\t\t\t   elems_ret, cd);\n+}\n+\n+/**\n+ * ice_aq_resume_sched_elems - resume scheduler elements\n+ * @hw: pointer to the hw struct\n+ * @elems_req: number of elements to resume\n+ * @buf: pointer to buffer\n+ * @buf_size: buffer size in bytes\n+ * @elems_ret: returns total number of elements resumed\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * resume scheduling elements (0x040A)\n+ */\n+static enum ice_status\n+ice_aq_resume_sched_elems(struct ice_hw *hw, u16 elems_req,\n+\t\t\t  struct ice_aqc_suspend_resume_elem *buf,\n+\t\t\t  u16 buf_size, u16 *elems_ret, struct ice_sq_cd *cd)\n+{\n+\treturn ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_resume_sched_elems,\n+\t\t\t\t\t   elems_req, (void *)buf, buf_size,\n+\t\t\t\t\t   elems_ret, cd);\n+}\n+\n+/**\n+ * ice_aq_query_sched_res - query scheduler resource\n+ * @hw: pointer to the hw struct\n+ * @buf_size: buffer size in bytes\n+ * @buf: pointer to buffer\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Query scheduler resource allocation (0x0412)\n+ */\n+static enum ice_status\n+ice_aq_query_sched_res(struct ice_hw *hw, u16 buf_size,\n+\t\t       struct ice_aqc_query_txsched_res_resp *buf,\n+\t\t       struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_query_sched_res);\n+\treturn ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+}\n+\n+\n+/**\n+ * ice_sched_suspend_resume_elems - suspend or resume hw nodes\n+ * @hw: pointer to the hw struct\n+ * @num_nodes: number of nodes\n+ * @node_teids: array of node teids to be suspended or resumed\n+ * @suspend: true means suspend / false means resume\n+ *\n+ * This function suspends or resumes hw nodes\n+ */\n+static enum ice_status\n+ice_sched_suspend_resume_elems(struct ice_hw *hw, u8 num_nodes, u32 *node_teids,\n+\t\t\t       bool suspend)\n+{\n+\tstruct ice_aqc_suspend_resume_elem *buf;\n+\tu16 i, buf_size, num_elem_ret = 0;\n+\tenum ice_status status;\n+\n+\tbuf_size = sizeof(*buf) * num_nodes;\n+\tbuf = (struct ice_aqc_suspend_resume_elem *)\n+\t\tice_malloc(hw, buf_size);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tfor (i = 0; i < num_nodes; i++)\n+\t\tbuf->teid[i] = CPU_TO_LE32(node_teids[i]);\n+\n+\tif (suspend)\n+\t\tstatus = ice_aq_suspend_sched_elems(hw, num_nodes, buf,\n+\t\t\t\t\t\t    buf_size, &num_elem_ret,\n+\t\t\t\t\t\t    NULL);\n+\telse\n+\t\tstatus = ice_aq_resume_sched_elems(hw, num_nodes, buf,\n+\t\t\t\t\t\t   buf_size, &num_elem_ret,\n+\t\t\t\t\t\t   NULL);\n+\tif (status != ICE_SUCCESS || num_elem_ret != num_nodes)\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"suspend/resume failed\\n\");\n+\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+\n+\n+\n+/**\n+ * ice_sched_clear_agg - clears the agg related information\n+ * @hw: pointer to the hardware structure\n+ *\n+ * This function removes agg list and free up agg related memory\n+ * previously allocated.\n+ */\n+void ice_sched_clear_agg(struct ice_hw *hw)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\tstruct ice_sched_agg_info *atmp;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &hw->agg_list,\n+\t\t\t\t ice_sched_agg_info,\n+\t\t\t\t list_entry) {\n+\t\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\t\tstruct ice_sched_agg_vsi_info *vtmp;\n+\n+\t\tLIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp,\n+\t\t\t\t\t &agg_info->agg_vsi_list,\n+\t\t\t\t\t ice_sched_agg_vsi_info, list_entry) {\n+\t\t\tLIST_DEL(&agg_vsi_info->list_entry);\n+\t\t\tice_free(hw, agg_vsi_info);\n+\t\t}\n+\t\tLIST_DEL(&agg_info->list_entry);\n+\t\tice_free(hw, agg_info);\n+\t}\n+}\n+\n+/**\n+ * ice_sched_clear_tx_topo - clears the schduler tree nodes\n+ * @pi: port information structure\n+ *\n+ * This function removes all the nodes from HW as well as from SW DB.\n+ */\n+static void ice_sched_clear_tx_topo(struct ice_port_info *pi)\n+{\n+\tif (!pi)\n+\t\treturn;\n+\tif (pi->root) {\n+\t\tice_free_sched_node(pi, pi->root);\n+\t\tpi->root = NULL;\n+\t}\n+}\n+\n+/**\n+ * ice_sched_clear_port - clear the scheduler elements from SW DB for a port\n+ * @pi: port information structure\n+ *\n+ * Cleanup scheduling elements from SW DB\n+ */\n+void ice_sched_clear_port(struct ice_port_info *pi)\n+{\n+\tif (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)\n+\t\treturn;\n+\n+\tpi->port_state = ICE_SCHED_PORT_STATE_INIT;\n+\tice_acquire_lock(&pi->sched_lock);\n+\tice_sched_clear_tx_topo(pi);\n+\tice_release_lock(&pi->sched_lock);\n+\tice_destroy_lock(&pi->sched_lock);\n+}\n+\n+/**\n+ * ice_sched_cleanup_all - cleanup scheduler elements from SW DB for all ports\n+ * @hw: pointer to the hw struct\n+ *\n+ * Cleanup scheduling elements from SW DB for all the ports\n+ */\n+void ice_sched_cleanup_all(struct ice_hw *hw)\n+{\n+\tif (!hw)\n+\t\treturn;\n+\n+\tif (hw->layer_info) {\n+\t\tice_free(hw, hw->layer_info);\n+\t\thw->layer_info = NULL;\n+\t}\n+\n+\tif (hw->port_info)\n+\t\tice_sched_clear_port(hw->port_info);\n+\n+\thw->num_tx_sched_layers = 0;\n+\thw->num_tx_sched_phys_layers = 0;\n+\thw->flattened_layers = 0;\n+\thw->max_cgds = 0;\n+}\n+\n+\n+/**\n+ * ice_sched_add_elems - add nodes to hw and SW DB\n+ * @pi: port information structure\n+ * @tc_node: pointer to the branch node\n+ * @parent: pointer to the parent node\n+ * @layer: layer number to add nodes\n+ * @num_nodes: number of nodes\n+ * @num_nodes_added: pointer to num nodes added\n+ * @first_node_teid: if new nodes are added then return the teid of first node\n+ *\n+ * This function add nodes to hw as well as to SW DB for a given layer\n+ */\n+static enum ice_status\n+ice_sched_add_elems(struct ice_port_info *pi, struct ice_sched_node *tc_node,\n+\t\t    struct ice_sched_node *parent, u8 layer, u16 num_nodes,\n+\t\t    u16 *num_nodes_added, u32 *first_node_teid)\n+{\n+\tstruct ice_sched_node *prev, *new_node;\n+\tstruct ice_aqc_add_elem *buf;\n+\tu16 i, num_groups_added = 0;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu16 buf_size;\n+\tu32 teid;\n+\n+\tbuf_size = sizeof(*buf) + sizeof(*buf->generic) * (num_nodes - 1);\n+\tbuf = (struct ice_aqc_add_elem *)ice_malloc(hw, buf_size);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tbuf->hdr.parent_teid = parent->info.node_teid;\n+\tbuf->hdr.num_elems = CPU_TO_LE16(num_nodes);\n+\tfor (i = 0; i < num_nodes; i++) {\n+\t\tbuf->generic[i].parent_teid = parent->info.node_teid;\n+\t\tbuf->generic[i].data.elem_type = ICE_AQC_ELEM_TYPE_SE_GENERIC;\n+\t\tbuf->generic[i].data.valid_sections =\n+\t\t\tICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR |\n+\t\t\tICE_AQC_ELEM_VALID_EIR;\n+\t\tbuf->generic[i].data.generic = 0;\n+\t\tbuf->generic[i].data.cir_bw.bw_profile_idx =\n+\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);\n+\t\tbuf->generic[i].data.cir_bw.bw_alloc =\n+\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);\n+\t\tbuf->generic[i].data.eir_bw.bw_profile_idx =\n+\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID);\n+\t\tbuf->generic[i].data.eir_bw.bw_alloc =\n+\t\t\tCPU_TO_LE16(ICE_SCHED_DFLT_BW_WT);\n+\t}\n+\n+\tstatus = ice_aq_add_sched_elems(hw, 1, buf, buf_size,\n+\t\t\t\t\t&num_groups_added, NULL);\n+\tif (status != ICE_SUCCESS || num_groups_added != 1) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"add elements failed\\n\");\n+\t\tice_free(hw, buf);\n+\t\treturn ICE_ERR_CFG;\n+\t}\n+\n+\t*num_nodes_added = num_nodes;\n+\t/* add nodes to the SW DB */\n+\tfor (i = 0; i < num_nodes; i++) {\n+\t\tstatus = ice_sched_add_node(pi, layer, &buf->generic[i]);\n+\t\tif (status != ICE_SUCCESS) {\n+\t\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t\t  \"add nodes in SW DB failed status =%d\\n\",\n+\t\t\t\t  status);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tteid = LE32_TO_CPU(buf->generic[i].node_teid);\n+\t\tnew_node = ice_sched_find_node_by_teid(parent, teid);\n+\t\tif (!new_node) {\n+\t\t\tice_debug(hw, ICE_DBG_SCHED,\n+\t\t\t\t  \"Node is missing for teid =%d\\n\", teid);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tnew_node->sibling = NULL;\n+\t\tnew_node->tc_num = tc_node->tc_num;\n+\n+\t\t/* add it to previous node sibling pointer */\n+\t\t/* Note: siblings are not linked across branches */\n+\t\tprev = ice_sched_get_first_node(hw, tc_node, layer);\n+\t\tif (prev && prev != new_node) {\n+\t\t\twhile (prev->sibling)\n+\t\t\t\tprev = prev->sibling;\n+\t\t\tprev->sibling = new_node;\n+\t\t}\n+\n+\t\tif (i == 0)\n+\t\t\t*first_node_teid = teid;\n+\t}\n+\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_add_nodes_to_layer - Add nodes to a given layer\n+ * @pi: port information structure\n+ * @tc_node: pointer to TC node\n+ * @parent: pointer to parent node\n+ * @layer: layer number to add nodes\n+ * @num_nodes: number of nodes to be added\n+ * @first_node_teid: pointer to the first node teid\n+ * @num_nodes_added: pointer to number of nodes added\n+ *\n+ * This function add nodes to a given layer.\n+ */\n+static enum ice_status\n+ice_sched_add_nodes_to_layer(struct ice_port_info *pi,\n+\t\t\t     struct ice_sched_node *tc_node,\n+\t\t\t     struct ice_sched_node *parent, u8 layer,\n+\t\t\t     u16 num_nodes, u32 *first_node_teid,\n+\t\t\t     u16 *num_nodes_added)\n+{\n+\tu32 *first_teid_ptr = first_node_teid;\n+\tu16 new_num_nodes, max_child_nodes;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu16 num_added = 0;\n+\tu32 temp;\n+\n+\t*num_nodes_added = 0;\n+\n+\tif (!num_nodes)\n+\t\treturn status;\n+\n+\tif (!parent || layer < hw->sw_entry_point_layer)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* max children per node per layer */\n+\tmax_child_nodes = hw->max_children[parent->tx_sched_layer];\n+\n+\t/* current number of children + required nodes exceed max children ? */\n+\tif ((parent->num_children + num_nodes) > max_child_nodes) {\n+\t\t/* Fail if the parent is a TC node */\n+\t\tif (parent == tc_node)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\t/* utilize all the spaces if the parent is not full */\n+\t\tif (parent->num_children < max_child_nodes) {\n+\t\t\tnew_num_nodes = max_child_nodes - parent->num_children;\n+\t\t\t/* this recursion is intentional, and wouldn't\n+\t\t\t * go more than 2 calls\n+\t\t\t */\n+\t\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node,\n+\t\t\t\t\t\t\t      parent, layer,\n+\t\t\t\t\t\t\t      new_num_nodes,\n+\t\t\t\t\t\t\t      first_node_teid,\n+\t\t\t\t\t\t\t      &num_added);\n+\t\t\tif (status != ICE_SUCCESS)\n+\t\t\t\treturn status;\n+\n+\t\t\t*num_nodes_added += num_added;\n+\t\t}\n+\t\t/* Don't modify the first node teid memory if the first node was\n+\t\t * added already in the above call. Instead send some temp\n+\t\t * memory for all other recursive calls.\n+\t\t */\n+\t\tif (num_added)\n+\t\t\tfirst_teid_ptr = &temp;\n+\n+\t\tnew_num_nodes = num_nodes - num_added;\n+\n+\t\t/* This parent is full, try the next sibling */\n+\t\tparent = parent->sibling;\n+\n+\t\t/* this recursion is intentional, for 1024 queues\n+\t\t * per VSI, it goes max of 16 iterations.\n+\t\t * 1024 / 8 = 128 layer 8 nodes\n+\t\t * 128 /8 = 16 (add 8 nodes per iteration)\n+\t\t */\n+\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node, parent,\n+\t\t\t\t\t\t      layer, new_num_nodes,\n+\t\t\t\t\t\t      first_teid_ptr,\n+\t\t\t\t\t\t      &num_added);\n+\t\t*num_nodes_added += num_added;\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_sched_add_elems(pi, tc_node, parent, layer, num_nodes,\n+\t\t\t\t     num_nodes_added, first_node_teid);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_get_qgrp_layer - get the current queue group layer number\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function returns the current queue group layer number\n+ */\n+static u8 ice_sched_get_qgrp_layer(struct ice_hw *hw)\n+{\n+\t/* It's always total layers - 1, the array is 0 relative so -2 */\n+\treturn hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET;\n+}\n+\n+/**\n+ * ice_sched_get_vsi_layer - get the current VSI layer number\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function returns the current VSI layer number\n+ */\n+static u8 ice_sched_get_vsi_layer(struct ice_hw *hw)\n+{\n+\t/* Num Layers       VSI layer\n+\t *     9               6\n+\t *     7               4\n+\t *     5 or less       sw_entry_point_layer\n+\t */\n+\t/* calculate the vsi layer based on number of layers. */\n+\tif (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) {\n+\t\tu8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;\n+\n+\t\tif (layer > hw->sw_entry_point_layer)\n+\t\t\treturn layer;\n+\t}\n+\treturn hw->sw_entry_point_layer;\n+}\n+\n+\n+/**\n+ * ice_rm_dflt_leaf_node - remove the default leaf node in the tree\n+ * @pi: port information structure\n+ *\n+ * This function removes the leaf node that was created by the FW\n+ * during initialization\n+ */\n+static void ice_rm_dflt_leaf_node(struct ice_port_info *pi)\n+{\n+\tstruct ice_sched_node *node;\n+\n+\tnode = pi->root;\n+\twhile (node) {\n+\t\tif (!node->num_children)\n+\t\t\tbreak;\n+\t\tnode = node->children[0];\n+\t}\n+\tif (node && node->info.data.elem_type == ICE_AQC_ELEM_TYPE_LEAF) {\n+\t\tu32 teid = LE32_TO_CPU(node->info.node_teid);\n+\t\tenum ice_status status;\n+\n+\t\t/* remove the default leaf node */\n+\t\tstatus = ice_sched_remove_elems(pi->hw, node->parent, 1, &teid);\n+\t\tif (!status)\n+\t\t\tice_free_sched_node(pi, node);\n+\t}\n+}\n+\n+/**\n+ * ice_sched_rm_dflt_nodes - free the default nodes in the tree\n+ * @pi: port information structure\n+ *\n+ * This function frees all the nodes except root and TC that were created by\n+ * the FW during initialization\n+ */\n+static void ice_sched_rm_dflt_nodes(struct ice_port_info *pi)\n+{\n+\tstruct ice_sched_node *node;\n+\n+\tice_rm_dflt_leaf_node(pi);\n+\n+\t/* remove the default nodes except TC and root nodes */\n+\tnode = pi->root;\n+\twhile (node) {\n+\t\tif (node->tx_sched_layer >= pi->hw->sw_entry_point_layer &&\n+\t\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_TC &&\n+\t\t    node->info.data.elem_type != ICE_AQC_ELEM_TYPE_ROOT_PORT) {\n+\t\t\tice_free_sched_node(pi, node);\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (!node->num_children)\n+\t\t\tbreak;\n+\t\tnode = node->children[0];\n+\t}\n+}\n+\n+/**\n+ * ice_sched_init_port - Initialize scheduler by querying information from FW\n+ * @pi: port info structure for the tree to cleanup\n+ *\n+ * This function is the initial call to find the total number of Tx scheduler\n+ * resources, default topology created by firmware and storing the information\n+ * in SW DB.\n+ */\n+enum ice_status ice_sched_init_port(struct ice_port_info *pi)\n+{\n+\tstruct ice_aqc_get_topo_elem *buf;\n+\tenum ice_status status;\n+\tstruct ice_hw *hw;\n+\tu8 num_branches;\n+\tu16 num_elems;\n+\tu8 i, j;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\thw = pi->hw;\n+\n+\t/* Query the Default Topology from FW */\n+\tbuf = (struct ice_aqc_get_topo_elem *)ice_malloc(hw,\n+\t\t\t\t\t\t\t ICE_AQ_MAX_BUF_LEN);\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t/* Query default scheduling tree topology */\n+\tstatus = ice_aq_get_dflt_topo(hw, pi->lport, buf, ICE_AQ_MAX_BUF_LEN,\n+\t\t\t\t      &num_branches, NULL);\n+\tif (status)\n+\t\tgoto err_init_port;\n+\n+\t/* num_branches should be between 1-8 */\n+\tif (num_branches < 1 || num_branches > ICE_TXSCHED_MAX_BRANCHES) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"num_branches unexpected %d\\n\",\n+\t\t\t  num_branches);\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto err_init_port;\n+\t}\n+\n+\t/* get the number of elements on the default/first branch */\n+\tnum_elems = LE16_TO_CPU(buf[0].hdr.num_elems);\n+\n+\t/* num_elems should always be between 1-9 */\n+\tif (num_elems < 1 || num_elems > ICE_AQC_TOPO_MAX_LEVEL_NUM) {\n+\t\tice_debug(hw, ICE_DBG_SCHED, \"num_elems unexpected %d\\n\",\n+\t\t\t  num_elems);\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto err_init_port;\n+\t}\n+\n+\t/* If the last node is a leaf node then the index of the Q group\n+\t * layer is two less than the number of elements.\n+\t */\n+\tif (num_elems > 2 && buf[0].generic[num_elems - 1].data.elem_type ==\n+\t    ICE_AQC_ELEM_TYPE_LEAF)\n+\t\tpi->last_node_teid =\n+\t\t\tLE32_TO_CPU(buf[0].generic[num_elems - 2].node_teid);\n+\telse\n+\t\tpi->last_node_teid =\n+\t\t\tLE32_TO_CPU(buf[0].generic[num_elems - 1].node_teid);\n+\n+\t/* Insert the Tx Sched root node */\n+\tstatus = ice_sched_add_root_node(pi, &buf[0].generic[0]);\n+\tif (status)\n+\t\tgoto err_init_port;\n+\n+\t/* Parse the default tree and cache the information */\n+\tfor (i = 0; i < num_branches; i++) {\n+\t\tnum_elems = LE16_TO_CPU(buf[i].hdr.num_elems);\n+\n+\t\t/* Skip root element as already inserted */\n+\t\tfor (j = 1; j < num_elems; j++) {\n+\t\t\t/* update the sw entry point */\n+\t\t\tif (buf[0].generic[j].data.elem_type ==\n+\t\t\t    ICE_AQC_ELEM_TYPE_ENTRY_POINT)\n+\t\t\t\thw->sw_entry_point_layer = j;\n+\n+\t\t\tstatus = ice_sched_add_node(pi, j, &buf[i].generic[j]);\n+\t\t\tif (status)\n+\t\t\t\tgoto err_init_port;\n+\t\t}\n+\t}\n+\n+\t/* Remove the default nodes. */\n+\tif (pi->root)\n+\t\tice_sched_rm_dflt_nodes(pi);\n+\n+\t/* initialize the port for handling the scheduler tree */\n+\tpi->port_state = ICE_SCHED_PORT_STATE_READY;\n+\tice_init_lock(&pi->sched_lock);\n+\n+err_init_port:\n+\tif (status && pi->root) {\n+\t\tice_free_sched_node(pi, pi->root);\n+\t\tpi->root = NULL;\n+\t}\n+\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_sched_query_res_alloc - query the FW for num of logical sched layers\n+ * @hw: pointer to the HW struct\n+ *\n+ * query FW for allocated scheduler resources and store in HW struct\n+ */\n+enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw)\n+{\n+\tstruct ice_aqc_query_txsched_res_resp *buf;\n+\tenum ice_status status = ICE_SUCCESS;\n+\t__le16 max_sibl;\n+\tu8 i;\n+\n+\tif (hw->layer_info)\n+\t\treturn status;\n+\n+\tbuf = (struct ice_aqc_query_txsched_res_resp *)\n+\t\tice_malloc(hw, sizeof(*buf));\n+\tif (!buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tstatus = ice_aq_query_sched_res(hw, sizeof(*buf), buf, NULL);\n+\tif (status)\n+\t\tgoto sched_query_out;\n+\n+\thw->num_tx_sched_layers = LE16_TO_CPU(buf->sched_props.logical_levels);\n+\thw->num_tx_sched_phys_layers =\n+\t\tLE16_TO_CPU(buf->sched_props.phys_levels);\n+\thw->flattened_layers = buf->sched_props.flattening_bitmap;\n+\thw->max_cgds = buf->sched_props.max_pf_cgds;\n+\n+\t/* max sibling group size of current layer refers to the max children\n+\t * of the below layer node.\n+\t * layer 1 node max children will be layer 2 max sibling group size\n+\t * layer 2 node max children will be layer 3 max sibling group size\n+\t * and so on. This array will be populated from root (index 0) to\n+\t * qgroup layer 7. Leaf node has no children.\n+\t */\n+\tfor (i = 0; i < hw->num_tx_sched_layers - 1; i++) {\n+\t\tmax_sibl = buf->layer_props[i + 1].max_sibl_grp_sz;\n+\t\thw->max_children[i] = LE16_TO_CPU(max_sibl);\n+\t}\n+\n+\thw->layer_info = (struct ice_aqc_layer_props *)\n+\t\t\t ice_memdup(hw, buf->layer_props,\n+\t\t\t\t    (hw->num_tx_sched_layers *\n+\t\t\t\t     sizeof(*hw->layer_info)),\n+\t\t\t\t    ICE_DMA_TO_DMA);\n+\tif (!hw->layer_info) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto sched_query_out;\n+\t}\n+\n+\n+sched_query_out:\n+\tice_free(hw, buf);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_find_node_in_subtree - Find node in part of base node subtree\n+ * @hw: pointer to the hw struct\n+ * @base: pointer to the base node\n+ * @node: pointer to the node to search\n+ *\n+ * This function checks whether a given node is part of the base node\n+ * subtree or not\n+ */\n+static bool\n+ice_sched_find_node_in_subtree(struct ice_hw *hw, struct ice_sched_node *base,\n+\t\t\t       struct ice_sched_node *node)\n+{\n+\tu8 i;\n+\n+\tfor (i = 0; i < base->num_children; i++) {\n+\t\tstruct ice_sched_node *child = base->children[i];\n+\n+\t\tif (node == child)\n+\t\t\treturn true;\n+\n+\t\tif (child->tx_sched_layer > node->tx_sched_layer)\n+\t\t\treturn false;\n+\n+\t\t/* this recursion is intentional, and wouldn't\n+\t\t * go more than 8 calls\n+\t\t */\n+\t\tif (ice_sched_find_node_in_subtree(hw, child, node))\n+\t\t\treturn true;\n+\t}\n+\treturn false;\n+}\n+\n+/**\n+ * ice_sched_get_free_qparent - Get a free lan or rdma q group node\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: branch number\n+ * @owner: lan or rdma\n+ *\n+ * This function retrieves a free lan or rdma q group node\n+ */\n+struct ice_sched_node *\n+ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\t   u8 owner)\n+{\n+\tstruct ice_sched_node *vsi_node, *qgrp_node = NULL;\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tu16 max_children;\n+\tu8 qgrp_layer;\n+\n+\tqgrp_layer = ice_sched_get_qgrp_layer(pi->hw);\n+\tmax_children = pi->hw->max_children[qgrp_layer];\n+\n+\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn NULL;\n+\tvsi_node = vsi_ctx->sched.vsi_node[tc];\n+\t/* validate invalid VSI id */\n+\tif (!vsi_node)\n+\t\tgoto lan_q_exit;\n+\n+\t/* get the first q group node from VSI sub-tree */\n+\tqgrp_node = ice_sched_get_first_node(pi->hw, vsi_node, qgrp_layer);\n+\twhile (qgrp_node) {\n+\t\t/* make sure the qgroup node is part of the VSI subtree */\n+\t\tif (ice_sched_find_node_in_subtree(pi->hw, vsi_node, qgrp_node))\n+\t\t\tif (qgrp_node->num_children < max_children &&\n+\t\t\t    qgrp_node->owner == owner)\n+\t\t\t\tbreak;\n+\t\tqgrp_node = qgrp_node->sibling;\n+\t}\n+\n+lan_q_exit:\n+\treturn qgrp_node;\n+}\n+\n+/**\n+ * ice_sched_get_vsi_node - Get a VSI node based on VSI id\n+ * @hw: pointer to the hw struct\n+ * @tc_node: pointer to the TC node\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function retrieves a VSI node for a given VSI id from a given\n+ * TC branch\n+ */\n+static struct ice_sched_node *\n+ice_sched_get_vsi_node(struct ice_hw *hw, struct ice_sched_node *tc_node,\n+\t\t       u16 vsi_handle)\n+{\n+\tstruct ice_sched_node *node;\n+\tu8 vsi_layer;\n+\n+\tvsi_layer = ice_sched_get_vsi_layer(hw);\n+\tnode = ice_sched_get_first_node(hw, tc_node, vsi_layer);\n+\n+\t/* Check whether it already exists */\n+\twhile (node) {\n+\t\tif (node->vsi_handle == vsi_handle)\n+\t\t\treturn node;\n+\t\tnode = node->sibling;\n+\t}\n+\n+\treturn node;\n+}\n+\n+\n+\n+/**\n+ * ice_sched_calc_vsi_child_nodes - calculate number of VSI child nodes\n+ * @hw: pointer to the hw struct\n+ * @num_qs: number of queues\n+ * @num_nodes: num nodes array\n+ *\n+ * This function calculates the number of VSI child nodes based on the\n+ * number of queues.\n+ */\n+static void\n+ice_sched_calc_vsi_child_nodes(struct ice_hw *hw, u16 num_qs, u16 *num_nodes)\n+{\n+\tu16 num = num_qs;\n+\tu8 i, qgl, vsil;\n+\n+\tqgl = ice_sched_get_qgrp_layer(hw);\n+\tvsil = ice_sched_get_vsi_layer(hw);\n+\n+\t/* calculate num nodes from q group to VSI layer */\n+\tfor (i = qgl; i > vsil; i--) {\n+\t\t/* round to the next integer if there is a remainder */\n+\t\tnum = DIVIDE_AND_ROUND_UP(num, hw->max_children[i]);\n+\n+\t\t/* need at least one node */\n+\t\tnum_nodes[i] = num ? num : 1;\n+\t}\n+}\n+\n+/**\n+ * ice_sched_add_vsi_child_nodes - add VSI child nodes to tree\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc_node: pointer to the TC node\n+ * @num_nodes: pointer to the num nodes that needs to be added per layer\n+ * @owner: node owner (lan or rdma)\n+ *\n+ * This function adds the VSI child nodes to tree. It gets called for\n+ * lan and rdma separately.\n+ */\n+static enum ice_status\n+ice_sched_add_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t      struct ice_sched_node *tc_node, u16 *num_nodes,\n+\t\t\t      u8 owner)\n+{\n+\tstruct ice_sched_node *parent, *node;\n+\tstruct ice_hw *hw = pi->hw;\n+\tenum ice_status status;\n+\tu32 first_node_teid;\n+\tu16 num_added = 0;\n+\tu8 i, qgl, vsil;\n+\n+\tqgl = ice_sched_get_qgrp_layer(hw);\n+\tvsil = ice_sched_get_vsi_layer(hw);\n+\tparent = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\tfor (i = vsil + 1; i <= qgl; i++) {\n+\t\tif (!parent)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i,\n+\t\t\t\t\t\t      num_nodes[i],\n+\t\t\t\t\t\t      &first_node_teid,\n+\t\t\t\t\t\t      &num_added);\n+\t\tif (status != ICE_SUCCESS || num_nodes[i] != num_added)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\t/* The newly added node can be a new parent for the next\n+\t\t * layer nodes\n+\t\t */\n+\t\tif (num_added) {\n+\t\t\tparent = ice_sched_find_node_by_teid(tc_node,\n+\t\t\t\t\t\t\t     first_node_teid);\n+\t\t\tnode = parent;\n+\t\t\twhile (node) {\n+\t\t\t\tnode->owner = owner;\n+\t\t\t\tnode = node->sibling;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tparent = parent->children[0];\n+\t\t}\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_rm_vsi_child_nodes - remove VSI child nodes from the tree\n+ * @pi: port information structure\n+ * @vsi_node: pointer to the VSI node\n+ * @num_nodes: pointer to the num nodes that needs to be removed per layer\n+ * @owner: node owner (lan or rdma)\n+ *\n+ * This function removes the VSI child nodes from the tree. It gets called for\n+ * lan and rdma separately.\n+ */\n+static void\n+ice_sched_rm_vsi_child_nodes(struct ice_port_info *pi,\n+\t\t\t     struct ice_sched_node *vsi_node, u16 *num_nodes,\n+\t\t\t     u8 owner)\n+{\n+\tstruct ice_sched_node *node, *next;\n+\tu8 i, qgl, vsil;\n+\tu16 num;\n+\n+\tqgl = ice_sched_get_qgrp_layer(pi->hw);\n+\tvsil = ice_sched_get_vsi_layer(pi->hw);\n+\n+\tfor (i = qgl; i > vsil; i--) {\n+\t\tnum = num_nodes[i];\n+\t\tnode = ice_sched_get_first_node(pi->hw, vsi_node, i);\n+\t\twhile (node && num) {\n+\t\t\tnext = node->sibling;\n+\t\t\tif (node->owner == owner && !node->num_children) {\n+\t\t\t\tice_free_sched_node(pi, node);\n+\t\t\t\tnum--;\n+\t\t\t}\n+\t\t\tnode = next;\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * ice_sched_calc_vsi_support_nodes - calculate number of VSI support nodes\n+ * @hw: pointer to the hw struct\n+ * @tc_node: pointer to TC node\n+ * @num_nodes: pointer to num nodes array\n+ *\n+ * This function calculates the number of supported nodes needed to add this\n+ * VSI into Tx tree including the VSI, parent and intermediate nodes in below\n+ * layers\n+ */\n+static void\n+ice_sched_calc_vsi_support_nodes(struct ice_hw *hw,\n+\t\t\t\t struct ice_sched_node *tc_node, u16 *num_nodes)\n+{\n+\tstruct ice_sched_node *node;\n+\tu8 vsil;\n+\tint i;\n+\n+\tvsil = ice_sched_get_vsi_layer(hw);\n+\tfor (i = vsil; i >= hw->sw_entry_point_layer; i--)\n+\t\t/* Add intermediate nodes if TC has no children and\n+\t\t * need at least one node for VSI\n+\t\t */\n+\t\tif (!tc_node->num_children || i == vsil) {\n+\t\t\tnum_nodes[i]++;\n+\t\t} else {\n+\t\t\t/* If intermediate nodes are reached max children\n+\t\t\t * then add a new one.\n+\t\t\t */\n+\t\t\tnode = ice_sched_get_first_node(hw, tc_node, (u8)i);\n+\t\t\t/* scan all the siblings */\n+\t\t\twhile (node) {\n+\t\t\t\tif (node->num_children < hw->max_children[i])\n+\t\t\t\t\tbreak;\n+\t\t\t\tnode = node->sibling;\n+\t\t\t}\n+\n+\t\t\t/* tree has one intermediate node to add this new VSI.\n+\t\t\t * So no need to calculate supported nodes for below\n+\t\t\t * layers.\n+\t\t\t */\n+\t\t\tif (node)\n+\t\t\t\tbreak;\n+\t\t\t/* all the nodes are full, allocate a new one */\n+\t\t\tnum_nodes[i]++;\n+\t\t}\n+}\n+\n+/**\n+ * ice_sched_add_vsi_support_nodes - add VSI supported nodes into Tx tree\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc_node: pointer to TC node\n+ * @num_nodes: pointer to num nodes array\n+ *\n+ * This function adds the VSI supported nodes into Tx tree including the\n+ * VSI, its parent and intermediate nodes in below layers\n+ */\n+static enum ice_status\n+ice_sched_add_vsi_support_nodes(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t\tstruct ice_sched_node *tc_node, u16 *num_nodes)\n+{\n+\tstruct ice_sched_node *parent = tc_node;\n+\tenum ice_status status;\n+\tu32 first_node_teid;\n+\tu16 num_added = 0;\n+\tu8 i, vsil;\n+\n+\tif (!pi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tvsil = ice_sched_get_vsi_layer(pi->hw);\n+\tfor (i = pi->hw->sw_entry_point_layer; i <= vsil; i++) {\n+\t\tstatus = ice_sched_add_nodes_to_layer(pi, tc_node, parent,\n+\t\t\t\t\t\t      i, num_nodes[i],\n+\t\t\t\t\t\t      &first_node_teid,\n+\t\t\t\t\t\t      &num_added);\n+\t\tif (status != ICE_SUCCESS || num_nodes[i] != num_added)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\t/* The newly added node can be a new parent for the next\n+\t\t * layer nodes\n+\t\t */\n+\t\tif (num_added)\n+\t\t\tparent = ice_sched_find_node_by_teid(tc_node,\n+\t\t\t\t\t\t\t     first_node_teid);\n+\t\telse\n+\t\t\tparent = parent->children[0];\n+\n+\t\tif (!parent)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\tif (i == vsil)\n+\t\t\tparent->vsi_handle = vsi_handle;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sched_add_vsi_to_topo - add a new VSI into tree\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: TC number\n+ *\n+ * This function adds a new VSI into scheduler tree\n+ */\n+static enum ice_status\n+ice_sched_add_vsi_to_topo(struct ice_port_info *pi, u16 vsi_handle, u8 tc)\n+{\n+\tu16 num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };\n+\tstruct ice_sched_node *tc_node;\n+\tstruct ice_hw *hw = pi->hw;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* calculate number of supported nodes needed for this VSI */\n+\tice_sched_calc_vsi_support_nodes(hw, tc_node, num_nodes);\n+\n+\t/* add vsi supported nodes to tc subtree */\n+\treturn ice_sched_add_vsi_support_nodes(pi, vsi_handle, tc_node,\n+\t\t\t\t\t       num_nodes);\n+}\n+\n+/**\n+ * ice_sched_update_vsi_child_nodes - update VSI child nodes\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: TC number\n+ * @new_numqs: new number of max queues\n+ * @owner: owner of this subtree\n+ *\n+ * This function updates the VSI child nodes based on the number of queues\n+ */\n+static enum ice_status\n+ice_sched_update_vsi_child_nodes(struct ice_port_info *pi, u16 vsi_handle,\n+\t\t\t\t u8 tc, u16 new_numqs, u8 owner)\n+{\n+\tu16 prev_num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };\n+\tu16 new_num_nodes[ICE_AQC_TOPO_MAX_LEVEL_NUM] = { 0 };\n+\tstruct ice_sched_node *vsi_node;\n+\tstruct ice_sched_node *tc_node;\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\tu16 prev_numqs;\n+\tu8 i;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tvsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\tif (!vsi_node)\n+\t\treturn ICE_ERR_CFG;\n+\n+\tvsi_ctx = ice_get_vsi_ctx(hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (owner == ICE_SCHED_NODE_OWNER_LAN)\n+\t\tprev_numqs = vsi_ctx->sched.max_lanq[tc];\n+\telse\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* num queues are not changed */\n+\tif (prev_numqs == new_numqs)\n+\t\treturn status;\n+\n+\t/* calculate number of nodes based on prev/new number of qs */\n+\tif (prev_numqs)\n+\t\tice_sched_calc_vsi_child_nodes(hw, prev_numqs, prev_num_nodes);\n+\n+\tif (new_numqs)\n+\t\tice_sched_calc_vsi_child_nodes(hw, new_numqs, new_num_nodes);\n+\n+\tif (prev_numqs > new_numqs) {\n+\t\tfor (i = 0; i < ICE_AQC_TOPO_MAX_LEVEL_NUM; i++)\n+\t\t\tnew_num_nodes[i] = prev_num_nodes[i] - new_num_nodes[i];\n+\n+\t\tice_sched_rm_vsi_child_nodes(pi, vsi_node, new_num_nodes,\n+\t\t\t\t\t     owner);\n+\t} else {\n+\t\tfor (i = 0; i < ICE_AQC_TOPO_MAX_LEVEL_NUM; i++)\n+\t\t\tnew_num_nodes[i] -= prev_num_nodes[i];\n+\n+\t\tstatus = ice_sched_add_vsi_child_nodes(pi, vsi_handle, tc_node,\n+\t\t\t\t\t\t       new_num_nodes, owner);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tvsi_ctx->sched.max_lanq[tc] = new_numqs;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_cfg_vsi - configure the new/existing VSI\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @tc: TC number\n+ * @maxqs: max number of queues\n+ * @owner: lan or rdma\n+ * @enable: TC enabled or disabled\n+ *\n+ * This function adds/updates VSI nodes based on the number of queues. If TC is\n+ * enabled and VSI is in suspended state then resume the VSI back. If TC is\n+ * disabled then suspend the VSI if it is not already.\n+ */\n+enum ice_status\n+ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,\n+\t\t  u8 owner, bool enable)\n+{\n+\tstruct ice_sched_node *vsi_node, *tc_node;\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct ice_hw *hw = pi->hw;\n+\n+\ttc_node = ice_sched_get_tc_node(pi, tc);\n+\tif (!tc_node)\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_ctx = ice_get_vsi_ctx(hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\n+\t/* suspend the VSI if tc is not enabled */\n+\tif (!enable) {\n+\t\tif (vsi_node && vsi_node->in_use) {\n+\t\t\tu32 teid = LE32_TO_CPU(vsi_node->info.node_teid);\n+\n+\t\t\tstatus = ice_sched_suspend_resume_elems(hw, 1, &teid,\n+\t\t\t\t\t\t\t\ttrue);\n+\t\t\tif (!status)\n+\t\t\t\tvsi_node->in_use = false;\n+\t\t}\n+\t\treturn status;\n+\t}\n+\n+\t/* TC is enabled, if it is a new VSI then add it to the tree */\n+\tif (!vsi_node) {\n+\t\tstatus = ice_sched_add_vsi_to_topo(pi, vsi_handle, tc);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\tvsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle);\n+\t\tif (!vsi_node)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\tvsi_ctx->sched.vsi_node[tc] = vsi_node;\n+\t\tvsi_node->in_use = true;\n+\t\t/* invalidate the max queues whenever VSI gets added first time\n+\t\t * into the scheduler tree (boot or after reset). We need to\n+\t\t * recreate the child nodes all the time in these cases.\n+\t\t */\n+\t\tvsi_ctx->sched.max_lanq[tc] = 0;\n+\t}\n+\n+\t/* update the VSI child nodes */\n+\tstatus = ice_sched_update_vsi_child_nodes(pi, vsi_handle, tc, maxqs,\n+\t\t\t\t\t\t  owner);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* TC is enabled, resume the VSI if it is in the suspend state */\n+\tif (!vsi_node->in_use) {\n+\t\tu32 teid = LE32_TO_CPU(vsi_node->info.node_teid);\n+\n+\t\tstatus = ice_sched_suspend_resume_elems(hw, 1, &teid, false);\n+\t\tif (!status)\n+\t\t\tvsi_node->in_use = true;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_sched_rm_agg_vsi_entry - remove agg related vsi info entry\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function removes single aggregator vsi info entry from\n+ * aggregator list.\n+ */\n+static void\n+ice_sched_rm_agg_vsi_info(struct ice_port_info *pi, u16 vsi_handle)\n+{\n+\tstruct ice_sched_agg_info *agg_info;\n+\tstruct ice_sched_agg_info *atmp;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(agg_info, atmp, &pi->hw->agg_list,\n+\t\t\t\t ice_sched_agg_info,\n+\t\t\t\t list_entry) {\n+\t\tstruct ice_sched_agg_vsi_info *agg_vsi_info;\n+\t\tstruct ice_sched_agg_vsi_info *vtmp;\n+\n+\t\tLIST_FOR_EACH_ENTRY_SAFE(agg_vsi_info, vtmp,\n+\t\t\t\t\t &agg_info->agg_vsi_list,\n+\t\t\t\t\t ice_sched_agg_vsi_info, list_entry)\n+\t\t\tif (agg_vsi_info->vsi_handle == vsi_handle) {\n+\t\t\t\tLIST_DEL(&agg_vsi_info->list_entry);\n+\t\t\t\tice_free(pi->hw, agg_vsi_info);\n+\t\t\t\treturn;\n+\t\t\t}\n+\t}\n+}\n+\n+/**\n+ * ice_sched_rm_vsi_cfg - remove the VSI and its children nodes\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ * @owner: lan or rdma\n+ *\n+ * This function removes the VSI and its lan or rdma children nodes from the\n+ * scheduler tree.\n+ */\n+static enum ice_status\n+ice_sched_rm_vsi_cfg(struct ice_port_info *pi, u16 vsi_handle, u8 owner)\n+{\n+\tenum ice_status status = ICE_ERR_PARAM;\n+\tstruct ice_vsi_ctx *vsi_ctx;\n+\tu8 i, j = 0;\n+\n+\tif (!ice_is_vsi_valid(pi->hw, vsi_handle))\n+\t\treturn status;\n+\tice_acquire_lock(&pi->sched_lock);\n+\tvsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);\n+\tif (!vsi_ctx)\n+\t\tgoto exit_sched_rm_vsi_cfg;\n+\n+\tfor (i = 0; i < ICE_MAX_TRAFFIC_CLASS; i++) {\n+\t\tstruct ice_sched_node *vsi_node, *tc_node;\n+\n+\t\ttc_node = ice_sched_get_tc_node(pi, i);\n+\t\tif (!tc_node)\n+\t\t\tcontinue;\n+\n+\t\tvsi_node = ice_sched_get_vsi_node(pi->hw, tc_node, vsi_handle);\n+\t\tif (!vsi_node)\n+\t\t\tcontinue;\n+\n+\t\twhile (j < vsi_node->num_children) {\n+\t\t\tif (vsi_node->children[j]->owner == owner) {\n+\t\t\t\tice_free_sched_node(pi, vsi_node->children[j]);\n+\n+\t\t\t\t/* reset the counter again since the num\n+\t\t\t\t * children will be updated after node removal\n+\t\t\t\t */\n+\t\t\t\tj = 0;\n+\t\t\t} else {\n+\t\t\t\tj++;\n+\t\t\t}\n+\t\t}\n+\t\t/* remove the VSI if it has no children */\n+\t\tif (!vsi_node->num_children) {\n+\t\t\tice_free_sched_node(pi, vsi_node);\n+\t\t\tvsi_ctx->sched.vsi_node[i] = NULL;\n+\n+\t\t\t/* clean up agg related vsi info if any */\n+\t\t\tice_sched_rm_agg_vsi_info(pi, vsi_handle);\n+\t\t}\n+\t\tif (owner == ICE_SCHED_NODE_OWNER_LAN)\n+\t\t\tvsi_ctx->sched.max_lanq[i] = 0;\n+\t}\n+\tstatus = ICE_SUCCESS;\n+\n+exit_sched_rm_vsi_cfg:\n+\tice_release_lock(&pi->sched_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_rm_vsi_lan_cfg - remove VSI and its lan children nodes\n+ * @pi: port information structure\n+ * @vsi_handle: software VSI handle\n+ *\n+ * This function clears the VSI and its lan children nodes from scheduler tree\n+ * for all TCs.\n+ */\n+enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle)\n+{\n+\treturn ice_sched_rm_vsi_cfg(pi, vsi_handle, ICE_SCHED_NODE_OWNER_LAN);\n+}\n+\n+\ndiff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h\nnew file mode 100644\nindex 0000000..9a8a215\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_sched.h\n@@ -0,0 +1,68 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_SCHED_H_\n+#define _ICE_SCHED_H_\n+\n+#include \"ice_common.h\"\n+\n+#define ICE_QGRP_LAYER_OFFSET\t2\n+#define ICE_VSI_LAYER_OFFSET\t4\n+#define ICE_AGG_LAYER_OFFSET\t6\n+#define ICE_SCHED_INVAL_LAYER_NUM\t0xFF\n+/* Burst size is a 12 bits register that is configured while creating the RL\n+ * profile(s). MSB is a granularity bit and tells the granularity type\n+ * 0 - LSB bits are in bytes granularity\n+ * 1 - LSB bits are in 1K bytes granularity\n+ */\n+#define ICE_BYTE_GRANULARITY\t\t\t0\n+#define ICE_KBYTE_GRANULARITY\t\t\t0x800\n+#define ICE_MIN_BURST_SIZE_ALLOWED\t\t1 /* In Bytes */\n+#define ICE_MAX_BURST_SIZE_ALLOWED\t\t(2047 * 1024) /* In Bytes */\n+#define ICE_MAX_BURST_SIZE_BYTE_GRANULARITY\t2047 /* In Bytes */\n+#define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY\tICE_MAX_BURST_SIZE_ALLOWED\n+\n+\n+\n+struct ice_sched_agg_vsi_info {\n+\tstruct LIST_ENTRY_TYPE list_entry;\n+\tice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);\n+\tu16 vsi_handle;\n+};\n+\n+struct ice_sched_agg_info {\n+\tstruct LIST_HEAD_TYPE agg_vsi_list;\n+\tstruct LIST_ENTRY_TYPE list_entry;\n+\tice_declare_bitmap(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);\n+\tu32 agg_id;\n+\tenum ice_agg_type agg_type;\n+\t/* bw_t_info saves agg bw information */\n+\tstruct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];\n+};\n+\n+/* FW AQ command calls */\n+enum ice_status ice_sched_init_port(struct ice_port_info *pi);\n+enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw);\n+\n+/* Functions to cleanup scheduler SW DB */\n+void ice_sched_clear_port(struct ice_port_info *pi);\n+void ice_sched_cleanup_all(struct ice_hw *hw);\n+void ice_sched_clear_agg(struct ice_hw *hw);\n+\n+struct ice_sched_node *\n+ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);\n+/* Add a scheduling node into SW DB for given info */\n+enum ice_status\n+ice_sched_add_node(struct ice_port_info *pi, u8 layer,\n+\t\t   struct ice_aqc_txsched_elem_data *info);\n+void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);\n+struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);\n+struct ice_sched_node *\n+ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,\n+\t\t\t   u8 owner);\n+enum ice_status\n+ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,\n+\t\t  u8 owner, bool enable);\n+enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle);\n+#endif /* _ICE_SCHED_H_ */\ndiff --git a/drivers/net/ice/base/ice_sriov.c b/drivers/net/ice/base/ice_sriov.c\nnew file mode 100644\nindex 0000000..0ee7496\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_sriov.c\n@@ -0,0 +1,129 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_common.h\"\n+#include \"ice_adminq_cmd.h\"\n+#include \"ice_sriov.h\"\n+\n+/**\n+ * ice_aq_send_msg_to_vf\n+ * @hw: pointer to the hardware structure\n+ * @vfid: VF ID to send msg\n+ * @v_opcode: opcodes for VF-PF communication\n+ * @v_retval: return error code\n+ * @msg: pointer to the msg buffer\n+ * @msglen: msg length\n+ * @cd: pointer to command details\n+ *\n+ * Send message to VF driver (0x0802) using mailbox\n+ * queue and asynchronously sending message via\n+ * ice_sq_send_cmd() function\n+ */\n+enum ice_status\n+ice_aq_send_msg_to_vf(struct ice_hw *hw, u16 vfid, u32 v_opcode, u32 v_retval,\n+\t\t      u8 *msg, u16 msglen, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_pf_vf_msg *cmd;\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_mbx_opc_send_msg_to_vf);\n+\n+\tcmd = &desc.params.virt;\n+\tcmd->id = CPU_TO_LE32(vfid);\n+\n+\tdesc.cookie_high = CPU_TO_LE32(v_opcode);\n+\tdesc.cookie_low = CPU_TO_LE32(v_retval);\n+\n+\tif (msglen)\n+\t\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\treturn ice_sq_send_cmd(hw, &hw->mailboxq, &desc, msg, msglen, cd);\n+}\n+\n+\n+/**\n+ * ice_conv_link_speed_to_virtchnl\n+ * @adv_link_support: determines the format of the returned link speed\n+ * @link_speed: variable containing the link_speed to be converted\n+ *\n+ * Convert link speed supported by hw to link speed supported by virtchnl.\n+ * If adv_link_support is true, then return link speed in Mbps. Else return\n+ * link speed as a VIRTCHNL_LINK_SPEED_* casted to a u32. Note that the caller\n+ * needs to cast back to an enum virtchnl_link_speed in the case where\n+ * adv_link_support is false, but when adv_link_support is true the caller can\n+ * expect the speed in Mbps.\n+ */\n+u32 ice_conv_link_speed_to_virtchnl(bool adv_link_support, u16 link_speed)\n+{\n+\tu32 speed;\n+\n+\tif (adv_link_support)\n+\t\tswitch (link_speed) {\n+\t\tcase ICE_AQ_LINK_SPEED_10MB:\n+\t\t\tspeed = ICE_LINK_SPEED_10MBPS;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_100MB:\n+\t\t\tspeed = ICE_LINK_SPEED_100MBPS;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_1000MB:\n+\t\t\tspeed = ICE_LINK_SPEED_1000MBPS;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_2500MB:\n+\t\t\tspeed = ICE_LINK_SPEED_2500MBPS;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_5GB:\n+\t\t\tspeed = ICE_LINK_SPEED_5000MBPS;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_10GB:\n+\t\t\tspeed = ICE_LINK_SPEED_10000MBPS;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_20GB:\n+\t\t\tspeed = ICE_LINK_SPEED_20000MBPS;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_25GB:\n+\t\t\tspeed = ICE_LINK_SPEED_25000MBPS;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_40GB:\n+\t\t\tspeed = ICE_LINK_SPEED_40000MBPS;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tspeed = ICE_LINK_SPEED_UNKNOWN;\n+\t\t\tbreak;\n+\t\t}\n+\telse\n+\t\t/* Virtchnl speeds are not defined for every speed supported in\n+\t\t * the hardware. To maintain compatibility with older AVF\n+\t\t * drivers, while reporting the speed the new speed values are\n+\t\t * resolved to the closest known virtchnl speeds\n+\t\t */\n+\t\tswitch (link_speed) {\n+\t\tcase ICE_AQ_LINK_SPEED_10MB:\n+\t\tcase ICE_AQ_LINK_SPEED_100MB:\n+\t\t\tspeed = (u32)VIRTCHNL_LINK_SPEED_100MB;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_1000MB:\n+\t\tcase ICE_AQ_LINK_SPEED_2500MB:\n+\t\tcase ICE_AQ_LINK_SPEED_5GB:\n+\t\t\tspeed = (u32)VIRTCHNL_LINK_SPEED_1GB;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_10GB:\n+\t\t\tspeed = (u32)VIRTCHNL_LINK_SPEED_10GB;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_20GB:\n+\t\t\tspeed = (u32)VIRTCHNL_LINK_SPEED_20GB;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_25GB:\n+\t\t\tspeed = (u32)VIRTCHNL_LINK_SPEED_25GB;\n+\t\t\tbreak;\n+\t\tcase ICE_AQ_LINK_SPEED_40GB:\n+\t\t\t/* fall through */\n+\t\t\tspeed = (u32)VIRTCHNL_LINK_SPEED_40GB;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tspeed = (u32)VIRTCHNL_LINK_SPEED_UNKNOWN;\n+\t\t\tbreak;\n+\t\t}\n+\n+\treturn speed;\n+}\ndiff --git a/drivers/net/ice/base/ice_sriov.h b/drivers/net/ice/base/ice_sriov.h\nnew file mode 100644\nindex 0000000..e1734d6\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_sriov.h\n@@ -0,0 +1,35 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_SRIOV_H_\n+#define _ICE_SRIOV_H_\n+\n+#include \"ice_common.h\"\n+\n+/* #ifdef CONFIG_PCI_IOV */\n+enum ice_status\n+ice_aq_send_msg_to_vf(struct ice_hw *hw, u16 vfid, u32 v_opcode, u32 v_retval,\n+\t\t      u8 *msg, u16 msglen, struct ice_sq_cd *cd);\n+\n+u32 ice_conv_link_speed_to_virtchnl(bool adv_link_support, u16 link_speed);\n+/* #else CONFIG_PCI_IOV */\n+static inline enum ice_status\n+ice_aq_send_msg_to_vf(struct ice_hw __always_unused *hw,\n+\t\t      u16 __always_unused vfid, u32 __always_unused v_opcode,\n+\t\t      u32 __always_unused v_retval, u8 __always_unused *msg,\n+\t\t      u16 __always_unused msglen,\n+\t\t      struct ice_sq_cd __always_unused *cd)\n+{\n+\treturn ICE_SUCCESS;\n+}\n+\n+static inline u32\n+ice_conv_link_speed_to_virtchnl(bool __always_unused adv_link_support,\n+\t\t\t\tu16 __always_unused link_speed)\n+{\n+\treturn 0;\n+}\n+\n+/* #endif CONFIG_PCI_IOV */\n+#endif /* _ICE_SRIOV_H_ */\ndiff --git a/drivers/net/ice/base/ice_status.h b/drivers/net/ice/base/ice_status.h\nnew file mode 100644\nindex 0000000..898bfa6\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_status.h\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_STATUS_H_\n+#define _ICE_STATUS_H_\n+\n+/* Error Codes */\n+enum ice_status {\n+\tICE_SUCCESS\t\t\t\t= 0,\n+\n+\t/* Generic codes : Range -1..-49 */\n+\tICE_ERR_PARAM\t\t\t\t= -1,\n+\tICE_ERR_NOT_IMPL\t\t\t= -2,\n+\tICE_ERR_NOT_READY\t\t\t= -3,\n+\tICE_ERR_BAD_PTR\t\t\t\t= -5,\n+\tICE_ERR_INVAL_SIZE\t\t\t= -6,\n+\tICE_ERR_DEVICE_NOT_SUPPORTED\t\t= -8,\n+\tICE_ERR_RESET_FAILED\t\t\t= -9,\n+\tICE_ERR_FW_API_VER\t\t\t= -10,\n+\tICE_ERR_NO_MEMORY\t\t\t= -11,\n+\tICE_ERR_CFG\t\t\t\t= -12,\n+\tICE_ERR_OUT_OF_RANGE\t\t\t= -13,\n+\tICE_ERR_ALREADY_EXISTS\t\t\t= -14,\n+\tICE_ERR_DOES_NOT_EXIST\t\t\t= -15,\n+\tICE_ERR_IN_USE\t\t\t\t= -16,\n+\tICE_ERR_MAX_LIMIT\t\t\t= -17,\n+\tICE_ERR_RESET_ONGOING\t\t\t= -18,\n+\tICE_ERR_HW_TABLE\t\t\t= -19,\n+\n+\t/* NVM specific error codes: Range -50..-59 */\n+\tICE_ERR_NVM\t\t\t\t= -50,\n+\tICE_ERR_NVM_CHECKSUM\t\t\t= -51,\n+\tICE_ERR_BUF_TOO_SHORT\t\t\t= -52,\n+\tICE_ERR_NVM_BLANK_MODE\t\t\t= -53,\n+\n+\t/* ARQ/ASQ specific error codes. Range -100..-109 */\n+\tICE_ERR_AQ_ERROR\t\t\t= -100,\n+\tICE_ERR_AQ_TIMEOUT\t\t\t= -101,\n+\tICE_ERR_AQ_FULL\t\t\t\t= -102,\n+\tICE_ERR_AQ_NO_WORK\t\t\t= -103,\n+\tICE_ERR_AQ_EMPTY\t\t\t= -104,\n+};\n+\n+#endif /* _ICE_STATUS_H_ */\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nnew file mode 100644\nindex 0000000..c768733\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -0,0 +1,2415 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_switch.h\"\n+\n+\n+#define ICE_ETH_DA_OFFSET\t\t0\n+#define ICE_ETH_ETHTYPE_OFFSET\t\t12\n+#define ICE_ETH_VLAN_TCI_OFFSET\t\t14\n+#define ICE_MAX_VLAN_ID\t\t\t0xFFF\n+\n+/* Dummy ethernet header needed in the ice_aqc_sw_rules_elem\n+ * struct to configure any switch filter rules.\n+ * {DA (6 bytes), SA(6 bytes),\n+ * Ether type (2 bytes for header without VLAN tag) OR\n+ * VLAN tag (4 bytes for header with VLAN tag) }\n+ *\n+ * Word on Hardcoded values\n+ * byte 0 = 0x2: to identify it as locally administered DA MAC\n+ * byte 6 = 0x2: to identify it as locally administered SA MAC\n+ * byte 12 = 0x81 & byte 13 = 0x00:\n+ *\tIn case of VLAN filter first two bytes defines ether type (0x8100)\n+ *\tand remaining two bytes are placeholder for programming a given VLAN id\n+ *\tIn case of Ether type filter it is treated as header without VLAN tag\n+ *\tand byte 12 and 13 is used to program a given Ether type instead\n+ */\n+#define DUMMY_ETH_HDR_LEN\t\t16\n+static const u8 dummy_eth_header[DUMMY_ETH_HDR_LEN] = { 0x2, 0, 0, 0, 0, 0,\n+\t\t\t\t\t\t\t0x2, 0, 0, 0, 0, 0,\n+\t\t\t\t\t\t\t0x81, 0, 0, 0};\n+\n+#define ICE_SW_RULE_RX_TX_ETH_HDR_SIZE \\\n+\t(sizeof(struct ice_aqc_sw_rules_elem) - \\\n+\t sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \\\n+\t sizeof(struct ice_sw_rule_lkup_rx_tx) + DUMMY_ETH_HDR_LEN - 1)\n+#define ICE_SW_RULE_RX_TX_NO_HDR_SIZE \\\n+\t(sizeof(struct ice_aqc_sw_rules_elem) - \\\n+\t sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \\\n+\t sizeof(struct ice_sw_rule_lkup_rx_tx) - 1)\n+#define ICE_SW_RULE_LG_ACT_SIZE(n) \\\n+\t(sizeof(struct ice_aqc_sw_rules_elem) - \\\n+\t sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \\\n+\t sizeof(struct ice_sw_rule_lg_act) - \\\n+\t sizeof(((struct ice_sw_rule_lg_act *)0)->act) + \\\n+\t ((n) * sizeof(((struct ice_sw_rule_lg_act *)0)->act)))\n+#define ICE_SW_RULE_VSI_LIST_SIZE(n) \\\n+\t(sizeof(struct ice_aqc_sw_rules_elem) - \\\n+\t sizeof(((struct ice_aqc_sw_rules_elem *)0)->pdata) + \\\n+\t sizeof(struct ice_sw_rule_vsi_list) - \\\n+\t sizeof(((struct ice_sw_rule_vsi_list *)0)->vsi) + \\\n+\t ((n) * sizeof(((struct ice_sw_rule_vsi_list *)0)->vsi)))\n+\n+\n+/**\n+ * ice_init_def_sw_recp - initialize the recipe book keeping tables\n+ * @hw: pointer to the hw struct\n+ *\n+ * Allocate memory for the entire recipe table and initialize the structures/\n+ * entries corresponding to basic recipes.\n+ */\n+enum ice_status ice_init_def_sw_recp(struct ice_hw *hw)\n+{\n+\tstruct ice_sw_recipe *recps;\n+\tu8 i;\n+\n+\trecps = (struct ice_sw_recipe *)\n+\t\tice_calloc(hw, ICE_MAX_NUM_RECIPES, sizeof(*recps));\n+\tif (!recps)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tfor (i = 0; i < ICE_SW_LKUP_LAST; i++) {\n+\t\trecps[i].root_rid = i;\n+\t\tINIT_LIST_HEAD(&recps[i].filt_rules);\n+\t\tINIT_LIST_HEAD(&recps[i].filt_replay_rules);\n+\t\tice_init_lock(&recps[i].filt_rule_lock);\n+\t}\n+\n+\thw->switch_info->recp_list = recps;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_aq_get_sw_cfg - get switch configuration\n+ * @hw: pointer to the hardware structure\n+ * @buf: pointer to the result buffer\n+ * @buf_size: length of the buffer available for response\n+ * @req_desc: pointer to requested descriptor\n+ * @num_elems: pointer to number of elements\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Get switch configuration (0x0200) to be placed in 'buff'.\n+ * This admin command returns information such as initial VSI/port number\n+ * and switch ID it belongs to.\n+ *\n+ * NOTE: *req_desc is both an input/output parameter.\n+ * The caller of this function first calls this function with *request_desc set\n+ * to 0. If the response from f/w has *req_desc set to 0, all the switch\n+ * configuration information has been returned; if non-zero (meaning not all\n+ * the information was returned), the caller should call this function again\n+ * with *req_desc set to the previous value returned by f/w to get the\n+ * next block of switch configuration information.\n+ *\n+ * *num_elems is output only parameter. This reflects the number of elements\n+ * in response buffer. The caller of this function to use *num_elems while\n+ * parsing the response buffer.\n+ */\n+static enum ice_status\n+ice_aq_get_sw_cfg(struct ice_hw *hw, struct ice_aqc_get_sw_cfg_resp *buf,\n+\t\t  u16 buf_size, u16 *req_desc, u16 *num_elems,\n+\t\t  struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_get_sw_cfg *cmd;\n+\tenum ice_status status;\n+\tstruct ice_aq_desc desc;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_sw_cfg);\n+\tcmd = &desc.params.get_sw_conf;\n+\tcmd->element = CPU_TO_LE16(*req_desc);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (!status) {\n+\t\t*req_desc = LE16_TO_CPU(cmd->element);\n+\t\t*num_elems = LE16_TO_CPU(cmd->num_elems);\n+\t}\n+\n+\treturn status;\n+}\n+\n+\n+\n+/**\n+ * ice_aq_add_vsi\n+ * @hw: pointer to the hw struct\n+ * @vsi_ctx: pointer to a VSI context struct\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Add a VSI context to the hardware (0x0210)\n+ */\n+static enum ice_status\n+ice_aq_add_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,\n+\t       struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_add_update_free_vsi_resp *res;\n+\tstruct ice_aqc_add_get_update_free_vsi *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.vsi_cmd;\n+\tres = &desc.params.add_update_free_vsi_res;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_vsi);\n+\n+\tif (!vsi_ctx->alloc_from_pool)\n+\t\tcmd->vsi_num = CPU_TO_LE16(vsi_ctx->vsi_num |\n+\t\t\t\t\t   ICE_AQ_VSI_IS_VALID);\n+\tcmd->vf_id = vsi_ctx->vf_num;\n+\n+\tcmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);\n+\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,\n+\t\t\t\t sizeof(vsi_ctx->info), cd);\n+\n+\tif (!status) {\n+\t\tvsi_ctx->vsi_num = LE16_TO_CPU(res->vsi_num) & ICE_AQ_VSI_NUM_M;\n+\t\tvsi_ctx->vsis_allocd = LE16_TO_CPU(res->vsi_used);\n+\t\tvsi_ctx->vsis_unallocated = LE16_TO_CPU(res->vsi_free);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_free_vsi\n+ * @hw: pointer to the hw struct\n+ * @vsi_ctx: pointer to a VSI context struct\n+ * @keep_vsi_alloc: keep VSI allocation as part of this PF's resources\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Free VSI context info from hardware (0x0213)\n+ */\n+static enum ice_status\n+ice_aq_free_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,\n+\t\tbool keep_vsi_alloc, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_add_update_free_vsi_resp *resp;\n+\tstruct ice_aqc_add_get_update_free_vsi *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.vsi_cmd;\n+\tresp = &desc.params.add_update_free_vsi_res;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_free_vsi);\n+\n+\tcmd->vsi_num = CPU_TO_LE16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID);\n+\tif (keep_vsi_alloc)\n+\t\tcmd->cmd_flags = CPU_TO_LE16(ICE_AQ_VSI_KEEP_ALLOC);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n+\tif (!status) {\n+\t\tvsi_ctx->vsis_allocd = LE16_TO_CPU(resp->vsi_used);\n+\t\tvsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_update_vsi\n+ * @hw: pointer to the hw struct\n+ * @vsi_ctx: pointer to a VSI context struct\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Update VSI context in the hardware (0x0211)\n+ */\n+static enum ice_status\n+ice_aq_update_vsi(struct ice_hw *hw, struct ice_vsi_ctx *vsi_ctx,\n+\t\t  struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_add_update_free_vsi_resp *resp;\n+\tstruct ice_aqc_add_get_update_free_vsi *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tcmd = &desc.params.vsi_cmd;\n+\tresp = &desc.params.add_update_free_vsi_res;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_update_vsi);\n+\n+\tcmd->vsi_num = CPU_TO_LE16(vsi_ctx->vsi_num | ICE_AQ_VSI_IS_VALID);\n+\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, &vsi_ctx->info,\n+\t\t\t\t sizeof(vsi_ctx->info), cd);\n+\n+\tif (!status) {\n+\t\tvsi_ctx->vsis_allocd = LE16_TO_CPU(resp->vsi_used);\n+\t\tvsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_is_vsi_valid - check whether the VSI is valid or not\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: VSI handle\n+ *\n+ * check whether the VSI is valid or not\n+ */\n+bool ice_is_vsi_valid(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\treturn vsi_handle < ICE_MAX_VSI && hw->vsi_ctx[vsi_handle];\n+}\n+\n+/**\n+ * ice_get_hw_vsi_num - return the hw VSI number\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: VSI handle\n+ *\n+ * return the hw VSI number\n+ * Caution: call this function only if VSI is valid (ice_is_vsi_valid)\n+ */\n+u16 ice_get_hw_vsi_num(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\treturn hw->vsi_ctx[vsi_handle]->vsi_num;\n+}\n+\n+/**\n+ * ice_get_vsi_ctx - return the VSI context entry for a given VSI handle\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: VSI handle\n+ *\n+ * return the VSI context entry for a given VSI handle\n+ */\n+struct ice_vsi_ctx *ice_get_vsi_ctx(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\treturn (vsi_handle >= ICE_MAX_VSI) ? NULL : hw->vsi_ctx[vsi_handle];\n+}\n+\n+/**\n+ * ice_save_vsi_ctx - save the VSI context for a given VSI handle\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: VSI handle\n+ * @vsi: VSI context pointer\n+ *\n+ * save the VSI context entry for a given VSI handle\n+ */\n+static void\n+ice_save_vsi_ctx(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi)\n+{\n+\thw->vsi_ctx[vsi_handle] = vsi;\n+}\n+\n+/**\n+ * ice_clear_vsi_ctx - clear the VSI context entry\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: VSI handle\n+ *\n+ * clear the VSI context entry\n+ */\n+static void ice_clear_vsi_ctx(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\tstruct ice_vsi_ctx *vsi;\n+\n+\tvsi = ice_get_vsi_ctx(hw, vsi_handle);\n+\tif (vsi) {\n+\t\tice_destroy_lock(&vsi->rss_locks);\n+\t\tice_free(hw, vsi);\n+\t\thw->vsi_ctx[vsi_handle] = NULL;\n+\t}\n+}\n+\n+/**\n+ * ice_clear_all_vsi_ctx - clear all the VSI context entries\n+ * @hw: pointer to the hw struct\n+ */\n+void ice_clear_all_vsi_ctx(struct ice_hw *hw)\n+{\n+\tu16 i;\n+\n+\tfor (i = 0; i < ICE_MAX_VSI; i++)\n+\t\tice_clear_vsi_ctx(hw, i);\n+}\n+\n+/**\n+ * ice_add_vsi - add VSI context to the hardware and VSI handle list\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: unique VSI handle provided by drivers\n+ * @vsi_ctx: pointer to a VSI context struct\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Add a VSI context to the hardware also add it into the VSI handle list.\n+ * If this function gets called after reset for exisiting VSIs then update\n+ * with the new HW VSI number in the corresponding VSI handle list entry.\n+ */\n+enum ice_status\n+ice_add_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,\n+\t    struct ice_sq_cd *cd)\n+{\n+\tstruct ice_vsi_ctx *tmp_vsi_ctx;\n+\tenum ice_status status;\n+\n+\tif (vsi_handle >= ICE_MAX_VSI)\n+\t\treturn ICE_ERR_PARAM;\n+\tstatus = ice_aq_add_vsi(hw, vsi_ctx, cd);\n+\tif (status)\n+\t\treturn status;\n+\ttmp_vsi_ctx = ice_get_vsi_ctx(hw, vsi_handle);\n+\tif (!tmp_vsi_ctx) {\n+\t\t/* Create a new vsi context */\n+\t\ttmp_vsi_ctx = (struct ice_vsi_ctx *)\n+\t\t\tice_malloc(hw, sizeof(*tmp_vsi_ctx));\n+\t\tif (!tmp_vsi_ctx) {\n+\t\t\tice_aq_free_vsi(hw, vsi_ctx, false, cd);\n+\t\t\treturn ICE_ERR_NO_MEMORY;\n+\t\t}\n+\t\t*tmp_vsi_ctx = *vsi_ctx;\n+\t\tice_init_lock(&tmp_vsi_ctx->rss_locks);\n+\t\tINIT_LIST_HEAD(&tmp_vsi_ctx->rss_list_head);\n+\t\tice_save_vsi_ctx(hw, vsi_handle, tmp_vsi_ctx);\n+\t} else {\n+\t\t/* update with new HW VSI num */\n+\t\tif (tmp_vsi_ctx->vsi_num != vsi_ctx->vsi_num)\n+\t\t\ttmp_vsi_ctx->vsi_num = vsi_ctx->vsi_num;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_free_vsi- free VSI context from hardware and VSI handle list\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: unique VSI handle\n+ * @vsi_ctx: pointer to a VSI context struct\n+ * @keep_vsi_alloc: keep VSI allocation as part of this PF's resources\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Free VSI context info from hardware as well as from VSI handle list\n+ */\n+enum ice_status\n+ice_free_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,\n+\t     bool keep_vsi_alloc, struct ice_sq_cd *cd)\n+{\n+\tenum ice_status status;\n+\n+\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_ctx->vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);\n+\tstatus = ice_aq_free_vsi(hw, vsi_ctx, keep_vsi_alloc, cd);\n+\tif (!status)\n+\t\tice_clear_vsi_ctx(hw, vsi_handle);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_update_vsi\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle: unique VSI handle\n+ * @vsi_ctx: pointer to a VSI context struct\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Update VSI context in the hardware\n+ */\n+enum ice_status\n+ice_update_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,\n+\t       struct ice_sq_cd *cd)\n+{\n+\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\tvsi_ctx->vsi_num = ice_get_hw_vsi_num(hw, vsi_handle);\n+\treturn ice_aq_update_vsi(hw, vsi_ctx, cd);\n+}\n+\n+\n+\n+/**\n+ * ice_aq_alloc_free_vsi_list\n+ * @hw: pointer to the hw struct\n+ * @vsi_list_id: VSI list id returned or used for lookup\n+ * @lkup_type: switch rule filter lookup type\n+ * @opc: switch rules population command type - pass in the command opcode\n+ *\n+ * allocates or free a VSI list resource\n+ */\n+static enum ice_status\n+ice_aq_alloc_free_vsi_list(struct ice_hw *hw, u16 *vsi_list_id,\n+\t\t\t   enum ice_sw_lkup_type lkup_type,\n+\t\t\t   enum ice_adminq_opc opc)\n+{\n+\tstruct ice_aqc_alloc_free_res_elem *sw_buf;\n+\tstruct ice_aqc_res_elem *vsi_ele;\n+\tenum ice_status status;\n+\tu16 buf_len;\n+\n+\tbuf_len = sizeof(*sw_buf);\n+\tsw_buf = (struct ice_aqc_alloc_free_res_elem *)\n+\t\tice_malloc(hw, buf_len);\n+\tif (!sw_buf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\tsw_buf->num_elems = CPU_TO_LE16(1);\n+\n+\tif (lkup_type == ICE_SW_LKUP_MAC ||\n+\t    lkup_type == ICE_SW_LKUP_MAC_VLAN ||\n+\t    lkup_type == ICE_SW_LKUP_ETHERTYPE ||\n+\t    lkup_type == ICE_SW_LKUP_ETHERTYPE_MAC ||\n+\t    lkup_type == ICE_SW_LKUP_PROMISC ||\n+\t    lkup_type == ICE_SW_LKUP_PROMISC_VLAN) {\n+\t\tsw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_VSI_LIST_REP);\n+\t} else if (lkup_type == ICE_SW_LKUP_VLAN) {\n+\t\tsw_buf->res_type =\n+\t\t\tCPU_TO_LE16(ICE_AQC_RES_TYPE_VSI_LIST_PRUNE);\n+\t} else {\n+\t\tstatus = ICE_ERR_PARAM;\n+\t\tgoto ice_aq_alloc_free_vsi_list_exit;\n+\t}\n+\n+\tif (opc == ice_aqc_opc_free_res)\n+\t\tsw_buf->elem[0].e.sw_resp = CPU_TO_LE16(*vsi_list_id);\n+\n+\tstatus = ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len, opc, NULL);\n+\tif (status)\n+\t\tgoto ice_aq_alloc_free_vsi_list_exit;\n+\n+\tif (opc == ice_aqc_opc_alloc_res) {\n+\t\tvsi_ele = &sw_buf->elem[0];\n+\t\t*vsi_list_id = LE16_TO_CPU(vsi_ele->e.sw_resp);\n+\t}\n+\n+ice_aq_alloc_free_vsi_list_exit:\n+\tice_free(hw, sw_buf);\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_aq_sw_rules - add/update/remove switch rules\n+ * @hw: pointer to the hw struct\n+ * @rule_list: pointer to switch rule population list\n+ * @rule_list_sz: total size of the rule list in bytes\n+ * @num_rules: number of switch rules in the rule_list\n+ * @opc: switch rules population command type - pass in the command opcode\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Add(0x02a0)/Update(0x02a1)/Remove(0x02a2) switch rules commands to firmware\n+ */\n+static enum ice_status\n+ice_aq_sw_rules(struct ice_hw *hw, void *rule_list, u16 rule_list_sz,\n+\t\tu8 num_rules, enum ice_adminq_opc opc, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_sw_rules\");\n+\n+\tif (opc != ice_aqc_opc_add_sw_rules &&\n+\t    opc != ice_aqc_opc_update_sw_rules &&\n+\t    opc != ice_aqc_opc_remove_sw_rules)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, opc);\n+\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\tdesc.params.sw_rules.num_rules_fltr_entry_index =\n+\t\tCPU_TO_LE16(num_rules);\n+\treturn ice_aq_send_cmd(hw, &desc, rule_list, rule_list_sz, cd);\n+}\n+\n+\n+/* ice_init_port_info - Initialize port_info with switch configuration data\n+ * @pi: pointer to port_info\n+ * @vsi_port_num: VSI number or port number\n+ * @type: Type of switch element (port or VSI)\n+ * @swid: switch ID of the switch the element is attached to\n+ * @pf_vf_num: PF or VF number\n+ * @is_vf: true if the element is a VF, false otherwise\n+ */\n+static void\n+ice_init_port_info(struct ice_port_info *pi, u16 vsi_port_num, u8 type,\n+\t\t   u16 swid, u16 pf_vf_num, bool is_vf)\n+{\n+\tswitch (type) {\n+\tcase ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT:\n+\t\tpi->lport = (u8)(vsi_port_num & ICE_LPORT_MASK);\n+\t\tpi->sw_id = swid;\n+\t\tpi->pf_vf_num = pf_vf_num;\n+\t\tpi->is_vf = is_vf;\n+\t\tpi->dflt_tx_vsi_num = ICE_DFLT_VSI_INVAL;\n+\t\tpi->dflt_rx_vsi_num = ICE_DFLT_VSI_INVAL;\n+\t\tbreak;\n+\tdefault:\n+\t\tice_debug(pi->hw, ICE_DBG_SW,\n+\t\t\t  \"incorrect VSI/port type received\\n\");\n+\t\tbreak;\n+\t}\n+}\n+\n+/* ice_get_initial_sw_cfg - Get initial port and default VSI data\n+ * @hw: pointer to the hardware structure\n+ */\n+enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw)\n+{\n+\tstruct ice_aqc_get_sw_cfg_resp *rbuf;\n+\tenum ice_status status;\n+\tu16 num_total_ports;\n+\tu16 req_desc = 0;\n+\tu16 num_elems;\n+\tu16 j = 0;\n+\tu16 i;\n+\n+\tnum_total_ports = 1;\n+\n+\trbuf = (struct ice_aqc_get_sw_cfg_resp *)\n+\t\tice_malloc(hw, ICE_SW_CFG_MAX_BUF_LEN);\n+\n+\tif (!rbuf)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t/* Multiple calls to ice_aq_get_sw_cfg may be required\n+\t * to get all the switch configuration information. The need\n+\t * for additional calls is indicated by ice_aq_get_sw_cfg\n+\t * writing a non-zero value in req_desc\n+\t */\n+\tdo {\n+\t\tstatus = ice_aq_get_sw_cfg(hw, rbuf, ICE_SW_CFG_MAX_BUF_LEN,\n+\t\t\t\t\t   &req_desc, &num_elems, NULL);\n+\n+\t\tif (status)\n+\t\t\tbreak;\n+\n+\t\tfor (i = 0; i < num_elems; i++) {\n+\t\t\tstruct ice_aqc_get_sw_cfg_resp_elem *ele;\n+\t\t\tu16 pf_vf_num, swid, vsi_port_num;\n+\t\t\tbool is_vf = false;\n+\t\t\tu8 type;\n+\n+\t\t\tele = rbuf[i].elements;\n+\t\t\tvsi_port_num = LE16_TO_CPU(ele->vsi_port_num) &\n+\t\t\t\tICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M;\n+\n+\t\t\tpf_vf_num = LE16_TO_CPU(ele->pf_vf_num) &\n+\t\t\t\tICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M;\n+\n+\t\t\tswid = LE16_TO_CPU(ele->swid);\n+\n+\t\t\tif (LE16_TO_CPU(ele->pf_vf_num) &\n+\t\t\t    ICE_AQC_GET_SW_CONF_RESP_IS_VF)\n+\t\t\t\tis_vf = true;\n+\n+\t\t\ttype = LE16_TO_CPU(ele->vsi_port_num) >>\n+\t\t\t\tICE_AQC_GET_SW_CONF_RESP_TYPE_S;\n+\n+\t\t\tswitch (type) {\n+\t\t\tcase ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT:\n+\t\t\tcase ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT:\n+\t\t\t\tif (j == num_total_ports) {\n+\t\t\t\t\tice_debug(hw, ICE_DBG_SW,\n+\t\t\t\t\t\t  \"more ports than expected\\n\");\n+\t\t\t\t\tstatus = ICE_ERR_CFG;\n+\t\t\t\t\tgoto out;\n+\t\t\t\t}\n+\t\t\t\tice_init_port_info(hw->port_info,\n+\t\t\t\t\t\t   vsi_port_num, type, swid,\n+\t\t\t\t\t\t   pf_vf_num, is_vf);\n+\t\t\t\tj++;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t} while (req_desc && !status);\n+\n+\n+out:\n+\tice_free(hw, (void *)rbuf);\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_fill_sw_info - Helper function to populate lb_en and lan_en\n+ * @hw: pointer to the hardware structure\n+ * @fi: filter info structure to fill/update\n+ *\n+ * This helper function populates the lb_en and lan_en elements of the provided\n+ * ice_fltr_info struct using the switch's type and characteristics of the\n+ * switch rule being configured.\n+ */\n+static void ice_fill_sw_info(struct ice_hw *hw, struct ice_fltr_info *fi)\n+{\n+\tfi->lb_en = false;\n+\tfi->lan_en = false;\n+\tif ((fi->flag & ICE_FLTR_TX) &&\n+\t    (fi->fltr_act == ICE_FWD_TO_VSI ||\n+\t     fi->fltr_act == ICE_FWD_TO_VSI_LIST ||\n+\t     fi->fltr_act == ICE_FWD_TO_Q ||\n+\t     fi->fltr_act == ICE_FWD_TO_QGRP)) {\n+\t\tfi->lb_en = true;\n+\t\t/* Do not set lan_en to TRUE if\n+\t\t * 1. The switch is a VEB AND\n+\t\t * 2\n+\t\t * 2.1 The lookup is MAC with unicast addr for MAC, OR\n+\t\t * 2.2 The lookup is MAC_VLAN with unicast addr for MAC\n+\t\t *\n+\t\t * In all other cases, the LAN enable has to be set to true.\n+\t\t */\n+\t\tif (!(hw->evb_veb &&\n+\t\t      ((fi->lkup_type == ICE_SW_LKUP_MAC &&\n+\t\t\tIS_UNICAST_ETHER_ADDR(fi->l_data.mac.mac_addr)) ||\n+\t\t       (fi->lkup_type == ICE_SW_LKUP_MAC_VLAN &&\n+\t\t\tIS_UNICAST_ETHER_ADDR(fi->l_data.mac_vlan.mac_addr)))))\n+\t\t\tfi->lan_en = true;\n+\t}\n+}\n+\n+/**\n+ * ice_ilog2 - Caculates integer log base 2 of a number\n+ * @n: number on which to perform operation\n+ */\n+static int ice_ilog2(u64 n)\n+{\n+\tint i;\n+\n+\tfor (i = 63; i >= 0; i--)\n+\t\tif (((u64)1 << i) & n)\n+\t\t\treturn i;\n+\n+\treturn -1;\n+}\n+\n+\n+/**\n+ * ice_fill_sw_rule - Helper function to fill switch rule structure\n+ * @hw: pointer to the hardware structure\n+ * @f_info: entry containing packet forwarding information\n+ * @s_rule: switch rule structure to be filled in based on mac_entry\n+ * @opc: switch rules population command type - pass in the command opcode\n+ */\n+static void\n+ice_fill_sw_rule(struct ice_hw *hw, struct ice_fltr_info *f_info,\n+\t\t struct ice_aqc_sw_rules_elem *s_rule, enum ice_adminq_opc opc)\n+{\n+\tu16 vlan_id = ICE_MAX_VLAN_ID + 1;\n+\tvoid *daddr = NULL;\n+\tu16 eth_hdr_sz;\n+\tu8 *eth_hdr;\n+\tu32 act = 0;\n+\t__be16 *off;\n+\tu8 q_rgn;\n+\n+\n+\tif (opc == ice_aqc_opc_remove_sw_rules) {\n+\t\ts_rule->pdata.lkup_tx_rx.act = 0;\n+\t\ts_rule->pdata.lkup_tx_rx.index =\n+\t\t\tCPU_TO_LE16(f_info->fltr_rule_id);\n+\t\ts_rule->pdata.lkup_tx_rx.hdr_len = 0;\n+\t\treturn;\n+\t}\n+\n+\teth_hdr_sz = sizeof(dummy_eth_header);\n+\teth_hdr = s_rule->pdata.lkup_tx_rx.hdr;\n+\n+\t/* initialize the ether header with a dummy header */\n+\tice_memcpy(eth_hdr, dummy_eth_header, eth_hdr_sz, ICE_NONDMA_TO_NONDMA);\n+\tice_fill_sw_info(hw, f_info);\n+\n+\tswitch (f_info->fltr_act) {\n+\tcase ICE_FWD_TO_VSI:\n+\t\tact |= (f_info->fwd_id.hw_vsi_id << ICE_SINGLE_ACT_VSI_ID_S) &\n+\t\t\tICE_SINGLE_ACT_VSI_ID_M;\n+\t\tif (f_info->lkup_type != ICE_SW_LKUP_VLAN)\n+\t\t\tact |= ICE_SINGLE_ACT_VSI_FORWARDING |\n+\t\t\t\tICE_SINGLE_ACT_VALID_BIT;\n+\t\tbreak;\n+\tcase ICE_FWD_TO_VSI_LIST:\n+\t\tact |= ICE_SINGLE_ACT_VSI_LIST;\n+\t\tact |= (f_info->fwd_id.vsi_list_id <<\n+\t\t\tICE_SINGLE_ACT_VSI_LIST_ID_S) &\n+\t\t\tICE_SINGLE_ACT_VSI_LIST_ID_M;\n+\t\tif (f_info->lkup_type != ICE_SW_LKUP_VLAN)\n+\t\t\tact |= ICE_SINGLE_ACT_VSI_FORWARDING |\n+\t\t\t\tICE_SINGLE_ACT_VALID_BIT;\n+\t\tbreak;\n+\tcase ICE_FWD_TO_Q:\n+\t\tact |= ICE_SINGLE_ACT_TO_Q;\n+\t\tact |= (f_info->fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) &\n+\t\t\tICE_SINGLE_ACT_Q_INDEX_M;\n+\t\tbreak;\n+\tcase ICE_DROP_PACKET:\n+\t\tact |= ICE_SINGLE_ACT_VSI_FORWARDING | ICE_SINGLE_ACT_DROP |\n+\t\t\tICE_SINGLE_ACT_VALID_BIT;\n+\t\tbreak;\n+\tcase ICE_FWD_TO_QGRP:\n+\t\tq_rgn = f_info->qgrp_size > 0 ?\n+\t\t\t(u8)ice_ilog2(f_info->qgrp_size) : 0;\n+\t\tact |= ICE_SINGLE_ACT_TO_Q;\n+\t\tact |= (f_info->fwd_id.q_id << ICE_SINGLE_ACT_Q_INDEX_S) &\n+\t\t\tICE_SINGLE_ACT_Q_INDEX_M;\n+\t\tact |= (q_rgn << ICE_SINGLE_ACT_Q_REGION_S) &\n+\t\t\tICE_SINGLE_ACT_Q_REGION_M;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tif (f_info->lb_en)\n+\t\tact |= ICE_SINGLE_ACT_LB_ENABLE;\n+\tif (f_info->lan_en)\n+\t\tact |= ICE_SINGLE_ACT_LAN_ENABLE;\n+\n+\tswitch (f_info->lkup_type) {\n+\tcase ICE_SW_LKUP_MAC:\n+\t\tdaddr = f_info->l_data.mac.mac_addr;\n+\t\tbreak;\n+\tcase ICE_SW_LKUP_VLAN:\n+\t\tvlan_id = f_info->l_data.vlan.vlan_id;\n+\t\tif (f_info->fltr_act == ICE_FWD_TO_VSI ||\n+\t\t    f_info->fltr_act == ICE_FWD_TO_VSI_LIST) {\n+\t\t\tact |= ICE_SINGLE_ACT_PRUNE;\n+\t\t\tact |= ICE_SINGLE_ACT_EGRESS | ICE_SINGLE_ACT_INGRESS;\n+\t\t}\n+\t\tbreak;\n+\tcase ICE_SW_LKUP_ETHERTYPE_MAC:\n+\t\tdaddr = f_info->l_data.ethertype_mac.mac_addr;\n+\t\t/* fall-through */\n+\tcase ICE_SW_LKUP_ETHERTYPE:\n+\t\toff = (__be16 *)(eth_hdr + ICE_ETH_ETHTYPE_OFFSET);\n+\t\t*off = CPU_TO_BE16(f_info->l_data.ethertype_mac.ethertype);\n+\t\tbreak;\n+\tcase ICE_SW_LKUP_MAC_VLAN:\n+\t\tdaddr = f_info->l_data.mac_vlan.mac_addr;\n+\t\tvlan_id = f_info->l_data.mac_vlan.vlan_id;\n+\t\tbreak;\n+\tcase ICE_SW_LKUP_PROMISC_VLAN:\n+\t\tvlan_id = f_info->l_data.mac_vlan.vlan_id;\n+\t\t/* fall-through */\n+\tcase ICE_SW_LKUP_PROMISC:\n+\t\tdaddr = f_info->l_data.mac_vlan.mac_addr;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\ts_rule->type = (f_info->flag & ICE_FLTR_RX) ?\n+\t\tCPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_RX) :\n+\t\tCPU_TO_LE16(ICE_AQC_SW_RULES_T_LKUP_TX);\n+\n+\t/* Recipe set depending on lookup type */\n+\ts_rule->pdata.lkup_tx_rx.recipe_id = CPU_TO_LE16(f_info->lkup_type);\n+\ts_rule->pdata.lkup_tx_rx.src = CPU_TO_LE16(f_info->src);\n+\ts_rule->pdata.lkup_tx_rx.act = CPU_TO_LE32(act);\n+\n+\tif (daddr)\n+\t\tice_memcpy(eth_hdr + ICE_ETH_DA_OFFSET, daddr, ETH_ALEN,\n+\t\t\t   ICE_NONDMA_TO_NONDMA);\n+\n+\tif (!(vlan_id > ICE_MAX_VLAN_ID)) {\n+\t\toff = (__be16 *)(eth_hdr + ICE_ETH_VLAN_TCI_OFFSET);\n+\t\t*off = CPU_TO_BE16(vlan_id);\n+\t}\n+\n+\t/* Create the switch rule with the final dummy Ethernet header */\n+\tif (opc != ice_aqc_opc_update_sw_rules)\n+\t\ts_rule->pdata.lkup_tx_rx.hdr_len = CPU_TO_LE16(eth_hdr_sz);\n+}\n+\n+/**\n+ * ice_add_marker_act\n+ * @hw: pointer to the hardware structure\n+ * @m_ent: the management entry for which sw marker needs to be added\n+ * @sw_marker: sw marker to tag the Rx descriptor with\n+ * @l_id: large action resource id\n+ *\n+ * Create a large action to hold software marker and update the switch rule\n+ * entry pointed by m_ent with newly created large action\n+ */\n+static enum ice_status\n+ice_add_marker_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n+\t\t   u16 sw_marker, u16 l_id)\n+{\n+\tstruct ice_aqc_sw_rules_elem *lg_act, *rx_tx;\n+\t/* For software marker we need 3 large actions\n+\t * 1. FWD action: FWD TO VSI or VSI LIST\n+\t * 2. GENERIC VALUE action to hold the profile id\n+\t * 3. GENERIC VALUE action to hold the software marker id\n+\t */\n+\tconst u16 num_lg_acts = 3;\n+\tenum ice_status status;\n+\tu16 lg_act_size;\n+\tu16 rules_size;\n+\tu32 act;\n+\tu16 id;\n+\n+\tif (m_ent->fltr_info.lkup_type != ICE_SW_LKUP_MAC)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Create two back-to-back switch rules and submit them to the HW using\n+\t * one memory buffer:\n+\t *    1. Large Action\n+\t *    2. Look up Tx Rx\n+\t */\n+\tlg_act_size = (u16)ICE_SW_RULE_LG_ACT_SIZE(num_lg_acts);\n+\trules_size = lg_act_size + ICE_SW_RULE_RX_TX_ETH_HDR_SIZE;\n+\tlg_act = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, rules_size);\n+\tif (!lg_act)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\trx_tx = (struct ice_aqc_sw_rules_elem *)((u8 *)lg_act + lg_act_size);\n+\n+\t/* Fill in the first switch rule i.e. large action */\n+\tlg_act->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_LG_ACT);\n+\tlg_act->pdata.lg_act.index = CPU_TO_LE16(l_id);\n+\tlg_act->pdata.lg_act.size = CPU_TO_LE16(num_lg_acts);\n+\n+\t/* First action VSI forwarding or VSI list forwarding depending on how\n+\t * many VSIs\n+\t */\n+\tid = (m_ent->vsi_count > 1) ? m_ent->fltr_info.fwd_id.vsi_list_id :\n+\t\tm_ent->fltr_info.fwd_id.hw_vsi_id;\n+\n+\tact = ICE_LG_ACT_VSI_FORWARDING | ICE_LG_ACT_VALID_BIT;\n+\tact |= (id << ICE_LG_ACT_VSI_LIST_ID_S) &\n+\t\tICE_LG_ACT_VSI_LIST_ID_M;\n+\tif (m_ent->vsi_count > 1)\n+\t\tact |= ICE_LG_ACT_VSI_LIST;\n+\tlg_act->pdata.lg_act.act[0] = CPU_TO_LE32(act);\n+\n+\t/* Second action descriptor type */\n+\tact = ICE_LG_ACT_GENERIC;\n+\n+\tact |= (1 << ICE_LG_ACT_GENERIC_VALUE_S) & ICE_LG_ACT_GENERIC_VALUE_M;\n+\tlg_act->pdata.lg_act.act[1] = CPU_TO_LE32(act);\n+\n+\tact = (ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX <<\n+\t       ICE_LG_ACT_GENERIC_OFFSET_S) & ICE_LG_ACT_GENERIC_OFFSET_M;\n+\n+\t/* Third action Marker value */\n+\tact |= ICE_LG_ACT_GENERIC;\n+\tact |= (sw_marker << ICE_LG_ACT_GENERIC_VALUE_S) &\n+\t\tICE_LG_ACT_GENERIC_VALUE_M;\n+\n+\tlg_act->pdata.lg_act.act[2] = CPU_TO_LE32(act);\n+\n+\t/* call the fill switch rule to fill the lookup Tx Rx structure */\n+\tice_fill_sw_rule(hw, &m_ent->fltr_info, rx_tx,\n+\t\t\t ice_aqc_opc_update_sw_rules);\n+\n+\t/* Update the action to point to the large action id */\n+\trx_tx->pdata.lkup_tx_rx.act =\n+\t\tCPU_TO_LE32(ICE_SINGLE_ACT_PTR |\n+\t\t\t    ((l_id << ICE_SINGLE_ACT_PTR_VAL_S) &\n+\t\t\t     ICE_SINGLE_ACT_PTR_VAL_M));\n+\n+\t/* Use the filter rule id of the previously created rule with single\n+\t * act. Once the update happens, hardware will treat this as large\n+\t * action\n+\t */\n+\trx_tx->pdata.lkup_tx_rx.index =\n+\t\tCPU_TO_LE16(m_ent->fltr_info.fltr_rule_id);\n+\n+\tstatus = ice_aq_sw_rules(hw, lg_act, rules_size, 2,\n+\t\t\t\t ice_aqc_opc_update_sw_rules, NULL);\n+\tif (!status) {\n+\t\tm_ent->lg_act_idx = l_id;\n+\t\tm_ent->sw_marker_id = sw_marker;\n+\t}\n+\n+\tice_free(hw, lg_act);\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_create_vsi_list_map\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle_arr: array of VSI handles to set in the VSI mapping\n+ * @num_vsi: number of VSI handles in the array\n+ * @vsi_list_id: VSI list id generated as part of allocate resource\n+ *\n+ * Helper function to create a new entry of VSI list id to VSI mapping\n+ * using the given VSI list id\n+ */\n+static struct ice_vsi_list_map_info *\n+ice_create_vsi_list_map(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,\n+\t\t\tu16 vsi_list_id)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct ice_vsi_list_map_info *v_map;\n+\tint i;\n+\n+\tv_map = (struct ice_vsi_list_map_info *)ice_calloc(hw, 1,\n+\t\tsizeof(*v_map));\n+\tif (!v_map)\n+\t\treturn NULL;\n+\n+\tv_map->vsi_list_id = vsi_list_id;\n+\tv_map->ref_cnt = 1;\n+\tfor (i = 0; i < num_vsi; i++)\n+\t\tice_set_bit(vsi_handle_arr[i], v_map->vsi_map);\n+\n+\tLIST_ADD(&v_map->list_entry, &sw->vsi_list_map_head);\n+\treturn v_map;\n+}\n+\n+/**\n+ * ice_update_vsi_list_rule\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle_arr: array of VSI handles to form a VSI list\n+ * @num_vsi: number of VSI handles in the array\n+ * @vsi_list_id: VSI list id generated as part of allocate resource\n+ * @remove: Boolean value to indicate if this is a remove action\n+ * @opc: switch rules population command type - pass in the command opcode\n+ * @lkup_type: lookup type of the filter\n+ *\n+ * Call AQ command to add a new switch rule or update existing switch rule\n+ * using the given VSI list id\n+ */\n+static enum ice_status\n+ice_update_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,\n+\t\t\t u16 vsi_list_id, bool remove, enum ice_adminq_opc opc,\n+\t\t\t enum ice_sw_lkup_type lkup_type)\n+{\n+\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\tenum ice_status status;\n+\tu16 s_rule_size;\n+\tu16 type;\n+\tint i;\n+\n+\tif (!num_vsi)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (lkup_type == ICE_SW_LKUP_MAC ||\n+\t    lkup_type == ICE_SW_LKUP_MAC_VLAN ||\n+\t    lkup_type == ICE_SW_LKUP_ETHERTYPE ||\n+\t    lkup_type == ICE_SW_LKUP_ETHERTYPE_MAC ||\n+\t    lkup_type == ICE_SW_LKUP_PROMISC ||\n+\t    lkup_type == ICE_SW_LKUP_PROMISC_VLAN)\n+\t\ttype = remove ? ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR :\n+\t\t\t\tICE_AQC_SW_RULES_T_VSI_LIST_SET;\n+\telse if (lkup_type == ICE_SW_LKUP_VLAN)\n+\t\ttype = remove ? ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR :\n+\t\t\t\tICE_AQC_SW_RULES_T_PRUNE_LIST_SET;\n+\telse\n+\t\treturn ICE_ERR_PARAM;\n+\n+\ts_rule_size = (u16)ICE_SW_RULE_VSI_LIST_SIZE(num_vsi);\n+\ts_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size);\n+\tif (!s_rule)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\tfor (i = 0; i < num_vsi; i++) {\n+\t\tif (!ice_is_vsi_valid(hw, vsi_handle_arr[i])) {\n+\t\t\tstatus = ICE_ERR_PARAM;\n+\t\t\tgoto exit;\n+\t\t}\n+\t\t/* AQ call requires hw_vsi_id(s) */\n+\t\ts_rule->pdata.vsi_list.vsi[i] =\n+\t\t\tCPU_TO_LE16(ice_get_hw_vsi_num(hw, vsi_handle_arr[i]));\n+\t}\n+\n+\ts_rule->type = CPU_TO_LE16(type);\n+\ts_rule->pdata.vsi_list.number_vsi = CPU_TO_LE16(num_vsi);\n+\ts_rule->pdata.vsi_list.index = CPU_TO_LE16(vsi_list_id);\n+\n+\tstatus = ice_aq_sw_rules(hw, s_rule, s_rule_size, 1, opc, NULL);\n+\n+exit:\n+\tice_free(hw, s_rule);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_create_vsi_list_rule - Creates and populates a VSI list rule\n+ * @hw: pointer to the hw struct\n+ * @vsi_handle_arr: array of VSI handles to form a VSI list\n+ * @num_vsi: number of VSI handles in the array\n+ * @vsi_list_id: stores the ID of the VSI list to be created\n+ * @lkup_type: switch rule filter's lookup type\n+ */\n+static enum ice_status\n+ice_create_vsi_list_rule(struct ice_hw *hw, u16 *vsi_handle_arr, u16 num_vsi,\n+\t\t\t u16 *vsi_list_id, enum ice_sw_lkup_type lkup_type)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_aq_alloc_free_vsi_list(hw, vsi_list_id, lkup_type,\n+\t\t\t\t\t    ice_aqc_opc_alloc_res);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Update the newly created VSI list to include the specified VSIs */\n+\treturn ice_update_vsi_list_rule(hw, vsi_handle_arr, num_vsi,\n+\t\t\t\t\t*vsi_list_id, false,\n+\t\t\t\t\tice_aqc_opc_add_sw_rules, lkup_type);\n+}\n+\n+/**\n+ * ice_create_pkt_fwd_rule\n+ * @hw: pointer to the hardware structure\n+ * @f_entry: entry containing packet forwarding information\n+ *\n+ * Create switch rule with given filter information and add an entry\n+ * to the corresponding filter management list to track this switch rule\n+ * and VSI mapping\n+ */\n+static enum ice_status\n+ice_create_pkt_fwd_rule(struct ice_hw *hw,\n+\t\t\tstruct ice_fltr_list_entry *f_entry)\n+{\n+\tstruct ice_fltr_mgmt_list_entry *fm_entry;\n+\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\tenum ice_sw_lkup_type l_type;\n+\tstruct ice_sw_recipe *recp;\n+\tenum ice_status status;\n+\n+\ts_rule = (struct ice_aqc_sw_rules_elem *)\n+\t\tice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE);\n+\tif (!s_rule)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\tfm_entry = (struct ice_fltr_mgmt_list_entry *)\n+\t\t   ice_malloc(hw, sizeof(*fm_entry));\n+\tif (!fm_entry) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto ice_create_pkt_fwd_rule_exit;\n+\t}\n+\n+\tfm_entry->fltr_info = f_entry->fltr_info;\n+\n+\t/* Initialize all the fields for the management entry */\n+\tfm_entry->vsi_count = 1;\n+\tfm_entry->lg_act_idx = ICE_INVAL_LG_ACT_INDEX;\n+\tfm_entry->sw_marker_id = ICE_INVAL_SW_MARKER_ID;\n+\tfm_entry->counter_index = ICE_INVAL_COUNTER_ID;\n+\n+\tice_fill_sw_rule(hw, &fm_entry->fltr_info, s_rule,\n+\t\t\t ice_aqc_opc_add_sw_rules);\n+\n+\tstatus = ice_aq_sw_rules(hw, s_rule, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE, 1,\n+\t\t\t\t ice_aqc_opc_add_sw_rules, NULL);\n+\tif (status) {\n+\t\tice_free(hw, fm_entry);\n+\t\tgoto ice_create_pkt_fwd_rule_exit;\n+\t}\n+\n+\tf_entry->fltr_info.fltr_rule_id =\n+\t\tLE16_TO_CPU(s_rule->pdata.lkup_tx_rx.index);\n+\tfm_entry->fltr_info.fltr_rule_id =\n+\t\tLE16_TO_CPU(s_rule->pdata.lkup_tx_rx.index);\n+\n+\t/* The book keeping entries will get removed when base driver\n+\t * calls remove filter AQ command\n+\t */\n+\tl_type = fm_entry->fltr_info.lkup_type;\n+\trecp = &hw->switch_info->recp_list[l_type];\n+\tLIST_ADD(&fm_entry->list_entry, &recp->filt_rules);\n+\n+ice_create_pkt_fwd_rule_exit:\n+\tice_free(hw, s_rule);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_update_pkt_fwd_rule\n+ * @hw: pointer to the hardware structure\n+ * @f_info: filter information for switch rule\n+ *\n+ * Call AQ command to update a previously created switch rule with a\n+ * VSI list id\n+ */\n+static enum ice_status\n+ice_update_pkt_fwd_rule(struct ice_hw *hw, struct ice_fltr_info *f_info)\n+{\n+\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\tenum ice_status status;\n+\n+\ts_rule = (struct ice_aqc_sw_rules_elem *)\n+\t\tice_malloc(hw, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE);\n+\tif (!s_rule)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tice_fill_sw_rule(hw, f_info, s_rule, ice_aqc_opc_update_sw_rules);\n+\n+\ts_rule->pdata.lkup_tx_rx.index = CPU_TO_LE16(f_info->fltr_rule_id);\n+\n+\t/* Update switch rule with new rule set to forward VSI list */\n+\tstatus = ice_aq_sw_rules(hw, s_rule, ICE_SW_RULE_RX_TX_ETH_HDR_SIZE, 1,\n+\t\t\t\t ice_aqc_opc_update_sw_rules, NULL);\n+\n+\tice_free(hw, s_rule);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_update_sw_rule_bridge_mode\n+ * @hw: pointer to the hw struct\n+ *\n+ * Updates unicast switch filter rules based on VEB/VEPA mode\n+ */\n+enum ice_status ice_update_sw_rule_bridge_mode(struct ice_hw *hw)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct ice_fltr_mgmt_list_entry *fm_entry;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tstruct LIST_HEAD_TYPE *rule_head;\n+\tstruct ice_lock *rule_lock; /* Lock to protect filter rule list */\n+\n+\trule_lock = &sw->recp_list[ICE_SW_LKUP_MAC].filt_rule_lock;\n+\trule_head = &sw->recp_list[ICE_SW_LKUP_MAC].filt_rules;\n+\n+\tice_acquire_lock(rule_lock);\n+\tLIST_FOR_EACH_ENTRY(fm_entry, rule_head, ice_fltr_mgmt_list_entry,\n+\t\t\t    list_entry) {\n+\t\tstruct ice_fltr_info *fi = &fm_entry->fltr_info;\n+\t\tu8 *addr = fi->l_data.mac.mac_addr;\n+\n+\t\t/* Update unicast Tx rules to reflect the selected\n+\t\t * VEB/VEPA mode\n+\t\t */\n+\t\tif ((fi->flag & ICE_FLTR_TX) && IS_UNICAST_ETHER_ADDR(addr) &&\n+\t\t    (fi->fltr_act == ICE_FWD_TO_VSI ||\n+\t\t     fi->fltr_act == ICE_FWD_TO_VSI_LIST ||\n+\t\t     fi->fltr_act == ICE_FWD_TO_Q ||\n+\t\t     fi->fltr_act == ICE_FWD_TO_QGRP)) {\n+\t\t\tstatus = ice_update_pkt_fwd_rule(hw, fi);\n+\t\t\tif (status)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tice_release_lock(rule_lock);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_add_update_vsi_list\n+ * @hw: pointer to the hardware structure\n+ * @m_entry: pointer to current filter management list entry\n+ * @cur_fltr: filter information from the book keeping entry\n+ * @new_fltr: filter information with the new VSI to be added\n+ *\n+ * Call AQ command to add or update previously created VSI list with new VSI.\n+ *\n+ * Helper function to do book keeping associated with adding filter information\n+ * The algorithm to do the book keeping is described below :\n+ * When a VSI needs to subscribe to a given filter (MAC/VLAN/Ethtype etc.)\n+ *\tif only one VSI has been added till now\n+ *\t\tAllocate a new VSI list and add two VSIs\n+ *\t\tto this list using switch rule command\n+ *\t\tUpdate the previously created switch rule with the\n+ *\t\tnewly created VSI list id\n+ *\tif a VSI list was previously created\n+ *\t\tAdd the new VSI to the previously created VSI list set\n+ *\t\tusing the update switch rule command\n+ */\n+static enum ice_status\n+ice_add_update_vsi_list(struct ice_hw *hw,\n+\t\t\tstruct ice_fltr_mgmt_list_entry *m_entry,\n+\t\t\tstruct ice_fltr_info *cur_fltr,\n+\t\t\tstruct ice_fltr_info *new_fltr)\n+{\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu16 vsi_list_id = 0;\n+\n+\tif ((cur_fltr->fltr_act == ICE_FWD_TO_Q ||\n+\t     cur_fltr->fltr_act == ICE_FWD_TO_QGRP))\n+\t\treturn ICE_ERR_NOT_IMPL;\n+\n+\tif ((new_fltr->fltr_act == ICE_FWD_TO_Q ||\n+\t     new_fltr->fltr_act == ICE_FWD_TO_QGRP) &&\n+\t    (cur_fltr->fltr_act == ICE_FWD_TO_VSI ||\n+\t     cur_fltr->fltr_act == ICE_FWD_TO_VSI_LIST))\n+\t\treturn ICE_ERR_NOT_IMPL;\n+\n+\tif (m_entry->vsi_count < 2 && !m_entry->vsi_list_info) {\n+\t\t/* Only one entry existed in the mapping and it was not already\n+\t\t * a part of a VSI list. So, create a VSI list with the old and\n+\t\t * new VSIs.\n+\t\t */\n+\t\tstruct ice_fltr_info tmp_fltr;\n+\t\tu16 vsi_handle_arr[2];\n+\n+\t\t/* A rule already exists with the new VSI being added */\n+\t\tif (cur_fltr->fwd_id.hw_vsi_id == new_fltr->fwd_id.hw_vsi_id)\n+\t\t\treturn ICE_ERR_ALREADY_EXISTS;\n+\n+\t\tvsi_handle_arr[0] = cur_fltr->vsi_handle;\n+\t\tvsi_handle_arr[1] = new_fltr->vsi_handle;\n+\t\tstatus = ice_create_vsi_list_rule(hw, &vsi_handle_arr[0], 2,\n+\t\t\t\t\t\t  &vsi_list_id,\n+\t\t\t\t\t\t  new_fltr->lkup_type);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\ttmp_fltr = *new_fltr;\n+\t\ttmp_fltr.fltr_rule_id = cur_fltr->fltr_rule_id;\n+\t\ttmp_fltr.fltr_act = ICE_FWD_TO_VSI_LIST;\n+\t\ttmp_fltr.fwd_id.vsi_list_id = vsi_list_id;\n+\t\t/* Update the previous switch rule of \"MAC forward to VSI\" to\n+\t\t * \"MAC fwd to VSI list\"\n+\t\t */\n+\t\tstatus = ice_update_pkt_fwd_rule(hw, &tmp_fltr);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\tcur_fltr->fwd_id.vsi_list_id = vsi_list_id;\n+\t\tcur_fltr->fltr_act = ICE_FWD_TO_VSI_LIST;\n+\t\tm_entry->vsi_list_info =\n+\t\t\tice_create_vsi_list_map(hw, &vsi_handle_arr[0], 2,\n+\t\t\t\t\t\tvsi_list_id);\n+\n+\t\t/* If this entry was large action then the large action needs\n+\t\t * to be updated to point to FWD to VSI list\n+\t\t */\n+\t\tif (m_entry->sw_marker_id != ICE_INVAL_SW_MARKER_ID)\n+\t\t\tstatus =\n+\t\t\t    ice_add_marker_act(hw, m_entry,\n+\t\t\t\t\t       m_entry->sw_marker_id,\n+\t\t\t\t\t       m_entry->lg_act_idx);\n+\t} else {\n+\t\tu16 vsi_handle = new_fltr->vsi_handle;\n+\t\tenum ice_adminq_opc opcode;\n+\n+\t\tif (!m_entry->vsi_list_info)\n+\t\t\treturn ICE_ERR_CFG;\n+\n+\t\t/* A rule already exists with the new VSI being added */\n+\t\tif (ice_is_bit_set(m_entry->vsi_list_info->vsi_map, vsi_handle))\n+\t\t\treturn ICE_SUCCESS;\n+\n+\t\t/* Update the previously created VSI list set with\n+\t\t * the new VSI id passed in\n+\t\t */\n+\t\tvsi_list_id = cur_fltr->fwd_id.vsi_list_id;\n+\t\topcode = ice_aqc_opc_update_sw_rules;\n+\n+\t\tstatus = ice_update_vsi_list_rule(hw, &vsi_handle, 1,\n+\t\t\t\t\t\t  vsi_list_id, false, opcode,\n+\t\t\t\t\t\t  new_fltr->lkup_type);\n+\t\t/* update VSI list mapping info with new VSI id */\n+\t\tif (!status)\n+\t\t\tice_set_bit(vsi_handle,\n+\t\t\t\t    m_entry->vsi_list_info->vsi_map);\n+\t}\n+\tif (!status)\n+\t\tm_entry->vsi_count++;\n+\treturn status;\n+}\n+\n+/**\n+ * ice_find_rule_entry - Search a rule entry\n+ * @hw: pointer to the hardware structure\n+ * @recp_id: lookup type for which the specified rule needs to be searched\n+ * @f_info: rule information\n+ *\n+ * Helper function to search for a given rule entry\n+ * Returns pointer to entry storing the rule if found\n+ */\n+static struct ice_fltr_mgmt_list_entry *\n+ice_find_rule_entry(struct ice_hw *hw, u8 recp_id, struct ice_fltr_info *f_info)\n+{\n+\tstruct ice_fltr_mgmt_list_entry *list_itr, *ret = NULL;\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct LIST_HEAD_TYPE *list_head;\n+\n+\tlist_head = &sw->recp_list[recp_id].filt_rules;\n+\tLIST_FOR_EACH_ENTRY(list_itr, list_head, ice_fltr_mgmt_list_entry,\n+\t\t\t    list_entry) {\n+\t\tif (!memcmp(&f_info->l_data, &list_itr->fltr_info.l_data,\n+\t\t\t    sizeof(f_info->l_data)) &&\n+\t\t    f_info->flag == list_itr->fltr_info.flag) {\n+\t\t\tret = list_itr;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\treturn ret;\n+}\n+\n+/**\n+ * ice_find_vsi_list_entry - Search VSI list map with VSI count 1\n+ * @hw: pointer to the hardware structure\n+ * @recp_id: lookup type for which VSI lists needs to be searched\n+ * @vsi_handle: VSI handle to be found in VSI list\n+ * @vsi_list_id: VSI list id found contaning vsi_handle\n+ *\n+ * Helper function to search a VSI list with single entry containing given VSI\n+ * handle element. This can be extended further to search VSI list with more\n+ * than 1 vsi_count. Returns pointer to VSI list entry if found.\n+ */\n+static struct ice_vsi_list_map_info *\n+ice_find_vsi_list_entry(struct ice_hw *hw, u8 recp_id, u16 vsi_handle,\n+\t\t\tu16 *vsi_list_id)\n+{\n+\tstruct ice_vsi_list_map_info *map_info = NULL;\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct ice_fltr_mgmt_list_entry *list_itr;\n+\tstruct LIST_HEAD_TYPE *list_head;\n+\n+\tlist_head = &sw->recp_list[recp_id].filt_rules;\n+\tLIST_FOR_EACH_ENTRY(list_itr, list_head, ice_fltr_mgmt_list_entry,\n+\t\t\t    list_entry) {\n+\t\tif (list_itr->vsi_count == 1 && list_itr->vsi_list_info) {\n+\t\t\tmap_info = list_itr->vsi_list_info;\n+\t\t\tif (ice_is_bit_set(map_info->vsi_map, vsi_handle)) {\n+\t\t\t\t*vsi_list_id = map_info->vsi_list_id;\n+\t\t\t\treturn map_info;\n+\t\t\t}\n+\t\t}\n+\t}\n+\treturn NULL;\n+}\n+\n+/**\n+ * ice_add_rule_internal - add rule for a given lookup type\n+ * @hw: pointer to the hardware structure\n+ * @recp_id: lookup type (recipe id) for which rule has to be added\n+ * @f_entry: structure containing MAC forwarding information\n+ *\n+ * Adds or updates the rule lists for a given recipe\n+ */\n+static enum ice_status\n+ice_add_rule_internal(struct ice_hw *hw, u8 recp_id,\n+\t\t      struct ice_fltr_list_entry *f_entry)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct ice_fltr_info *new_fltr, *cur_fltr;\n+\tstruct ice_fltr_mgmt_list_entry *m_entry;\n+\tstruct ice_lock *rule_lock; /* Lock to protect filter rule list */\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\tif (!ice_is_vsi_valid(hw, f_entry->fltr_info.vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Load the hw_vsi_id only if the fwd action is fwd to VSI */\n+\tif (f_entry->fltr_info.fltr_act == ICE_FWD_TO_VSI)\n+\t\tf_entry->fltr_info.fwd_id.hw_vsi_id =\n+\t\t\tice_get_hw_vsi_num(hw, f_entry->fltr_info.vsi_handle);\n+\n+\trule_lock = &sw->recp_list[recp_id].filt_rule_lock;\n+\n+\tice_acquire_lock(rule_lock);\n+\tnew_fltr = &f_entry->fltr_info;\n+\tif (new_fltr->flag & ICE_FLTR_RX)\n+\t\tnew_fltr->src = hw->port_info->lport;\n+\telse if (new_fltr->flag & ICE_FLTR_TX)\n+\t\tnew_fltr->src =\n+\t\t\tice_get_hw_vsi_num(hw, f_entry->fltr_info.vsi_handle);\n+\n+\tm_entry = ice_find_rule_entry(hw, recp_id, new_fltr);\n+\tif (!m_entry) {\n+\t\tice_release_lock(rule_lock);\n+\t\treturn ice_create_pkt_fwd_rule(hw, f_entry);\n+\t}\n+\n+\tcur_fltr = &m_entry->fltr_info;\n+\tstatus = ice_add_update_vsi_list(hw, m_entry, cur_fltr, new_fltr);\n+\tice_release_lock(rule_lock);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_remove_vsi_list_rule\n+ * @hw: pointer to the hardware structure\n+ * @vsi_list_id: VSI list id generated as part of allocate resource\n+ * @lkup_type: switch rule filter lookup type\n+ *\n+ * The VSI list should be emptied before this function is called to remove the\n+ * VSI list.\n+ */\n+static enum ice_status\n+ice_remove_vsi_list_rule(struct ice_hw *hw, u16 vsi_list_id,\n+\t\t\t enum ice_sw_lkup_type lkup_type)\n+{\n+\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\tenum ice_status status;\n+\tu16 s_rule_size;\n+\n+\ts_rule_size = (u16)ICE_SW_RULE_VSI_LIST_SIZE(0);\n+\ts_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size);\n+\tif (!s_rule)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\ts_rule->type = CPU_TO_LE16(ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR);\n+\ts_rule->pdata.vsi_list.index = CPU_TO_LE16(vsi_list_id);\n+\n+\t/* Free the vsi_list resource that we allocated. It is assumed that the\n+\t * list is empty at this point.\n+\t */\n+\tstatus = ice_aq_alloc_free_vsi_list(hw, &vsi_list_id, lkup_type,\n+\t\t\t\t\t    ice_aqc_opc_free_res);\n+\n+\tice_free(hw, s_rule);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_rem_update_vsi_list\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: VSI handle of the VSI to remove\n+ * @fm_list: filter management entry for which the VSI list management needs to\n+ *\t     be done\n+ */\n+static enum ice_status\n+ice_rem_update_vsi_list(struct ice_hw *hw, u16 vsi_handle,\n+\t\t\tstruct ice_fltr_mgmt_list_entry *fm_list)\n+{\n+\tenum ice_sw_lkup_type lkup_type;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu16 vsi_list_id;\n+\n+\tif (fm_list->fltr_info.fltr_act != ICE_FWD_TO_VSI_LIST ||\n+\t    fm_list->vsi_count == 0)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* A rule with the VSI being removed does not exist */\n+\tif (!ice_is_bit_set(fm_list->vsi_list_info->vsi_map, vsi_handle))\n+\t\treturn ICE_ERR_DOES_NOT_EXIST;\n+\n+\tlkup_type = fm_list->fltr_info.lkup_type;\n+\tvsi_list_id = fm_list->fltr_info.fwd_id.vsi_list_id;\n+\tstatus = ice_update_vsi_list_rule(hw, &vsi_handle, 1, vsi_list_id, true,\n+\t\t\t\t\t  ice_aqc_opc_update_sw_rules,\n+\t\t\t\t\t  lkup_type);\n+\tif (status)\n+\t\treturn status;\n+\n+\tfm_list->vsi_count--;\n+\tice_clear_bit(vsi_handle, fm_list->vsi_list_info->vsi_map);\n+\n+\tif (fm_list->vsi_count == 1 && lkup_type != ICE_SW_LKUP_VLAN) {\n+\t\tstruct ice_fltr_info tmp_fltr_info = fm_list->fltr_info;\n+\t\tstruct ice_vsi_list_map_info *vsi_list_info =\n+\t\t\tfm_list->vsi_list_info;\n+\t\tu16 rem_vsi_handle;\n+\n+\t\trem_vsi_handle = ice_find_first_bit(vsi_list_info->vsi_map,\n+\t\t\t\t\t\t    ICE_MAX_VSI);\n+\t\tif (!ice_is_vsi_valid(hw, rem_vsi_handle))\n+\t\t\treturn ICE_ERR_OUT_OF_RANGE;\n+\n+\t\t/* Make sure VSI list is empty before removing it below */\n+\t\tstatus = ice_update_vsi_list_rule(hw, &rem_vsi_handle, 1,\n+\t\t\t\t\t\t  vsi_list_id, true,\n+\t\t\t\t\t\t  ice_aqc_opc_update_sw_rules,\n+\t\t\t\t\t\t  lkup_type);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\ttmp_fltr_info.fltr_act = ICE_FWD_TO_VSI;\n+\t\ttmp_fltr_info.fwd_id.hw_vsi_id =\n+\t\t\tice_get_hw_vsi_num(hw, rem_vsi_handle);\n+\t\ttmp_fltr_info.vsi_handle = rem_vsi_handle;\n+\t\tstatus = ice_update_pkt_fwd_rule(hw, &tmp_fltr_info);\n+\t\tif (status) {\n+\t\t\tice_debug(hw, ICE_DBG_SW,\n+\t\t\t\t  \"Failed to update pkt fwd rule to FWD_TO_VSI on HW VSI %d, error %d\\n\",\n+\t\t\t\t  tmp_fltr_info.fwd_id.hw_vsi_id, status);\n+\t\t\treturn status;\n+\t\t}\n+\n+\t\tfm_list->fltr_info = tmp_fltr_info;\n+\t}\n+\n+\tif ((fm_list->vsi_count == 1 && lkup_type != ICE_SW_LKUP_VLAN) ||\n+\t    (fm_list->vsi_count == 0 && lkup_type == ICE_SW_LKUP_VLAN)) {\n+\t\tstruct ice_vsi_list_map_info *vsi_list_info =\n+\t\t\tfm_list->vsi_list_info;\n+\n+\t\t/* Remove the VSI list since it is no longer used */\n+\t\tstatus = ice_remove_vsi_list_rule(hw, vsi_list_id, lkup_type);\n+\t\tif (status) {\n+\t\t\tice_debug(hw, ICE_DBG_SW,\n+\t\t\t\t  \"Failed to remove VSI list %d, error %d\\n\",\n+\t\t\t\t  vsi_list_id, status);\n+\t\t\treturn status;\n+\t\t}\n+\n+\t\tLIST_DEL(&vsi_list_info->list_entry);\n+\t\tice_free(hw, vsi_list_info);\n+\t\tfm_list->vsi_list_info = NULL;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_remove_rule_internal - Remove a filter rule of a given type\n+ *\n+ * @hw: pointer to the hardware structure\n+ * @recp_id: recipe id for which the rule needs to removed\n+ * @f_entry: rule entry containing filter information\n+ */\n+static enum ice_status\n+ice_remove_rule_internal(struct ice_hw *hw, u8 recp_id,\n+\t\t\t struct ice_fltr_list_entry *f_entry)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct ice_fltr_mgmt_list_entry *list_elem;\n+\tstruct ice_lock *rule_lock; /* Lock to protect filter rule list */\n+\tenum ice_status status = ICE_SUCCESS;\n+\tbool remove_rule = false;\n+\tu16 vsi_handle;\n+\n+\tif (!ice_is_vsi_valid(hw, f_entry->fltr_info.vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\tf_entry->fltr_info.fwd_id.hw_vsi_id =\n+\t\tice_get_hw_vsi_num(hw, f_entry->fltr_info.vsi_handle);\n+\n+\trule_lock = &sw->recp_list[recp_id].filt_rule_lock;\n+\tice_acquire_lock(rule_lock);\n+\tlist_elem = ice_find_rule_entry(hw, recp_id, &f_entry->fltr_info);\n+\tif (!list_elem) {\n+\t\tstatus = ICE_ERR_DOES_NOT_EXIST;\n+\t\tgoto exit;\n+\t}\n+\n+\tif (list_elem->fltr_info.fltr_act != ICE_FWD_TO_VSI_LIST) {\n+\t\tremove_rule = true;\n+\t} else if (!list_elem->vsi_list_info) {\n+\t\tstatus = ICE_ERR_DOES_NOT_EXIST;\n+\t\tgoto exit;\n+\t} else {\n+\t\tif (list_elem->vsi_list_info->ref_cnt > 1)\n+\t\t\tlist_elem->vsi_list_info->ref_cnt--;\n+\t\tvsi_handle = f_entry->fltr_info.vsi_handle;\n+\t\tstatus = ice_rem_update_vsi_list(hw, vsi_handle, list_elem);\n+\t\tif (status)\n+\t\t\tgoto exit;\n+\t\t/* if vsi count goes to zero after updating the vsi list */\n+\t\tif (list_elem->vsi_count == 0)\n+\t\t\tremove_rule = true;\n+\t}\n+\n+\tif (remove_rule) {\n+\t\t/* Remove the lookup rule */\n+\t\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\n+\t\ts_rule = (struct ice_aqc_sw_rules_elem *)\n+\t\t\tice_malloc(hw, ICE_SW_RULE_RX_TX_NO_HDR_SIZE);\n+\t\tif (!s_rule) {\n+\t\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tice_fill_sw_rule(hw, &list_elem->fltr_info, s_rule,\n+\t\t\t\t ice_aqc_opc_remove_sw_rules);\n+\n+\t\tstatus = ice_aq_sw_rules(hw, s_rule,\n+\t\t\t\t\t ICE_SW_RULE_RX_TX_NO_HDR_SIZE, 1,\n+\t\t\t\t\t ice_aqc_opc_remove_sw_rules, NULL);\n+\t\tif (status)\n+\t\t\tgoto exit;\n+\n+\t\t/* Remove a book keeping from the list */\n+\t\tice_free(hw, s_rule);\n+\n+\t\tLIST_DEL(&list_elem->list_entry);\n+\t\tice_free(hw, list_elem);\n+\t}\n+exit:\n+\tice_release_lock(rule_lock);\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_add_mac - Add a MAC address based filter rule\n+ * @hw: pointer to the hardware structure\n+ * @m_list: list of MAC addresses and forwarding information\n+ *\n+ * IMPORTANT: When the ucast_shared flag is set to false and m_list has\n+ * multiple unicast addresses, the function assumes that all the\n+ * addresses are unique in a given add_mac call. It doesn't\n+ * check for duplicates in this case, removing duplicates from a given\n+ * list should be taken care of in the caller of this function.\n+ */\n+enum ice_status\n+ice_add_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list)\n+{\n+\tstruct ice_aqc_sw_rules_elem *s_rule, *r_iter;\n+\tstruct ice_fltr_list_entry *m_list_itr;\n+\tstruct LIST_HEAD_TYPE *rule_head;\n+\tu16 elem_sent, total_elem_left;\n+\tstruct ice_switch_info *sw;\n+\tstruct ice_lock *rule_lock; /* Lock to protect filter rule list */\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu16 num_unicast = 0;\n+\tu16 s_rule_size;\n+\n+\tif (!m_list || !hw)\n+\t\treturn ICE_ERR_PARAM;\n+\ts_rule = NULL;\n+\tsw = hw->switch_info;\n+\trule_lock = &sw->recp_list[ICE_SW_LKUP_MAC].filt_rule_lock;\n+\tLIST_FOR_EACH_ENTRY(m_list_itr, m_list, ice_fltr_list_entry,\n+\t\t\t    list_entry) {\n+\t\tu8 *add = &m_list_itr->fltr_info.l_data.mac.mac_addr[0];\n+\t\tu16 vsi_handle;\n+\t\tu16 hw_vsi_id;\n+\n+\t\tm_list_itr->fltr_info.flag = ICE_FLTR_TX;\n+\t\tvsi_handle = m_list_itr->fltr_info.vsi_handle;\n+\t\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\t\treturn ICE_ERR_PARAM;\n+\t\thw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);\n+\t\tm_list_itr->fltr_info.fwd_id.hw_vsi_id = hw_vsi_id;\n+\t\t/* update the src in case it is vsi num */\n+\t\tif (m_list_itr->fltr_info.src_id != ICE_SRC_ID_VSI)\n+\t\t\treturn ICE_ERR_PARAM;\n+\t\tm_list_itr->fltr_info.src = hw_vsi_id;\n+\t\tif (m_list_itr->fltr_info.lkup_type != ICE_SW_LKUP_MAC ||\n+\t\t    IS_ZERO_ETHER_ADDR(add))\n+\t\t\treturn ICE_ERR_PARAM;\n+\t\tif (IS_UNICAST_ETHER_ADDR(add) && !hw->ucast_shared) {\n+\t\t\t/* Don't overwrite the unicast address */\n+\t\t\tice_acquire_lock(rule_lock);\n+\t\t\tif (ice_find_rule_entry(hw, ICE_SW_LKUP_MAC,\n+\t\t\t\t\t\t&m_list_itr->fltr_info)) {\n+\t\t\t\tice_release_lock(rule_lock);\n+\t\t\t\treturn ICE_ERR_ALREADY_EXISTS;\n+\t\t\t}\n+\t\t\tice_release_lock(rule_lock);\n+\t\t\tnum_unicast++;\n+\t\t} else if (IS_MULTICAST_ETHER_ADDR(add) ||\n+\t\t\t   (IS_UNICAST_ETHER_ADDR(add) && hw->ucast_shared)) {\n+\t\t\tm_list_itr->status =\n+\t\t\t\tice_add_rule_internal(hw, ICE_SW_LKUP_MAC,\n+\t\t\t\t\t\t      m_list_itr);\n+\t\t\tif (m_list_itr->status)\n+\t\t\t\treturn m_list_itr->status;\n+\t\t}\n+\t}\n+\n+\tice_acquire_lock(rule_lock);\n+\t/* Exit if no suitable entries were found for adding bulk switch rule */\n+\tif (!num_unicast) {\n+\t\tstatus = ICE_SUCCESS;\n+\t\tgoto ice_add_mac_exit;\n+\t}\n+\n+\trule_head = &sw->recp_list[ICE_SW_LKUP_MAC].filt_rules;\n+\n+\t/* Allocate switch rule buffer for the bulk update for unicast */\n+\ts_rule_size = ICE_SW_RULE_RX_TX_ETH_HDR_SIZE;\n+\ts_rule = (struct ice_aqc_sw_rules_elem *)\n+\t\tice_calloc(hw, num_unicast, s_rule_size);\n+\tif (!s_rule) {\n+\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\tgoto ice_add_mac_exit;\n+\t}\n+\n+\tr_iter = s_rule;\n+\tLIST_FOR_EACH_ENTRY(m_list_itr, m_list, ice_fltr_list_entry,\n+\t\t\t    list_entry) {\n+\t\tstruct ice_fltr_info *f_info = &m_list_itr->fltr_info;\n+\t\tu8 *mac_addr = &f_info->l_data.mac.mac_addr[0];\n+\n+\t\tif (IS_UNICAST_ETHER_ADDR(mac_addr)) {\n+\t\t\tice_fill_sw_rule(hw, &m_list_itr->fltr_info, r_iter,\n+\t\t\t\t\t ice_aqc_opc_add_sw_rules);\n+\t\t\tr_iter = (struct ice_aqc_sw_rules_elem *)\n+\t\t\t\t((u8 *)r_iter + s_rule_size);\n+\t\t}\n+\t}\n+\n+\t/* Call AQ bulk switch rule update for all unicast addresses */\n+\tr_iter = s_rule;\n+\t/* Call AQ switch rule in AQ_MAX chunk */\n+\tfor (total_elem_left = num_unicast; total_elem_left > 0;\n+\t     total_elem_left -= elem_sent) {\n+\t\tstruct ice_aqc_sw_rules_elem *entry = r_iter;\n+\n+\t\telem_sent = min(total_elem_left,\n+\t\t\t\t(u16)(ICE_AQ_MAX_BUF_LEN / s_rule_size));\n+\t\tstatus = ice_aq_sw_rules(hw, entry, elem_sent * s_rule_size,\n+\t\t\t\t\t elem_sent, ice_aqc_opc_add_sw_rules,\n+\t\t\t\t\t NULL);\n+\t\tif (status)\n+\t\t\tgoto ice_add_mac_exit;\n+\t\tr_iter = (struct ice_aqc_sw_rules_elem *)\n+\t\t\t((u8 *)r_iter + (elem_sent * s_rule_size));\n+\t}\n+\n+\t/* Fill up rule id based on the value returned from FW */\n+\tr_iter = s_rule;\n+\tLIST_FOR_EACH_ENTRY(m_list_itr, m_list, ice_fltr_list_entry,\n+\t\t\t    list_entry) {\n+\t\tstruct ice_fltr_info *f_info = &m_list_itr->fltr_info;\n+\t\tu8 *mac_addr = &f_info->l_data.mac.mac_addr[0];\n+\t\tstruct ice_fltr_mgmt_list_entry *fm_entry;\n+\n+\t\tif (IS_UNICAST_ETHER_ADDR(mac_addr)) {\n+\t\t\tf_info->fltr_rule_id =\n+\t\t\t\tLE16_TO_CPU(r_iter->pdata.lkup_tx_rx.index);\n+\t\t\tf_info->fltr_act = ICE_FWD_TO_VSI;\n+\t\t\t/* Create an entry to track this MAC address */\n+\t\t\tfm_entry = (struct ice_fltr_mgmt_list_entry *)\n+\t\t\t\tice_malloc(hw, sizeof(*fm_entry));\n+\t\t\tif (!fm_entry) {\n+\t\t\t\tstatus = ICE_ERR_NO_MEMORY;\n+\t\t\t\tgoto ice_add_mac_exit;\n+\t\t\t}\n+\t\t\tfm_entry->fltr_info = *f_info;\n+\t\t\tfm_entry->vsi_count = 1;\n+\t\t\t/* The book keeping entries will get removed when\n+\t\t\t * base driver calls remove filter AQ command\n+\t\t\t */\n+\n+\t\t\tLIST_ADD(&fm_entry->list_entry, rule_head);\n+\t\t\tr_iter = (struct ice_aqc_sw_rules_elem *)\n+\t\t\t\t((u8 *)r_iter + s_rule_size);\n+\t\t}\n+\t}\n+\n+ice_add_mac_exit:\n+\tice_release_lock(rule_lock);\n+\tif (s_rule)\n+\t\tice_free(hw, s_rule);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_add_vlan_internal - Add one VLAN based filter rule\n+ * @hw: pointer to the hardware structure\n+ * @f_entry: filter entry containing one VLAN information\n+ */\n+static enum ice_status\n+ice_add_vlan_internal(struct ice_hw *hw, struct ice_fltr_list_entry *f_entry)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct ice_fltr_mgmt_list_entry *v_list_itr;\n+\tstruct ice_fltr_info *new_fltr, *cur_fltr;\n+\tenum ice_sw_lkup_type lkup_type;\n+\tu16 vsi_list_id = 0, vsi_handle;\n+\tstruct ice_lock *rule_lock; /* Lock to protect filter rule list */\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\tif (!ice_is_vsi_valid(hw, f_entry->fltr_info.vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tf_entry->fltr_info.fwd_id.hw_vsi_id =\n+\t\tice_get_hw_vsi_num(hw, f_entry->fltr_info.vsi_handle);\n+\tnew_fltr = &f_entry->fltr_info;\n+\n+\t/* VLAN id should only be 12 bits */\n+\tif (new_fltr->l_data.vlan.vlan_id > ICE_MAX_VLAN_ID)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (new_fltr->src_id != ICE_SRC_ID_VSI)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tnew_fltr->src = new_fltr->fwd_id.hw_vsi_id;\n+\tlkup_type = new_fltr->lkup_type;\n+\tvsi_handle = new_fltr->vsi_handle;\n+\trule_lock = &sw->recp_list[ICE_SW_LKUP_VLAN].filt_rule_lock;\n+\tice_acquire_lock(rule_lock);\n+\tv_list_itr = ice_find_rule_entry(hw, ICE_SW_LKUP_VLAN, new_fltr);\n+\tif (!v_list_itr) {\n+\t\tstruct ice_vsi_list_map_info *map_info = NULL;\n+\n+\t\tif (new_fltr->fltr_act == ICE_FWD_TO_VSI) {\n+\t\t\t/* All VLAN pruning rules use a VSI list. Check if\n+\t\t\t * there is already a VSI list containing VSI that we\n+\t\t\t * want to add. If found, use the same vsi_list_id for\n+\t\t\t * this new VLAN rule or else create a new list.\n+\t\t\t */\n+\t\t\tmap_info = ice_find_vsi_list_entry(hw, ICE_SW_LKUP_VLAN,\n+\t\t\t\t\t\t\t   vsi_handle,\n+\t\t\t\t\t\t\t   &vsi_list_id);\n+\t\t\tif (!map_info) {\n+\t\t\t\tstatus = ice_create_vsi_list_rule(hw,\n+\t\t\t\t\t\t\t\t  &vsi_handle,\n+\t\t\t\t\t\t\t\t  1,\n+\t\t\t\t\t\t\t\t  &vsi_list_id,\n+\t\t\t\t\t\t\t\t  lkup_type);\n+\t\t\t\tif (status)\n+\t\t\t\t\tgoto exit;\n+\t\t\t}\n+\t\t\t/* Convert the action to forwarding to a VSI list. */\n+\t\t\tnew_fltr->fltr_act = ICE_FWD_TO_VSI_LIST;\n+\t\t\tnew_fltr->fwd_id.vsi_list_id = vsi_list_id;\n+\t\t}\n+\n+\t\tstatus = ice_create_pkt_fwd_rule(hw, f_entry);\n+\t\tif (!status) {\n+\t\t\tv_list_itr = ice_find_rule_entry(hw, ICE_SW_LKUP_VLAN,\n+\t\t\t\t\t\t\t new_fltr);\n+\t\t\tif (!v_list_itr) {\n+\t\t\t\tstatus = ICE_ERR_DOES_NOT_EXIST;\n+\t\t\t\tgoto exit;\n+\t\t\t}\n+\t\t\t/* reuse VSI list for new rule and increment ref_cnt */\n+\t\t\tif (map_info) {\n+\t\t\t\tv_list_itr->vsi_list_info = map_info;\n+\t\t\t\tmap_info->ref_cnt++;\n+\t\t\t} else {\n+\t\t\t\tv_list_itr->vsi_list_info =\n+\t\t\t\t\tice_create_vsi_list_map(hw, &vsi_handle,\n+\t\t\t\t\t\t\t\t1, vsi_list_id);\n+\t\t\t}\n+\t\t}\n+\t} else if (v_list_itr->vsi_list_info->ref_cnt == 1) {\n+\t\t/* Update existing VSI list to add new VSI id only if it used\n+\t\t * by one VLAN rule.\n+\t\t */\n+\t\tcur_fltr = &v_list_itr->fltr_info;\n+\t\tstatus = ice_add_update_vsi_list(hw, v_list_itr, cur_fltr,\n+\t\t\t\t\t\t new_fltr);\n+\t} else {\n+\t\t/* If VLAN rule exists and VSI list being used by this rule is\n+\t\t * referenced by more than 1 VLAN rule. Then create a new VSI\n+\t\t * list appending previous VSI with new VSI and update existing\n+\t\t * VLAN rule to point to new VSI list id\n+\t\t */\n+\t\tstruct ice_fltr_info tmp_fltr;\n+\t\tu16 vsi_handle_arr[2];\n+\t\tu16 cur_handle;\n+\n+\t\t/* Current implementation only supports reusing VSI list with\n+\t\t * one VSI count. We should never hit below condition\n+\t\t */\n+\t\tif (v_list_itr->vsi_count > 1 &&\n+\t\t    v_list_itr->vsi_list_info->ref_cnt > 1) {\n+\t\t\tice_debug(hw, ICE_DBG_SW,\n+\t\t\t\t  \"Invalid configuration: Optimization to reuse VSI list with more than one VSI is not being done yet\\n\");\n+\t\t\tstatus = ICE_ERR_CFG;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tcur_handle =\n+\t\t\tice_find_first_bit(v_list_itr->vsi_list_info->vsi_map,\n+\t\t\t\t\t   ICE_MAX_VSI);\n+\n+\t\t/* A rule already exists with the new VSI being added */\n+\t\tif (cur_handle == vsi_handle) {\n+\t\t\tstatus = ICE_ERR_ALREADY_EXISTS;\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tvsi_handle_arr[0] = cur_handle;\n+\t\tvsi_handle_arr[1] = vsi_handle;\n+\t\tstatus = ice_create_vsi_list_rule(hw, &vsi_handle_arr[0], 2,\n+\t\t\t\t\t\t  &vsi_list_id, lkup_type);\n+\t\tif (status)\n+\t\t\tgoto exit;\n+\n+\t\ttmp_fltr = v_list_itr->fltr_info;\n+\t\ttmp_fltr.fltr_rule_id = v_list_itr->fltr_info.fltr_rule_id;\n+\t\ttmp_fltr.fwd_id.vsi_list_id = vsi_list_id;\n+\t\ttmp_fltr.fltr_act = ICE_FWD_TO_VSI_LIST;\n+\t\t/* Update the previous switch rule to a new VSI list which\n+\t\t * includes current VSI that is requested\n+\t\t */\n+\t\tstatus = ice_update_pkt_fwd_rule(hw, &tmp_fltr);\n+\t\tif (status)\n+\t\t\tgoto exit;\n+\n+\t\t/* before overriding VSI list map info. decrement ref_cnt of\n+\t\t * previous VSI list\n+\t\t */\n+\t\tv_list_itr->vsi_list_info->ref_cnt--;\n+\n+\t\t/* now update to newly created list */\n+\t\tv_list_itr->fltr_info.fwd_id.vsi_list_id = vsi_list_id;\n+\t\tv_list_itr->vsi_list_info =\n+\t\t\tice_create_vsi_list_map(hw, &vsi_handle_arr[0], 2,\n+\t\t\t\t\t\tvsi_list_id);\n+\t\tv_list_itr->vsi_count++;\n+\t}\n+\n+exit:\n+\tice_release_lock(rule_lock);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_add_vlan - Add VLAN based filter rule\n+ * @hw: pointer to the hardware structure\n+ * @v_list: list of VLAN entries and forwarding information\n+ */\n+enum ice_status\n+ice_add_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list)\n+{\n+\tstruct ice_fltr_list_entry *v_list_itr;\n+\n+\tif (!v_list || !hw)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tLIST_FOR_EACH_ENTRY(v_list_itr, v_list, ice_fltr_list_entry,\n+\t\t\t    list_entry) {\n+\t\tif (v_list_itr->fltr_info.lkup_type != ICE_SW_LKUP_VLAN)\n+\t\t\treturn ICE_ERR_PARAM;\n+\t\tv_list_itr->fltr_info.flag = ICE_FLTR_TX;\n+\t\tv_list_itr->status = ice_add_vlan_internal(hw, v_list_itr);\n+\t\tif (v_list_itr->status)\n+\t\t\treturn v_list_itr->status;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+\n+\n+/**\n+ * ice_rem_sw_rule_info\n+ * @hw: pointer to the hardware structure\n+ * @rule_head: pointer to the switch list structure that we want to delete\n+ */\n+static void\n+ice_rem_sw_rule_info(struct ice_hw *hw, struct LIST_HEAD_TYPE *rule_head)\n+{\n+\tif (!LIST_EMPTY(rule_head)) {\n+\t\tstruct ice_fltr_mgmt_list_entry *entry;\n+\t\tstruct ice_fltr_mgmt_list_entry *tmp;\n+\n+\t\tLIST_FOR_EACH_ENTRY_SAFE(entry, tmp, rule_head,\n+\t\t\t\t\t ice_fltr_mgmt_list_entry, list_entry) {\n+\t\t\tLIST_DEL(&entry->list_entry);\n+\t\t\tice_free(hw, entry);\n+\t\t}\n+\t}\n+}\n+\n+\n+\n+/**\n+ * ice_cfg_dflt_vsi - change state of VSI to set/clear default\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: VSI handle to set as default\n+ * @set: true to add the above mentioned switch rule, false to remove it\n+ * @direction: ICE_FLTR_RX or ICE_FLTR_TX\n+ *\n+ * add filter rule to set/unset given VSI as default VSI for the switch\n+ * (represented by swid)\n+ */\n+enum ice_status\n+ice_cfg_dflt_vsi(struct ice_hw *hw, u16 vsi_handle, bool set, u8 direction)\n+{\n+\tstruct ice_aqc_sw_rules_elem *s_rule;\n+\tstruct ice_fltr_info f_info;\n+\tenum ice_adminq_opc opcode;\n+\tenum ice_status status;\n+\tu16 s_rule_size;\n+\tu16 hw_vsi_id;\n+\n+\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\thw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);\n+\n+\ts_rule_size = set ? ICE_SW_RULE_RX_TX_ETH_HDR_SIZE :\n+\t\t\t    ICE_SW_RULE_RX_TX_NO_HDR_SIZE;\n+\ts_rule = (struct ice_aqc_sw_rules_elem *)ice_malloc(hw, s_rule_size);\n+\tif (!s_rule)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\tice_memset(&f_info, 0, sizeof(f_info), ICE_NONDMA_MEM);\n+\n+\tf_info.lkup_type = ICE_SW_LKUP_DFLT;\n+\tf_info.flag = direction;\n+\tf_info.fltr_act = ICE_FWD_TO_VSI;\n+\tf_info.fwd_id.hw_vsi_id = hw_vsi_id;\n+\n+\tif (f_info.flag & ICE_FLTR_RX) {\n+\t\tf_info.src = hw->port_info->lport;\n+\t\tf_info.src_id = ICE_SRC_ID_LPORT;\n+\t\tif (!set)\n+\t\t\tf_info.fltr_rule_id =\n+\t\t\t\thw->port_info->dflt_rx_vsi_rule_id;\n+\t} else if (f_info.flag & ICE_FLTR_TX) {\n+\t\tf_info.src_id = ICE_SRC_ID_VSI;\n+\t\tf_info.src = hw_vsi_id;\n+\t\tif (!set)\n+\t\t\tf_info.fltr_rule_id =\n+\t\t\t\thw->port_info->dflt_tx_vsi_rule_id;\n+\t}\n+\n+\tif (set)\n+\t\topcode = ice_aqc_opc_add_sw_rules;\n+\telse\n+\t\topcode = ice_aqc_opc_remove_sw_rules;\n+\n+\tice_fill_sw_rule(hw, &f_info, s_rule, opcode);\n+\n+\tstatus = ice_aq_sw_rules(hw, s_rule, s_rule_size, 1, opcode, NULL);\n+\tif (status || !(f_info.flag & ICE_FLTR_TX_RX))\n+\t\tgoto out;\n+\tif (set) {\n+\t\tu16 index = LE16_TO_CPU(s_rule->pdata.lkup_tx_rx.index);\n+\n+\t\tif (f_info.flag & ICE_FLTR_TX) {\n+\t\t\thw->port_info->dflt_tx_vsi_num = hw_vsi_id;\n+\t\t\thw->port_info->dflt_tx_vsi_rule_id = index;\n+\t\t} else if (f_info.flag & ICE_FLTR_RX) {\n+\t\t\thw->port_info->dflt_rx_vsi_num = hw_vsi_id;\n+\t\t\thw->port_info->dflt_rx_vsi_rule_id = index;\n+\t\t}\n+\t} else {\n+\t\tif (f_info.flag & ICE_FLTR_TX) {\n+\t\t\thw->port_info->dflt_tx_vsi_num = ICE_DFLT_VSI_INVAL;\n+\t\t\thw->port_info->dflt_tx_vsi_rule_id = ICE_INVAL_ACT;\n+\t\t} else if (f_info.flag & ICE_FLTR_RX) {\n+\t\t\thw->port_info->dflt_rx_vsi_num = ICE_DFLT_VSI_INVAL;\n+\t\t\thw->port_info->dflt_rx_vsi_rule_id = ICE_INVAL_ACT;\n+\t\t}\n+\t}\n+\n+out:\n+\tice_free(hw, s_rule);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_remove_mac - remove a MAC address based filter rule\n+ * @hw: pointer to the hardware structure\n+ * @m_list: list of MAC addresses and forwarding information\n+ *\n+ * This function removes either a MAC filter rule or a specific VSI from a\n+ * VSI list for a multicast MAC address.\n+ *\n+ * Returns ICE_ERR_DOES_NOT_EXIST if a given entry was not added by\n+ * ice_add_mac. Caller should be aware that this call will only work if all\n+ * the entries passed into m_list were added previously. It will not attempt to\n+ * do a partial remove of entries that were found.\n+ */\n+enum ice_status\n+ice_remove_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list)\n+{\n+\tstruct ice_fltr_list_entry *list_itr, *tmp;\n+\n+\tif (!m_list)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(list_itr, tmp, m_list, ice_fltr_list_entry,\n+\t\t\t\t list_entry) {\n+\t\tenum ice_sw_lkup_type l_type = list_itr->fltr_info.lkup_type;\n+\n+\t\tif (l_type != ICE_SW_LKUP_MAC)\n+\t\t\treturn ICE_ERR_PARAM;\n+\t\tlist_itr->status = ice_remove_rule_internal(hw,\n+\t\t\t\t\t\t\t    ICE_SW_LKUP_MAC,\n+\t\t\t\t\t\t\t    list_itr);\n+\t\tif (list_itr->status)\n+\t\t\treturn list_itr->status;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_remove_vlan - Remove VLAN based filter rule\n+ * @hw: pointer to the hardware structure\n+ * @v_list: list of VLAN entries and forwarding information\n+ */\n+enum ice_status\n+ice_remove_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list)\n+{\n+\tstruct ice_fltr_list_entry *v_list_itr, *tmp;\n+\n+\tif (!v_list || !hw)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(v_list_itr, tmp, v_list, ice_fltr_list_entry,\n+\t\t\t\t list_entry) {\n+\t\tenum ice_sw_lkup_type l_type = v_list_itr->fltr_info.lkup_type;\n+\n+\t\tif (l_type != ICE_SW_LKUP_VLAN)\n+\t\t\treturn ICE_ERR_PARAM;\n+\t\tv_list_itr->status = ice_remove_rule_internal(hw,\n+\t\t\t\t\t\t\t      ICE_SW_LKUP_VLAN,\n+\t\t\t\t\t\t\t      v_list_itr);\n+\t\tif (v_list_itr->status)\n+\t\t\treturn v_list_itr->status;\n+\t}\n+\treturn ICE_SUCCESS;\n+}\n+\n+\n+/**\n+ * ice_vsi_uses_fltr - Determine if given VSI uses specified filter\n+ * @fm_entry: filter entry to inspect\n+ * @vsi_handle: VSI handle to compare with filter info\n+ */\n+static bool\n+ice_vsi_uses_fltr(struct ice_fltr_mgmt_list_entry *fm_entry, u16 vsi_handle)\n+{\n+\treturn ((fm_entry->fltr_info.fltr_act == ICE_FWD_TO_VSI &&\n+\t\t fm_entry->fltr_info.vsi_handle == vsi_handle) ||\n+\t\t(fm_entry->fltr_info.fltr_act == ICE_FWD_TO_VSI_LIST &&\n+\t\t (ice_is_bit_set(fm_entry->vsi_list_info->vsi_map,\n+\t\t\t\t vsi_handle))));\n+}\n+\n+/**\n+ * ice_add_entry_to_vsi_fltr_list - Add copy of fltr_list_entry to remove list\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: VSI handle to remove filters from\n+ * @vsi_list_head: pointer to the list to add entry to\n+ * @fi: pointer to fltr_info of filter entry to copy & add\n+ *\n+ * Helper function, used when creating a list of filters to remove from\n+ * a specific VSI. The entry added to vsi_list_head is a COPY of the\n+ * original filter entry, with the exception of fltr_info.fltr_act and\n+ * fltr_info.fwd_id fields. These are set such that later logic can\n+ * extract which VSI to remove the fltr from, and pass on that information.\n+ */\n+static enum ice_status\n+ice_add_entry_to_vsi_fltr_list(struct ice_hw *hw, u16 vsi_handle,\n+\t\t\t       struct LIST_HEAD_TYPE *vsi_list_head,\n+\t\t\t       struct ice_fltr_info *fi)\n+{\n+\tstruct ice_fltr_list_entry *tmp;\n+\n+\t/* this memory is freed up in the caller function\n+\t * once filters for this VSI are removed\n+\t */\n+\ttmp = (struct ice_fltr_list_entry *)ice_malloc(hw, sizeof(*tmp));\n+\tif (!tmp)\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\ttmp->fltr_info = *fi;\n+\n+\t/* Overwrite these fields to indicate which VSI to remove filter from,\n+\t * so find and remove logic can extract the information from the\n+\t * list entries. Note that original entries will still have proper\n+\t * values.\n+\t */\n+\ttmp->fltr_info.fltr_act = ICE_FWD_TO_VSI;\n+\ttmp->fltr_info.vsi_handle = vsi_handle;\n+\ttmp->fltr_info.fwd_id.hw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);\n+\n+\tLIST_ADD(&tmp->list_entry, vsi_list_head);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_add_to_vsi_fltr_list - Add VSI filters to the list\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: VSI handle to remove filters from\n+ * @lkup_list_head: pointer to the list that has certain lookup type filters\n+ * @vsi_list_head: pointer to the list pertaining to VSI with vsi_handle\n+ *\n+ * Locates all filters in lkup_list_head that are used by the given VSI,\n+ * and adds COPIES of those entries to vsi_list_head (intended to be used\n+ * to remove the listed filters).\n+ * Note that this means all entries in vsi_list_head must be explicitly\n+ * deallocated by the caller when done with list.\n+ */\n+#if defined(SRIOV_SUPPORT) && !defined(NO_VF_PROMISC_SUPPORT)\n+enum ice_status\n+#else\n+static enum ice_status\n+#endif\n+ice_add_to_vsi_fltr_list(struct ice_hw *hw, u16 vsi_handle,\n+\t\t\t struct LIST_HEAD_TYPE *lkup_list_head,\n+\t\t\t struct LIST_HEAD_TYPE *vsi_list_head)\n+{\n+\tstruct ice_fltr_mgmt_list_entry *fm_entry;\n+\tenum ice_status status = ICE_SUCCESS;\n+\n+\t/* check to make sure VSI id is valid and within boundary */\n+\tif (!ice_is_vsi_valid(hw, vsi_handle))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tLIST_FOR_EACH_ENTRY(fm_entry, lkup_list_head,\n+\t\t\t    ice_fltr_mgmt_list_entry, list_entry) {\n+\t\tstruct ice_fltr_info *fi;\n+\n+\t\tfi = &fm_entry->fltr_info;\n+\t\tif (!fi || !ice_vsi_uses_fltr(fm_entry, vsi_handle))\n+\t\t\tcontinue;\n+\n+\t\tstatus = ice_add_entry_to_vsi_fltr_list(hw, vsi_handle,\n+\t\t\t\t\t\t\tvsi_list_head, fi);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\treturn status;\n+}\n+\n+\n+\n+/**\n+ * ice_remove_vsi_lkup_fltr - Remove lookup type filters for a VSI\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: VSI handle to remove filters from\n+ * @lkup: switch rule filter lookup type\n+ */\n+static void\n+ice_remove_vsi_lkup_fltr(struct ice_hw *hw, u16 vsi_handle,\n+\t\t\t enum ice_sw_lkup_type lkup)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tstruct ice_fltr_list_entry *fm_entry;\n+\tstruct LIST_HEAD_TYPE remove_list_head;\n+\tstruct LIST_HEAD_TYPE *rule_head;\n+\tstruct ice_fltr_list_entry *tmp;\n+\tstruct ice_lock *rule_lock;\t/* Lock to protect filter rule list */\n+\tenum ice_status status;\n+\n+\tINIT_LIST_HEAD(&remove_list_head);\n+\trule_lock = &sw->recp_list[lkup].filt_rule_lock;\n+\trule_head = &sw->recp_list[lkup].filt_rules;\n+\tice_acquire_lock(rule_lock);\n+\tstatus = ice_add_to_vsi_fltr_list(hw, vsi_handle, rule_head,\n+\t\t\t\t\t  &remove_list_head);\n+\tice_release_lock(rule_lock);\n+\tif (status)\n+\t\treturn;\n+\n+\tswitch (lkup) {\n+\tcase ICE_SW_LKUP_MAC:\n+\t\tice_remove_mac(hw, &remove_list_head);\n+\t\tbreak;\n+\tcase ICE_SW_LKUP_VLAN:\n+\t\tice_remove_vlan(hw, &remove_list_head);\n+\t\tbreak;\n+\tcase ICE_SW_LKUP_MAC_VLAN:\n+\tcase ICE_SW_LKUP_ETHERTYPE:\n+\tcase ICE_SW_LKUP_ETHERTYPE_MAC:\n+\tcase ICE_SW_LKUP_PROMISC:\n+\tcase ICE_SW_LKUP_DFLT:\n+\t\tice_debug(hw, ICE_DBG_SW,\n+\t\t\t  \"Remove filters for this lookup type hasn't been implemented yet\\n\");\n+\t\tbreak;\n+\tcase ICE_SW_LKUP_PROMISC_VLAN:\n+\tcase ICE_SW_LKUP_LAST:\n+\t\tice_debug(hw, ICE_DBG_SW, \"Unsupported lookup type\\n\");\n+\t\tbreak;\n+\t}\n+\n+\tLIST_FOR_EACH_ENTRY_SAFE(fm_entry, tmp, &remove_list_head,\n+\t\t\t\t ice_fltr_list_entry, list_entry) {\n+\t\tLIST_DEL(&fm_entry->list_entry);\n+\t\tice_free(hw, fm_entry);\n+\t}\n+}\n+\n+/**\n+ * ice_remove_vsi_fltr - Remove all filters for a VSI\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: VSI handle to remove filters from\n+ */\n+void ice_remove_vsi_fltr(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_remove_vsi_fltr\\n\");\n+\n+\tice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_MAC);\n+\tice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_MAC_VLAN);\n+\tice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_PROMISC);\n+\tice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_VLAN);\n+\tice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_DFLT);\n+\tice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_ETHERTYPE);\n+\tice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_ETHERTYPE_MAC);\n+\tice_remove_vsi_lkup_fltr(hw, vsi_handle, ICE_SW_LKUP_PROMISC_VLAN);\n+}\n+\n+\n+\n+\n+\n+/**\n+ * ice_replay_vsi_fltr - Replay filters for requested VSI\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: driver vsi handle\n+ * @recp_id: Recipe id for which rules need to be replayed\n+ * @list_head: list for which filters need to be replayed\n+ *\n+ * Replays the filter of recipe recp_id for a VSI represented via vsi_handle.\n+ * It is required to pass valid VSI handle.\n+ */\n+static enum ice_status\n+ice_replay_vsi_fltr(struct ice_hw *hw, u16 vsi_handle, u8 recp_id,\n+\t\t    struct LIST_HEAD_TYPE *list_head)\n+{\n+\tstruct ice_fltr_mgmt_list_entry *itr;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu16 hw_vsi_id;\n+\n+\tif (LIST_EMPTY(list_head))\n+\t\treturn status;\n+\thw_vsi_id = ice_get_hw_vsi_num(hw, vsi_handle);\n+\n+\tLIST_FOR_EACH_ENTRY(itr, list_head, ice_fltr_mgmt_list_entry,\n+\t\t\t    list_entry) {\n+\t\tstruct ice_fltr_list_entry f_entry;\n+\n+\t\tf_entry.fltr_info = itr->fltr_info;\n+\t\tif (itr->vsi_count < 2 && recp_id != ICE_SW_LKUP_VLAN &&\n+\t\t    itr->fltr_info.vsi_handle == vsi_handle) {\n+\t\t\t/* update the src in case it is vsi num */\n+\t\t\tif (f_entry.fltr_info.src_id == ICE_SRC_ID_VSI)\n+\t\t\t\tf_entry.fltr_info.src = hw_vsi_id;\n+\t\t\tstatus = ice_add_rule_internal(hw, recp_id, &f_entry);\n+\t\t\tif (status != ICE_SUCCESS)\n+\t\t\t\tgoto end;\n+\t\t\tcontinue;\n+\t\t}\n+\t\tif (!itr->vsi_list_info ||\n+\t\t    !ice_is_bit_set(itr->vsi_list_info->vsi_map, vsi_handle))\n+\t\t\tcontinue;\n+\t\t/* Clearing it so that the logic can add it back */\n+\t\tice_clear_bit(vsi_handle, itr->vsi_list_info->vsi_map);\n+\t\tf_entry.fltr_info.vsi_handle = vsi_handle;\n+\t\tf_entry.fltr_info.fltr_act = ICE_FWD_TO_VSI;\n+\t\t/* update the src in case it is vsi num */\n+\t\tif (f_entry.fltr_info.src_id == ICE_SRC_ID_VSI)\n+\t\t\tf_entry.fltr_info.src = hw_vsi_id;\n+\t\tif (recp_id == ICE_SW_LKUP_VLAN)\n+\t\t\tstatus = ice_add_vlan_internal(hw, &f_entry);\n+\t\telse\n+\t\t\tstatus = ice_add_rule_internal(hw, recp_id, &f_entry);\n+\t\tif (status != ICE_SUCCESS)\n+\t\t\tgoto end;\n+\t}\n+end:\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_replay_vsi_all_fltr - replay all filters stored in bookkeeping lists\n+ * @hw: pointer to the hardware structure\n+ * @vsi_handle: driver vsi handle\n+ *\n+ * Replays filters for requested VSI via vsi_handle.\n+ */\n+enum ice_status ice_replay_vsi_all_fltr(struct ice_hw *hw, u16 vsi_handle)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu8 i;\n+\n+\tfor (i = 0; i < ICE_MAX_NUM_RECIPES; i++) {\n+\t\t/* Update the default recipe lines and ones that were created */\n+\t\tif (i < ICE_SW_LKUP_LAST || sw->recp_list[i].recp_created) {\n+\t\t\tstruct LIST_HEAD_TYPE *head;\n+\n+\t\t\thead = &sw->recp_list[i].filt_replay_rules;\n+\t\t\tif (!sw->recp_list[i].adv_rule)\n+\t\t\t\tstatus = ice_replay_vsi_fltr(hw, vsi_handle, i,\n+\t\t\t\t\t\t\t     head);\n+\t\t\tif (status != ICE_SUCCESS)\n+\t\t\t\treturn status;\n+\t\t}\n+\t}\n+\treturn status;\n+}\n+\n+/**\n+ * ice_rm_all_sw_replay_rule_info - deletes filter replay rules\n+ * @hw: pointer to the hw struct\n+ *\n+ * Deletes the filter replay rules.\n+ */\n+void ice_rm_all_sw_replay_rule_info(struct ice_hw *hw)\n+{\n+\tstruct ice_switch_info *sw = hw->switch_info;\n+\tu8 i;\n+\n+\tif (!sw)\n+\t\treturn;\n+\n+\tfor (i = 0; i < ICE_SW_LKUP_LAST; i++) {\n+\t\tif (!LIST_EMPTY(&sw->recp_list[i].filt_replay_rules)) {\n+\t\t\tstruct LIST_HEAD_TYPE *l_head;\n+\n+\t\t\tl_head = &sw->recp_list[i].filt_replay_rules;\n+\t\t\tif (!sw->recp_list[i].adv_rule)\n+\t\t\t\tice_rem_sw_rule_info(hw, l_head);\n+\t\t}\n+\t}\n+}\ndiff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h\nnew file mode 100644\nindex 0000000..1c55c63\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_switch.h\n@@ -0,0 +1,320 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_SWITCH_H_\n+#define _ICE_SWITCH_H_\n+\n+#include \"ice_common.h\"\n+#include \"ice_protocol_type.h\"\n+\n+#define ICE_SW_CFG_MAX_BUF_LEN 2048\n+#define ICE_MAX_SW 256\n+#define ICE_DFLT_VSI_INVAL 0xff\n+\n+\n+\n+#define ICE_VSI_INVAL_ID 0xFFFF\n+\n+/* VSI context structure for add/get/update/free operations */\n+struct ice_vsi_ctx {\n+\tu16 vsi_num;\n+\tu16 vsis_allocd;\n+\tu16 vsis_unallocated;\n+\tu16 flags;\n+\tstruct ice_aqc_vsi_props info;\n+\tstruct ice_sched_vsi_info sched;\n+\tu8 alloc_from_pool;\n+\tu8 vf_num;\n+\tstruct ice_lock rss_locks;\n+\tstruct LIST_HEAD_TYPE rss_list_head;\n+};\n+\n+\n+/* Switch recipe ID enum values are specific to hardware */\n+enum ice_sw_lkup_type {\n+\tICE_SW_LKUP_ETHERTYPE = 0,\n+\tICE_SW_LKUP_MAC = 1,\n+\tICE_SW_LKUP_MAC_VLAN = 2,\n+\tICE_SW_LKUP_PROMISC = 3,\n+\tICE_SW_LKUP_VLAN = 4,\n+\tICE_SW_LKUP_DFLT = 5,\n+\tICE_SW_LKUP_ETHERTYPE_MAC = 8,\n+\tICE_SW_LKUP_PROMISC_VLAN = 9,\n+\tICE_SW_LKUP_LAST\n+};\n+\n+/* type of filter src id */\n+enum ice_src_id {\n+\tICE_SRC_ID_UNKNOWN = 0,\n+\tICE_SRC_ID_VSI,\n+\tICE_SRC_ID_QUEUE,\n+\tICE_SRC_ID_LPORT,\n+};\n+\n+struct ice_fltr_info {\n+\t/* Look up information: how to look up packet */\n+\tenum ice_sw_lkup_type lkup_type;\n+\t/* Forward action: filter action to do after lookup */\n+\tenum ice_sw_fwd_act_type fltr_act;\n+\t/* rule ID returned by firmware once filter rule is created */\n+\tu16 fltr_rule_id;\n+\tu16 flag;\n+#define ICE_FLTR_RX\t\tBIT(0)\n+#define ICE_FLTR_TX\t\tBIT(1)\n+#define ICE_FLTR_TX_RX\t\t(ICE_FLTR_RX | ICE_FLTR_TX)\n+\n+\t/* Source VSI for LOOKUP_TX or source port for LOOKUP_RX */\n+\tu16 src;\n+\tenum ice_src_id src_id;\n+\n+\tunion {\n+\t\tstruct {\n+\t\t\tu8 mac_addr[ETH_ALEN];\n+\t\t} mac;\n+\t\tstruct {\n+\t\t\tu8 mac_addr[ETH_ALEN];\n+\t\t\tu16 vlan_id;\n+\t\t} mac_vlan;\n+\t\tstruct {\n+\t\t\tu16 vlan_id;\n+\t\t} vlan;\n+\t\t/* Set lkup_type as ICE_SW_LKUP_ETHERTYPE\n+\t\t * if just using ethertype as filter. Set lkup_type as\n+\t\t * ICE_SW_LKUP_ETHERTYPE_MAC if MAC also needs to be\n+\t\t * passed in as filter.\n+\t\t */\n+\t\tstruct {\n+\t\t\tu16 ethertype;\n+\t\t\tu8 mac_addr[ETH_ALEN]; /* optional */\n+\t\t} ethertype_mac;\n+\t} l_data; /* Make sure to zero out the memory of l_data before using\n+\t\t   * it or only set the data associated with lookup match\n+\t\t   * rest everything should be zero\n+\t\t   */\n+\n+\t/* Depending on filter action */\n+\tunion {\n+\t\t/* queue id in case of ICE_FWD_TO_Q and starting\n+\t\t * queue id in case of ICE_FWD_TO_QGRP.\n+\t\t */\n+\t\tu16 q_id:11;\n+\t\tu16 hw_vsi_id:10;\n+\t\tu16 vsi_id:10;\n+\t\tu16 vsi_list_id:10;\n+\t} fwd_id;\n+\n+\t/* Sw VSI handle */\n+\tu16 vsi_handle;\n+\n+\t/* Set to num_queues if action is ICE_FWD_TO_QGRP. This field\n+\t * determines the range of queues the packet needs to be forwarded to.\n+\t * Note that qgrp_size must be set to a power of 2.\n+\t */\n+\tu8 qgrp_size;\n+\n+\t/* Rule creations populate these indicators basing on the switch type */\n+\tu8 lb_en;\t/* Indicate if packet can be looped back */\n+\tu8 lan_en;\t/* Indicate if packet can be forwarded to the uplink */\n+};\n+\n+struct ice_adv_lkup_elem {\n+\tenum ice_protocol_type type;\n+\tunion ice_prot_hdr h_u;\t/* Header values */\n+\tunion ice_prot_hdr m_u;\t/* Mask of header values to match */\n+};\n+\n+struct ice_sw_act_ctrl {\n+\t/* Source VSI for LOOKUP_TX or source port for LOOKUP_RX */\n+\tu16 src;\n+\tu16 flag;\n+#define ICE_FLTR_RX             BIT(0)\n+#define ICE_FLTR_TX             BIT(1)\n+#define ICE_FLTR_TX_RX (ICE_FLTR_RX | ICE_FLTR_TX)\n+\n+\tenum ice_sw_fwd_act_type fltr_act;\n+\t/* Depending on filter action */\n+\tunion {\n+\t\t/* This is a queue id in case of ICE_FWD_TO_Q and starting\n+\t\t * queue id in case of ICE_FWD_TO_QGRP.\n+\t\t */\n+\t\tu16 q_id:11;\n+\t\tu16 vsi_id:10;\n+\t\tu16 hw_vsi_id:10;\n+\t\tu16 vsi_list_id:10;\n+\t} fwd_id;\n+\t/* software VSI handle */\n+\tu16 vsi_handle;\n+\tu8 qgrp_size;\n+};\n+\n+struct ice_adv_rule_info {\n+\tenum ice_sw_tunnel_type tun_type;\n+\tstruct ice_sw_act_ctrl sw_act;\n+\tu32 priority;\n+};\n+\n+/* A collection of one or more four word recipe */\n+struct ice_sw_recipe {\n+\t/* For a chained recipe the root recipe is what should be used for\n+\t * programming rules\n+\t */\n+\tu8 root_rid;\n+\tu8 recp_created;\n+\n+\t/* Number of extraction words */\n+\tu8 n_ext_words;\n+\t/* Protocol ID and Offset pair (extraction word) to describe the\n+\t * recipe\n+\t */\n+\tstruct ice_fv_word ext_words[ICE_MAX_CHAIN_WORDS];\n+\n+\t/* if this recipe is a collection of other recipe */\n+\tu8 big_recp;\n+\n+\t/* if this recipe is part of another bigger recipe then chain index\n+\t * corresponding to this recipe\n+\t */\n+\tu8 chain_idx;\n+\n+\t/* if this recipe is a collection of other recipe then count of other\n+\t * recipes and recipe ids of those recipes\n+\t */\n+\tu8 n_grp_count;\n+\n+\t/* Bit map specifying the IDs associated with this group of recipe */\n+\tice_declare_bitmap(r_bitmap, ICE_MAX_NUM_RECIPES);\n+\n+\tenum ice_sw_tunnel_type tun_type;\n+\n+\t/* List of type ice_fltr_mgmt_list_entry or adv_rule */\n+\tu8 adv_rule;\n+\tstruct LIST_HEAD_TYPE filt_rules;\n+\tstruct LIST_HEAD_TYPE filt_replay_rules;\n+\n+\t/* Lock to protect filter rule structure */\n+\tstruct ice_lock filt_rule_lock;\n+\n+\t/* Profiles this recipe should be associated with */\n+\tstruct LIST_HEAD_TYPE fv_list;\n+\n+\t/* Profiles this recipe is associated with */\n+\tu8 num_profs, *prof_ids;\n+\n+\tstruct LIST_HEAD_TYPE rg_list;\n+\n+\t/* AQ buffer associated with this recipe */\n+\tstruct ice_aqc_recipe_data_elem *root_buf;\n+};\n+\n+/* Bookkeeping structure to hold bitmap of VSIs corresponding to VSI list id */\n+struct ice_vsi_list_map_info {\n+\tstruct LIST_ENTRY_TYPE list_entry;\n+\tice_declare_bitmap(vsi_map, ICE_MAX_VSI);\n+\tu16 vsi_list_id;\n+\t/* counter to track how many rules are reusing this VSI list */\n+\tu16 ref_cnt;\n+};\n+\n+struct ice_fltr_list_entry {\n+\tstruct LIST_ENTRY_TYPE list_entry;\n+\tenum ice_status status;\n+\tstruct ice_fltr_info fltr_info;\n+};\n+\n+/* This defines an entry in the list that maintains MAC or VLAN membership\n+ * to HW list mapping, since multiple VSIs can subscribe to the same MAC or\n+ * VLAN. As an optimization the VSI list should be created only when a\n+ * second VSI becomes a subscriber to the same MAC address. VSI lists are always\n+ * used for VLAN membership.\n+ */\n+struct ice_fltr_mgmt_list_entry {\n+\t/* back pointer to VSI list id to VSI list mapping */\n+\tstruct ice_vsi_list_map_info *vsi_list_info;\n+\tu16 vsi_count;\n+#define ICE_INVAL_LG_ACT_INDEX 0xffff\n+\tu16 lg_act_idx;\n+#define ICE_INVAL_SW_MARKER_ID 0xffff\n+\tu16 sw_marker_id;\n+\tstruct LIST_ENTRY_TYPE list_entry;\n+\tstruct ice_fltr_info fltr_info;\n+#define ICE_INVAL_COUNTER_ID 0xff\n+\tu8 counter_index;\n+};\n+\n+struct ice_adv_fltr_mgmt_list_entry {\n+\tstruct LIST_ENTRY_TYPE list_entry;\n+\n+\tstruct ice_adv_lkup_elem *lkups;\n+\tstruct ice_adv_rule_info rule_info;\n+\tu16 lkups_cnt;\n+};\n+\n+enum ice_promisc_flags {\n+\tICE_PROMISC_UCAST_RX = 0x1,\n+\tICE_PROMISC_UCAST_TX = 0x2,\n+\tICE_PROMISC_MCAST_RX = 0x4,\n+\tICE_PROMISC_MCAST_TX = 0x8,\n+\tICE_PROMISC_BCAST_RX = 0x10,\n+\tICE_PROMISC_BCAST_TX = 0x20,\n+\tICE_PROMISC_VLAN_RX = 0x40,\n+\tICE_PROMISC_VLAN_TX = 0x80,\n+};\n+\n+/* VSI related commands */\n+enum ice_status\n+ice_add_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,\n+\t    struct ice_sq_cd *cd);\n+enum ice_status\n+ice_free_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,\n+\t     bool keep_vsi_alloc, struct ice_sq_cd *cd);\n+enum ice_status\n+ice_update_vsi(struct ice_hw *hw, u16 vsi_handle, struct ice_vsi_ctx *vsi_ctx,\n+\t       struct ice_sq_cd *cd);\n+struct ice_vsi_ctx *ice_get_vsi_ctx(struct ice_hw *hw, u16 vsi_handle);\n+void ice_clear_all_vsi_ctx(struct ice_hw *hw);\n+/* Switch config */\n+enum ice_status ice_get_initial_sw_cfg(struct ice_hw *hw);\n+\n+enum ice_status\n+ice_alloc_vlan_res_counter(struct ice_hw *hw, u16 *counter_id);\n+enum ice_status\n+ice_free_vlan_res_counter(struct ice_hw *hw, u16 counter_id);\n+\n+/* Switch/bridge related commands */\n+enum ice_status ice_update_sw_rule_bridge_mode(struct ice_hw *hw);\n+enum ice_status\n+ice_add_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list);\n+enum ice_status\n+ice_add_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list);\n+enum ice_status ice_add_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst);\n+enum ice_status ice_remove_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst);\n+enum ice_status\n+ice_remove_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list);\n+enum ice_status\n+ice_remove_mac_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *v_list);\n+\n+void ice_remove_vsi_fltr(struct ice_hw *hw, u16 vsi_handle);\n+#if defined(SRIOV_SUPPORT) && !defined(NO_VF_PROMISC_SUPPORT)\n+enum ice_status\n+ice_add_to_vsi_fltr_list(struct ice_hw *hw, u16 vsi_handle,\n+\t\t\t struct LIST_HEAD_TYPE *lkup_list_head,\n+\t\t\t struct LIST_HEAD_TYPE *vsi_list_head);\n+#endif\n+\n+\n+enum ice_status\n+ice_cfg_dflt_vsi(struct ice_hw *hw, u16 vsi_handle, bool set, u8 direction);\n+\n+\n+\n+\n+\n+enum ice_status ice_init_def_sw_recp(struct ice_hw *hw);\n+u16 ice_get_hw_vsi_num(struct ice_hw *hw, u16 vsi_handle);\n+bool ice_is_vsi_valid(struct ice_hw *hw, u16 vsi_handle);\n+\n+enum ice_status ice_replay_vsi_all_fltr(struct ice_hw *hw, u16 vsi_handle);\n+void ice_rm_all_sw_replay_rule_info(struct ice_hw *hw);\n+\n+#endif /* _ICE_SWITCH_H_ */\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nnew file mode 100644\nindex 0000000..057bc85\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -0,0 +1,789 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _ICE_TYPE_H_\n+#define _ICE_TYPE_H_\n+\n+#define ETH_ALEN\t6\n+\n+#define ETH_HEADER_LEN\t14\n+\n+#define BIT(a) (1UL << (a))\n+\n+#define BITS_PER_BYTE\t8\n+\n+#define ICE_BYTES_PER_WORD\t2\n+#define ICE_BYTES_PER_DWORD\t4\n+#define ICE_MAX_TRAFFIC_CLASS\t8\n+\n+\n+#include \"ice_status.h\"\n+#include \"ice_hw_autogen.h\"\n+#include \"ice_devids.h\"\n+#include \"ice_osdep.h\"\n+#include \"ice_controlq.h\"\n+#include \"ice_lan_tx_rx.h\"\n+#include \"ice_flex_type.h\"\n+#include \"ice_protocol_type.h\"\n+\n+static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)\n+{\n+\treturn ice_is_bit_set(&bitmap, tc);\n+}\n+\n+#ifndef DIV_64BIT\n+#define DIV_64BIT(n, d) div64_long((n), (d))\n+#endif /* DIV_64BIT */\n+\n+static inline u64 round_up_64bit(u64 a, u32 b)\n+{\n+\treturn DIV_64BIT(((a) + (b) / 2), (b));\n+}\n+\n+\n+/* Driver always calls main vsi_handle first */\n+#define ICE_MAIN_VSI_HANDLE\t\t0\n+\n+/* Switch from ms to the 1usec global time (this is the GTIME resolution) */\n+#define ICE_MS_TO_GTIME(time)\t\t((time) * 1000)\n+\n+/* Data type manipulation macros. */\n+#define ICE_HI_DWORD(x)\t\t((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))\n+#define ICE_LO_DWORD(x)\t\t((u32)((x) & 0xFFFFFFFF))\n+#define ICE_HI_WORD(x)\t\t((u16)(((x) >> 16) & 0xFFFF))\n+\n+/* debug masks - set these bits in hw->debug_mask to control output */\n+#define ICE_DBG_INIT\t\tBIT_ULL(1)\n+#define ICE_DBG_RELEASE\t\tBIT_ULL(2)\n+\n+#define ICE_DBG_LINK\t\tBIT_ULL(4)\n+#define ICE_DBG_PHY\t\tBIT_ULL(5)\n+#define ICE_DBG_QCTX\t\tBIT_ULL(6)\n+#define ICE_DBG_NVM\t\tBIT_ULL(7)\n+#define ICE_DBG_LAN\t\tBIT_ULL(8)\n+#define ICE_DBG_FLOW\t\tBIT_ULL(9)\n+#define ICE_DBG_DCB\t\tBIT_ULL(10)\n+#define ICE_DBG_DIAG\t\tBIT_ULL(11)\n+#define ICE_DBG_FD\t\tBIT_ULL(12)\n+#define ICE_DBG_SW\t\tBIT_ULL(13)\n+#define ICE_DBG_SCHED\t\tBIT_ULL(14)\n+\n+#define ICE_DBG_PKG\t\tBIT_ULL(16)\n+#define ICE_DBG_RES\t\tBIT_ULL(17)\n+#define ICE_DBG_AQ_MSG\t\tBIT_ULL(24)\n+#define ICE_DBG_AQ_DESC\t\tBIT_ULL(25)\n+#define ICE_DBG_AQ_DESC_BUF\tBIT_ULL(26)\n+#define ICE_DBG_AQ_CMD\t\tBIT_ULL(27)\n+#define ICE_DBG_AQ\t\t(ICE_DBG_AQ_MSG\t\t| \\\n+\t\t\t\t ICE_DBG_AQ_DESC\t| \\\n+\t\t\t\t ICE_DBG_AQ_DESC_BUF\t| \\\n+\t\t\t\t ICE_DBG_AQ_CMD)\n+\n+#define ICE_DBG_USER\t\tBIT_ULL(31)\n+#define ICE_DBG_ALL\t\t0xFFFFFFFFFFFFFFFFULL\n+\n+\n+\n+\n+\n+\n+enum ice_aq_res_ids {\n+\tICE_NVM_RES_ID = 1,\n+\tICE_SPD_RES_ID,\n+\tICE_CHANGE_LOCK_RES_ID,\n+\tICE_GLOBAL_CFG_LOCK_RES_ID\n+};\n+\n+/* FW update timeout definitions are in milliseconds */\n+#define ICE_NVM_TIMEOUT\t\t\t180000\n+#define ICE_CHANGE_LOCK_TIMEOUT\t\t1000\n+#define ICE_GLOBAL_CFG_LOCK_TIMEOUT\t3000\n+\n+enum ice_aq_res_access_type {\n+\tICE_RES_READ = 1,\n+\tICE_RES_WRITE\n+};\n+\n+struct ice_driver_ver {\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\tu8 build_ver;\n+\tu8 subbuild_ver;\n+\tu8 driver_string[32];\n+};\n+\n+enum ice_fc_mode {\n+\tICE_FC_NONE = 0,\n+\tICE_FC_RX_PAUSE,\n+\tICE_FC_TX_PAUSE,\n+\tICE_FC_FULL,\n+\tICE_FC_PFC,\n+\tICE_FC_DFLT\n+};\n+\n+enum ice_fec_mode {\n+\tICE_FEC_NONE = 0,\n+\tICE_FEC_RS,\n+\tICE_FEC_BASER,\n+\tICE_FEC_AUTO\n+};\n+\n+enum ice_set_fc_aq_failures {\n+\tICE_SET_FC_AQ_FAIL_NONE = 0,\n+\tICE_SET_FC_AQ_FAIL_GET,\n+\tICE_SET_FC_AQ_FAIL_SET,\n+\tICE_SET_FC_AQ_FAIL_UPDATE\n+};\n+\n+/* These are structs for managing the hardware information and the operations */\n+/* MAC types */\n+enum ice_mac_type {\n+\tICE_MAC_UNKNOWN = 0,\n+\tICE_MAC_VF,\n+\tICE_MAC_GENERIC,\n+};\n+\n+/* Media Types */\n+enum ice_media_type {\n+\tICE_MEDIA_UNKNOWN = 0,\n+\tICE_MEDIA_FIBER,\n+\tICE_MEDIA_BASET,\n+\tICE_MEDIA_BACKPLANE,\n+\tICE_MEDIA_DA,\n+};\n+\n+/* Software VSI types. */\n+enum ice_vsi_type {\n+\tICE_VSI_PF = 0,\n+\tICE_VSI_VF = 1,\n+};\n+\n+struct ice_link_status {\n+\t/* Refer to ice_aq_phy_type for bits definition */\n+\tu64 phy_type_low;\n+\tu8 topo_media_conflict;\n+\tu16 max_frame_size;\n+\tu16 link_speed;\n+\tu16 req_speeds;\n+\tu8 lse_ena;\t/* Link Status Event notification */\n+\tu8 link_info;\n+\tu8 an_info;\n+\tu8 ext_info;\n+\tu8 fec_info;\n+\tu8 pacing;\n+\t/* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of\n+\t * ice_aqc_get_phy_caps structure\n+\t */\n+\tu8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];\n+};\n+\n+/* Different data queue types: These are mainly for SW consumption. */\n+enum ice_q {\n+\tICE_DATA_Q_DOORBELL,\n+\tICE_DATA_Q_CMPL,\n+\tICE_DATA_Q_QUANTA,\n+\tICE_DATA_Q_RX,\n+\tICE_DATA_Q_TX,\n+};\n+\n+/* Different reset sources for which a disable queue AQ call has to be made in\n+ * order to clean the TX scheduler as a part of the reset\n+ */\n+enum ice_disq_rst_src {\n+\tICE_NO_RESET = 0,\n+\tICE_VM_RESET,\n+\tICE_VF_RESET,\n+};\n+\n+/* PHY info such as phy_type, etc... */\n+struct ice_phy_info {\n+\tstruct ice_link_status link_info;\n+\tstruct ice_link_status link_info_old;\n+\tu64 phy_type_low;\n+\tenum ice_media_type media_type;\n+\tu8 get_link_info;\n+};\n+\n+#define ICE_MAX_NUM_MIRROR_RULES\t64\n+\n+/* Common HW capabilities for SW use */\n+struct ice_hw_common_caps {\n+\t/* Write CSR protection */\n+\tu64 wr_csr_prot;\n+\tu32 switching_mode;\n+\t/* switching mode supported - EVB switching (including cloud) */\n+#define ICE_NVM_IMAGE_TYPE_EVB\t\t0x0\n+\n+\t/* Manageablity mode & supported protocols over MCTP */\n+\tu32 mgmt_mode;\n+#define ICE_MGMT_MODE_PASS_THRU_MODE_M\t\t0xF\n+#define ICE_MGMT_MODE_CTL_INTERFACE_M\t\t0xF0\n+#define ICE_MGMT_MODE_REDIR_SB_INTERFACE_M\t0xF00\n+\n+\tu32 mgmt_protocols_mctp;\n+#define ICE_MGMT_MODE_PROTO_RSVD\tBIT(0)\n+#define ICE_MGMT_MODE_PROTO_PLDM\tBIT(1)\n+#define ICE_MGMT_MODE_PROTO_OEM\t\tBIT(2)\n+#define ICE_MGMT_MODE_PROTO_NC_SI\tBIT(3)\n+\n+\tu32 os2bmc;\n+\tu32 valid_functions;\n+\n+\t/* RSS related capabilities */\n+\tu32 rss_table_size;\t\t/* 512 for PFs and 64 for VFs */\n+\tu32 rss_table_entry_width;\t/* RSS Entry width in bits */\n+\n+\t/* TX/RX queues */\n+\tu32 num_rxq;\t\t\t/* Number/Total RX queues */\n+\tu32 rxq_first_id;\t\t/* First queue ID for RX queues */\n+\tu32 num_txq;\t\t\t/* Number/Total TX queues */\n+\tu32 txq_first_id;\t\t/* First queue ID for TX queues */\n+\n+\t/* MSI-X vectors */\n+\tu32 num_msix_vectors;\n+\tu32 msix_vector_first_id;\n+\n+\t/* Max MTU for function or device */\n+\tu32 max_mtu;\n+\n+\t/* WOL related */\n+\tu32 num_wol_proxy_fltr;\n+\tu32 wol_proxy_vsi_seid;\n+\n+\t/* LED/SDP pin count */\n+\tu32 led_pin_num;\n+\tu32 sdp_pin_num;\n+\n+\t/* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */\n+#define ICE_MAX_SUPPORTED_GPIO_LED\t12\n+#define ICE_MAX_SUPPORTED_GPIO_SDP\t8\n+\tu8 led[ICE_MAX_SUPPORTED_GPIO_LED];\n+\tu8 sdp[ICE_MAX_SUPPORTED_GPIO_SDP];\n+\n+\t/* Virtualization support */\n+\tu8 sr_iov_1_1;\t\t\t/* SR-IOV enabled */\n+\n+\t/* EVB capabilities */\n+\tu8 evb_802_1_qbg;\t\t/* Edge Virtual Bridging */\n+\tu8 evb_802_1_qbh;\t\t/* Bridge Port Extension */\n+\n+\tu8 iscsi;\n+\tu8 mgmt_cem;\n+\n+\t/* WoL and APM support */\n+#define ICE_WOL_SUPPORT_M\t\tBIT(0)\n+#define ICE_ACPI_PROG_MTHD_M\t\tBIT(1)\n+#define ICE_PROXY_SUPPORT_M\t\tBIT(2)\n+\tu8 apm_wol_support;\n+\tu8 acpi_prog_mthd;\n+\tu8 proxy_support;\n+};\n+\n+\n+/* Function specific capabilities */\n+struct ice_hw_func_caps {\n+\tstruct ice_hw_common_caps common_cap;\n+\tu32 num_allocd_vfs;\t\t/* Number of allocated VFs */\n+\tu32 vf_base_id;\t\t\t/* Logical ID of the first VF */\n+\tu32 guar_num_vsi;\n+};\n+\n+/* Device wide capabilities */\n+struct ice_hw_dev_caps {\n+\tstruct ice_hw_common_caps common_cap;\n+\tu32 num_vfs_exposed;\t\t/* Total number of VFs exposed */\n+\tu32 num_vsi_allocd_to_host;\t/* Excluding EMP VSI */\n+};\n+\n+\n+/* Information about MAC such as address, etc... */\n+struct ice_mac_info {\n+\tu8 lan_addr[ETH_ALEN];\n+\tu8 perm_addr[ETH_ALEN];\n+\tu8 port_addr[ETH_ALEN];\n+\tu8 wol_addr[ETH_ALEN];\n+};\n+\n+/* PCI bus types */\n+enum ice_bus_type {\n+\tice_bus_unknown = 0,\n+\tice_bus_pci_express,\n+\tice_bus_embedded, /* Is device Embedded versus card */\n+\tice_bus_reserved\n+};\n+\n+/* PCI bus speeds */\n+enum ice_pcie_bus_speed {\n+\tice_pcie_speed_unknown\t= 0xff,\n+\tice_pcie_speed_2_5GT\t= 0x14,\n+\tice_pcie_speed_5_0GT\t= 0x15,\n+\tice_pcie_speed_8_0GT\t= 0x16,\n+\tice_pcie_speed_16_0GT\t= 0x17\n+};\n+\n+/* PCI bus widths */\n+enum ice_pcie_link_width {\n+\tice_pcie_lnk_width_resrv\t= 0x00,\n+\tice_pcie_lnk_x1\t\t\t= 0x01,\n+\tice_pcie_lnk_x2\t\t\t= 0x02,\n+\tice_pcie_lnk_x4\t\t\t= 0x04,\n+\tice_pcie_lnk_x8\t\t\t= 0x08,\n+\tice_pcie_lnk_x12\t\t= 0x0C,\n+\tice_pcie_lnk_x16\t\t= 0x10,\n+\tice_pcie_lnk_x32\t\t= 0x20,\n+\tice_pcie_lnk_width_unknown\t= 0xff,\n+};\n+\n+/* Reset types used to determine which kind of reset was requested. These\n+ * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.\n+ * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register\n+ * because its reset source is different than the other types listed.\n+ */\n+enum ice_reset_req {\n+\tICE_RESET_POR\t= 0,\n+\tICE_RESET_INVAL\t= 0,\n+\tICE_RESET_CORER\t= 1,\n+\tICE_RESET_GLOBR\t= 2,\n+\tICE_RESET_EMPR\t= 3,\n+\tICE_RESET_PFR\t= 4,\n+};\n+\n+/* Bus parameters */\n+struct ice_bus_info {\n+\tenum ice_pcie_bus_speed speed;\n+\tenum ice_pcie_link_width width;\n+\tenum ice_bus_type type;\n+\tu16 domain_num;\n+\tu16 device;\n+\tu8 func;\n+\tu8 bus_num;\n+};\n+\n+/* Flow control (FC) parameters */\n+struct ice_fc_info {\n+\tenum ice_fc_mode current_mode;\t/* FC mode in effect */\n+\tenum ice_fc_mode req_mode;\t/* FC mode requested by caller */\n+};\n+\n+/* NVM Information */\n+struct ice_nvm_info {\n+\tu32 eetrack;\t\t\t/* NVM data version */\n+\tu32 oem_ver;\t\t\t/* OEM version info */\n+\tu16 sr_words;\t\t\t/* Shadow RAM size in words */\n+\tu16 ver;\t\t\t/* NVM package version */\n+\tu8 blank_nvm_mode;\t\t/* is NVM empty (no FW present)*/\n+};\n+\n+/* Max number of port to queue branches w.r.t topology */\n+#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS\n+/* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects\n+ * to driver defined policy for default aggregator\n+ */\n+#define ICE_INVAL_TEID 0xFFFFFFFF\n+#define ICE_DFLT_AGG_ID 0\n+\n+struct ice_sched_node {\n+\tstruct ice_sched_node *parent;\n+\tstruct ice_sched_node *sibling; /* next sibling in the same layer */\n+\tstruct ice_sched_node **children;\n+\tstruct ice_aqc_txsched_elem_data info;\n+\tu32 agg_id;\t\t\t/* aggregator group id */\n+\tu16 vsi_handle;\n+\tu8 in_use;\t\t\t/* suspended or in use */\n+\tu8 tx_sched_layer;\t\t/* Logical Layer (1-9) */\n+\tu8 num_children;\n+\tu8 tc_num;\n+\tu8 owner;\n+#define ICE_SCHED_NODE_OWNER_LAN\t0\n+#define ICE_SCHED_NODE_OWNER_AE\t\t1\n+#define ICE_SCHED_NODE_OWNER_RDMA\t2\n+};\n+\n+/* Access Macros for Tx Sched Elements data */\n+#define ICE_TXSCHED_GET_NODE_TEID(x) LE32_TO_CPU((x)->info.node_teid)\n+#define ICE_TXSCHED_GET_PARENT_TEID(x) LE32_TO_CPU((x)->info.parent_teid)\n+#define ICE_TXSCHED_GET_CIR_RL_ID(x)\t\\\n+\tLE16_TO_CPU((x)->info.cir_bw.bw_profile_idx)\n+#define ICE_TXSCHED_GET_EIR_RL_ID(x)\t\\\n+\tLE16_TO_CPU((x)->info.eir_bw.bw_profile_idx)\n+#define ICE_TXSCHED_GET_SRL_ID(x) LE16_TO_CPU((x)->info.srl_id)\n+#define ICE_TXSCHED_GET_CIR_BWALLOC(x)\t\\\n+\tLE16_TO_CPU((x)->info.cir_bw.bw_alloc)\n+#define ICE_TXSCHED_GET_EIR_BWALLOC(x)\t\\\n+\tLE16_TO_CPU((x)->info.eir_bw.bw_alloc)\n+\n+\n+/* The aggregator type determines if identifier is for a VSI group,\n+ * aggregator group, aggregator of queues, or queue group.\n+ */\n+enum ice_agg_type {\n+\tICE_AGG_TYPE_UNKNOWN = 0,\n+\tICE_AGG_TYPE_TC,\n+\tICE_AGG_TYPE_AGG, /* aggregator */\n+\tICE_AGG_TYPE_VSI,\n+\tICE_AGG_TYPE_QG,\n+\tICE_AGG_TYPE_Q\n+};\n+\n+\n+#define ICE_SCHED_MIN_BW\t\t500\t\t/* in Kbps */\n+#define ICE_SCHED_MAX_BW\t\t100000000\t/* in Kbps */\n+#define ICE_SCHED_DFLT_BW\t\t0xFFFFFFFF\t/* unlimited */\n+#define ICE_SCHED_NO_PRIORITY\t\t0\n+#define ICE_SCHED_NO_BW_WT\t\t0\n+#define ICE_SCHED_DFLT_RL_PROF_ID\t0\n+#define ICE_SCHED_DFLT_BW_WT\t\t1\n+#define ICE_SCHED_INVAL_PROF_ID\t\t0xFFFF\n+#define ICE_SCHED_DFLT_BURST_SIZE\t(15 * 1024)\t/* in bytes (15k) */\n+\n+\n+/* The following tree example shows the naming conventions followed under\n+ * ice_port_info struct for default scheduler tree topology.\n+ *\n+ *                 A tree on a port\n+ *                       *                ---> root node\n+ *        (TC0)/  /  /  / \\  \\  \\  \\(TC7) ---> num_branches (range:1- 8)\n+ *            *  *  *  *   *  *  *  *     |\n+ *           /                            |\n+ *          *                             |\n+ *         /                              |-> num_elements (range:1 - 9)\n+ *        *                               |   implies num_of_layers\n+ *       /                                |\n+ *   (a)*                                 |\n+ *\n+ *  (a) is the last_node_teid(not of type Leaf). A leaf node is created under\n+ *  (a) as child node where queues get added, add Tx/Rx queue admin commands;\n+ *  need teid of (a) to add queues.\n+ *\n+ *  This tree\n+ *       -> has 8 branches (one for each TC)\n+ *       -> First branch (TC0) has 4 elements\n+ *       -> has 4 layers\n+ *       -> (a) is the topmost layer node created by firmware on branch 0\n+ *\n+ *  Note: Above asterisk tree covers only basic terminology and scenario.\n+ *  Refer to the documentation for more info.\n+ */\n+\n+ /* Data structure for saving bw information */\n+enum ice_bw_type {\n+\tICE_BW_TYPE_PRIO,\n+\tICE_BW_TYPE_CIR,\n+\tICE_BW_TYPE_CIR_WT,\n+\tICE_BW_TYPE_EIR,\n+\tICE_BW_TYPE_EIR_WT,\n+\tICE_BW_TYPE_SHARED,\n+\tICE_BW_TYPE_CNT\t\t/* This must be last */\n+};\n+\n+struct ice_bw {\n+\tu32 bw;\n+\tu16 bw_alloc;\n+};\n+\n+struct ice_bw_type_info {\n+\tice_declare_bitmap(bw_t_bitmap, ICE_BW_TYPE_CNT);\n+\tu8 generic;\n+\tstruct ice_bw cir_bw;\n+\tstruct ice_bw eir_bw;\n+\tu32 shared_bw;\n+};\n+\n+/* vsi type list entry to locate corresponding vsi/ag nodes */\n+struct ice_sched_vsi_info {\n+\tstruct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];\n+\tstruct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];\n+\tu16 max_lanq[ICE_MAX_TRAFFIC_CLASS];\n+\t/* bw_t_info saves VSI bw information */\n+\tstruct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];\n+};\n+\n+\n+struct ice_port_info {\n+\tstruct ice_sched_node *root;\t/* Root Node per Port */\n+\tstruct ice_hw *hw;\t\t/* back pointer to hw instance */\n+\tu32 last_node_teid;\t\t/* scheduler last node info */\n+\tu16 sw_id;\t\t\t/* Initial switch ID belongs to port */\n+\tu16 pf_vf_num;\n+\tu8 port_state;\n+#define ICE_SCHED_PORT_STATE_INIT\t0x0\n+#define ICE_SCHED_PORT_STATE_READY\t0x1\n+\tu16 dflt_tx_vsi_rule_id;\n+\tu16 dflt_tx_vsi_num;\n+\tu16 dflt_rx_vsi_rule_id;\n+\tu16 dflt_rx_vsi_num;\n+\tstruct ice_fc_info fc;\n+\tstruct ice_mac_info mac;\n+\tstruct ice_phy_info phy;\n+\tstruct ice_lock sched_lock;\t/* protect access to TXSched tree */\n+\tu8 lport;\n+#define ICE_LPORT_MASK\t\t0xff\n+\tu8 is_vf;\n+};\n+\n+struct ice_switch_info {\n+\tstruct LIST_HEAD_TYPE vsi_list_map_head;\n+\tstruct ice_sw_recipe *recp_list;\n+};\n+\n+/* FW logging configuration */\n+struct ice_fw_log_evnt {\n+\tu8 cfg : 4;\t/* New event enables to configure */\n+\tu8 cur : 4;\t/* Current/active event enables */\n+};\n+\n+struct ice_fw_log_cfg {\n+\tu8 cq_en : 1;    /* FW logging is enabled via the control queue */\n+\tu8 uart_en : 1;  /* FW logging is enabled via UART for all PFs */\n+\tu8 actv_evnts;   /* Cumulation of currently enabled log events */\n+\n+#define ICE_FW_LOG_EVNT_INFO\t(ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)\n+#define ICE_FW_LOG_EVNT_INIT\t(ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)\n+#define ICE_FW_LOG_EVNT_FLOW\t(ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)\n+#define ICE_FW_LOG_EVNT_ERR\t(ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)\n+\tstruct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];\n+};\n+\n+/* Port hardware description */\n+struct ice_hw {\n+\tu8 *hw_addr;\n+\tvoid *back;\n+\tstruct ice_aqc_layer_props *layer_info;\n+\tstruct ice_port_info *port_info;\n+\tu64 debug_mask;\t\t/* BITMAP for debug mask */\n+\tenum ice_mac_type mac_type;\n+\n+\t/* pci info */\n+\tu16 device_id;\n+\tu16 vendor_id;\n+\tu16 subsystem_device_id;\n+\tu16 subsystem_vendor_id;\n+\tu8 revision_id;\n+\n+\tu8 pf_id;\t\t/* device profile info */\n+\n+\t/* TX Scheduler values */\n+\tu16 num_tx_sched_layers;\n+\tu16 num_tx_sched_phys_layers;\n+\tu8 flattened_layers;\n+\tu8 max_cgds;\n+\tu8 sw_entry_point_layer;\n+\tu16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];\n+\tstruct LIST_HEAD_TYPE agg_list;\t/* lists all aggregator */\n+\n+\tstruct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];\n+\tu8 evb_veb;\t\t/* true for VEB, false for VEPA */\n+\tu8 reset_ongoing;\t/* true if hw is in reset, false otherwise */\n+\tstruct ice_bus_info bus;\n+\tstruct ice_nvm_info nvm;\n+\tstruct ice_hw_dev_caps dev_caps;\t/* device capabilities */\n+\tstruct ice_hw_func_caps func_caps;\t/* function capabilities */\n+\n+\tstruct ice_switch_info *switch_info;\t/* switch filter lists */\n+\n+\t/* Control Queue info */\n+\tstruct ice_ctl_q_info adminq;\n+\tstruct ice_ctl_q_info mailboxq;\n+\n+\tu8 api_branch;\t\t/* API branch version */\n+\tu8 api_maj_ver;\t\t/* API major version */\n+\tu8 api_min_ver;\t\t/* API minor version */\n+\tu8 api_patch;\t\t/* API patch version */\n+\tu8 fw_branch;\t\t/* firmware branch version */\n+\tu8 fw_maj_ver;\t\t/* firmware major version */\n+\tu8 fw_min_ver;\t\t/* firmware minor version */\n+\tu8 fw_patch;\t\t/* firmware patch version */\n+\tu32 fw_build;\t\t/* firmware build number */\n+\n+\tstruct ice_fw_log_cfg fw_log;\n+\n+/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL\n+ * register. Used for determining the itr/intrl granularity during\n+ * initialization.\n+ */\n+#define ICE_MAX_AGG_BW_200G\t0x0\n+#define ICE_MAX_AGG_BW_100G\t0X1\n+#define ICE_MAX_AGG_BW_50G\t0x2\n+#define ICE_MAX_AGG_BW_25G\t0x3\n+\t/* ITR granularity for different speeds */\n+#define ICE_ITR_GRAN_ABOVE_25\t2\n+#define ICE_ITR_GRAN_MAX_25\t4\n+\t/* ITR granularity in 1 us */\n+\tu8 itr_gran;\n+\t/* INTRL granularity for different speeds */\n+#define ICE_INTRL_GRAN_ABOVE_25\t4\n+#define ICE_INTRL_GRAN_MAX_25\t8\n+\t/* INTRL granularity in 1 us */\n+\tu8 intrl_gran;\n+\n+\tu8 ucast_shared;\t/* true if VSIs can share unicast addr */\n+\n+\n+};\n+\n+/* Statistics collected by each port, VSI, VEB, and S-channel */\n+struct ice_eth_stats {\n+\tu64 rx_bytes;\t\t\t/* gorc */\n+\tu64 rx_unicast;\t\t\t/* uprc */\n+\tu64 rx_multicast;\t\t/* mprc */\n+\tu64 rx_broadcast;\t\t/* bprc */\n+\tu64 rx_discards;\t\t/* rdpc */\n+\tu64 rx_unknown_protocol;\t/* rupp */\n+\tu64 tx_bytes;\t\t\t/* gotc */\n+\tu64 tx_unicast;\t\t\t/* uptc */\n+\tu64 tx_multicast;\t\t/* mptc */\n+\tu64 tx_broadcast;\t\t/* bptc */\n+\tu64 tx_discards;\t\t/* tdpc */\n+\tu64 tx_errors;\t\t\t/* tepc */\n+};\n+\n+#define ICE_MAX_UP\t8\n+\n+/* Statistics collected per VEB per User Priority (UP) for up to 8 UPs */\n+struct ice_veb_up_stats {\n+\tu64 up_rx_pkts[ICE_MAX_UP];\n+\tu64 up_rx_bytes[ICE_MAX_UP];\n+\tu64 up_tx_pkts[ICE_MAX_UP];\n+\tu64 up_tx_bytes[ICE_MAX_UP];\n+};\n+\n+/* Statistics collected by the MAC */\n+struct ice_hw_port_stats {\n+\t/* eth stats collected by the port */\n+\tstruct ice_eth_stats eth;\n+\t/* additional port specific stats */\n+\tu64 tx_dropped_link_down;\t/* tdold */\n+\tu64 crc_errors;\t\t\t/* crcerrs */\n+\tu64 illegal_bytes;\t\t/* illerrc */\n+\tu64 error_bytes;\t\t/* errbc */\n+\tu64 mac_local_faults;\t\t/* mlfc */\n+\tu64 mac_remote_faults;\t\t/* mrfc */\n+\tu64 rx_len_errors;\t\t/* rlec */\n+\tu64 link_xon_rx;\t\t/* lxonrxc */\n+\tu64 link_xoff_rx;\t\t/* lxoffrxc */\n+\tu64 link_xon_tx;\t\t/* lxontxc */\n+\tu64 link_xoff_tx;\t\t/* lxofftxc */\n+\tu64 rx_size_64;\t\t\t/* prc64 */\n+\tu64 rx_size_127;\t\t/* prc127 */\n+\tu64 rx_size_255;\t\t/* prc255 */\n+\tu64 rx_size_511;\t\t/* prc511 */\n+\tu64 rx_size_1023;\t\t/* prc1023 */\n+\tu64 rx_size_1522;\t\t/* prc1522 */\n+\tu64 rx_size_big;\t\t/* prc9522 */\n+\tu64 rx_undersize;\t\t/* ruc */\n+\tu64 rx_fragments;\t\t/* rfc */\n+\tu64 rx_oversize;\t\t/* roc */\n+\tu64 rx_jabber;\t\t\t/* rjc */\n+\tu64 tx_size_64;\t\t\t/* ptc64 */\n+\tu64 tx_size_127;\t\t/* ptc127 */\n+\tu64 tx_size_255;\t\t/* ptc255 */\n+\tu64 tx_size_511;\t\t/* ptc511 */\n+\tu64 tx_size_1023;\t\t/* ptc1023 */\n+\tu64 tx_size_1522;\t\t/* ptc1522 */\n+\tu64 tx_size_big;\t\t/* ptc9522 */\n+\tu64 mac_short_pkt_dropped;\t/* mspdc */\n+\t/* EEE LPI */\n+\tu32 tx_lpi_status;\n+\tu32 rx_lpi_status;\n+\tu64 tx_lpi_count;\t\t/* etlpic */\n+\tu64 rx_lpi_count;\t\t/* erlpic */\n+};\n+\n+enum ice_sw_fwd_act_type {\n+\tICE_FWD_TO_VSI = 0,\n+\tICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */\n+\tICE_FWD_TO_Q,\n+\tICE_FWD_TO_QGRP,\n+\tICE_DROP_PACKET,\n+\tICE_INVAL_ACT\n+};\n+\n+/* Checksum and Shadow RAM pointers */\n+#define ICE_SR_NVM_CTRL_WORD\t\t\t0x00\n+#define ICE_SR_PHY_ANALOG_PTR\t\t\t0x04\n+#define ICE_SR_OPTION_ROM_PTR\t\t\t0x05\n+#define ICE_SR_RO_PCIR_REGS_AUTO_LOAD_PTR\t0x06\n+#define ICE_SR_AUTO_GENERATED_POINTERS_PTR\t0x07\n+#define ICE_SR_PCIR_REGS_AUTO_LOAD_PTR\t\t0x08\n+#define ICE_SR_EMP_GLOBAL_MODULE_PTR\t\t0x09\n+#define ICE_SR_EMP_IMAGE_PTR\t\t\t0x0B\n+#define ICE_SR_PE_IMAGE_PTR\t\t\t0x0C\n+#define ICE_SR_CSR_PROTECTED_LIST_PTR\t\t0x0D\n+#define ICE_SR_MNG_CFG_PTR\t\t\t0x0E\n+#define ICE_SR_EMP_MODULE_PTR\t\t\t0x0F\n+#define ICE_SR_PBA_FLAGS\t\t\t0x15\n+#define ICE_SR_PBA_BLOCK_PTR\t\t\t0x16\n+#define ICE_SR_BOOT_CFG_PTR\t\t\t0x17\n+#define ICE_SR_NVM_WOL_CFG\t\t\t0x19\n+#define ICE_NVM_OEM_VER_OFF\t\t\t0x83\n+#define ICE_SR_NVM_DEV_STARTER_VER\t\t0x18\n+#define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR\t0x27\n+#define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR\t0x28\n+#define ICE_SR_NVM_MAP_VER\t\t\t0x29\n+#define ICE_SR_NVM_IMAGE_VER\t\t\t0x2A\n+#define ICE_SR_NVM_STRUCTURE_VER\t\t0x2B\n+#define ICE_SR_NVM_EETRACK_LO\t\t\t0x2D\n+#define ICE_SR_NVM_EETRACK_HI\t\t\t0x2E\n+#define ICE_NVM_VER_LO_SHIFT\t\t\t0\n+#define ICE_NVM_VER_LO_MASK\t\t\t(0xff << ICE_NVM_VER_LO_SHIFT)\n+#define ICE_NVM_VER_HI_SHIFT\t\t\t12\n+#define ICE_NVM_VER_HI_MASK\t\t\t(0xf << ICE_NVM_VER_HI_SHIFT)\n+#define ICE_OEM_EETRACK_ID\t\t\t0xffffffff\n+#define ICE_OEM_VER_PATCH_SHIFT\t\t\t0\n+#define ICE_OEM_VER_PATCH_MASK\t\t(0xff << ICE_OEM_VER_PATCH_SHIFT)\n+#define ICE_OEM_VER_BUILD_SHIFT\t\t\t8\n+#define ICE_OEM_VER_BUILD_MASK\t\t(0xffff << ICE_OEM_VER_BUILD_SHIFT)\n+#define ICE_OEM_VER_SHIFT\t\t\t24\n+#define ICE_OEM_VER_MASK\t\t\t(0xff << ICE_OEM_VER_SHIFT)\n+#define ICE_SR_VPD_PTR\t\t\t\t0x2F\n+#define ICE_SR_PXE_SETUP_PTR\t\t\t0x30\n+#define ICE_SR_PXE_CFG_CUST_OPTIONS_PTR\t\t0x31\n+#define ICE_SR_NVM_ORIGINAL_EETRACK_LO\t\t0x34\n+#define ICE_SR_NVM_ORIGINAL_EETRACK_HI\t\t0x35\n+#define ICE_SR_VLAN_CFG_PTR\t\t\t0x37\n+#define ICE_SR_POR_REGS_AUTO_LOAD_PTR\t\t0x38\n+#define ICE_SR_EMPR_REGS_AUTO_LOAD_PTR\t\t0x3A\n+#define ICE_SR_GLOBR_REGS_AUTO_LOAD_PTR\t\t0x3B\n+#define ICE_SR_CORER_REGS_AUTO_LOAD_PTR\t\t0x3C\n+#define ICE_SR_PHY_CFG_SCRIPT_PTR\t\t0x3D\n+#define ICE_SR_PCIE_ALT_AUTO_LOAD_PTR\t\t0x3E\n+#define ICE_SR_SW_CHECKSUM_WORD\t\t\t0x3F\n+#define ICE_SR_PFA_PTR\t\t\t\t0x40\n+#define ICE_SR_1ST_SCRATCH_PAD_PTR\t\t0x41\n+#define ICE_SR_1ST_NVM_BANK_PTR\t\t\t0x42\n+#define ICE_SR_NVM_BANK_SIZE\t\t\t0x43\n+#define ICE_SR_1ND_OROM_BANK_PTR\t\t0x44\n+#define ICE_SR_OROM_BANK_SIZE\t\t\t0x45\n+#define ICE_SR_EMP_SR_SETTINGS_PTR\t\t0x48\n+#define ICE_SR_CONFIGURATION_METADATA_PTR\t0x4D\n+#define ICE_SR_IMMEDIATE_VALUES_PTR\t\t0x4E\n+\n+/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n+#define ICE_SR_VPD_SIZE_WORDS\t\t512\n+#define ICE_SR_PCIE_ALT_SIZE_WORDS\t512\n+#define ICE_SR_CTRL_WORD_1_S\t\t0x06\n+#define ICE_SR_CTRL_WORD_1_M\t\t(0x03 << ICE_SR_CTRL_WORD_1_S)\n+\n+/* Shadow RAM related */\n+#define ICE_SR_SECTOR_SIZE_IN_WORDS\t0x800\n+#define ICE_SR_BUF_ALIGNMENT\t\t4096\n+#define ICE_SR_WORDS_IN_1KB\t\t512\n+/* Checksum should be calculated such that after adding all the words,\n+ * including the checksum word itself, the sum should be 0xBABA.\n+ */\n+#define ICE_SR_SW_CHECKSUM_BASE\t\t0xBABA\n+\n+#define ICE_PBA_FLAG_DFLT\t\t0xFAFA\n+/* Hash redirection LUT for VSI - maximum array size */\n+#define ICE_VSIQF_HLUT_ARRAY_SIZE\t((VSIQF_HLUT_MAX_INDEX + 1) * 4)\n+\n+/*\n+ * Defines for values in the VF_PE_DB_SIZE bits in the GLPCI_LBARCTRL register.\n+ * This is needed to determine the BAR0 space for the VFs\n+ */\n+#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_0KB 0x0\n+#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_8KB 0x1\n+#define GLPCI_LBARCTRL_VF_PE_DB_SIZE_64KB 0x2\n+\n+#endif /* _ICE_TYPE_H_ */\ndiff --git a/drivers/net/ice/base/virtchnl.h b/drivers/net/ice/base/virtchnl.h\nnew file mode 100644\nindex 0000000..90192f5\n--- /dev/null\n+++ b/drivers/net/ice/base/virtchnl.h\n@@ -0,0 +1,787 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#ifndef _VIRTCHNL_H_\n+#define _VIRTCHNL_H_\n+\n+/* Description:\n+ * This header file describes the VF-PF communication protocol used\n+ * by the drivers for all devices starting from our 40G product line\n+ *\n+ * Admin queue buffer usage:\n+ * desc->opcode is always aqc_opc_send_msg_to_pf\n+ * flags, retval, datalen, and data addr are all used normally.\n+ * The Firmware copies the cookie fields when sending messages between the\n+ * PF and VF, but uses all other fields internally. Due to this limitation,\n+ * we must send all messages as \"indirect\", i.e. using an external buffer.\n+ *\n+ * All the VSI indexes are relative to the VF. Each VF can have maximum of\n+ * three VSIs. All the queue indexes are relative to the VSI.  Each VF can\n+ * have a maximum of sixteen queues for all of its VSIs.\n+ *\n+ * The PF is required to return a status code in v_retval for all messages\n+ * except RESET_VF, which does not require any response. The return value\n+ * is of status_code type, defined in the shared type.h.\n+ *\n+ * In general, VF driver initialization should roughly follow the order of\n+ * these opcodes. The VF driver must first validate the API version of the\n+ * PF driver, then request a reset, then get resources, then configure\n+ * queues and interrupts. After these operations are complete, the VF\n+ * driver may start its queues, optionally add MAC and VLAN filters, and\n+ * process traffic.\n+ */\n+\n+/* START GENERIC DEFINES\n+ * Need to ensure the following enums and defines hold the same meaning and\n+ * value in current and future projects\n+ */\n+\n+/* Error Codes */\n+enum virtchnl_status_code {\n+\tVIRTCHNL_STATUS_SUCCESS\t\t\t\t= 0,\n+\tVIRTCHNL_STATUS_ERR_PARAM\t\t\t= -5,\n+\tVIRTCHNL_STATUS_ERR_NO_MEMORY\t\t\t= -18,\n+\tVIRTCHNL_STATUS_ERR_OPCODE_MISMATCH\t\t= -38,\n+\tVIRTCHNL_STATUS_ERR_CQP_COMPL_ERROR\t\t= -39,\n+\tVIRTCHNL_STATUS_ERR_INVALID_VF_ID\t\t= -40,\n+\tVIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR\t\t= -53,\n+\tVIRTCHNL_STATUS_ERR_NOT_SUPPORTED\t\t= -64,\n+};\n+\n+/* Backward compatibility */\n+#define VIRTCHNL_ERR_PARAM VIRTCHNL_STATUS_ERR_PARAM\n+#define VIRTCHNL_STATUS_NOT_SUPPORTED VIRTCHNL_STATUS_ERR_NOT_SUPPORTED\n+\n+#define VIRTCHNL_LINK_SPEED_100MB_SHIFT\t\t0x1\n+#define VIRTCHNL_LINK_SPEED_1000MB_SHIFT\t0x2\n+#define VIRTCHNL_LINK_SPEED_10GB_SHIFT\t\t0x3\n+#define VIRTCHNL_LINK_SPEED_40GB_SHIFT\t\t0x4\n+#define VIRTCHNL_LINK_SPEED_20GB_SHIFT\t\t0x5\n+#define VIRTCHNL_LINK_SPEED_25GB_SHIFT\t\t0x6\n+\n+enum virtchnl_link_speed {\n+\tVIRTCHNL_LINK_SPEED_UNKNOWN\t= 0,\n+\tVIRTCHNL_LINK_SPEED_100MB\t= BIT(VIRTCHNL_LINK_SPEED_100MB_SHIFT),\n+\tVIRTCHNL_LINK_SPEED_1GB\t\t= BIT(VIRTCHNL_LINK_SPEED_1000MB_SHIFT),\n+\tVIRTCHNL_LINK_SPEED_10GB\t= BIT(VIRTCHNL_LINK_SPEED_10GB_SHIFT),\n+\tVIRTCHNL_LINK_SPEED_40GB\t= BIT(VIRTCHNL_LINK_SPEED_40GB_SHIFT),\n+\tVIRTCHNL_LINK_SPEED_20GB\t= BIT(VIRTCHNL_LINK_SPEED_20GB_SHIFT),\n+\tVIRTCHNL_LINK_SPEED_25GB\t= BIT(VIRTCHNL_LINK_SPEED_25GB_SHIFT),\n+};\n+\n+/* for hsplit_0 field of Rx HMC context */\n+/* deprecated with AVF 1.0 */\n+enum virtchnl_rx_hsplit {\n+\tVIRTCHNL_RX_HSPLIT_NO_SPLIT      = 0,\n+\tVIRTCHNL_RX_HSPLIT_SPLIT_L2      = 1,\n+\tVIRTCHNL_RX_HSPLIT_SPLIT_IP      = 2,\n+\tVIRTCHNL_RX_HSPLIT_SPLIT_TCP_UDP = 4,\n+\tVIRTCHNL_RX_HSPLIT_SPLIT_SCTP    = 8,\n+};\n+\n+/* END GENERIC DEFINES */\n+\n+/* Opcodes for VF-PF communication. These are placed in the v_opcode field\n+ * of the virtchnl_msg structure.\n+ */\n+enum virtchnl_ops {\n+/* The PF sends status change events to VFs using\n+ * the VIRTCHNL_OP_EVENT opcode.\n+ * VFs send requests to the PF using the other ops.\n+ * Use of \"advanced opcode\" features must be negotiated as part of capabilities\n+ * exchange and are not considered part of base mode feature set.\n+ */\n+\tVIRTCHNL_OP_UNKNOWN = 0,\n+\tVIRTCHNL_OP_VERSION = 1, /* must ALWAYS be 1 */\n+\tVIRTCHNL_OP_RESET_VF = 2,\n+\tVIRTCHNL_OP_GET_VF_RESOURCES = 3,\n+\tVIRTCHNL_OP_CONFIG_TX_QUEUE = 4,\n+\tVIRTCHNL_OP_CONFIG_RX_QUEUE = 5,\n+\tVIRTCHNL_OP_CONFIG_VSI_QUEUES = 6,\n+\tVIRTCHNL_OP_CONFIG_IRQ_MAP = 7,\n+\tVIRTCHNL_OP_ENABLE_QUEUES = 8,\n+\tVIRTCHNL_OP_DISABLE_QUEUES = 9,\n+\tVIRTCHNL_OP_ADD_ETH_ADDR = 10,\n+\tVIRTCHNL_OP_DEL_ETH_ADDR = 11,\n+\tVIRTCHNL_OP_ADD_VLAN = 12,\n+\tVIRTCHNL_OP_DEL_VLAN = 13,\n+\tVIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE = 14,\n+\tVIRTCHNL_OP_GET_STATS = 15,\n+\tVIRTCHNL_OP_RSVD = 16,\n+\tVIRTCHNL_OP_EVENT = 17, /* must ALWAYS be 17 */\n+\t/* opcode 19 is reserved */\n+\t/* opcodes 20, 21, and 22 are reserved */\n+\tVIRTCHNL_OP_CONFIG_RSS_KEY = 23,\n+\tVIRTCHNL_OP_CONFIG_RSS_LUT = 24,\n+\tVIRTCHNL_OP_GET_RSS_HENA_CAPS = 25,\n+\tVIRTCHNL_OP_SET_RSS_HENA = 26,\n+\tVIRTCHNL_OP_ENABLE_VLAN_STRIPPING = 27,\n+\tVIRTCHNL_OP_DISABLE_VLAN_STRIPPING = 28,\n+\tVIRTCHNL_OP_REQUEST_QUEUES = 29,\n+\tVIRTCHNL_OP_ENABLE_CHANNELS = 30,\n+\tVIRTCHNL_OP_DISABLE_CHANNELS = 31,\n+\tVIRTCHNL_OP_ADD_CLOUD_FILTER = 32,\n+\tVIRTCHNL_OP_DEL_CLOUD_FILTER = 33,\n+\n+};\n+\n+/* These macros are used to generate compilation errors if a structure/union\n+ * is not exactly the correct length. It gives a divide by zero error if the\n+ * structure/union is not of the correct size, otherwise it creates an enum\n+ * that is never used.\n+ */\n+#define VIRTCHNL_CHECK_STRUCT_LEN(n, X) enum virtchnl_static_assert_enum_##X \\\n+\t{ virtchnl_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }\n+#define VIRTCHNL_CHECK_UNION_LEN(n, X) enum virtchnl_static_asset_enum_##X \\\n+\t{ virtchnl_static_assert_##X = (n)/((sizeof(union X) == (n)) ? 1 : 0) }\n+\n+/* Virtual channel message descriptor. This overlays the admin queue\n+ * descriptor. All other data is passed in external buffers.\n+ */\n+\n+struct virtchnl_msg {\n+\tu8 pad[8];\t\t\t /* AQ flags/opcode/len/retval fields */\n+\tenum virtchnl_ops v_opcode; /* avoid confusion with desc->opcode */\n+\tenum virtchnl_status_code v_retval;  /* ditto for desc->retval */\n+\tu32 vfid;\t\t\t /* used by PF when sending to VF */\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(20, virtchnl_msg);\n+\n+/* Message descriptions and data structures. */\n+\n+/* VIRTCHNL_OP_VERSION\n+ * VF posts its version number to the PF. PF responds with its version number\n+ * in the same format, along with a return code.\n+ * Reply from PF has its major/minor versions also in param0 and param1.\n+ * If there is a major version mismatch, then the VF cannot operate.\n+ * If there is a minor version mismatch, then the VF can operate but should\n+ * add a warning to the system log.\n+ *\n+ * This enum element MUST always be specified as == 1, regardless of other\n+ * changes in the API. The PF must always respond to this message without\n+ * error regardless of version mismatch.\n+ */\n+#define VIRTCHNL_VERSION_MAJOR\t\t1\n+#define VIRTCHNL_VERSION_MINOR\t\t1\n+#define VIRTCHNL_VERSION_MINOR_NO_VF_CAPS\t0\n+\n+struct virtchnl_version_info {\n+\tu32 major;\n+\tu32 minor;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_version_info);\n+\n+#define VF_IS_V10(_v) (((_v)->major == 1) && ((_v)->minor == 0))\n+#define VF_IS_V11(_ver) (((_ver)->major == 1) && ((_ver)->minor == 1))\n+\n+/* VIRTCHNL_OP_RESET_VF\n+ * VF sends this request to PF with no parameters\n+ * PF does NOT respond! VF driver must delay then poll VFGEN_RSTAT register\n+ * until reset completion is indicated. The admin queue must be reinitialized\n+ * after this operation.\n+ *\n+ * When reset is complete, PF must ensure that all queues in all VSIs associated\n+ * with the VF are stopped, all queue configurations in the HMC are set to 0,\n+ * and all MAC and VLAN filters (except the default MAC address) on all VSIs\n+ * are cleared.\n+ */\n+\n+/* VSI types that use VIRTCHNL interface for VF-PF communication. VSI_SRIOV\n+ * vsi_type should always be 6 for backward compatibility. Add other fields\n+ * as needed.\n+ */\n+enum virtchnl_vsi_type {\n+\tVIRTCHNL_VSI_TYPE_INVALID = 0,\n+\tVIRTCHNL_VSI_SRIOV = 6,\n+};\n+\n+/* VIRTCHNL_OP_GET_VF_RESOURCES\n+ * Version 1.0 VF sends this request to PF with no parameters\n+ * Version 1.1 VF sends this request to PF with u32 bitmap of its capabilities\n+ * PF responds with an indirect message containing\n+ * virtchnl_vf_resource and one or more\n+ * virtchnl_vsi_resource structures.\n+ */\n+\n+struct virtchnl_vsi_resource {\n+\tu16 vsi_id;\n+\tu16 num_queue_pairs;\n+\tenum virtchnl_vsi_type vsi_type;\n+\tu16 qset_handle;\n+\tu8 default_mac_addr[ETH_ALEN];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource);\n+\n+/* VF capability flags\n+ * VIRTCHNL_VF_OFFLOAD_L2 flag is inclusive of base mode L2 offloads including\n+ * TX/RX Checksum offloading and TSO for non-tunnelled packets.\n+ */\n+#define VIRTCHNL_VF_OFFLOAD_L2\t\t\t0x00000001\n+#define VIRTCHNL_VF_OFFLOAD_IWARP\t\t0x00000002\n+#define VIRTCHNL_VF_OFFLOAD_RSVD\t\t0x00000004\n+#define VIRTCHNL_VF_OFFLOAD_RSS_AQ\t\t0x00000008\n+#define VIRTCHNL_VF_OFFLOAD_RSS_REG\t\t0x00000010\n+#define VIRTCHNL_VF_OFFLOAD_WB_ON_ITR\t\t0x00000020\n+#define VIRTCHNL_VF_OFFLOAD_REQ_QUEUES\t\t0x00000040\n+#define VIRTCHNL_VF_OFFLOAD_VLAN\t\t0x00010000\n+#define VIRTCHNL_VF_OFFLOAD_RX_POLLING\t\t0x00020000\n+#define VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2\t0x00040000\n+#define VIRTCHNL_VF_OFFLOAD_RSS_PF\t\t0X00080000\n+#define VIRTCHNL_VF_OFFLOAD_ENCAP\t\t0X00100000\n+#define VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM\t\t0X00200000\n+#define VIRTCHNL_VF_OFFLOAD_RX_ENCAP_CSUM\t0X00400000\n+#define VIRTCHNL_VF_OFFLOAD_ADQ\t\t\t0X00800000\n+/* Define below the capability flags that are not offloads */\n+#define VIRTCHNL_VF_CAP_ADV_LINK_SPEED\t\t0x00000080\n+\n+#define VF_BASE_MODE_OFFLOADS (VIRTCHNL_VF_OFFLOAD_L2 | \\\n+\t\t\t       VIRTCHNL_VF_OFFLOAD_VLAN | \\\n+\t\t\t       VIRTCHNL_VF_OFFLOAD_RSS_PF)\n+\n+struct virtchnl_vf_resource {\n+\tu16 num_vsis;\n+\tu16 num_queue_pairs;\n+\tu16 max_vectors;\n+\tu16 max_mtu;\n+\n+\tu32 vf_cap_flags;\n+\tu32 rss_key_size;\n+\tu32 rss_lut_size;\n+\n+\tstruct virtchnl_vsi_resource vsi_res[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(36, virtchnl_vf_resource);\n+\n+/* VIRTCHNL_OP_CONFIG_TX_QUEUE\n+ * VF sends this message to set up parameters for one TX queue.\n+ * External data buffer contains one instance of virtchnl_txq_info.\n+ * PF configures requested queue and returns a status code.\n+ */\n+\n+/* Tx queue config info */\n+struct virtchnl_txq_info {\n+\tu16 vsi_id;\n+\tu16 queue_id;\n+\tu16 ring_len;\t\t/* number of descriptors, multiple of 8 */\n+\tu16 headwb_enabled; /* deprecated with AVF 1.0 */\n+\tu64 dma_ring_addr;\n+\tu64 dma_headwb_addr; /* deprecated with AVF 1.0 */\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_txq_info);\n+\n+/* VIRTCHNL_OP_CONFIG_RX_QUEUE\n+ * VF sends this message to set up parameters for one RX queue.\n+ * External data buffer contains one instance of virtchnl_rxq_info.\n+ * PF configures requested queue and returns a status code.\n+ */\n+\n+/* Rx queue config info */\n+struct virtchnl_rxq_info {\n+\tu16 vsi_id;\n+\tu16 queue_id;\n+\tu32 ring_len;\t\t/* number of descriptors, multiple of 32 */\n+\tu16 hdr_size;\n+\tu16 splithdr_enabled; /* deprecated with AVF 1.0 */\n+\tu32 databuffer_size;\n+\tu32 max_pkt_size;\n+\tu32 pad1;\n+\tu64 dma_ring_addr;\n+\tenum virtchnl_rx_hsplit rx_split_pos; /* deprecated with AVF 1.0 */\n+\tu32 pad2;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_rxq_info);\n+\n+/* VIRTCHNL_OP_CONFIG_VSI_QUEUES\n+ * VF sends this message to set parameters for all active TX and RX queues\n+ * associated with the specified VSI.\n+ * PF configures queues and returns status.\n+ * If the number of queues specified is greater than the number of queues\n+ * associated with the VSI, an error is returned and no queues are configured.\n+ */\n+struct virtchnl_queue_pair_info {\n+\t/* NOTE: vsi_id and queue_id should be identical for both queues. */\n+\tstruct virtchnl_txq_info txq;\n+\tstruct virtchnl_rxq_info rxq;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(64, virtchnl_queue_pair_info);\n+\n+struct virtchnl_vsi_queue_config_info {\n+\tu16 vsi_id;\n+\tu16 num_queue_pairs;\n+\tu32 pad;\n+\tstruct virtchnl_queue_pair_info qpair[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(72, virtchnl_vsi_queue_config_info);\n+\n+/* VIRTCHNL_OP_REQUEST_QUEUES\n+ * VF sends this message to request the PF to allocate additional queues to\n+ * this VF.  Each VF gets a guaranteed number of queues on init but asking for\n+ * additional queues must be negotiated.  This is a best effort request as it\n+ * is possible the PF does not have enough queues left to support the request.\n+ * If the PF cannot support the number requested it will respond with the\n+ * maximum number it is able to support.  If the request is successful, PF will\n+ * then reset the VF to institute required changes.\n+ */\n+\n+/* VF resource request */\n+struct virtchnl_vf_res_request {\n+\tu16 num_queue_pairs;\n+};\n+\n+/* VIRTCHNL_OP_CONFIG_IRQ_MAP\n+ * VF uses this message to map vectors to queues.\n+ * The rxq_map and txq_map fields are bitmaps used to indicate which queues\n+ * are to be associated with the specified vector.\n+ * The \"other\" causes are always mapped to vector 0.\n+ * PF configures interrupt mapping and returns status.\n+ */\n+struct virtchnl_vector_map {\n+\tu16 vsi_id;\n+\tu16 vector_id;\n+\tu16 rxq_map;\n+\tu16 txq_map;\n+\tu16 rxitr_idx;\n+\tu16 txitr_idx;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_vector_map);\n+\n+struct virtchnl_irq_map_info {\n+\tu16 num_vectors;\n+\tstruct virtchnl_vector_map vecmap[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(14, virtchnl_irq_map_info);\n+\n+/* VIRTCHNL_OP_ENABLE_QUEUES\n+ * VIRTCHNL_OP_DISABLE_QUEUES\n+ * VF sends these message to enable or disable TX/RX queue pairs.\n+ * The queues fields are bitmaps indicating which queues to act upon.\n+ * (Currently, we only support 16 queues per VF, but we make the field\n+ * u32 to allow for expansion.)\n+ * PF performs requested action and returns status.\n+ */\n+struct virtchnl_queue_select {\n+\tu16 vsi_id;\n+\tu16 pad;\n+\tu32 rx_queues;\n+\tu32 tx_queues;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_queue_select);\n+\n+/* VIRTCHNL_OP_ADD_ETH_ADDR\n+ * VF sends this message in order to add one or more unicast or multicast\n+ * address filters for the specified VSI.\n+ * PF adds the filters and returns status.\n+ */\n+\n+/* VIRTCHNL_OP_DEL_ETH_ADDR\n+ * VF sends this message in order to remove one or more unicast or multicast\n+ * filters for the specified VSI.\n+ * PF removes the filters and returns status.\n+ */\n+\n+struct virtchnl_ether_addr {\n+\tu8 addr[ETH_ALEN];\n+\tu8 pad[2];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_ether_addr);\n+\n+struct virtchnl_ether_addr_list {\n+\tu16 vsi_id;\n+\tu16 num_elements;\n+\tstruct virtchnl_ether_addr list[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_ether_addr_list);\n+\n+/* VIRTCHNL_OP_ADD_VLAN\n+ * VF sends this message to add one or more VLAN tag filters for receives.\n+ * PF adds the filters and returns status.\n+ * If a port VLAN is configured by the PF, this operation will return an\n+ * error to the VF.\n+ */\n+\n+/* VIRTCHNL_OP_DEL_VLAN\n+ * VF sends this message to remove one or more VLAN tag filters for receives.\n+ * PF removes the filters and returns status.\n+ * If a port VLAN is configured by the PF, this operation will return an\n+ * error to the VF.\n+ */\n+\n+struct virtchnl_vlan_filter_list {\n+\tu16 vsi_id;\n+\tu16 num_elements;\n+\tu16 vlan_id[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(6, virtchnl_vlan_filter_list);\n+\n+/* VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE\n+ * VF sends VSI id and flags.\n+ * PF returns status code in retval.\n+ * Note: we assume that broadcast accept mode is always enabled.\n+ */\n+struct virtchnl_promisc_info {\n+\tu16 vsi_id;\n+\tu16 flags;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(4, virtchnl_promisc_info);\n+\n+#define FLAG_VF_UNICAST_PROMISC\t0x00000001\n+#define FLAG_VF_MULTICAST_PROMISC\t0x00000002\n+\n+/* VIRTCHNL_OP_GET_STATS\n+ * VF sends this message to request stats for the selected VSI. VF uses\n+ * the virtchnl_queue_select struct to specify the VSI. The queue_id\n+ * field is ignored by the PF.\n+ *\n+ * PF replies with struct virtchnl_eth_stats in an external buffer.\n+ */\n+\n+struct virtchnl_eth_stats {\n+\tu64 rx_bytes;\t\t\t/* received bytes */\n+\tu64 rx_unicast;\t\t\t/* received unicast pkts */\n+\tu64 rx_multicast;\t\t/* received multicast pkts */\n+\tu64 rx_broadcast;\t\t/* received broadcast pkts */\n+\tu64 rx_discards;\n+\tu64 rx_unknown_protocol;\n+\tu64 tx_bytes;\t\t\t/* transmitted bytes */\n+\tu64 tx_unicast;\t\t\t/* transmitted unicast pkts */\n+\tu64 tx_multicast;\t\t/* transmitted multicast pkts */\n+\tu64 tx_broadcast;\t\t/* transmitted broadcast pkts */\n+\tu64 tx_discards;\n+\tu64 tx_errors;\n+};\n+\n+/* VIRTCHNL_OP_CONFIG_RSS_KEY\n+ * VIRTCHNL_OP_CONFIG_RSS_LUT\n+ * VF sends these messages to configure RSS. Only supported if both PF\n+ * and VF drivers set the VIRTCHNL_VF_OFFLOAD_RSS_PF bit during\n+ * configuration negotiation. If this is the case, then the RSS fields in\n+ * the VF resource struct are valid.\n+ * Both the key and LUT are initialized to 0 by the PF, meaning that\n+ * RSS is effectively disabled until set up by the VF.\n+ */\n+struct virtchnl_rss_key {\n+\tu16 vsi_id;\n+\tu16 key_len;\n+\tu8 key[1];         /* RSS hash key, packed bytes */\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(6, virtchnl_rss_key);\n+\n+struct virtchnl_rss_lut {\n+\tu16 vsi_id;\n+\tu16 lut_entries;\n+\tu8 lut[1];        /* RSS lookup table */\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(6, virtchnl_rss_lut);\n+\n+/* VIRTCHNL_OP_GET_RSS_HENA_CAPS\n+ * VIRTCHNL_OP_SET_RSS_HENA\n+ * VF sends these messages to get and set the hash filter enable bits for RSS.\n+ * By default, the PF sets these to all possible traffic types that the\n+ * hardware supports. The VF can query this value if it wants to change the\n+ * traffic types that are hashed by the hardware.\n+ */\n+struct virtchnl_rss_hena {\n+\tu64 hena;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_rss_hena);\n+\n+/* VIRTCHNL_OP_ENABLE_CHANNELS\n+ * VIRTCHNL_OP_DISABLE_CHANNELS\n+ * VF sends these messages to enable or disable channels based on\n+ * the user specified queue count and queue offset for each traffic class.\n+ * This struct encompasses all the information that the PF needs from\n+ * VF to create a channel.\n+ */\n+struct virtchnl_channel_info {\n+\tu16 count; /* number of queues in a channel */\n+\tu16 offset; /* queues in a channel start from 'offset' */\n+\tu32 pad;\n+\tu64 max_tx_rate;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_channel_info);\n+\n+struct virtchnl_tc_info {\n+\tu32\tnum_tc;\n+\tu32\tpad;\n+\tstruct\tvirtchnl_channel_info list[1];\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_tc_info);\n+\n+/* VIRTCHNL_ADD_CLOUD_FILTER\n+ * VIRTCHNL_DEL_CLOUD_FILTER\n+ * VF sends these messages to add or delete a cloud filter based on the\n+ * user specified match and action filters. These structures encompass\n+ * all the information that the PF needs from the VF to add/delete a\n+ * cloud filter.\n+ */\n+\n+struct virtchnl_l4_spec {\n+\tu8\tsrc_mac[ETH_ALEN];\n+\tu8\tdst_mac[ETH_ALEN];\n+\t__be16\tvlan_id;\n+\t__be16\tpad; /* reserved for future use */\n+\t__be32\tsrc_ip[4];\n+\t__be32\tdst_ip[4];\n+\t__be16\tsrc_port;\n+\t__be16\tdst_port;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(52, virtchnl_l4_spec);\n+\n+union virtchnl_flow_spec {\n+\tstruct\tvirtchnl_l4_spec tcp_spec;\n+\tu8\tbuffer[128]; /* reserved for future use */\n+};\n+\n+VIRTCHNL_CHECK_UNION_LEN(128, virtchnl_flow_spec);\n+\n+enum virtchnl_action {\n+\t/* action types */\n+\tVIRTCHNL_ACTION_DROP = 0,\n+\tVIRTCHNL_ACTION_TC_REDIRECT,\n+};\n+\n+enum virtchnl_flow_type {\n+\t/* flow types */\n+\tVIRTCHNL_TCP_V4_FLOW = 0,\n+\tVIRTCHNL_TCP_V6_FLOW,\n+};\n+\n+struct virtchnl_filter {\n+\tunion\tvirtchnl_flow_spec data;\n+\tunion\tvirtchnl_flow_spec mask;\n+\tenum\tvirtchnl_flow_type flow_type;\n+\tenum\tvirtchnl_action action;\n+\tu32\taction_meta;\n+\tu8\tfield_flags;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(272, virtchnl_filter);\n+\n+/* VIRTCHNL_OP_EVENT\n+ * PF sends this message to inform the VF driver of events that may affect it.\n+ * No direct response is expected from the VF, though it may generate other\n+ * messages in response to this one.\n+ */\n+enum virtchnl_event_codes {\n+\tVIRTCHNL_EVENT_UNKNOWN = 0,\n+\tVIRTCHNL_EVENT_LINK_CHANGE,\n+\tVIRTCHNL_EVENT_RESET_IMPENDING,\n+\tVIRTCHNL_EVENT_PF_DRIVER_CLOSE,\n+};\n+\n+#define PF_EVENT_SEVERITY_INFO\t\t0\n+#define PF_EVENT_SEVERITY_CERTAIN_DOOM\t255\n+\n+struct virtchnl_pf_event {\n+\tenum virtchnl_event_codes event;\n+\tunion {\n+\t\t/* If the PF driver does not support the new speed reporting\n+\t\t * capabilities then use link_event else use link_event_adv to\n+\t\t * get the speed and link information. The ability to understand\n+\t\t * new speeds is indicated by setting the capability flag\n+\t\t * VIRTCHNL_VF_CAP_ADV_LINK_SPEED in vf_cap_flags parameter\n+\t\t * in virtchnl_vf_resource struct and can be used to determine\n+\t\t * which link event struct to use below.\n+\t\t */\n+\t\tstruct {\n+\t\t\tenum virtchnl_link_speed link_speed;\n+\t\t\tu8 link_status;\n+\t\t} link_event;\n+\t\tstruct {\n+\t\t\t/* link_speed provided in Mbps */\n+\t\t\tu32 link_speed;\n+\t\t\tu8 link_status;\n+\t\t} link_event_adv;\n+\t} event_data;\n+\n+\tint severity;\n+};\n+\n+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_pf_event);\n+\n+\n+/* VF reset states - these are written into the RSTAT register:\n+ * VFGEN_RSTAT on the VF\n+ * When the PF initiates a reset, it writes 0\n+ * When the reset is complete, it writes 1\n+ * When the PF detects that the VF has recovered, it writes 2\n+ * VF checks this register periodically to determine if a reset has occurred,\n+ * then polls it to know when the reset is complete.\n+ * If either the PF or VF reads the register while the hardware\n+ * is in a reset state, it will return DEADBEEF, which, when masked\n+ * will result in 3.\n+ */\n+enum virtchnl_vfr_states {\n+\tVIRTCHNL_VFR_INPROGRESS = 0,\n+\tVIRTCHNL_VFR_COMPLETED,\n+\tVIRTCHNL_VFR_VFACTIVE,\n+};\n+\n+/**\n+ * virtchnl_vc_validate_vf_msg\n+ * @ver: Virtchnl version info\n+ * @v_opcode: Opcode for the message\n+ * @msg: pointer to the msg buffer\n+ * @msglen: msg length\n+ *\n+ * validate msg format against struct for each opcode\n+ */\n+static inline int\n+virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,\n+\t\t\t    u8 *msg, u16 msglen)\n+{\n+\tbool err_msg_format = false;\n+\tint valid_len = 0;\n+\n+\t/* Validate message length. */\n+\tswitch (v_opcode) {\n+\tcase VIRTCHNL_OP_VERSION:\n+\t\tvalid_len = sizeof(struct virtchnl_version_info);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_RESET_VF:\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_GET_VF_RESOURCES:\n+\t\tif (VF_IS_V11(ver))\n+\t\t\tvalid_len = sizeof(u32);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_CONFIG_TX_QUEUE:\n+\t\tvalid_len = sizeof(struct virtchnl_txq_info);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_CONFIG_RX_QUEUE:\n+\t\tvalid_len = sizeof(struct virtchnl_rxq_info);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_CONFIG_VSI_QUEUES:\n+\t\tvalid_len = sizeof(struct virtchnl_vsi_queue_config_info);\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl_vsi_queue_config_info *vqc =\n+\t\t\t    (struct virtchnl_vsi_queue_config_info *)msg;\n+\t\t\tvalid_len += (vqc->num_queue_pairs *\n+\t\t\t\t      sizeof(struct\n+\t\t\t\t\t     virtchnl_queue_pair_info));\n+\t\t\tif (vqc->num_queue_pairs == 0)\n+\t\t\t\terr_msg_format = true;\n+\t\t}\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_CONFIG_IRQ_MAP:\n+\t\tvalid_len = sizeof(struct virtchnl_irq_map_info);\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl_irq_map_info *vimi =\n+\t\t\t    (struct virtchnl_irq_map_info *)msg;\n+\t\t\tvalid_len += (vimi->num_vectors *\n+\t\t\t\t      sizeof(struct virtchnl_vector_map));\n+\t\t\tif (vimi->num_vectors == 0)\n+\t\t\t\terr_msg_format = true;\n+\t\t}\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_ENABLE_QUEUES:\n+\tcase VIRTCHNL_OP_DISABLE_QUEUES:\n+\t\tvalid_len = sizeof(struct virtchnl_queue_select);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_ADD_ETH_ADDR:\n+\tcase VIRTCHNL_OP_DEL_ETH_ADDR:\n+\t\tvalid_len = sizeof(struct virtchnl_ether_addr_list);\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl_ether_addr_list *veal =\n+\t\t\t    (struct virtchnl_ether_addr_list *)msg;\n+\t\t\tvalid_len += veal->num_elements *\n+\t\t\t    sizeof(struct virtchnl_ether_addr);\n+\t\t\tif (veal->num_elements == 0)\n+\t\t\t\terr_msg_format = true;\n+\t\t}\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_ADD_VLAN:\n+\tcase VIRTCHNL_OP_DEL_VLAN:\n+\t\tvalid_len = sizeof(struct virtchnl_vlan_filter_list);\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl_vlan_filter_list *vfl =\n+\t\t\t    (struct virtchnl_vlan_filter_list *)msg;\n+\t\t\tvalid_len += vfl->num_elements * sizeof(u16);\n+\t\t\tif (vfl->num_elements == 0)\n+\t\t\t\terr_msg_format = true;\n+\t\t}\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:\n+\t\tvalid_len = sizeof(struct virtchnl_promisc_info);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_GET_STATS:\n+\t\tvalid_len = sizeof(struct virtchnl_queue_select);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_CONFIG_RSS_KEY:\n+\t\tvalid_len = sizeof(struct virtchnl_rss_key);\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl_rss_key *vrk =\n+\t\t\t\t(struct virtchnl_rss_key *)msg;\n+\t\t\tvalid_len += vrk->key_len - 1;\n+\t\t}\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_CONFIG_RSS_LUT:\n+\t\tvalid_len = sizeof(struct virtchnl_rss_lut);\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl_rss_lut *vrl =\n+\t\t\t\t(struct virtchnl_rss_lut *)msg;\n+\t\t\tvalid_len += vrl->lut_entries - 1;\n+\t\t}\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_GET_RSS_HENA_CAPS:\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_SET_RSS_HENA:\n+\t\tvalid_len = sizeof(struct virtchnl_rss_hena);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_ENABLE_VLAN_STRIPPING:\n+\tcase VIRTCHNL_OP_DISABLE_VLAN_STRIPPING:\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_REQUEST_QUEUES:\n+\t\tvalid_len = sizeof(struct virtchnl_vf_res_request);\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_ENABLE_CHANNELS:\n+\t\tvalid_len = sizeof(struct virtchnl_tc_info);\n+\t\tif (msglen >= valid_len) {\n+\t\t\tstruct virtchnl_tc_info *vti =\n+\t\t\t\t(struct virtchnl_tc_info *)msg;\n+\t\t\tvalid_len += (vti->num_tc - 1) *\n+\t\t\t\t     sizeof(struct virtchnl_channel_info);\n+\t\t\tif (vti->num_tc == 0)\n+\t\t\t\terr_msg_format = true;\n+\t\t}\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_DISABLE_CHANNELS:\n+\t\tbreak;\n+\tcase VIRTCHNL_OP_ADD_CLOUD_FILTER:\n+\tcase VIRTCHNL_OP_DEL_CLOUD_FILTER:\n+\t\tvalid_len = sizeof(struct virtchnl_filter);\n+\t\tbreak;\n+\t/* These are always errors coming from the VF. */\n+\tcase VIRTCHNL_OP_EVENT:\n+\tcase VIRTCHNL_OP_UNKNOWN:\n+\tdefault:\n+\t\treturn VIRTCHNL_STATUS_ERR_PARAM;\n+\t}\n+\t/* few more checks */\n+\tif (err_msg_format || valid_len != msglen)\n+\t\treturn VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH;\n+\n+\treturn 0;\n+}\n+#endif /* _VIRTCHNL_H_ */\n",
    "prefixes": [
        "01/19"
    ]
}