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GET /api/patches/46705/?format=api
{ "id": 46705, "url": "http://patches.dpdk.org/api/patches/46705/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/4a77b5e45cc3c2a741804c0efd62436df9885ed5.1539338074.git.igor.russkikh@aquantia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<4a77b5e45cc3c2a741804c0efd62436df9885ed5.1539338074.git.igor.russkikh@aquantia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/4a77b5e45cc3c2a741804c0efd62436df9885ed5.1539338074.git.igor.russkikh@aquantia.com", "date": "2018-10-12T11:09:27", "name": "[v6,10/22] net/atlantic: implement Tx path", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "e7f9382e9776c22b518e08d39ddf8eed8bcc8adf", "submitter": { "id": 1124, "url": "http://patches.dpdk.org/api/people/1124/?format=api", "name": "Igor Russkikh", "email": "igor.russkikh@aquantia.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/4a77b5e45cc3c2a741804c0efd62436df9885ed5.1539338074.git.igor.russkikh@aquantia.com/mbox/", "series": [ { "id": 1862, "url": "http://patches.dpdk.org/api/series/1862/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1862", "date": "2018-10-12T11:09:01", "name": "net/atlantic: Aquantia aQtion 10G NIC Family DPDK PMD driver", "version": 6, "mbox": "http://patches.dpdk.org/series/1862/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/46705/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/46705/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3F3DE1B5BB;\n\tFri, 12 Oct 2018 13:09:33 +0200 (CEST)", "from NAM02-BL2-obe.outbound.protection.outlook.com\n\t(mail-bl2nam02on0083.outbound.protection.outlook.com [104.47.38.83])\n\tby dpdk.org (Postfix) with ESMTP id 2AE7C1B5AD\n\tfor <dev@dpdk.org>; Fri, 12 Oct 2018 13:09:30 +0200 (CEST)", "from BY1PR0701MB1660.namprd07.prod.outlook.com (10.162.110.22) by\n\tBY1PR0701MB1627.namprd07.prod.outlook.com (10.162.110.156) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1228.22; Fri, 12 Oct 2018 11:09:27 +0000", "from BY1PR0701MB1660.namprd07.prod.outlook.com\n\t([fe80::346d:e756:e70e:17]) by\n\tBY1PR0701MB1660.namprd07.prod.outlook.com\n\t([fe80::346d:e756:e70e:17%3]) with mapi id 15.20.1228.020;\n\tFri, 12 Oct 2018 11:09:27 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=AQUANTIA1COM.onmicrosoft.com; s=selector1-aquantia-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=eeMUay/QIVhlnmzBOCzccgCmYnwyaOGunUigTthUmhs=;\n\tb=OhlxQCK3pcYqEbTLsmNEkiI/CvFWYMa7UydUuNzoDSP1i6H5rV6vBTXGrmEmPqTETTpUQuyy/cvOIe2Fey+ujanfh0qgqiLL6Z1sDk/2ec0a+8fgo3uZuwUuepbNOH+Pvr0KqFxqZcvQ0tidgoYctwWHFlPerH8BBm/vK24VYNo=", "From": "Igor Russkikh <Igor.Russkikh@aquantia.com>", "To": "\"dev@dpdk.org\" <dev@dpdk.org>", "CC": "Pavel Belous <Pavel.Belous@aquantia.com>, Igor Russkikh\n\t<Igor.Russkikh@aquantia.com>, \"ferruh.yigit@intel.com\"\n\t<ferruh.yigit@intel.com>", "Thread-Topic": "[PATCH v6 10/22] net/atlantic: implement Tx path", "Thread-Index": "AQHUYhwKGhPlLvxpsk2EUCBTBWKZQQ==", "Date": "Fri, 12 Oct 2018 11:09:27 +0000", "Message-ID": "<4a77b5e45cc3c2a741804c0efd62436df9885ed5.1539338074.git.igor.russkikh@aquantia.com>", "References": "<cover.1539338074.git.igor.russkikh@aquantia.com>", "In-Reply-To": "<cover.1539338074.git.igor.russkikh@aquantia.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "AM5PR0701CA0008.eurprd07.prod.outlook.com\n\t(2603:10a6:203:51::18) To BY1PR0701MB1660.namprd07.prod.outlook.com\n\t(2a01:111:e400:522a::22)", "authentication-results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Igor.Russkikh@aquantia.com; ", "x-ms-exchange-messagesentrepresentingtype": "1", "x-originating-ip": "[95.79.108.179]", "x-ms-publictraffictype": "Email", "x-microsoft-exchange-diagnostics": "1; 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"x-forefront-antispam-report": "SFV:NSPM;\n\tSFS:(10009020)(346002)(366004)(376002)(136003)(39850400004)(396003)(189003)(199004)(186003)(6116002)(486006)(5640700003)(446003)(6436002)(6512007)(53936002)(71200400001)(71190400001)(14454004)(72206003)(316002)(2351001)(44832011)(3846002)(7736002)(305945005)(2906002)(4326008)(6486002)(97736004)(26005)(2501003)(102836004)(53946003)(5250100002)(11346002)(86362001)(25786009)(4744004)(476003)(2616005)(106356001)(54906003)(105586002)(256004)(14444005)(5660300001)(66066001)(81166006)(81156014)(1730700003)(8676002)(478600001)(36756003)(68736007)(6916009)(8936002)(99286004)(386003)(6506007)(118296001)(2900100001)(52116002)(76176011)(309714004);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BY1PR0701MB1627;\n\tH:BY1PR0701MB1660.namprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; \n\tPTR:InfoNoRecords; MX:1; A:1; ", "received-spf": "None (protection.outlook.com: aquantia.com does not designate\n\tpermitted sender hosts)", "x-microsoft-antispam-message-info": "k48DKjN0ykEXtrLfJSOIViOskTuqrEtrjhayBh0AZ4A7DmAN5n+mxILI6DKehirBSsRhJ28WBgL7FhPgG/CyDMG+DGKJCniaEtcDhCpQdqE3T91376ZqZ2swnPUkBF29ItXMUnghkSJW/FaCT2+aLvm6XwcCnliIWMI0LfB0An1GwUbT+UWh8LyUV8+TsSL6hJfbnecVZmCxYeGYQWv5QopLavmo4nQKYy7yDbE8k8D6UMLRg2oTrjQCh8PrYU4nOpY2rDr8a2hztdLdCISRUG1NcNdk2wDflZxnt8LPtHisX5MZtfl2IZK45gZrNv8lENSKrJ8YUDViaAPKaSBSJAwwv84EFF9ExwwP9+6qgp0=", "spamdiagnosticoutput": "1:99", "spamdiagnosticmetadata": "NSPM", "Content-Type": "text/plain; charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "aquantia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "eeb37344-0231-4b11-75c1-08d630332c7e", "X-MS-Exchange-CrossTenant-originalarrivaltime": "12 Oct 2018 11:09:27.2068\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "83e2e134-991c-4ede-8ced-34d47e38e6b1", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY1PR0701MB1627", "Subject": "[dpdk-dev] [PATCH v6 10/22] net/atlantic: implement Tx path", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavel Belous <pavel.belous@aquantia.com>\n\nAdd implementation for TX datapath.\n\nSigned-off-by: Igor Russkikh <igor.russkikh@aquantia.com>\nSigned-off-by: Pavel Belous <pavel.belous@aquantia.com>\n---\n drivers/net/atlantic/atl_ethdev.c | 28 ++\n drivers/net/atlantic/atl_ethdev.h | 7 +\n drivers/net/atlantic/atl_rxtx.c | 546 +++++++++++++++++++++++++++++++++++++-\n 3 files changed, 572 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/atlantic/atl_ethdev.c b/drivers/net/atlantic/atl_ethdev.c\nindex 521376d1398c..156f1be99cdf 100644\n--- a/drivers/net/atlantic/atl_ethdev.c\n+++ b/drivers/net/atlantic/atl_ethdev.c\n@@ -82,12 +82,27 @@ static struct rte_pci_driver rte_atl_pmd = {\n \t\t\t| DEV_RX_OFFLOAD_TCP_CKSUM \\\n \t\t\t| DEV_RX_OFFLOAD_JUMBO_FRAME)\n \n+#define ATL_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT \\\n+\t\t\t| DEV_TX_OFFLOAD_IPV4_CKSUM \\\n+\t\t\t| DEV_TX_OFFLOAD_UDP_CKSUM \\\n+\t\t\t| DEV_TX_OFFLOAD_TCP_CKSUM \\\n+\t\t\t| DEV_TX_OFFLOAD_TCP_TSO \\\n+\t\t\t| DEV_TX_OFFLOAD_MULTI_SEGS)\n+\n static const struct rte_eth_desc_lim rx_desc_lim = {\n \t.nb_max = ATL_MAX_RING_DESC,\n \t.nb_min = ATL_MIN_RING_DESC,\n \t.nb_align = ATL_RXD_ALIGN,\n };\n \n+static const struct rte_eth_desc_lim tx_desc_lim = {\n+\t.nb_max = ATL_MAX_RING_DESC,\n+\t.nb_min = ATL_MIN_RING_DESC,\n+\t.nb_align = ATL_TXD_ALIGN,\n+\t.nb_seg_max = ATL_TX_MAX_SEG,\n+\t.nb_mtu_seg_max = ATL_TX_MAX_SEG,\n+};\n+\n static const struct eth_dev_ops atl_eth_dev_ops = {\n \t.dev_configure\t = atl_dev_configure,\n \t.dev_start\t = atl_dev_start,\n@@ -104,6 +119,11 @@ static const struct eth_dev_ops atl_eth_dev_ops = {\n \t.rx_queue_stop\t = atl_rx_queue_stop,\n \t.rx_queue_setup = atl_rx_queue_setup,\n \t.rx_queue_release = atl_rx_queue_release,\n+\n+\t.tx_queue_start\t = atl_tx_queue_start,\n+\t.tx_queue_stop\t = atl_tx_queue_stop,\n+\t.tx_queue_setup = atl_tx_queue_setup,\n+\t.tx_queue_release = atl_tx_queue_release,\n };\n \n static inline int32_t\n@@ -350,11 +370,19 @@ atl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \n \tdev_info->rx_offload_capa = ATL_RX_OFFLOADS;\n \n+\tdev_info->tx_offload_capa = ATL_TX_OFFLOADS;\n+\n+\n \tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n \t\t.rx_free_thresh = ATL_DEFAULT_RX_FREE_THRESH,\n \t};\n \n+\tdev_info->default_txconf = (struct rte_eth_txconf) {\n+\t\t.tx_free_thresh = ATL_DEFAULT_TX_FREE_THRESH,\n+\t};\n+\n \tdev_info->rx_desc_lim = rx_desc_lim;\n+\tdev_info->tx_desc_lim = tx_desc_lim;\n }\n \n static const uint32_t *\ndiff --git a/drivers/net/atlantic/atl_ethdev.h b/drivers/net/atlantic/atl_ethdev.h\nindex a9a9fc8fe7ff..92bb302ffe55 100644\n--- a/drivers/net/atlantic/atl_ethdev.h\n+++ b/drivers/net/atlantic/atl_ethdev.h\n@@ -29,12 +29,17 @@ struct atl_adapter {\n * RX/TX function prototypes\n */\n void atl_rx_queue_release(void *rxq);\n+void atl_tx_queue_release(void *txq);\n \n int atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n \t\tuint16_t nb_rx_desc, unsigned int socket_id,\n \t\tconst struct rte_eth_rxconf *rx_conf,\n \t\tstruct rte_mempool *mb_pool);\n \n+int atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n+\t\tuint16_t nb_tx_desc, unsigned int socket_id,\n+\t\tconst struct rte_eth_txconf *tx_conf);\n+\n int atl_rx_init(struct rte_eth_dev *dev);\n int atl_tx_init(struct rte_eth_dev *dev);\n \n@@ -45,6 +50,8 @@ void atl_free_queues(struct rte_eth_dev *dev);\n int atl_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n int atl_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);\n \n+int atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+int atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n \n uint16_t atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tuint16_t nb_pkts);\ndiff --git a/drivers/net/atlantic/atl_rxtx.c b/drivers/net/atlantic/atl_rxtx.c\nindex 61dbb83b4572..1d4c8099325d 100644\n--- a/drivers/net/atlantic/atl_rxtx.c\n+++ b/drivers/net/atlantic/atl_rxtx.c\n@@ -4,6 +4,7 @@\n \n #include <rte_malloc.h>\n #include <rte_ethdev_driver.h>\n+#include <rte_net.h>\n \n #include \"atl_ethdev.h\"\n #include \"atl_hw_regs.h\"\n@@ -13,6 +14,20 @@\n #include \"hw_atl/hw_atl_b0.h\"\n #include \"hw_atl/hw_atl_b0_internal.h\"\n \n+#define ATL_TX_CKSUM_OFFLOAD_MASK (\t\t\t \\\n+\tPKT_TX_IP_CKSUM |\t\t\t\t \\\n+\tPKT_TX_L4_MASK |\t\t\t\t \\\n+\tPKT_TX_TCP_SEG)\n+\n+#define ATL_TX_OFFLOAD_MASK (\t\t\t\t \\\n+\tPKT_TX_VLAN |\t\t\t\t\t \\\n+\tPKT_TX_IP_CKSUM |\t\t\t\t \\\n+\tPKT_TX_L4_MASK |\t\t\t\t \\\n+\tPKT_TX_TCP_SEG)\n+\n+#define ATL_TX_OFFLOAD_NOTSUP_MASK \\\n+\t(PKT_TX_OFFLOAD_MASK ^ ATL_TX_OFFLOAD_MASK)\n+\n /**\n * Structure associated with each descriptor of the RX ring of a RX queue.\n */\n@@ -21,6 +36,15 @@ struct atl_rx_entry {\n };\n \n /**\n+ * Structure associated with each descriptor of the TX ring of a TX queue.\n+ */\n+struct atl_tx_entry {\n+\tstruct rte_mbuf *mbuf;\n+\tuint16_t next_id;\n+\tuint16_t last_id;\n+};\n+\n+/**\n * Structure associated with each RX queue.\n */\n struct atl_rx_queue {\n@@ -39,6 +63,22 @@ struct atl_rx_queue {\n \tbool\t\t\tl4_csum_enabled;\n };\n \n+/**\n+ * Structure associated with each TX queue.\n+ */\n+struct atl_tx_queue {\n+\tstruct hw_atl_txd_s\t*hw_ring;\n+\tuint64_t\t\thw_ring_phys_addr;\n+\tstruct atl_tx_entry\t*sw_ring;\n+\tuint16_t\t\tnb_tx_desc;\n+\tuint16_t\t\ttx_tail;\n+\tuint16_t\t\ttx_head;\n+\tuint16_t\t\tqueue_id;\n+\tuint16_t\t\tport_id;\n+\tuint16_t\t\ttx_free_thresh;\n+\tuint16_t\t\ttx_free;\n+};\n+\n static inline void\n atl_reset_rx_queue(struct atl_rx_queue *rxq)\n {\n@@ -147,13 +187,152 @@ atl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n \treturn 0;\n }\n \n+static inline void\n+atl_reset_tx_queue(struct atl_tx_queue *txq)\n+{\n+\tstruct atl_tx_entry *tx_entry;\n+\tunion hw_atl_txc_s *txc;\n+\tuint16_t i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (!txq) {\n+\t\tPMD_DRV_LOG(ERR, \"Pointer to txq is NULL\");\n+\t\treturn;\n+\t}\n+\n+\ttx_entry = txq->sw_ring;\n+\n+\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n+\t\ttxc = (union hw_atl_txc_s *)&txq->hw_ring[i];\n+\t\ttxc->flags1 = 0;\n+\t\ttxc->flags2 = 2;\n+\t}\n+\n+\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n+\t\ttxq->hw_ring[i].dd = 1;\n+\t\ttx_entry[i].mbuf = NULL;\n+\t}\n+\n+\ttxq->tx_tail = 0;\n+\ttxq->tx_head = 0;\n+\ttxq->tx_free = txq->nb_tx_desc - 1;\n+}\n+\n int\n-atl_tx_init(struct rte_eth_dev *eth_dev __rte_unused)\n+atl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,\n+\t\t uint16_t nb_tx_desc, unsigned int socket_id,\n+\t\t const struct rte_eth_txconf *tx_conf)\n {\n+\tstruct atl_tx_queue *txq;\n+\tconst struct rte_memzone *mz;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\t/* make sure a valid number of descriptors have been requested */\n+\tif (nb_tx_desc < AQ_HW_MIN_TX_RING_SIZE ||\n+\t\tnb_tx_desc > AQ_HW_MAX_TX_RING_SIZE) {\n+\t\tPMD_INIT_LOG(ERR, \"Number of Tx descriptors must be \"\n+\t\t\t\"less than or equal to %d, \"\n+\t\t\t\"greater than or equal to %d\", AQ_HW_MAX_TX_RING_SIZE,\n+\t\t\tAQ_HW_MIN_TX_RING_SIZE);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * if this queue existed already, free the associated memory. The\n+\t * queue cannot be reused in case we need to allocate memory on\n+\t * different socket than was previously used.\n+\t */\n+\tif (dev->data->tx_queues[tx_queue_id] != NULL) {\n+\t\tatl_tx_queue_release(dev->data->tx_queues[tx_queue_id]);\n+\t\tdev->data->tx_queues[tx_queue_id] = NULL;\n+\t}\n+\n+\t/* allocate memory for the queue structure */\n+\ttxq = rte_zmalloc_socket(\"atlantic Tx queue\", sizeof(*txq),\n+\t\t\t\t RTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq == NULL) {\n+\t\tPMD_INIT_LOG(ERR, \"Cannot allocate queue structure\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* setup queue */\n+\ttxq->nb_tx_desc = nb_tx_desc;\n+\ttxq->port_id = dev->data->port_id;\n+\ttxq->queue_id = tx_queue_id;\n+\ttxq->tx_free_thresh = tx_conf->tx_free_thresh;\n+\n+\n+\t/* allocate memory for the software ring */\n+\ttxq->sw_ring = rte_zmalloc_socket(\"atlantic sw tx ring\",\n+\t\t\t\tnb_tx_desc * sizeof(struct atl_tx_entry),\n+\t\t\t\tRTE_CACHE_LINE_SIZE, socket_id);\n+\tif (txq->sw_ring == NULL) {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\"Port %d: Cannot allocate software ring for queue %d\",\n+\t\t\ttxq->port_id, txq->queue_id);\n+\t\trte_free(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/*\n+\t * allocate memory for the hardware descriptor ring. A memzone large\n+\t * enough to hold the maximum ring size is requested to allow for\n+\t * resizing in later calls to the queue setup function.\n+\t */\n+\tmz = rte_eth_dma_zone_reserve(dev, \"tx hw_ring\", tx_queue_id,\n+\t\t\t\tHW_ATL_B0_MAX_TXD * sizeof(struct hw_atl_txd_s),\n+\t\t\t\t128, socket_id);\n+\tif (mz == NULL) {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\"Port %d: Cannot allocate hardware ring for queue %d\",\n+\t\t\ttxq->port_id, txq->queue_id);\n+\t\trte_free(txq->sw_ring);\n+\t\trte_free(txq);\n+\t\treturn -ENOMEM;\n+\t}\n+\ttxq->hw_ring = mz->addr;\n+\ttxq->hw_ring_phys_addr = mz->iova;\n+\n+\tatl_reset_tx_queue(txq);\n+\n+\tdev->data->tx_queues[tx_queue_id] = txq;\n \treturn 0;\n }\n \n int\n+atl_tx_init(struct rte_eth_dev *eth_dev)\n+{\n+\tstruct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n+\tstruct atl_tx_queue *txq;\n+\tuint64_t base_addr = 0;\n+\tint i = 0;\n+\tint err = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n+\t\ttxq = eth_dev->data->tx_queues[i];\n+\t\tbase_addr = txq->hw_ring_phys_addr;\n+\n+\t\terr = hw_atl_b0_hw_ring_tx_init(hw, base_addr,\n+\t\t\t\t\t\ttxq->queue_id,\n+\t\t\t\t\t\ttxq->nb_tx_desc, 0,\n+\t\t\t\t\t\ttxq->port_id);\n+\n+\t\tif (err) {\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t\"Port %d: Cannot init TX queue %d\",\n+\t\t\t\ttxq->port_id, txq->queue_id);\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn err;\n+}\n+\n+int\n atl_rx_init(struct rte_eth_dev *eth_dev)\n {\n \tstruct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);\n@@ -325,15 +504,78 @@ atl_rx_queue_release(void *rx_queue)\n \t}\n }\n \n-uint16_t\n-atl_prep_pkts(void *tx_queue __rte_unused,\n-\t struct rte_mbuf **tx_pkts __rte_unused,\n-\t uint16_t nb_pkts __rte_unused)\n+static void\n+atl_tx_queue_release_mbufs(struct atl_tx_queue *txq)\n+{\n+\tint i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (txq->sw_ring != NULL) {\n+\t\tfor (i = 0; i < txq->nb_tx_desc; i++) {\n+\t\t\tif (txq->sw_ring[i].mbuf != NULL) {\n+\t\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n+\t\t\t\ttxq->sw_ring[i].mbuf = NULL;\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+int\n+atl_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (tx_queue_id < dev->data->nb_tx_queues) {\n+\t\thw_atl_b0_hw_ring_tx_start(hw, tx_queue_id);\n+\n+\t\trte_wmb();\n+\t\thw_atl_b0_hw_tx_ring_tail_update(hw, 0, tx_queue_id);\n+\t\tdev->data->tx_queue_state[tx_queue_id] =\n+\t\t\tRTE_ETH_QUEUE_STATE_STARTED;\n+\t} else {\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+atl_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n {\n+\tstruct aq_hw_s *hw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct atl_tx_queue *txq;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\n+\thw_atl_b0_hw_ring_tx_stop(hw, tx_queue_id);\n+\n+\tatl_tx_queue_release_mbufs(txq);\n+\tatl_reset_tx_queue(txq);\n+\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n \treturn 0;\n }\n \n void\n+atl_tx_queue_release(void *tx_queue)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (tx_queue != NULL) {\n+\t\tstruct atl_tx_queue *txq = (struct atl_tx_queue *)tx_queue;\n+\n+\t\tatl_tx_queue_release_mbufs(txq);\n+\t\trte_free(txq->sw_ring);\n+\t\trte_free(txq);\n+\t}\n+}\n+\n+void\n atl_free_queues(struct rte_eth_dev *dev)\n {\n \tunsigned int i;\n@@ -345,6 +587,12 @@ atl_free_queues(struct rte_eth_dev *dev)\n \t\tdev->data->rx_queues[i] = 0;\n \t}\n \tdev->data->nb_rx_queues = 0;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tatl_tx_queue_release(dev->data->tx_queues[i]);\n+\t\tdev->data->tx_queues[i] = 0;\n+\t}\n+\tdev->data->nb_tx_queues = 0;\n }\n \n int\n@@ -354,6 +602,15 @@ atl_start_queues(struct rte_eth_dev *dev)\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tif (atl_tx_queue_start(dev, i) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\"Port %d: Start Tx queue %d failed\",\n+\t\t\t\tdev->data->port_id, i);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\tif (atl_rx_queue_start(dev, i) != 0) {\n \t\t\tPMD_DRV_LOG(ERR,\n@@ -373,6 +630,15 @@ atl_stop_queues(struct rte_eth_dev *dev)\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\tif (atl_tx_queue_stop(dev, i) != 0) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\"Port %d: Stop Tx queue %d failed\",\n+\t\t\t\tdev->data->port_id, i);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n \tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n \t\tif (atl_rx_queue_stop(dev, i) != 0) {\n \t\t\tPMD_DRV_LOG(ERR,\n@@ -385,6 +651,47 @@ atl_stop_queues(struct rte_eth_dev *dev)\n \treturn 0;\n }\n \n+uint16_t\n+atl_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t uint16_t nb_pkts)\n+{\n+\tint i, ret;\n+\tuint64_t ol_flags;\n+\tstruct rte_mbuf *m;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tfor (i = 0; i < nb_pkts; i++) {\n+\t\tm = tx_pkts[i];\n+\t\tol_flags = m->ol_flags;\n+\n+\t\tif (m->nb_segs > AQ_HW_MAX_SEGS_SIZE) {\n+\t\t\trte_errno = -EINVAL;\n+\t\t\treturn i;\n+\t\t}\n+\n+\t\tif (ol_flags & ATL_TX_OFFLOAD_NOTSUP_MASK) {\n+\t\t\trte_errno = -ENOTSUP;\n+\t\t\treturn i;\n+\t\t}\n+\n+#ifdef RTE_LIBRTE_ETHDEV_DEBUG\n+\t\tret = rte_validate_tx_offload(m);\n+\t\tif (ret != 0) {\n+\t\t\trte_errno = ret;\n+\t\t\treturn i;\n+\t\t}\n+#endif\n+\t\tret = rte_net_intel_cksum_prepare(m);\n+\t\tif (ret != 0) {\n+\t\t\trte_errno = ret;\n+\t\t\treturn i;\n+\t\t}\n+\t}\n+\n+\treturn i;\n+}\n+\n static uint64_t\n atl_desc_to_offload_flags(struct atl_rx_queue *rxq,\n \t\t\t struct hw_atl_rxd_wb_s *rxd_wb)\n@@ -653,12 +960,233 @@ atl_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \treturn nb_rx;\n }\n \n+static void\n+atl_xmit_cleanup(struct atl_tx_queue *txq)\n+{\n+\tstruct atl_tx_entry *sw_ring;\n+\tstruct hw_atl_txd_s *txd;\n+\tint to_clean = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (txq != NULL) {\n+\t\tsw_ring = txq->sw_ring;\n+\t\tint head = txq->tx_head;\n+\t\tint cnt;\n+\t\tint i;\n+\n+\t\tfor (i = 0, cnt = head; ; i++) {\n+\t\t\ttxd = &txq->hw_ring[cnt];\n+\n+\t\t\tif (txd->dd)\n+\t\t\t\tto_clean++;\n+\n+\t\t\tcnt = (cnt + 1) % txq->nb_tx_desc;\n+\t\t\tif (cnt == txq->tx_tail)\n+\t\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (to_clean == 0)\n+\t\t\treturn;\n+\n+\t\twhile (to_clean) {\n+\t\t\ttxd = &txq->hw_ring[head];\n+\n+\t\t\tstruct atl_tx_entry *rx_entry = &sw_ring[head];\n+\n+\t\t\tif (rx_entry->mbuf) {\n+\t\t\t\trte_pktmbuf_free_seg(rx_entry->mbuf);\n+\t\t\t\trx_entry->mbuf = NULL;\n+\t\t\t}\n+\n+\t\t\tif (txd->dd)\n+\t\t\t\tto_clean--;\n+\n+\t\t\ttxd->buf_addr = 0;\n+\t\t\ttxd->flags = 0;\n+\n+\t\t\thead = (head + 1) % txq->nb_tx_desc;\n+\t\t\ttxq->tx_free++;\n+\t\t}\n+\n+\t\ttxq->tx_head = head;\n+\t}\n+}\n+\n+static int\n+atl_tso_setup(struct rte_mbuf *tx_pkt, union hw_atl_txc_s *txc)\n+{\n+\tuint32_t tx_cmd = 0;\n+\tuint64_t ol_flags = tx_pkt->ol_flags;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tif (ol_flags & PKT_TX_TCP_SEG) {\n+\t\tPMD_DRV_LOG(DEBUG, \"xmit TSO pkt\");\n+\n+\t\ttx_cmd |= tx_desc_cmd_lso | tx_desc_cmd_l4cs;\n+\n+\t\ttxc->cmd = 0x4;\n+\n+\t\tif (ol_flags & PKT_TX_IPV6)\n+\t\t\ttxc->cmd |= 0x2;\n+\n+\t\ttxc->l2_len = tx_pkt->l2_len;\n+\t\ttxc->l3_len = tx_pkt->l3_len;\n+\t\ttxc->l4_len = tx_pkt->l4_len;\n+\n+\t\ttxc->mss_len = tx_pkt->tso_segsz;\n+\t}\n+\n+\tif (ol_flags & PKT_TX_VLAN) {\n+\t\ttx_cmd |= tx_desc_cmd_vlan;\n+\t\ttxc->vlan_tag = tx_pkt->vlan_tci;\n+\t}\n+\n+\tif (tx_cmd) {\n+\t\ttxc->type = tx_desc_type_ctx;\n+\t\ttxc->idx = 0;\n+\t}\n+\n+\treturn tx_cmd;\n+}\n+\n+static inline void\n+atl_setup_csum_offload(struct rte_mbuf *mbuf, struct hw_atl_txd_s *txd,\n+\t\t uint32_t tx_cmd)\n+{\n+\ttxd->cmd |= tx_desc_cmd_fcs;\n+\ttxd->cmd |= (mbuf->ol_flags & PKT_TX_IP_CKSUM) ? tx_desc_cmd_ipv4 : 0;\n+\t/* L4 csum requested */\n+\ttxd->cmd |= (mbuf->ol_flags & PKT_TX_L4_MASK) ? tx_desc_cmd_l4cs : 0;\n+\ttxd->cmd |= tx_cmd;\n+}\n+\n+static inline void\n+atl_xmit_pkt(struct aq_hw_s *hw, struct atl_tx_queue *txq,\n+\t struct rte_mbuf *tx_pkt)\n+{\n+\tuint32_t pay_len = 0;\n+\tint tail = 0;\n+\tstruct atl_tx_entry *tx_entry;\n+\tuint64_t buf_dma_addr;\n+\tstruct rte_mbuf *m_seg;\n+\tunion hw_atl_txc_s *txc = NULL;\n+\tstruct hw_atl_txd_s *txd = NULL;\n+\tu32 tx_cmd = 0U;\n+\tint desc_count = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttail = txq->tx_tail;\n+\n+\ttxc = (union hw_atl_txc_s *)&txq->hw_ring[tail];\n+\n+\ttxc->flags1 = 0U;\n+\ttxc->flags2 = 0U;\n+\n+\ttx_cmd = atl_tso_setup(tx_pkt, txc);\n+\n+\tif (tx_cmd) {\n+\t\t/* We've consumed the first desc, adjust counters */\n+\t\ttail = (tail + 1) % txq->nb_tx_desc;\n+\t\ttxq->tx_tail = tail;\n+\t\ttxq->tx_free -= 1;\n+\n+\t\ttxd = &txq->hw_ring[tail];\n+\t\ttxd->flags = 0U;\n+\t} else {\n+\t\ttxd = (struct hw_atl_txd_s *)txc;\n+\t}\n+\n+\ttxd->ct_en = !!tx_cmd;\n+\n+\ttxd->type = tx_desc_type_desc;\n+\n+\tatl_setup_csum_offload(tx_pkt, txd, tx_cmd);\n+\n+\tif (tx_cmd)\n+\t\ttxd->ct_idx = 0;\n+\n+\tpay_len = tx_pkt->pkt_len;\n+\n+\ttxd->pay_len = pay_len;\n+\n+\tfor (m_seg = tx_pkt; m_seg; m_seg = m_seg->next) {\n+\t\tif (desc_count > 0) {\n+\t\t\ttxd = &txq->hw_ring[tail];\n+\t\t\ttxd->flags = 0U;\n+\t\t}\n+\n+\t\tbuf_dma_addr = rte_mbuf_data_iova(m_seg);\n+\t\ttxd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);\n+\n+\t\ttxd->type = tx_desc_type_desc;\n+\t\ttxd->len = m_seg->data_len;\n+\t\ttxd->pay_len = pay_len;\n+\n+\t\t/* Store mbuf for freeing later */\n+\t\ttx_entry = &txq->sw_ring[tail];\n+\n+\t\tif (tx_entry->mbuf)\n+\t\t\trte_pktmbuf_free_seg(tx_entry->mbuf);\n+\t\ttx_entry->mbuf = m_seg;\n+\n+\t\ttail = (tail + 1) % txq->nb_tx_desc;\n+\n+\t\tdesc_count++;\n+\t}\n+\n+\t// Last descriptor requires EOP and WB\n+\ttxd->eop = 1U;\n+\ttxd->cmd |= tx_desc_cmd_wb;\n+\n+\thw_atl_b0_hw_tx_ring_tail_update(hw, tail, txq->queue_id);\n+\n+\ttxq->tx_tail = tail;\n+\n+\ttxq->tx_free -= desc_count;\n+}\n \n uint16_t\n-atl_xmit_pkts(void *tx_queue __rte_unused,\n-\t struct rte_mbuf **tx_pkts __rte_unused,\n-\t uint16_t nb_pkts __rte_unused)\n+atl_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n {\n-\treturn 0;\n+\tstruct rte_eth_dev *dev = NULL;\n+\tstruct aq_hw_s *hw = NULL;\n+\tstruct atl_tx_queue *txq = tx_queue;\n+\tstruct rte_mbuf *tx_pkt;\n+\tuint16_t nb_tx;\n+\n+\tdev = &rte_eth_devices[txq->port_id];\n+\thw = ATL_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tPMD_TX_LOG(DEBUG,\n+\t\t\"port %d txq %d pkts: %d tx_free=%d tx_tail=%d tx_head=%d\",\n+\t\ttxq->port_id, txq->queue_id, nb_pkts, txq->tx_free,\n+\t\ttxq->tx_tail, txq->tx_head);\n+\n+\tfor (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {\n+\t\ttx_pkt = *tx_pkts++;\n+\n+\t\t/* Clean Tx queue if needed */\n+\t\tif (txq->tx_free < txq->tx_free_thresh)\n+\t\t\tatl_xmit_cleanup(txq);\n+\n+\t\t/* Check if we have enough free descriptors */\n+\t\tif (txq->tx_free < tx_pkt->nb_segs)\n+\t\t\tbreak;\n+\n+\t\t/* check mbuf is valid */\n+\t\tif ((tx_pkt->nb_segs == 0) ||\n+\t\t\t((tx_pkt->nb_segs > 1) && (tx_pkt->next == NULL)))\n+\t\t\tbreak;\n+\n+\t\t/* Send the packet */\n+\t\tatl_xmit_pkt(hw, txq, tx_pkt);\n+\t}\n+\n+\tPMD_TX_LOG(DEBUG, \"atl_xmit_pkts %d transmitted\", nb_tx);\n+\n+\treturn nb_tx;\n }\n \n", "prefixes": [ "v6", "10/22" ] }