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GET /api/patches/46335/?format=api
{ "id": 46335, "url": "http://patches.dpdk.org/api/patches/46335/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-15-git-send-email-anoob.joseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1539076076-19786-15-git-send-email-anoob.joseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1539076076-19786-15-git-send-email-anoob.joseph@caviumnetworks.com", "date": "2018-10-09T09:07:47", "name": "[v4,14/23] common/cpt: add microcode interface for decryption", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a7fb0105d049b30f7c8d8057c4afae4e5ec92201", "submitter": { "id": 893, "url": "http://patches.dpdk.org/api/people/893/?format=api", "name": "Anoob Joseph", "email": "anoob.joseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-15-git-send-email-anoob.joseph@caviumnetworks.com/mbox/", "series": [ { "id": 1770, "url": "http://patches.dpdk.org/api/series/1770/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1770", "date": "2018-10-09T09:07:33", "name": "Adding Cavium's OCTEON TX crypto PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/1770/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/46335/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/46335/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5BA1B1B12E;\n\tTue, 9 Oct 2018 11:09:39 +0200 (CEST)", "from NAM03-DM3-obe.outbound.protection.outlook.com\n\t(mail-dm3nam03on0046.outbound.protection.outlook.com [104.47.41.46])\n\tby dpdk.org (Postfix) with ESMTP id 556461B1F0\n\tfor <dev@dpdk.org>; Tue, 9 Oct 2018 11:09:37 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBN7PR07MB4897.namprd07.prod.outlook.com (2603:10b6:406:ef::26) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1207.28; Tue, 9 Oct 2018 09:09:32 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=t56chZDqepCyAhI2QTLFGjjgP9Jox1mCg4O/DUkTAXo=;\n\tb=HfPmi9hXysimnQzbYX4pYu9cA8pdn4BKxeO2s8DFyv1uJr1QW6zhtZbarUD2axgzcp88WWlc70P20Tam8VpmtQw4mqsxvOO3ctAMd1/pVxwKsJY9Ri4w8OeNAgTrJbYpgS3ekDMD8HWur/dCx4A/CZZx4SOHfTj1Ztfk6HGKer0=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tAnkur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>, dev@dpdk.org", "Date": "Tue, 9 Oct 2018 14:37:47 +0530", "Message-Id": "<1539076076-19786-15-git-send-email-anoob.joseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "References": "<1538744363-30340-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "PN1PR0101CA0004.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:c00:e::14) To BN7PR07MB4897.namprd07.prod.outlook.com\n\t(2603:10b6:406:ef::26)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "251b4b80-a75e-4ec7-8ef7-08d62dc6ef1b", "X-Microsoft-Antispam": "BCL:0; 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"vNg1484BmlFtgE8Y8VCPncK33wlR6EXXAYp9eGRYyeWxdqg9OxQVoMmOml5+NqBNVtfIw9v4pZfEA5mKpdTYQi+tk1jjnU8ir+jV8gOz0e9eISthoZAzAc5wQyBjYG5YliS79N9NzitQcy+MCfOmG9zMNjGrCvGVUmI/JMDbXweYCEGG1G1zLjyQvLRSEuaAcOhBqb9OCDCg0zGUUj3aaCRjQQkrMruvHiZlzqmoIc9MuVYrUF3EdbEMASFghkKepdl4DsjsirPUJWF3d3hf7Wh4pjh9H8+a9D6tydN/pLbgdVDVfEIfuPp8SOWT2KRKs4xdc6Tz21V6A2jIXKyGgVUuyPp4i+t0Vb5gmpIojbY=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Oct 2018 09:09:32.4996\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "251b4b80-a75e-4ec7-8ef7-08d62dc6ef1b", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN7PR07MB4897", "Subject": "[dpdk-dev] [PATCH v4 14/23] common/cpt: add microcode interface for\n\tdecryption", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\n\nAdding microcode interface additions for supporting decryption.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/common/cpt/cpt_ucode.h | 417 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 417 insertions(+)", "diff": "diff --git a/drivers/common/cpt/cpt_ucode.h b/drivers/common/cpt/cpt_ucode.h\nindex f5247d5..9d4d4c8 100644\n--- a/drivers/common/cpt/cpt_ucode.h\n+++ b/drivers/common/cpt/cpt_ucode.h\n@@ -844,6 +844,420 @@ cpt_enc_hmac_prep(uint32_t flags,\n \treturn 0;\n }\n \n+static __rte_always_inline int\n+cpt_dec_hmac_prep(uint32_t flags,\n+\t\t uint64_t d_offs,\n+\t\t uint64_t d_lens,\n+\t\t fc_params_t *fc_params,\n+\t\t void *op,\n+\t\t void **prep_req)\n+{\n+\tuint32_t iv_offset = 0, size;\n+\tint32_t inputlen, outputlen, enc_dlen, auth_dlen;\n+\tstruct cpt_ctx *cpt_ctx;\n+\tint32_t hash_type, mac_len, m_size;\n+\tuint8_t iv_len = 16;\n+\tstruct cpt_request_info *req;\n+\tbuf_ptr_t *meta_p, *aad_buf = NULL;\n+\tuint32_t encr_offset, auth_offset;\n+\tuint32_t encr_data_len, auth_data_len, aad_len = 0;\n+\tuint32_t passthrough_len = 0;\n+\tvoid *m_vaddr, *offset_vaddr;\n+\tuint64_t m_dma, offset_dma, ctx_dma;\n+\topcode_info_t opcode;\n+\tvq_cmd_word0_t vq_cmd_w0;\n+\tvq_cmd_word3_t vq_cmd_w3;\n+\tvoid *c_vaddr;\n+\tuint64_t c_dma;\n+\n+\tmeta_p = &fc_params->meta_buf;\n+\tm_vaddr = meta_p->vaddr;\n+\tm_dma = meta_p->dma_addr;\n+\tm_size = meta_p->size;\n+\n+\tencr_offset = ENCR_OFFSET(d_offs);\n+\tauth_offset = AUTH_OFFSET(d_offs);\n+\tencr_data_len = ENCR_DLEN(d_lens);\n+\tauth_data_len = AUTH_DLEN(d_lens);\n+\n+\tif (unlikely(flags & VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * We dont support both aad\n+\t\t * and auth data separately\n+\t\t */\n+\t\tauth_data_len = 0;\n+\t\tauth_offset = 0;\n+\t\taad_len = fc_params->aad_buf.size;\n+\t\taad_buf = &fc_params->aad_buf;\n+\t}\n+\n+\tcpt_ctx = fc_params->ctx_buf.vaddr;\n+\thash_type = cpt_ctx->hash_type;\n+\tmac_len = cpt_ctx->mac_len;\n+\n+\tif (hash_type == GMAC_TYPE)\n+\t\tencr_data_len = 0;\n+\n+\tif (unlikely(!(flags & VALID_IV_BUF))) {\n+\t\tiv_len = 0;\n+\t\tiv_offset = ENCR_IV_OFFSET(d_offs);\n+\t}\n+\n+\tif (unlikely(flags & VALID_AAD_BUF)) {\n+\t\t/*\n+\t\t * When AAD is given, data above encr_offset is pass through\n+\t\t * Since AAD is given as separate pointer and not as offset,\n+\t\t * this is a special case as we need to fragment input data\n+\t\t * into passthrough + encr_data and then insert AAD in between.\n+\t\t */\n+\t\tif (hash_type != GMAC_TYPE) {\n+\t\t\tpassthrough_len = encr_offset;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tencr_offset = passthrough_len + aad_len + iv_len;\n+\t\t\tauth_data_len = aad_len + encr_data_len;\n+\t\t} else {\n+\t\t\tpassthrough_len = 16 + aad_len;\n+\t\t\tauth_offset = passthrough_len + iv_len;\n+\t\t\tauth_data_len = aad_len;\n+\t\t}\n+\t} else {\n+\t\tencr_offset += iv_len;\n+\t\tauth_offset += iv_len;\n+\t}\n+\n+\t/*\n+\t * Save initial space that followed app data for completion code &\n+\t * alternate completion code to fall in same cache line as app data\n+\t */\n+\tm_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;\n+\tm_dma += COMPLETION_CODE_SIZE;\n+\tsize = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -\n+\t (uint8_t *)m_vaddr;\n+\tc_vaddr = (uint8_t *)m_vaddr + size;\n+\tc_dma = m_dma + size;\n+\tsize += sizeof(cpt_res_s_t);\n+\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* start cpt request info structure at 8 byte alignment */\n+\tsize = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -\n+\t\t(uint8_t *)m_vaddr;\n+\n+\treq = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);\n+\n+\tsize += sizeof(struct cpt_request_info);\n+\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\tm_dma += size;\n+\tm_size -= size;\n+\n+\t/* Decryption */\n+\topcode.s.major = CPT_MAJOR_OP_FC;\n+\topcode.s.minor = 1;\n+\n+\tenc_dlen = encr_offset + encr_data_len;\n+\tauth_dlen = auth_offset + auth_data_len;\n+\n+\tif (auth_dlen > enc_dlen) {\n+\t\tinputlen = auth_dlen + mac_len;\n+\t\toutputlen = auth_dlen;\n+\t} else {\n+\t\tinputlen = enc_dlen + mac_len;\n+\t\toutputlen = enc_dlen;\n+\t}\n+\n+\tif (hash_type == GMAC_TYPE)\n+\t\tencr_offset = inputlen;\n+\n+\tvq_cmd_w0.u64 = 0;\n+\tvq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);\n+\tvq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);\n+\n+\t/*\n+\t * In 83XX since we have a limitation of\n+\t * IV & Offset control word not part of instruction\n+\t * and need to be part of Data Buffer, we check if\n+\t * head room is there and then only do the Direct mode processing\n+\t */\n+\tif (likely((flags & SINGLE_BUF_INPLACE) &&\n+\t\t (flags & SINGLE_BUF_HEADTAILROOM))) {\n+\t\tvoid *dm_vaddr = fc_params->bufs[0].vaddr;\n+\t\tuint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;\n+\t\t/*\n+\t\t * This flag indicates that there is 24 bytes head room and\n+\t\t * 8 bytes tail room available, so that we get to do\n+\t\t * DIRECT MODE with limitation\n+\t\t */\n+\n+\t\toffset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;\n+\t\toffset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;\n+\t\treq->ist.ei1 = offset_dma;\n+\n+\t\t/* RPTR should just exclude offset control word */\n+\t\treq->ist.ei2 = dm_dma_addr - iv_len;\n+\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr +\n+\t\t\t\t\toutputlen - iv_len);\n+\t\t/* since this is decryption,\n+\t\t * don't touch the content of\n+\t\t * alternate ccode space as it contains\n+\t\t * hmac.\n+\t\t */\n+\n+\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);\n+\n+\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t\t\t OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\trte_cpu_to_be_64(((uint64_t)encr_offset << 16) |\n+\t\t\t\t((uint64_t)iv_offset << 8) |\n+\t\t\t\t((uint64_t)auth_offset));\n+\n+\t} else {\n+\t\tuint64_t dptr_dma, rptr_dma;\n+\t\tuint32_t g_size_bytes, s_size_bytes;\n+\t\tsg_comp_t *gather_comp;\n+\t\tsg_comp_t *scatter_comp;\n+\t\tuint8_t *in_buffer;\n+\t\tuint8_t i = 0;\n+\n+\t\t/* This falls under strict SG mode */\n+\t\toffset_vaddr = m_vaddr;\n+\t\toffset_dma = m_dma;\n+\t\tsize = OFF_CTRL_LEN + iv_len;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\topcode.s.major |= CPT_DMA_MODE;\n+\n+\t\tvq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);\n+\n+\t\tif (likely(iv_len)) {\n+\t\t\tuint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +\n+\t\t\t\t\t\t OFF_CTRL_LEN);\n+\t\t\tuint64_t *src = fc_params->iv_buf;\n+\t\t\tdest[0] = src[0];\n+\t\t\tdest[1] = src[1];\n+\t\t}\n+\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\trte_cpu_to_be_64(((uint64_t)encr_offset << 16) |\n+\t\t\t\t((uint64_t)iv_offset << 8) |\n+\t\t\t\t((uint64_t)auth_offset));\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\t\tdptr_dma = m_dma;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\t/* TODO Add error check if space will be sufficient */\n+\t\tgather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/*\n+\t\t * Input Gather List\n+\t\t */\n+\t\ti = 0;\n+\n+\t\t/* Offset control word that includes iv */\n+\t\ti = fill_sg_comp(gather_comp, i, offset_dma,\n+\t\t\t\t OFF_CTRL_LEN + iv_len);\n+\n+\t\t/* Add input data */\n+\t\tif (flags & VALID_MAC_BUF) {\n+\t\t\tsize = inputlen - iv_len - mac_len;\n+\t\t\tif (size) {\n+\t\t\t\t/* input data only */\n+\t\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\t\tgather_comp, i,\n+\t\t\t\t\t\t\tfc_params->bufs,\n+\t\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\tuint32_t aad_offset = aad_len ?\n+\t\t\t\t\t\tpassthrough_len : 0;\n+\n+\t\t\t\t\ti = fill_sg_comp_from_iov(gather_comp,\n+\t\t\t\t\t\t\ti,\n+\t\t\t\t\t\t\tfc_params->src_iov,\n+\t\t\t\t\t\t\t0, &size,\n+\t\t\t\t\t\t\taad_buf,\n+\t\t\t\t\t\t\taad_offset);\n+\t\t\t\t}\n+\t\t\t\tif (size)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\n+\t\t\t/* mac data */\n+\t\t\tif (mac_len) {\n+\t\t\t\ti = fill_sg_comp_from_buf(gather_comp, i,\n+\t\t\t\t\t\t\t &fc_params->mac_buf);\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* input data + mac */\n+\t\t\tsize = inputlen - iv_len;\n+\t\t\tif (size) {\n+\t\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t\ti = fill_sg_comp_from_buf_min(\n+\t\t\t\t\t\t\tgather_comp, i,\n+\t\t\t\t\t\t\tfc_params->bufs,\n+\t\t\t\t\t\t\t&size);\n+\t\t\t\t} else {\n+\t\t\t\t\tuint32_t aad_offset = aad_len ?\n+\t\t\t\t\t\tpassthrough_len : 0;\n+\n+\t\t\t\t\tif (!fc_params->src_iov)\n+\t\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\t\t\t\t\ti = fill_sg_comp_from_iov(\n+\t\t\t\t\t\t\tgather_comp, i,\n+\t\t\t\t\t\t\tfc_params->src_iov,\n+\t\t\t\t\t\t\t0, &size,\n+\t\t\t\t\t\t\taad_buf,\n+\t\t\t\t\t\t\taad_offset);\n+\t\t\t\t}\n+\n+\t\t\t\tif (size)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\t\tg_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\t/*\n+\t\t * Output Scatter List\n+\t\t */\n+\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);\n+\n+\t\t/* Add iv */\n+\t\tif (iv_len) {\n+\t\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t\t offset_dma + OFF_CTRL_LEN,\n+\t\t\t\t\t iv_len);\n+\t\t}\n+\n+\t\t/* Add output data */\n+\t\tsize = outputlen - iv_len;\n+\t\tif (size) {\n+\t\t\tif (unlikely(flags & SINGLE_BUF_INPLACE)) {\n+\t\t\t\t/* handle single buffer here */\n+\t\t\t\ti = fill_sg_comp_from_buf_min(scatter_comp, i,\n+\t\t\t\t\t\t\t fc_params->bufs,\n+\t\t\t\t\t\t\t &size);\n+\t\t\t} else {\n+\t\t\t\tuint32_t aad_offset = aad_len ?\n+\t\t\t\t\tpassthrough_len : 0;\n+\n+\t\t\t\tif (!fc_params->dst_iov)\n+\t\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\n+\t\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t\t\t fc_params->dst_iov, 0,\n+\t\t\t\t\t\t\t &size, aad_buf,\n+\t\t\t\t\t\t\t aad_offset);\n+\t\t\t}\n+\n+\t\t\tif (unlikely(size))\n+\t\t\t\treturn ERR_BAD_INPUT_ARG;\n+\t\t}\n+\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\t\ts_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len incase of SG mode */\n+\t\tvq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + size;\n+\t\tm_dma += size;\n+\t\tm_size -= size;\n+\n+\t\t/* cpt alternate completion address saved earlier */\n+\t\treq->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);\n+\t\t*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);\n+\t\trptr_dma = c_dma - 8;\n+\t\tsize += COMPLETION_CODE_SIZE;\n+\n+\t\treq->ist.ei1 = dptr_dma;\n+\t\treq->ist.ei2 = rptr_dma;\n+\t}\n+\n+\t/* First 16-bit swap then 64-bit swap */\n+\t/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions\n+\t * to eliminate all the swapping\n+\t */\n+\tvq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);\n+\n+\tctx_dma = fc_params->ctx_buf.dma_addr +\n+\t\toffsetof(struct cpt_ctx, fctx);\n+\t/* vq command w3 */\n+\tvq_cmd_w3.u64 = 0;\n+\tvq_cmd_w3.s.grp = 0;\n+\tvq_cmd_w3.s.cptr = ctx_dma;\n+\n+\t/* 16 byte aligned cpt res address */\n+\treq->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);\n+\t*req->completion_addr = COMPLETION_CODE_INIT;\n+\treq->comp_baddr = c_dma;\n+\n+\t/* Fill microcode part of instruction */\n+\treq->ist.ei0 = vq_cmd_w0.u64;\n+\treq->ist.ei3 = vq_cmd_w3.u64;\n+\n+\treq->op = op;\n+\n+\t*prep_req = req;\n+\treturn 0;\n+}\n+\n+static __rte_always_inline void *\n+cpt_fc_dec_hmac_prep(uint32_t flags,\n+\t\t uint64_t d_offs,\n+\t\t uint64_t d_lens,\n+\t\t fc_params_t *fc_params,\n+\t\t void *op, int *ret_val)\n+{\n+\tstruct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;\n+\tuint8_t fc_type;\n+\tvoid *prep_req = NULL;\n+\tint ret;\n+\n+\tfc_type = ctx->fc_type;\n+\n+\tif (likely(fc_type == FC_GEN)) {\n+\t\tret = cpt_dec_hmac_prep(flags, d_offs, d_lens,\n+\t\t\t\t\tfc_params, op, &prep_req);\n+\t} else {\n+\t\t/*\n+\t\t * For AUTH_ONLY case,\n+\t\t * MC only supports digest generation and verification\n+\t\t * should be done in software by memcmp()\n+\t\t */\n+\n+\t\tret = ERR_EIO;\n+\t}\n+\n+\tif (unlikely(!prep_req))\n+\t\t*ret_val = ret;\n+\treturn prep_req;\n+}\n+\n static __rte_always_inline void *__hot\n cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,\n \t\t fc_params_t *fc_params, void *op, int *ret_val)\n@@ -1693,6 +2107,9 @@ fill_fc_params(struct rte_crypto_op *cop,\n \tif (cpt_op & CPT_OP_ENCODE)\n \t\tprep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,\n \t\t\t\t\t\t&fc_params, op, op_ret);\n+\telse\n+\t\tprep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,\n+\t\t\t\t\t\t&fc_params, op, op_ret);\n \n \tif (unlikely(!prep_req))\n \t\tfree_op_meta(mdata, cpt_m_info->cptvf_meta_pool);\n", "prefixes": [ "v4", "14/23" ] }