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GET /api/patches/46324/?format=api
{ "id": 46324, "url": "http://patches.dpdk.org/api/patches/46324/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-4-git-send-email-anoob.joseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1539076076-19786-4-git-send-email-anoob.joseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1539076076-19786-4-git-send-email-anoob.joseph@caviumnetworks.com", "date": "2018-10-09T09:07:36", "name": "[v4,03/23] crypto/octeontx: add hardware register access for misc poll", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "1d80bb5220fce09ba44cd2861219ca4930d3085e", "submitter": { "id": 893, "url": "http://patches.dpdk.org/api/people/893/?format=api", "name": "Anoob Joseph", "email": "anoob.joseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-4-git-send-email-anoob.joseph@caviumnetworks.com/mbox/", "series": [ { "id": 1770, "url": "http://patches.dpdk.org/api/series/1770/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1770", "date": "2018-10-09T09:07:33", "name": "Adding Cavium's OCTEON TX crypto PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/1770/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/46324/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/46324/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 586DB1B139;\n\tTue, 9 Oct 2018 11:08:53 +0200 (CEST)", "from NAM05-CO1-obe.outbound.protection.outlook.com\n\t(mail-eopbgr720049.outbound.protection.outlook.com [40.107.72.49])\n\tby dpdk.org (Postfix) with ESMTP id 845471B124\n\tfor <dev@dpdk.org>; Tue, 9 Oct 2018 11:08:51 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBN7PR07MB4897.namprd07.prod.outlook.com (2603:10b6:406:ef::26) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1207.28; Tue, 9 Oct 2018 09:08:45 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=85z9XqSF8Is+Xeppdjmtxa2ojZpWKzZ6g/d8VQgJ/OM=;\n\tb=efli5hVjxG8J9N0FiHEGBcinUDBapGheC1+38LhipJfgO7EMDy9T+f+140MtDE/S1tI3LpwS90OgjjemKWtitma7a/WUlRtfBwdbrzLspFkrfFa9Bh2ycpxN5qEZrvsGIYVn90G2lf6SlF7+j9wMzwGZrLqjVz9Ns4V3WkuO3p8=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>, dev@dpdk.org", "Date": "Tue, 9 Oct 2018 14:37:36 +0530", "Message-Id": "<1539076076-19786-4-git-send-email-anoob.joseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "References": "<1538744363-30340-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "PN1PR0101CA0004.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:c00:e::14) To BN7PR07MB4897.namprd07.prod.outlook.com\n\t(2603:10b6:406:ef::26)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "bbbaa216-a713-4fd6-d093-08d62dc6d37d", "X-Microsoft-Antispam": "BCL:0; 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"74sS0rs99Pyax/yKTP54xUQMKc3dD0vZ/WupJSUm56qHBL1Ynm4kzADNZsMyVgCpMW0vK8AHvCtbFpNFtYvpsKjX5d1q/M9lrZqnsspNQWiWXIMspNVlCexy+66FSDqyVUrUMmkQiplCqECpbif1raZxo8Wpj2Q1dYz5CWpOsP2lCD85VAocKykXojIAfryXSNZcfXVb90TDLBi/EY3Y5M8S+1Ua9wi9mybrAvBkPk9ZlDW7zuimLqq4hxCz2kA/VJC406IsNPMEfnBgc7yf0SZpKTZyurqYEph0trKbcisG6Ymq1iHpApQespi8SHxxCde9PFojc7LkOJBfrrQFSLHctClG+PwxcxX8UwZPpO0=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Oct 2018 09:08:45.8651\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "bbbaa216-a713-4fd6-d093-08d62dc6d37d", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN7PR07MB4897", "Subject": "[dpdk-dev] [PATCH v4 03/23] crypto/octeontx: add hardware register\n\taccess for misc poll", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\n\nAdding hardware register accesses required for misc poll\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/common/cpt/cpt_hw_types.h | 519 ++++++++++++++++++++++\n drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 192 +++++++-\n drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 11 +\n 3 files changed, 721 insertions(+), 1 deletion(-)\n create mode 100644 drivers/common/cpt/cpt_hw_types.h", "diff": "diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h\nnew file mode 100644\nindex 0000000..0a98621\n--- /dev/null\n+++ b/drivers/common/cpt/cpt_hw_types.h\n@@ -0,0 +1,519 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _CPT_HW_TYPES_H_\n+#define _CPT_HW_TYPES_H_\n+\n+#include <rte_byteorder.h>\n+\n+/*\n+ * This file defines HRM specific structs.\n+ *\n+ */\n+\n+#define CPT_VF_INTR_MBOX_MASK (1<<0)\n+#define CPT_VF_INTR_DOVF_MASK (1<<1)\n+#define CPT_VF_INTR_IRDE_MASK (1<<2)\n+#define CPT_VF_INTR_NWRP_MASK (1<<3)\n+#define CPT_VF_INTR_SWERR_MASK (1<<4)\n+#define CPT_VF_INTR_HWERR_MASK (1<<5)\n+#define CPT_VF_INTR_FAULT_MASK (1<<6)\n+\n+/*\n+ * CPT_INST_S software command definitions\n+ * Words EI (0-3)\n+ */\n+typedef union {\n+\tuint64_t u64;\n+\tstruct {\n+\t\tuint16_t opcode;\n+\t\tuint16_t param1;\n+\t\tuint16_t param2;\n+\t\tuint16_t dlen;\n+\t} s;\n+} vq_cmd_word0_t;\n+\n+typedef union {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t grp\t: 3;\n+\t\tuint64_t cptr\t: 61;\n+#else\n+\t\tuint64_t cptr\t: 61;\n+\t\tuint64_t grp\t: 3;\n+#endif\n+\t} s;\n+} vq_cmd_word3_t;\n+\n+typedef struct cpt_vq_command {\n+\tvq_cmd_word0_t cmd;\n+\tuint64_t dptr;\n+\tuint64_t rptr;\n+\tvq_cmd_word3_t cptr;\n+} cpt_vq_cmd_t;\n+\n+/**\n+ * Structure cpt_inst_s\n+ *\n+ * CPT Instruction Structure\n+ * This structure specifies the instruction layout.\n+ * Instructions are stored in memory as little-endian unless\n+ * CPT()_PF_Q()_CTL[INST_BE] is set.\n+ */\n+typedef union cpt_inst_s {\n+\tuint64_t u[8];\n+\tstruct cpt_inst_s_8s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_17_63 : 47;\n+\t\t/* [ 16: 16] Done interrupt.\n+\t\t * 0 = No interrupts related to this instruction.\n+\t\t * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]\n+\t\t * will be incremented, and based on the rules described\n+\t\t * there an interrupt may occur.\n+\t\t */\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t reserved_0_15 : 16;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t reserved_0_15 : 16;\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t reserved_17_63 : 47;\n+#endif /* Word 0 - End */\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */\n+\t\t/* [127: 64] Result IOVA.\n+\t\t * If nonzero, specifies where to write CPT_RES_S.\n+\t\t * If zero, no result structure will be written.\n+\t\t * Address must be 16-byte aligned.\n+\t\t *\n+\t\t * Bits <63:49> are ignored by hardware; software should\n+\t\t * use a sign-extended bit <48> for forward compatibility.\n+\t\t */\n+\t\tuint64_t res_addr : 64;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t res_addr : 64;\n+#endif /* Word 1 - End */\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */\n+\t\tuint64_t reserved_172_191 : 20;\n+\t\t/* [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to\n+\t\t * use when CPT submits work to SSO.\n+\t\t * For the SSO to not discard the add-work request, FPA_PF_MAP()\n+\t\t * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.\n+\t\t */\n+\t\tuint64_t grp : 10;\n+\t\t/* [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use\n+\t\t * when CPT submits work to SSO.\n+\t\t */\n+\t\tuint64_t tt : 2;\n+\t\t/* [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when\n+\t\t * CPT submits work to SSO.\n+\t\t */\n+\t\tuint64_t tag : 32;\n+#else /* Word 2 - Little Endian */\n+\t\tuint64_t tag : 32;\n+\t\tuint64_t tt : 2;\n+\t\tuint64_t grp : 10;\n+\t\tuint64_t reserved_172_191 : 20;\n+#endif /* Word 2 - End */\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */\n+\t\t/** [255:192] If [WQ_PTR] is nonzero, it is a pointer to a\n+\t\t * work-queue entry that CPT submits work to SSO after all\n+\t\t * context, output data, and result write operations are\n+\t\t * visible to other CNXXXX units and the cores.\n+\t\t * Bits <2:0> must be zero.\n+\t\t * Bits <63:49> are ignored by hardware; software should use a\n+\t\t * sign-extended bit <48> for forward compatibility.\n+\t\t * Internal:Bits <63:49>, <2:0> are ignored by hardware,\n+\t\t * treated as always 0x0.\n+\t\t **/\n+\t\tuint64_t wq_ptr : 64;\n+#else /* Word 3 - Little Endian */\n+\t\tuint64_t wq_ptr : 64;\n+#endif /* Word 3 - End */\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 4 - Big Endian */\n+\t\tunion {\n+\t\t\t/** [319:256] Engine instruction word 0. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tuint64_t ei0 : 64;\n+\t\t\tvq_cmd_word0_t vq_cmd_w0;\n+\t\t};\n+#else /* Word 4 - Little Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei0 : 64;\n+\t\t\tvq_cmd_word0_t vq_cmd_w0;\n+\t\t};\n+#endif /* Word 4 - End */\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 5 - Big Endian */\n+\t\tunion {\n+\t\t\t/** [383:320] Engine instruction word 1. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tuint64_t ei1 : 64;\n+\t\t\tuint64_t dptr;\n+\t\t};\n+#else /* Word 5 - Little Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei1 : 64;\n+\t\t\tuint64_t dptr;\n+\t\t};\n+#endif /* Word 5 - End */\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 6 - Big Endian */\n+\t\tunion {\n+\t\t\t/** [447:384] Engine instruction word 2. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tuint64_t ei2 : 64;\n+\t\t\tuint64_t rptr;\n+\t\t};\n+#else /* Word 6 - Little Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei2 : 64;\n+\t\t\tuint64_t rptr;\n+\t\t};\n+#endif /* Word 6 - End */\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 7 - Big Endian */\n+\t\tunion {\n+\t\t\t/** [511:448] Engine instruction word 3. Passed to the\n+\t\t\t * AE/SE.\n+\t\t\t **/\n+\t\t\tuint64_t ei3 : 64;\n+\t\t\tvq_cmd_word3_t vq_cmd_w3;\n+\t\t};\n+#else /* Word 7 - Little Endian */\n+\t\tunion {\n+\t\t\tuint64_t ei3 : 64;\n+\t\t\tvq_cmd_word3_t vq_cmd_w3;\n+\t\t};\n+#endif /* Word 7 - End */\n+\t} s8x;\n+} cpt_inst_s_t;\n+\n+/**\n+ * Structure cpt_res_s\n+ *\n+ * CPT Result Structure\n+ * The CPT coprocessor writes the result structure after it completes a\n+ * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each\n+ * instruction completion produces exactly one result structure.\n+ *\n+ * This structure is stored in memory as little-endian unless\n+ * CPT()_PF_Q()_CTL[INST_BE] is set.\n+ */\n+typedef union cpt_res_s {\n+\tuint64_t u[2];\n+\tstruct cpt_res_s_8s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_17_63 : 47;\n+\t\t/** [ 16: 16] Done interrupt. This bit is copied from the\n+\t\t * corresponding instruction's CPT_INST_S[DONEINT].\n+\t\t **/\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t reserved_8_15 : 8;\n+\t\t/** [ 7: 0] Indicates completion/error status of the CPT\n+\t\t * coprocessor for the associated instruction, as enumerated by\n+\t\t * CPT_COMP_E. Core software may write the memory location\n+\t\t * containing [COMPCODE] to 0x0 before ringing the doorbell, and\n+\t\t * then poll for completion by checking for a nonzero value.\n+\t\t *\n+\t\t * Once the core observes a nonzero [COMPCODE] value in this\n+\t\t * case, the CPT coprocessor will have also completed L2/DRAM\n+\t\t * write operations.\n+\t\t **/\n+\t\tuint64_t compcode : 8;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t compcode : 8;\n+\t\tuint64_t reserved_8_15 : 8;\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t reserved_17_63 : 47;\n+#endif /* Word 0 - End */\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */\n+\t\tuint64_t reserved_64_127 : 64;\n+#else /* Word 1 - Little Endian */\n+\t\tuint64_t reserved_64_127 : 64;\n+#endif /* Word 1 - End */\n+\t} s8x;\n+} cpt_res_s_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_ctl\n+ *\n+ * CPT VF Queue Control Registers\n+ * This register configures queues. This register should be changed (other than\n+ * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_ctl_s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_1_63 : 63;\n+\t\t/** [ 0: 0](R/W/H) Enables the logical instruction queue.\n+\t\t * See also CPT()_PF_Q()_CTL[CONT_ERR] and\n+\t\t * CPT()_VQ()_INPROG[INFLIGHT].\n+\t\t * 1 = Queue is enabled.\n+\t\t * 0 = Queue is disabled.\n+\t\t **/\n+\t\tuint64_t ena : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t ena : 1;\n+\t\tuint64_t reserved_1_63 : 63;\n+#endif /* Word 0 - End */\n+\t} s;\n+} cptx_vqx_ctl_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_done\n+ *\n+ * CPT Queue Done Count Registers\n+ * These registers contain the per-queue instruction done count.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_done_s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_20_63 : 44;\n+\t\t/** [ 19: 0](R/W/H) Done count. When CPT_INST_S[DONEINT] set\n+\t\t * and that instruction completes,CPT()_VQ()_DONE[DONE] is\n+\t\t * incremented when the instruction finishes. Write to this\n+\t\t * field are for diagnostic use only; instead software writes\n+\t\t * CPT()_VQ()_DONE_ACK with the number of decrements for this\n+\t\t * field.\n+\t\t *\n+\t\t * Interrupts are sent as follows:\n+\t\t *\n+\t\t * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,\n+\t\t * the interrupt coalescing timer is held to zero, and an\n+\t\t * interrupt is not sent.\n+\t\t *\n+\t\t * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt\n+\t\t * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE\n+\t\t * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()\n+\t\t * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough\n+\t\t * results have arrived, then the interrupt is sent. Otherwise,\n+\t\t * it is not sent due to coalescing.\n+\t\t *\n+\t\t * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is\n+\t\t * written but this is not typical), the interrupt coalescing\n+\t\t * timer restarts. Note after decrementing this interrupt\n+\t\t * equation is recomputed, for example if CPT()_VQ()_DONE[DONE]\n+\t\t * >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is\n+\t\t * zero, the interrupt will be resent immediately. (This covers\n+\t\t * the race case between software acknowledging an interrupt and\n+\t\t * a result returning.)\n+\t\t *\n+\t\t * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not\n+\t\t * sent, but the counting described above still occurs.\n+\t\t *\n+\t\t * Since CPT instructions complete out-of-order, if software is\n+\t\t * using completion interrupts the suggested scheme is to\n+\t\t * request a DONEINT on each request, and when an interrupt\n+\t\t * arrives perform a \"greedy\" scan for completions; even if a\n+\t\t * later command is acknowledged first this will not result in\n+\t\t * missing a completion.\n+\t\t *\n+\t\t * Software is responsible for making sure [DONE] does not\n+\t\t * overflow; for example by insuring there are not more than\n+\t\t * 2^20-1 instructions in flight that may request interrupts.\n+\t\t **/\n+\t\tuint64_t done : 20;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t done : 20;\n+\t\tuint64_t reserved_20_63 : 44;\n+#endif /* Word 0 - End */\n+\t} s;\n+} cptx_vqx_done_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_done_ack\n+ *\n+ * CPT Queue Done Count Ack Registers\n+ * This register is written by software to acknowledge interrupts.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_done_ack_s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_20_63 : 44;\n+\t\t/** [ 19: 0](R/W/H) Number of decrements to CPT()_VQ()_DONE\n+\t\t * [DONE]. Reads CPT()_VQ()_DONE[DONE].\n+\t\t *\n+\t\t * Written by software to acknowledge interrupts. If CPT()_VQ()_\n+\t\t * DONE[DONE] is still nonzero the interrupt will be re-sent if\n+\t\t * the conditions described in CPT()_VQ()_DONE[DONE] are\n+\t\t * satisfied.\n+\t\t **/\n+\t\tuint64_t done_ack : 20;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t done_ack : 20;\n+\t\tuint64_t reserved_20_63 : 44;\n+#endif /* Word 0 - End */\n+\t} s;\n+} cptx_vqx_done_ack_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_done_wait\n+ *\n+ * CPT Queue Done Interrupt Coalescing Wait Registers\n+ * Specifies the per queue interrupt coalescing settings.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_done_wait_s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_48_63 : 16;\n+\t\t/** [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =\n+\t\t * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When\n+\t\t * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing\n+\t\t * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is\n+\t\t * disabled.\n+\t\t **/\n+\t\tuint64_t time_wait : 16;\n+\t\tuint64_t reserved_20_31 : 12;\n+\t\t/** [ 19: 0](R/W) Number of messages hold-off. When\n+\t\t * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing\n+\t\t * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as\n+\t\t * 0x1.\n+\t\t **/\n+\t\tuint64_t num_wait : 20;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t num_wait : 20;\n+\t\tuint64_t reserved_20_31 : 12;\n+\t\tuint64_t time_wait : 16;\n+\t\tuint64_t reserved_48_63 : 16;\n+#endif /* Word 0 - End */\n+\t} s;\n+} cptx_vqx_done_wait_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_doorbell\n+ *\n+ * CPT Queue Doorbell Registers\n+ * Doorbells for the CPT instruction queues.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_doorbell_s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_20_63 : 44;\n+\t\tuint64_t dbell_cnt : 20;\n+\t\t/** [ 19: 0](R/W/H) Number of instruction queue 64-bit words\n+\t\t * to add to the CPT instruction doorbell count. Readback value\n+\t\t * is the the current number of pending doorbell requests.\n+\t\t *\n+\t\t * If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.\n+\t\t *\n+\t\t * To reset the count back to zero, write one to clear\n+\t\t * CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value\n+\t\t * of 2^20 minus the read [DBELL_CNT], then write one to\n+\t\t * CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and\n+\t\t * CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].\n+\t\t *\n+\t\t * Must be a multiple of 8. All CPT instructions are 8 words\n+\t\t * and require a doorbell count of multiple of 8.\n+\t\t **/\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t dbell_cnt : 20;\n+\t\tuint64_t reserved_20_63 : 44;\n+#endif /* Word 0 - End */\n+\t} s;\n+} cptx_vqx_doorbell_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_inprog\n+ *\n+ * CPT Queue In Progress Count Registers\n+ * These registers contain the per-queue instruction in flight registers.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_inprog_s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_8_63 : 56;\n+\t\t/** [ 7: 0](RO/H) Inflight count. Counts the number of\n+\t\t * instructions for the VF for which CPT is fetching, executing\n+\t\t * or responding to instructions. However this does not include\n+\t\t * any interrupts that are awaiting software handling\n+\t\t * (CPT()_VQ()_DONE[DONE] != 0x0).\n+\t\t *\n+\t\t * A queue may not be reconfigured until:\n+\t\t * 1. CPT()_VQ()_CTL[ENA] is cleared by software.\n+\t\t * 2. [INFLIGHT] is polled until equals to zero.\n+\t\t **/\n+\t\tuint64_t inflight : 8;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t inflight : 8;\n+\t\tuint64_t reserved_8_63 : 56;\n+#endif /* Word 0 - End */\n+\t} s;\n+} cptx_vqx_inprog_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_misc_int\n+ *\n+ * CPT Queue Misc Interrupt Register\n+ * These registers contain the per-queue miscellaneous interrupts.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_misc_int_s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_7_63 : 57;\n+\t\t/** [ 6: 6](R/W1C/H) Translation fault detected. */\n+\t\tuint64_t fault\t\t : 1;\n+\t\t/** [ 5: 5](R/W1C/H) Hardware error from engines. */\n+\t\tuint64_t hwerr\t\t : 1;\n+\t\t/** [ 4: 4](R/W1C/H) Software error from engines. */\n+\t\tuint64_t swerr : 1;\n+\t\t/** [ 3: 3](R/W1C/H) NCB result write response error. */\n+\t\tuint64_t nwrp : 1;\n+\t\t/** [ 2: 2](R/W1C/H) Instruction NCB read response error. */\n+\t\tuint64_t irde : 1;\n+\t\t/** [ 1: 1](R/W1C/H) Doorbell overflow. */\n+\t\tuint64_t dovf : 1;\n+\t\t/** [ 0: 0](R/W1C/H) PF to VF mailbox interrupt. Set when\n+\t\t * CPT()_VF()_PF_MBOX(0) is written.\n+\t\t **/\n+\t\tuint64_t mbox : 1;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t mbox : 1;\n+\t\tuint64_t dovf : 1;\n+\t\tuint64_t irde : 1;\n+\t\tuint64_t nwrp : 1;\n+\t\tuint64_t swerr : 1;\n+\t\tuint64_t hwerr\t\t : 1;\n+\t\tuint64_t fault\t\t : 1;\n+\t\tuint64_t reserved_5_63 : 59;\n+#endif /* Word 0 - End */\n+\t} s;\n+} cptx_vqx_misc_int_t;\n+\n+/**\n+ * Register (NCB) cpt#_vq#_saddr\n+ *\n+ * CPT Queue Starting Buffer Address Registers\n+ * These registers set the instruction buffer starting address.\n+ */\n+typedef union {\n+\tuint64_t u;\n+\tstruct cptx_vqx_saddr_s\t{\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t reserved_49_63 : 15;\n+\t\t/** [ 48: 6](R/W/H) Instruction buffer IOVA <48:6>\n+\t\t * (64-byte aligned). When written, it is the initial buffer\n+\t\t * starting address; when read, it is the next read pointer to\n+\t\t * be requested from L2C. The PTR field is overwritten with the\n+\t\t * next pointer each time that the command buffer segment is\n+\t\t * exhausted. New commands will then be read from the newly\n+\t\t * specified command buffer pointer.\n+\t\t **/\n+\t\tuint64_t ptr : 43;\n+\t\tuint64_t reserved_0_5 : 6;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t reserved_0_5 : 6;\n+\t\tuint64_t ptr : 43;\n+\t\tuint64_t reserved_49_63 : 15;\n+#endif /* Word 0 - End */\n+\t} s;\n+} cptx_vqx_saddr_t;\n+\n+#endif /*_CPT_HW_TYPES_H_ */\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\nindex 99fe3cf..369d62b 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n@@ -3,11 +3,19 @@\n */\n #include <string.h>\n \n+#include <rte_branch_prediction.h>\n #include <rte_common.h>\n \n #include \"otx_cryptodev_hw_access.h\"\n \n #include \"cpt_pmd_logs.h\"\n+#include \"cpt_hw_types.h\"\n+\n+/*\n+ * VF HAL functions\n+ * Access its own BAR0/4 registers by passing VF number as 0.\n+ * OS/PCI maps them accordingly.\n+ */\n \n static int\n otx_cpt_vf_init(struct cpt_vf *cptvf)\n@@ -19,10 +27,192 @@ otx_cpt_vf_init(struct cpt_vf *cptvf)\n \treturn ret;\n }\n \n+/*\n+ * Read Interrupt status of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static uint64_t\n+otx_cpt_read_vf_misc_intr_status(struct cpt_vf *cptvf)\n+{\n+\treturn CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf), CPTX_VQX_MISC_INT(0, 0));\n+}\n+\n+/*\n+ * Clear mailbox interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_mbox_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.mbox = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear instruction NCB read error interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_irde_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.irde = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear NCB result write response error interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_nwrp_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.nwrp = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear swerr interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_swerr_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.swerr = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear hwerr interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_hwerr_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.hwerr = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear translation fault interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_fault_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\tCPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.fault = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\tCPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n+/*\n+ * Clear doorbell overflow interrupt of the VF\n+ *\n+ * @param cptvf\tcptvf structure\n+ */\n+static void\n+otx_cpt_clear_dovf_intr(struct cpt_vf *cptvf)\n+{\n+\tcptx_vqx_misc_int_t vqx_misc_int;\n+\n+\tvqx_misc_int.u = CPT_READ_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t\t\t CPTX_VQX_MISC_INT(0, 0));\n+\t/* W1C for the VF */\n+\tvqx_misc_int.s.dovf = 1;\n+\tCPT_WRITE_CSR(CPT_CSR_REG_BASE(cptvf),\n+\t\t CPTX_VQX_MISC_INT(0, 0), vqx_misc_int.u);\n+}\n+\n void\n otx_cpt_poll_misc(struct cpt_vf *cptvf)\n {\n-\tRTE_SET_USED(cptvf);\n+\tuint64_t intr;\n+\n+\tintr = otx_cpt_read_vf_misc_intr_status(cptvf);\n+\n+\tif (!intr)\n+\t\treturn;\n+\n+\t/* Check for MISC interrupt types */\n+\tif (likely(intr & CPT_VF_INTR_MBOX_MASK)) {\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Mailbox interrupt 0x%lx on CPT VF %d\",\n+\t\t\tcptvf->dev_name, (unsigned int long)intr, cptvf->vfid);\n+\t\totx_cpt_clear_mbox_intr(cptvf);\n+\t} else if (unlikely(intr & CPT_VF_INTR_IRDE_MASK)) {\n+\t\totx_cpt_clear_irde_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Instruction NCB read error interrupt \"\n+\t\t\t\t\"0x%lx on CPT VF %d\", cptvf->dev_name,\n+\t\t\t\t(unsigned int long)intr, cptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_NWRP_MASK)) {\n+\t\totx_cpt_clear_nwrp_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: NCB response write error interrupt 0x%lx\"\n+\t\t\t\t\" on CPT VF %d\", cptvf->dev_name,\n+\t\t\t\t(unsigned int long)intr, cptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_SWERR_MASK)) {\n+\t\totx_cpt_clear_swerr_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Software error interrupt 0x%lx on CPT VF \"\n+\t\t\t\t\"%d\", cptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_HWERR_MASK)) {\n+\t\totx_cpt_clear_hwerr_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Hardware error interrupt 0x%lx on CPT VF \"\n+\t\t\t\t\"%d\", cptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_FAULT_MASK)) {\n+\t\totx_cpt_clear_fault_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Translation fault interrupt 0x%lx on CPT VF \"\n+\t\t\t\t\"%d\", cptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n+\t} else if (unlikely(intr & CPT_VF_INTR_DOVF_MASK)) {\n+\t\totx_cpt_clear_dovf_intr(cptvf);\n+\t\tCPT_LOG_DP_DEBUG(\"%s: Doorbell overflow interrupt 0x%lx on CPT VF \"\n+\t\t\t\t\"%d\", cptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n+\t} else\n+\t\tCPT_LOG_DP_ERR(\"%s: Unhandled interrupt 0x%lx in CPT VF %d\",\n+\t\t\t\tcptvf->dev_name, (unsigned int long)intr,\n+\t\t\t\tcptvf->vfid);\n }\n \n int\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\nindex 1e1877c..73473ed 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n@@ -7,6 +7,7 @@\n \n #include <stdbool.h>\n \n+#include <rte_io.h>\n #include <rte_memory.h>\n \n #include \"cpt_common.h\"\n@@ -16,6 +17,16 @@\n /* Default command queue length */\n #define DEFAULT_CMD_QCHUNKS\t\t2\n \n+#define CPT_CSR_REG_BASE(cpt)\t\t((cpt)->reg_base)\n+\n+/* Read hw register */\n+#define CPT_READ_CSR(__hw_addr, __offset) \\\n+\trte_read64_relaxed((uint8_t *)__hw_addr + __offset)\n+\n+/* Write hw register */\n+#define CPT_WRITE_CSR(__hw_addr, __offset, __val) \\\n+\trte_write64_relaxed((__val), ((uint8_t *)__hw_addr + __offset))\n+\n /* cpt instance */\n struct cpt_instance {\n \tuint32_t queue_id;\n", "prefixes": [ "v4", "03/23" ] }