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GET /api/patches/46323/?format=api
{ "id": 46323, "url": "http://patches.dpdk.org/api/patches/46323/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-3-git-send-email-anoob.joseph@caviumnetworks.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1539076076-19786-3-git-send-email-anoob.joseph@caviumnetworks.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1539076076-19786-3-git-send-email-anoob.joseph@caviumnetworks.com", "date": "2018-10-09T09:07:35", "name": "[v4,02/23] crypto/octeontx: add hardware init routine", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d022994adf19784c6b60d61dd85864594dd884b4", "submitter": { "id": 893, "url": "http://patches.dpdk.org/api/people/893/?format=api", "name": "Anoob Joseph", "email": "anoob.joseph@caviumnetworks.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1539076076-19786-3-git-send-email-anoob.joseph@caviumnetworks.com/mbox/", "series": [ { "id": 1770, "url": "http://patches.dpdk.org/api/series/1770/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1770", "date": "2018-10-09T09:07:33", "name": "Adding Cavium's OCTEON TX crypto PMD", "version": 4, "mbox": "http://patches.dpdk.org/series/1770/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/46323/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/46323/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 838E11B12E;\n\tTue, 9 Oct 2018 11:08:48 +0200 (CEST)", "from NAM03-DM3-obe.outbound.protection.outlook.com\n\t(mail-dm3nam03on0041.outbound.protection.outlook.com [104.47.41.41])\n\tby dpdk.org (Postfix) with ESMTP id BA9D11B12E\n\tfor <dev@dpdk.org>; Tue, 9 Oct 2018 11:08:46 +0200 (CEST)", "from ajoseph83.caveonetworks.com.com (115.113.156.2) by\n\tBN7PR07MB4897.namprd07.prod.outlook.com (2603:10b6:406:ef::26) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1207.28; Tue, 9 Oct 2018 09:08:41 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=o+jG0vFbIjRcGedaeBT33mcXMxs/LS/dMpZW7Oi5Bls=;\n\tb=n/jN6JXiAQAogEtQm1+jEyFHWSCkU1+r4GtUqAdXhXTqFN+p4aQE7qEI5Mcdx3JTDXPkW3YGgOw22d9+zDRmXJy+f7MfzJgoxoo0DcqeBhWSnnlzx/mMml4Dak0zmdyt7mEbK+HmsCpYe5myN6r7UKQgIcCs2IC91f2TbeKR/tw=", "Authentication-Results": "spf=none (sender IP is )\n\tsmtp.mailfrom=Anoob.Joseph@cavium.com; ", "From": "Anoob Joseph <anoob.joseph@caviumnetworks.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>,\n\tPablo de Lara <pablo.de.lara.guarch@intel.com>,\n\tThomas Monjalon <thomas@monjalon.net>", "Cc": "Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>,\n\tJerin Jacob <jerin.jacob@caviumnetworks.com>,\n\tNarayana Prasad <narayanaprasad.athreya@caviumnetworks.com>,\n\tAnoob Joseph <anoob.joseph@caviumnetworks.com>,\n\tMurthy NSSR <nidadavolu.murthy@caviumnetworks.com>,\n\tNithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>,\n\tRagothaman Jayaraman <rjayaraman@caviumnetworks.com>,\n\tSrisivasubramanian S <ssrinivasan@caviumnetworks.com>,\n\tTejasree Kondoj <kondoj.tejasree@caviumnetworks.com>, dev@dpdk.org", "Date": "Tue, 9 Oct 2018 14:37:35 +0530", "Message-Id": "<1539076076-19786-3-git-send-email-anoob.joseph@caviumnetworks.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "References": "<1538744363-30340-1-git-send-email-anoob.joseph@caviumnetworks.com>\n\t<1539076076-19786-1-git-send-email-anoob.joseph@caviumnetworks.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[115.113.156.2]", "X-ClientProxiedBy": "PN1PR0101CA0004.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:c00:e::14) To BN7PR07MB4897.namprd07.prod.outlook.com\n\t(2603:10b6:406:ef::26)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "38f183f4-e6f3-4724-e113-08d62dc6d0f2", "X-Microsoft-Antispam": "BCL:0; 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PCL:0;\n\tRULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(3002001)(93006095)(10201501046)(3231355)(944501410)(52105095)(149066)(150057)(6041310)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123564045)(20161123558120)(201708071742011)(7699051);\n\tSRVR:BN7PR07MB4897; BCL:0; PCL:0; RULEID:; SRVR:BN7PR07MB4897; ", "X-Forefront-PRVS": "08200063E9", "X-Forefront-Antispam-Report": "SFV:NSPM;\n\tSFS:(10009020)(396003)(366004)(376002)(136003)(346002)(39860400002)(199004)(189003)(42882007)(47776003)(106356001)(6666003)(186003)(5660300001)(26005)(68736007)(16526019)(8936002)(25786009)(6116002)(2906002)(81156014)(50226002)(305945005)(81166006)(7736002)(3846002)(105586002)(478600001)(8676002)(54906003)(110136005)(48376002)(16586007)(14444005)(6486002)(6506007)(50466002)(316002)(53936002)(386003)(51416003)(52116002)(76176011)(11346002)(6512007)(44832011)(446003)(36756003)(55236004)(956004)(2616005)(4744004)(486006)(4326008)(66066001)(97736004)(72206003)(476003);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:BN7PR07MB4897;\n\tH:ajoseph83.caveonetworks.com.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; A:1; MX:1; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "X-Microsoft-Antispam-Message-Info": "NEltFKgbcLMQYAnFfeY/oFIDqsCg+ckYyqbO8ENmaq97KFaI77OxGCVw0ACC0BXQdUhQwLR5cmM9YZj4TSzqoukUpCWt78+i8SM65wY0ARLDmX4xs4V+4+3mpZ/VkDZ2PFugfZZ6OKnzqNeAdFQw4JXS74qrtrnokKJpJo18nHY/eqsAvjGUFW/qzMx+E1xDgtzwHG6TIBv/TTibJ11O4zad8omr5ESjhwqH+FZ8nYM5YowG7I9mqsjRBjWXwdL8h9G+5ykEMfoGiHbSCAcTIsRb5NJB2dF2fnXEB2AjQ8VUQOR0Gyn8ITTqR8Fvd4fdKxFLHDAubnFdCyyF1t0/4seU+IZSarCJTuxDhLYbOCc=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "caviumnetworks.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Oct 2018 09:08:41.6321\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "38f183f4-e6f3-4724-e113-08d62dc6d0f2", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN7PR07MB4897", "Subject": "[dpdk-dev] [PATCH v4 02/23] crypto/octeontx: add hardware init\n\troutine", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\n\nAdding hardware init routine for OCTEON TX crypto device. A place holder\nis added for misc polling routine. That will be added in the further\npatches.\n\nSigned-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>\nSigned-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>\nSigned-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>\nSigned-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>\nSigned-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>\nSigned-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>\nSigned-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>\n---\n drivers/common/cpt/cpt_common.h | 47 ++++++++\n drivers/crypto/octeontx/Makefile | 1 +\n drivers/crypto/octeontx/meson.build | 1 +\n drivers/crypto/octeontx/otx_cryptodev_hw_access.c | 48 ++++++++\n drivers/crypto/octeontx/otx_cryptodev_hw_access.h | 134 ++++++++++++++++++++++\n drivers/crypto/octeontx/otx_cryptodev_ops.c | 92 ++++++++++++++-\n 6 files changed, 322 insertions(+), 1 deletion(-)\n create mode 100644 drivers/common/cpt/cpt_common.h\n create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n create mode 100644 drivers/crypto/octeontx/otx_cryptodev_hw_access.h", "diff": "diff --git a/drivers/common/cpt/cpt_common.h b/drivers/common/cpt/cpt_common.h\nnew file mode 100644\nindex 0000000..5e2099a\n--- /dev/null\n+++ b/drivers/common/cpt/cpt_common.h\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _CPT_COMMON_H_\n+#define _CPT_COMMON_H_\n+\n+/*\n+ * This file defines common macros and structs\n+ */\n+\n+/*\n+ * Macros to determine CPT model. Driver makefile will define CPT_MODEL\n+ * accordingly\n+ */\n+#define CRYPTO_OCTEONTX\t\t0x1\n+\n+#define AE_TYPE 1\n+#define SE_TYPE 2\n+\n+struct cptvf_meta_info {\n+\tvoid *cptvf_meta_pool;\n+\tint cptvf_op_mlen;\n+\tint cptvf_op_sb_mlen;\n+};\n+\n+struct rid {\n+\t/** Request id of a crypto operation */\n+\tuintptr_t rid;\n+};\n+\n+/*\n+ * Pending queue structure\n+ *\n+ */\n+struct pending_queue {\n+\t/** Tail of queue to be used for enqueue */\n+\tuint16_t enq_tail;\n+\t/** Head of queue to be used for dequeue */\n+\tuint16_t deq_head;\n+\t/** Array of pending requests */\n+\tstruct rid *rid_queue;\n+\t/** Pending requests count */\n+\tuint64_t pending_count;\n+};\n+\n+#endif /* _CPT_COMMON_H_ */\ndiff --git a/drivers/crypto/octeontx/Makefile b/drivers/crypto/octeontx/Makefile\nindex 12fec75..4582540 100644\n--- a/drivers/crypto/octeontx/Makefile\n+++ b/drivers/crypto/octeontx/Makefile\n@@ -24,6 +24,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt\n \n # PMD code\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c\n \n # export include files\ndiff --git a/drivers/crypto/octeontx/meson.build b/drivers/crypto/octeontx/meson.build\nindex 6564090..eca1cf1 100644\n--- a/drivers/crypto/octeontx/meson.build\n+++ b/drivers/crypto/octeontx/meson.build\n@@ -8,6 +8,7 @@ deps += ['bus_pci']\n name = 'octeontx_crypto'\n \n sources = files('otx_cryptodev.c',\n+\t\t'otx_cryptodev_hw_access.c',\n \t\t'otx_cryptodev_ops.c')\n \n cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.c b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\nnew file mode 100644\nindex 0000000..99fe3cf\n--- /dev/null\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.c\n@@ -0,0 +1,48 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+#include <string.h>\n+\n+#include <rte_common.h>\n+\n+#include \"otx_cryptodev_hw_access.h\"\n+\n+#include \"cpt_pmd_logs.h\"\n+\n+static int\n+otx_cpt_vf_init(struct cpt_vf *cptvf)\n+{\n+\tint ret = 0;\n+\n+\tCPT_LOG_DP_DEBUG(\"%s: %s done\", cptvf->dev_name, __func__);\n+\n+\treturn ret;\n+}\n+\n+void\n+otx_cpt_poll_misc(struct cpt_vf *cptvf)\n+{\n+\tRTE_SET_USED(cptvf);\n+}\n+\n+int\n+otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)\n+{\n+\tmemset(cptvf, 0, sizeof(struct cpt_vf));\n+\n+\t/* Bar0 base address */\n+\tcptvf->reg_base = reg_base;\n+\tstrncpy(cptvf->dev_name, name, 32);\n+\n+\tcptvf->pdev = pdev;\n+\n+\t/* To clear if there are any pending mbox msgs */\n+\totx_cpt_poll_misc(cptvf);\n+\n+\tif (otx_cpt_vf_init(cptvf)) {\n+\t\tCPT_LOG_ERR(\"Failed to initialize CPT VF device\");\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_hw_access.h b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\nnew file mode 100644\nindex 0000000..1e1877c\n--- /dev/null\n+++ b/drivers/crypto/octeontx/otx_cryptodev_hw_access.h\n@@ -0,0 +1,134 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Cavium, Inc\n+ */\n+\n+#ifndef _OTX_CRYPTODEV_HW_ACCESS_H_\n+#define _OTX_CRYPTODEV_HW_ACCESS_H_\n+\n+#include <stdbool.h>\n+\n+#include <rte_memory.h>\n+\n+#include \"cpt_common.h\"\n+\n+#define CPT_INTR_POLL_INTERVAL_MS\t(50)\n+\n+/* Default command queue length */\n+#define DEFAULT_CMD_QCHUNKS\t\t2\n+\n+/* cpt instance */\n+struct cpt_instance {\n+\tuint32_t queue_id;\n+\tuintptr_t rsvd;\n+};\n+\n+struct command_chunk {\n+\t/** 128-byte aligned real_vaddr */\n+\tuint8_t *head;\n+\t/** 128-byte aligned real_dma_addr */\n+\tphys_addr_t dma_addr;\n+};\n+\n+/**\n+ * Command queue structure\n+ */\n+struct command_queue {\n+\t/** Command queue host write idx */\n+\tuint32_t idx;\n+\t/** Command queue chunk */\n+\tuint32_t cchunk;\n+\t/** Command queue head; instructions are inserted here */\n+\tuint8_t *qhead;\n+\t/** Command chunk list head */\n+\tstruct command_chunk chead[DEFAULT_CMD_QCHUNKS];\n+};\n+\n+/**\n+ * CPT VF device structure\n+ */\n+struct cpt_vf {\n+\t/** CPT instance */\n+\tstruct cpt_instance instance;\n+\t/** Register start address */\n+\tuint8_t *reg_base;\n+\t/** Command queue information */\n+\tstruct command_queue cqueue;\n+\t/** Pending queue information */\n+\tstruct pending_queue pqueue;\n+\t/** Meta information per vf */\n+\tstruct cptvf_meta_info meta_info;\n+\n+\t/** Below fields are accessed only in control path */\n+\n+\t/** Env specific pdev representing the pci dev */\n+\tvoid *pdev;\n+\t/** Calculated queue size */\n+\tuint32_t qsize;\n+\t/** Device index (0...CPT_MAX_VQ_NUM)*/\n+\tuint8_t vfid;\n+\t/** VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */\n+\tuint8_t vftype;\n+\t/** VF group (0 - 8) */\n+\tuint8_t vfgrp;\n+\t/** Operating node: Bits (46:44) in BAR0 address */\n+\tuint8_t node;\n+\n+\t/** VF-PF mailbox communication */\n+\n+\t/** Flag if acked */\n+\tbool pf_acked;\n+\t/** Flag if not acked */\n+\tbool pf_nacked;\n+\n+\t/** Device name */\n+\tchar dev_name[32];\n+} __rte_cache_aligned;\n+\n+/*\n+ * CPT Registers map for 81xx\n+ */\n+\n+/* VF registers */\n+#define CPTX_VQX_CTL(a, b)\t\t(0x0000100ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x0) + 0x100000ll * (b))\n+#define CPTX_VQX_SADDR(a, b)\t\t(0x0000200ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x0) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_WAIT(a, b)\t(0x0000400ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x0) + 0x100000ll * (b))\n+#define CPTX_VQX_INPROG(a, b)\t\t(0x0000410ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x0) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE(a, b)\t\t(0x0000420ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_ACK(a, b)\t\t(0x0000440ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_INT_W1S(a, b)\t(0x0000460ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_INT_W1C(a, b)\t(0x0000468ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_ENA_W1S(a, b)\t(0x0000470ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DONE_ENA_W1C(a, b)\t(0x0000478ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_MISC_INT(a, b)\t\t(0x0000500ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_MISC_INT_W1S(a, b)\t(0x0000508ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_MISC_ENA_W1S(a, b)\t(0x0000510ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_MISC_ENA_W1C(a, b)\t(0x0000518ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VQX_DOORBELL(a, b)\t\t(0x0000600ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b))\n+#define CPTX_VFX_PF_MBOXX(a, b, c)\t(0x0001000ll + 0x1000000000ll * \\\n+\t\t\t\t\t ((a) & 0x1) + 0x100000ll * (b) + \\\n+\t\t\t\t\t 8ll * ((c) & 0x1))\n+\n+/* VF HAL functions */\n+\n+void\n+otx_cpt_poll_misc(struct cpt_vf *cptvf);\n+\n+int\n+otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);\n+\n+#endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */\ndiff --git a/drivers/crypto/octeontx/otx_cryptodev_ops.c b/drivers/crypto/octeontx/otx_cryptodev_ops.c\nindex 1b5f108..3bf6cd2 100644\n--- a/drivers/crypto/octeontx/otx_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx/otx_cryptodev_ops.c\n@@ -2,14 +2,104 @@\n * Copyright(c) 2018 Cavium, Inc\n */\n \n+#include <rte_alarm.h>\n+#include <rte_bus_pci.h>\n #include <rte_cryptodev.h>\n+#include <rte_malloc.h>\n+\n+#include \"cpt_pmd_logs.h\"\n \n #include \"otx_cryptodev.h\"\n+#include \"otx_cryptodev_hw_access.h\"\n #include \"otx_cryptodev_ops.h\"\n \n+/* Alarm routines */\n+\n+static void\n+otx_cpt_alarm_cb(void *arg)\n+{\n+\tstruct cpt_vf *cptvf = arg;\n+\totx_cpt_poll_misc(cptvf);\n+\trte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,\n+\t\t\t otx_cpt_alarm_cb, cptvf);\n+}\n+\n+static int\n+otx_cpt_periodic_alarm_start(void *arg)\n+{\n+\treturn rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,\n+\t\t\t\t otx_cpt_alarm_cb, arg);\n+}\n+\n int\n otx_cpt_dev_create(struct rte_cryptodev *c_dev)\n {\n-\tRTE_SET_USED(c_dev);\n+\tstruct rte_pci_device *pdev = RTE_DEV_TO_PCI(c_dev->device);\n+\tstruct cpt_vf *cptvf = NULL;\n+\tvoid *reg_base;\n+\tchar dev_name[32];\n+\tint ret;\n+\n+\tif (pdev->mem_resource[0].phys_addr == 0ULL)\n+\t\treturn -EIO;\n+\n+\t/* for secondary processes, we don't initialise any further as primary\n+\t * has already done this work.\n+\t */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\tcptvf = rte_zmalloc_socket(\"otx_cryptodev_private_mem\",\n+\t\t\tsizeof(struct cpt_vf), RTE_CACHE_LINE_SIZE,\n+\t\t\trte_socket_id());\n+\n+\tif (cptvf == NULL) {\n+\t\tCPT_LOG_ERR(\"Cannot allocate memory for device private data\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tsnprintf(dev_name, 32, \"%02x:%02x.%x\",\n+\t\t\tpdev->addr.bus, pdev->addr.devid, pdev->addr.function);\n+\n+\treg_base = pdev->mem_resource[0].addr;\n+\tif (!reg_base) {\n+\t\tCPT_LOG_ERR(\"Failed to map BAR0 of %s\", dev_name);\n+\t\tret = -ENODEV;\n+\t\tgoto fail;\n+\t}\n+\n+\tret = otx_cpt_hw_init(cptvf, pdev, reg_base, dev_name);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Failed to init cptvf %s\", dev_name);\n+\t\tret = -EIO;\n+\t\tgoto fail;\n+\t}\n+\n+\t/* Start off timer for mailbox interrupts */\n+\totx_cpt_periodic_alarm_start(cptvf);\n+\n+\tc_dev->dev_ops = NULL;\n+\n+\tc_dev->enqueue_burst = NULL;\n+\tc_dev->dequeue_burst = NULL;\n+\n+\tc_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n+\t\t\tRTE_CRYPTODEV_FF_IN_PLACE_SGL |\n+\t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\tRTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;\n+\n+\t/* Save dev private data */\n+\tc_dev->data->dev_private = cptvf;\n+\n \treturn 0;\n+\n+fail:\n+\tif (cptvf) {\n+\t\t/* Free private data allocated */\n+\t\trte_free(cptvf);\n+\t}\n+\n+\treturn ret;\n }\n", "prefixes": [ "v4", "02/23" ] }