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{
    "id": 45658,
    "url": "http://patches.dpdk.org/api/patches/45658/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1538208822-9726-15-git-send-email-rasesh.mody@cavium.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1538208822-9726-15-git-send-email-rasesh.mody@cavium.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1538208822-9726-15-git-send-email-rasesh.mody@cavium.com",
    "date": "2018-09-29T08:14:35",
    "name": "[14/18] net/qede/base: changes for 100G",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "2d0cb474abd9f92e7de6d3a0c3fc04e746ac53f9",
    "submitter": {
        "id": 569,
        "url": "http://patches.dpdk.org/api/people/569/?format=api",
        "name": "Mody, Rasesh",
        "email": "rasesh.mody@cavium.com"
    },
    "delegate": {
        "id": 319,
        "url": "http://patches.dpdk.org/api/users/319/?format=api",
        "username": "fyigit",
        "first_name": "Ferruh",
        "last_name": "Yigit",
        "email": "ferruh.yigit@amd.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1538208822-9726-15-git-send-email-rasesh.mody@cavium.com/mbox/",
    "series": [
        {
            "id": 1596,
            "url": "http://patches.dpdk.org/api/series/1596/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1596",
            "date": "2018-09-29T08:13:57",
            "name": "net/qede: base driver update",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/1596/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/45658/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/45658/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "\"Mody, Rasesh\" <Rasesh.Mody@cavium.com>",
        "To": "\"dev@dpdk.org\" <dev@dpdk.org>",
        "CC": "\"Mody, Rasesh\" <Rasesh.Mody@cavium.com>, \"ferruh.yigit@intel.com\"\n\t<ferruh.yigit@intel.com>, Dept-Eng DPDK Dev <Dept-EngDPDKDev@cavium.com>",
        "Thread-Topic": "[PATCH 14/18] net/qede/base: changes for 100G",
        "Thread-Index": "AQHUV8x0Wxto90mJiUierAfhgGi+BQ==",
        "Date": "Sat, 29 Sep 2018 08:14:35 +0000",
        "Message-ID": "<1538208822-9726-15-git-send-email-rasesh.mody@cavium.com>",
        "References": "<1538208822-9726-1-git-send-email-rasesh.mody@cavium.com>",
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        "Subject": "[dpdk-dev] [PATCH 14/18] net/qede/base: changes for 100G",
        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
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    },
    "content": "Change details:\n\n - Get engine affinity from the management FW and configure accordingly\n - Add an LLH filter with the primary MAC address in QPAR/NPAR\n - Move some of the LLH APIs around\n - Add PPFID APIs\n - Update all allocated ppfids with the same value for the\n   following PORT_PF registers:\n   NIG_REG_DSCP_TO_TC_MAP_ENABLE\n - Add port_id, src_pfid and dst_pfid to DMA engine params\n\nSigned-off-by: Rasesh Mody <rasesh.mody@cavium.com>\n---\n drivers/net/qede/base/ecore.h          |   49 +-\n drivers/net/qede/base/ecore_cxt.c      |    4 +-\n drivers/net/qede/base/ecore_dcbx.c     |   11 +-\n drivers/net/qede/base/ecore_dev.c      | 1740 +++++++++++++++++++++++---------\n drivers/net/qede/base/ecore_dev_api.h  |  161 ++-\n drivers/net/qede/base/ecore_hw.c       |  103 +-\n drivers/net/qede/base/ecore_hw.h       |   28 +-\n drivers/net/qede/base/ecore_init_ops.c |   14 +-\n drivers/net/qede/base/ecore_int.c      |   13 +-\n drivers/net/qede/base/ecore_l2.c       |    6 +-\n drivers/net/qede/base/ecore_mcp.c      |   69 ++\n drivers/net/qede/base/ecore_mcp.h      |   21 +-\n drivers/net/qede/base/ecore_sriov.c    |    4 +-\n drivers/net/qede/base/mcp_public.h     |   15 +\n drivers/net/qede/base/reg_addr.h       |    4 +\n 15 files changed, 1684 insertions(+), 558 deletions(-)",
    "diff": "diff --git a/drivers/net/qede/base/ecore.h b/drivers/net/qede/base/ecore.h\nindex b9f5993..524a1dd 100644\n--- a/drivers/net/qede/base/ecore.h\n+++ b/drivers/net/qede/base/ecore.h\n@@ -19,6 +19,7 @@\n #include <zlib.h>\n #endif\n \n+#include \"ecore_status.h\"\n #include \"ecore_hsi_common.h\"\n #include \"ecore_hsi_debug_tools.h\"\n #include \"ecore_hsi_init_func.h\"\n@@ -207,6 +208,7 @@ enum DP_MODULE {\n struct ecore_igu_info;\n struct ecore_mcp_info;\n struct ecore_dcbx_info;\n+struct ecore_llh_info;\n \n struct ecore_rt_data {\n \tu32\t*init_val;\n@@ -743,6 +745,7 @@ struct ecore_dev {\n #endif\n #define ECORE_IS_AH(dev)\t((dev)->type == ECORE_DEV_TYPE_AH)\n #define ECORE_IS_K2(dev)\tECORE_IS_AH(dev)\n+#define ECORE_IS_E4(dev)\t(ECORE_IS_BB(dev) || ECORE_IS_AH(dev))\n \n \tu16 vendor_id;\n \tu16 device_id;\n@@ -837,8 +840,26 @@ struct ecore_dev {\n \t/* HW functions */\n \tu8\t\t\t\tnum_hwfns;\n \tstruct ecore_hwfn\t\thwfns[MAX_HWFNS_PER_DEVICE];\n+#define ECORE_LEADING_HWFN(dev)\t\t(&dev->hwfns[0])\n #define ECORE_IS_CMT(dev)\t\t((dev)->num_hwfns > 1)\n \n+\t/* Engine affinity */\n+\tu8\t\t\t\tl2_affin_hint;\n+\tu8\t\t\t\tfir_affin;\n+\tu8\t\t\t\tiwarp_affin;\n+\t/* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */\n+#define ECORE_FIR_AFFIN_HWFN(dev)\t(&dev->hwfns[dev->fir_affin])\n+\t/* Macro for getting the engine-affinitized hwfn for iWARP */\n+#define ECORE_IWARP_AFFIN_HWFN(dev)\t(&dev->hwfns[dev->iwarp_affin])\n+\t/* Generic macro for getting the engine-affinitized hwfn */\n+#define ECORE_AFFIN_HWFN(dev) \\\n+\t(ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \\\n+\t ECORE_IWARP_AFFIN_HWFN(dev) : \\\n+\t ECORE_FIR_AFFIN_HWFN(dev))\n+\t/* Macro for getting the index (0/1) of the engine-affinitized hwfn */\n+#define ECORE_AFFIN_HWFN_IDX(dev) \\\n+\t(IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1)\n+\n \t/* SRIOV */\n \tstruct ecore_hw_sriov_info\t*p_iov_info;\n #define IS_ECORE_SRIOV(p_dev)\t\t(!!(p_dev)->p_iov_info)\n@@ -873,6 +894,9 @@ struct ecore_dev {\n #ifndef ASIC_ONLY\n \tbool\t\t\t\tb_is_emul_full;\n #endif\n+\t/* LLH info */\n+\tu8\t\t\t\tppfid_bitmap;\n+\tstruct ecore_llh_info\t\t*p_llh_info;\n \n \t/* Indicates whether this PF serves a storage target */\n \tbool\t\t\t\tb_is_target;\n@@ -974,6 +998,29 @@ void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,\n u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);\n u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);\n \n-#define ECORE_LEADING_HWFN(dev)\t(&dev->hwfns[0])\n+#define MFW_PORT(_p_hwfn)\t((_p_hwfn)->abs_pf_id % \\\n+\t\t\t\t ecore_device_num_ports((_p_hwfn)->p_dev))\n+\n+/* The PFID<->PPFID calculation is based on the relative index of a PF on its\n+ * port. In BB there is a bug in the LLH in which the PPFID is actually engine\n+ * based, and thus it equals the PFID.\n+ */\n+#define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \\\n+\t(ECORE_IS_BB((_p_hwfn)->p_dev) ? \\\n+\t (abs_ppfid) : \\\n+\t (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \\\n+\t MFW_PORT(_p_hwfn))\n+#define ECORE_PPFID_BY_PFID(_p_hwfn) \\\n+\t(ECORE_IS_BB((_p_hwfn)->p_dev) ? \\\n+\t (_p_hwfn)->rel_pf_id : \\\n+\t (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine)\n+\n+enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t struct ecore_ptt *p_ptt, u32 addr,\n+\t\t\t\t\t u32 val);\n+\n+/* Utility functions for dumping the content of the NIG LLH filters */\n+enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);\n+enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);\n \n #endif /* __ECORE_H */\ndiff --git a/drivers/net/qede/base/ecore_cxt.c b/drivers/net/qede/base/ecore_cxt.c\nindex 6bc6348..5c3370e 100644\n--- a/drivers/net/qede/base/ecore_cxt.c\n+++ b/drivers/net/qede/base/ecore_cxt.c\n@@ -2114,7 +2114,7 @@ enum _ecore_status_t\n \n \tecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,\n \t\t\t    reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),\n-\t\t\t    0 /* no flags */);\n+\t\t\t    OSAL_NULL /* default parameters */);\n \n \tif (elem_type == ECORE_ELEM_CXT) {\n \t\tu32 last_cid_allocated = (1 + (iid / elems_per_p)) *\n@@ -2221,7 +2221,7 @@ enum _ecore_status_t\n \t\t\t\t    (u64)(osal_uintptr_t)&ilt_hw_entry,\n \t\t\t\t    reg_offset,\n \t\t\t\t    sizeof(ilt_hw_entry) / sizeof(u32),\n-\t\t\t\t    0 /* no flags */);\n+\t\t\t\t    OSAL_NULL /* default parameters */);\n \t}\n \n \tecore_ptt_release(p_hwfn, p_ptt);\ndiff --git a/drivers/net/qede/base/ecore_dcbx.c b/drivers/net/qede/base/ecore_dcbx.c\nindex 9667874..7668ad6 100644\n--- a/drivers/net/qede/base/ecore_dcbx.c\n+++ b/drivers/net/qede/base/ecore_dcbx.c\n@@ -893,12 +893,19 @@ enum _ecore_status_t\n \n \tecore_dcbx_get_params(p_hwfn, &p_hwfn->p_dcbx_info->get, type);\n \n-\t/* Update the DSCP to TC mapping bit if required */\n+\t/* Update the DSCP to TC mapping enable bit if required */\n \tif ((type == ECORE_DCBX_OPERATIONAL_MIB) &&\n \t    p_hwfn->p_dcbx_info->dscp_nig_update) {\n \t\tu8 val = !!p_hwfn->p_dcbx_info->get.dscp.enabled;\n+\t\tu32 addr = NIG_REG_DSCP_TO_TC_MAP_ENABLE;\n+\n+\t\trc = ecore_all_ppfids_wr(p_hwfn, p_ptt, addr, val);\n+\t\tif (rc != ECORE_SUCCESS) {\n+\t\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t\t  \"Failed to update the DSCP to TC mapping enable bit\\n\");\n+\t\t\treturn rc;\n+\t\t}\n \n-\t\tecore_wr(p_hwfn, p_ptt, NIG_REG_DSCP_TO_TC_MAP_ENABLE, val);\n \t\tp_hwfn->p_dcbx_info->dscp_nig_update = false;\n \t}\n \ndiff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c\nindex 30e12e9..cf454b1 100644\n--- a/drivers/net/qede/base/ecore_dev.c\n+++ b/drivers/net/qede/base/ecore_dev.c\n@@ -352,6 +352,1189 @@ void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,\n }\n /******************** Doorbell Recovery end ****************/\n \n+/********************************** NIG LLH ***********************************/\n+\n+enum ecore_llh_filter_type {\n+\tECORE_LLH_FILTER_TYPE_MAC,\n+\tECORE_LLH_FILTER_TYPE_PROTOCOL,\n+};\n+\n+struct ecore_llh_mac_filter {\n+\tu8 addr[ETH_ALEN];\n+};\n+\n+struct ecore_llh_protocol_filter {\n+\tenum ecore_llh_prot_filter_type_t type;\n+\tu16 source_port_or_eth_type;\n+\tu16 dest_port;\n+};\n+\n+union ecore_llh_filter {\n+\tstruct ecore_llh_mac_filter mac;\n+\tstruct ecore_llh_protocol_filter protocol;\n+};\n+\n+struct ecore_llh_filter_info {\n+\tbool b_enabled;\n+\tu32 ref_cnt;\n+\tenum ecore_llh_filter_type type;\n+\tunion ecore_llh_filter filter;\n+};\n+\n+struct ecore_llh_info {\n+\t/* Number of LLH filters banks */\n+\tu8 num_ppfid;\n+\n+#define MAX_NUM_PPFID\t8\n+\tu8 ppfid_array[MAX_NUM_PPFID];\n+\n+\t/* Array of filters arrays:\n+\t * \"num_ppfid\" elements of filters banks, where each is an array of\n+\t * \"NIG_REG_LLH_FUNC_FILTER_EN_SIZE\" filters.\n+\t */\n+\tstruct ecore_llh_filter_info **pp_filters;\n+};\n+\n+static void ecore_llh_free(struct ecore_dev *p_dev)\n+{\n+\tstruct ecore_llh_info *p_llh_info = p_dev->p_llh_info;\n+\tu32 i;\n+\n+\tif (p_llh_info != OSAL_NULL) {\n+\t\tif (p_llh_info->pp_filters != OSAL_NULL) {\n+\t\t\tfor (i = 0; i < p_llh_info->num_ppfid; i++)\n+\t\t\t\tOSAL_FREE(p_dev, p_llh_info->pp_filters[i]);\n+\t\t}\n+\n+\t\tOSAL_FREE(p_dev, p_llh_info->pp_filters);\n+\t}\n+\n+\tOSAL_FREE(p_dev, p_llh_info);\n+\tp_dev->p_llh_info = OSAL_NULL;\n+}\n+\n+static enum _ecore_status_t ecore_llh_alloc(struct ecore_dev *p_dev)\n+{\n+\tstruct ecore_llh_info *p_llh_info;\n+\tu32 size;\n+\tu8 i;\n+\n+\tp_llh_info = OSAL_ZALLOC(p_dev, GFP_KERNEL, sizeof(*p_llh_info));\n+\tif (!p_llh_info)\n+\t\treturn ECORE_NOMEM;\n+\tp_dev->p_llh_info = p_llh_info;\n+\n+\tfor (i = 0; i < MAX_NUM_PPFID; i++) {\n+\t\tif (!(p_dev->ppfid_bitmap & (0x1 << i)))\n+\t\t\tcontinue;\n+\n+\t\tp_llh_info->ppfid_array[p_llh_info->num_ppfid] = i;\n+\t\tDP_VERBOSE(p_dev, ECORE_MSG_SP, \"ppfid_array[%d] = %hhd\\n\",\n+\t\t\t   p_llh_info->num_ppfid, i);\n+\t\tp_llh_info->num_ppfid++;\n+\t}\n+\n+\tsize = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters);\n+\tp_llh_info->pp_filters = OSAL_ZALLOC(p_dev, GFP_KERNEL, size);\n+\tif (!p_llh_info->pp_filters)\n+\t\treturn ECORE_NOMEM;\n+\n+\tsize = NIG_REG_LLH_FUNC_FILTER_EN_SIZE *\n+\t       sizeof(**p_llh_info->pp_filters);\n+\tfor (i = 0; i < p_llh_info->num_ppfid; i++) {\n+\t\tp_llh_info->pp_filters[i] = OSAL_ZALLOC(p_dev, GFP_KERNEL,\n+\t\t\t\t\t\t\tsize);\n+\t\tif (!p_llh_info->pp_filters[i])\n+\t\t\treturn ECORE_NOMEM;\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t ecore_llh_shadow_sanity(struct ecore_dev *p_dev,\n+\t\t\t\t\t\t    u8 ppfid, u8 filter_idx,\n+\t\t\t\t\t\t    const char *action)\n+{\n+\tstruct ecore_llh_info *p_llh_info = p_dev->p_llh_info;\n+\n+\tif (ppfid >= p_llh_info->num_ppfid) {\n+\t\tDP_NOTICE(p_dev, false,\n+\t\t\t  \"LLH shadow [%s]: using ppfid %d while only %d ppfids are available\\n\",\n+\t\t\t  action, ppfid, p_llh_info->num_ppfid);\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\tif (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) {\n+\t\tDP_NOTICE(p_dev, false,\n+\t\t\t  \"LLH shadow [%s]: using filter_idx %d while only %d filters are available\\n\",\n+\t\t\t  action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE);\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+#define ECORE_LLH_INVALID_FILTER_IDX\t0xff\n+\n+static enum _ecore_status_t\n+ecore_llh_shadow_search_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t       union ecore_llh_filter *p_filter,\n+\t\t\t       u8 *p_filter_idx)\n+{\n+\tstruct ecore_llh_info *p_llh_info = p_dev->p_llh_info;\n+\tstruct ecore_llh_filter_info *p_filters;\n+\tenum _ecore_status_t rc;\n+\tu8 i;\n+\n+\trc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, \"search\");\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\t*p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;\n+\n+\tp_filters = p_llh_info->pp_filters[ppfid];\n+\tfor (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {\n+\t\tif (!OSAL_MEMCMP(p_filter, &p_filters[i].filter,\n+\t\t\t\t sizeof(*p_filter))) {\n+\t\t\t*p_filter_idx = i;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_shadow_get_free_idx(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t      u8 *p_filter_idx)\n+{\n+\tstruct ecore_llh_info *p_llh_info = p_dev->p_llh_info;\n+\tstruct ecore_llh_filter_info *p_filters;\n+\tenum _ecore_status_t rc;\n+\tu8 i;\n+\n+\trc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, \"get_free_idx\");\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\t*p_filter_idx = ECORE_LLH_INVALID_FILTER_IDX;\n+\n+\tp_filters = p_llh_info->pp_filters[ppfid];\n+\tfor (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {\n+\t\tif (!p_filters[i].b_enabled) {\n+\t\t\t*p_filter_idx = i;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+__ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid, u8 filter_idx,\n+\t\t\t      enum ecore_llh_filter_type type,\n+\t\t\t      union ecore_llh_filter *p_filter, u32 *p_ref_cnt)\n+{\n+\tstruct ecore_llh_info *p_llh_info = p_dev->p_llh_info;\n+\tstruct ecore_llh_filter_info *p_filters;\n+\tenum _ecore_status_t rc;\n+\n+\trc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, \"add\");\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\tp_filters = p_llh_info->pp_filters[ppfid];\n+\tif (!p_filters[filter_idx].ref_cnt) {\n+\t\tp_filters[filter_idx].b_enabled = true;\n+\t\tp_filters[filter_idx].type = type;\n+\t\tOSAL_MEMCPY(&p_filters[filter_idx].filter, p_filter,\n+\t\t\t    sizeof(p_filters[filter_idx].filter));\n+\t}\n+\n+\t*p_ref_cnt = ++p_filters[filter_idx].ref_cnt;\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_shadow_add_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t    enum ecore_llh_filter_type type,\n+\t\t\t    union ecore_llh_filter *p_filter,\n+\t\t\t    u8 *p_filter_idx, u32 *p_ref_cnt)\n+{\n+\tenum _ecore_status_t rc;\n+\n+\t/* Check if the same filter already exist */\n+\trc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,\n+\t\t\t\t\t    p_filter_idx);\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\t/* Find a new entry in case of a new filter */\n+\tif (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {\n+\t\trc = ecore_llh_shadow_get_free_idx(p_dev, ppfid, p_filter_idx);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\treturn rc;\n+\t}\n+\n+\t/* No free entry was found */\n+\tif (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {\n+\t\tDP_NOTICE(p_dev, false,\n+\t\t\t  \"Failed to find an empty LLH filter to utilize [ppfid %d]\\n\",\n+\t\t\t  ppfid);\n+\t\treturn ECORE_NORESOURCES;\n+\t}\n+\n+\treturn __ecore_llh_shadow_add_filter(p_dev, ppfid, *p_filter_idx, type,\n+\t\t\t\t\t     p_filter, p_ref_cnt);\n+}\n+\n+static enum _ecore_status_t\n+__ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t\t u8 filter_idx, u32 *p_ref_cnt)\n+{\n+\tstruct ecore_llh_info *p_llh_info = p_dev->p_llh_info;\n+\tstruct ecore_llh_filter_info *p_filters;\n+\tenum _ecore_status_t rc;\n+\n+\trc = ecore_llh_shadow_sanity(p_dev, ppfid, filter_idx, \"remove\");\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\tp_filters = p_llh_info->pp_filters[ppfid];\n+\tif (!p_filters[filter_idx].ref_cnt) {\n+\t\tDP_NOTICE(p_dev, false,\n+\t\t\t  \"LLH shadow: trying to remove a filter with ref_cnt=0\\n\");\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\t*p_ref_cnt = --p_filters[filter_idx].ref_cnt;\n+\tif (!p_filters[filter_idx].ref_cnt)\n+\t\tOSAL_MEM_ZERO(&p_filters[filter_idx],\n+\t\t\t      sizeof(p_filters[filter_idx]));\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_shadow_remove_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t       union ecore_llh_filter *p_filter,\n+\t\t\t       u8 *p_filter_idx, u32 *p_ref_cnt)\n+{\n+\tenum _ecore_status_t rc;\n+\n+\trc = ecore_llh_shadow_search_filter(p_dev, ppfid, p_filter,\n+\t\t\t\t\t    p_filter_idx);\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\t/* No matching filter was found */\n+\tif (*p_filter_idx == ECORE_LLH_INVALID_FILTER_IDX) {\n+\t\tDP_NOTICE(p_dev, false,\n+\t\t\t  \"Failed to find a filter in the LLH shadow\\n\");\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\treturn __ecore_llh_shadow_remove_filter(p_dev, ppfid, *p_filter_idx,\n+\t\t\t\t\t\tp_ref_cnt);\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_shadow_remove_all_filters(struct ecore_dev *p_dev, u8 ppfid)\n+{\n+\tstruct ecore_llh_info *p_llh_info = p_dev->p_llh_info;\n+\tstruct ecore_llh_filter_info *p_filters;\n+\tenum _ecore_status_t rc;\n+\n+\trc = ecore_llh_shadow_sanity(p_dev, ppfid, 0, \"remove_all\");\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\tp_filters = p_llh_info->pp_filters[ppfid];\n+\tOSAL_MEM_ZERO(p_filters,\n+\t\t      NIG_REG_LLH_FUNC_FILTER_EN_SIZE * sizeof(*p_filters));\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t ecore_abs_ppfid(struct ecore_dev *p_dev,\n+\t\t\t\t\t    u8 rel_ppfid, u8 *p_abs_ppfid)\n+{\n+\tstruct ecore_llh_info *p_llh_info = p_dev->p_llh_info;\n+\tu8 ppfids = p_llh_info->num_ppfid - 1;\n+\n+\tif (rel_ppfid >= p_llh_info->num_ppfid) {\n+\t\tDP_NOTICE(p_dev, false,\n+\t\t\t  \"rel_ppfid %d is not valid, available indices are 0..%hhd\\n\",\n+\t\t\t  rel_ppfid, ppfids);\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\t*p_abs_ppfid = p_llh_info->ppfid_array[rel_ppfid];\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+__ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)\n+{\n+\tstruct ecore_dev *p_dev = p_hwfn->p_dev;\n+\tenum ecore_eng eng;\n+\tu8 ppfid;\n+\tenum _ecore_status_t rc;\n+\n+\trc = ecore_mcp_get_engine_config(p_hwfn, p_ptt);\n+\tif (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL) {\n+\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t  \"Failed to get the engine affinity configuration\\n\");\n+\t\treturn rc;\n+\t}\n+\n+\t/* RoCE PF is bound to a single engine */\n+\tif (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {\n+\t\teng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;\n+\t\trc = ecore_llh_set_roce_affinity(p_dev, eng);\n+\t\tif (rc != ECORE_SUCCESS) {\n+\t\t\tDP_NOTICE(p_dev, false,\n+\t\t\t\t  \"Failed to set the RoCE engine affinity\\n\");\n+\t\t\treturn rc;\n+\t\t}\n+\n+\t\tDP_VERBOSE(p_dev, ECORE_MSG_SP,\n+\t\t\t   \"LLH: Set the engine affinity of RoCE packets as %d\\n\",\n+\t\t\t   eng);\n+\t}\n+\n+\t/* Storage PF is bound to a single engine while L2 PF uses both */\n+\tif (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||\n+\t    ECORE_IS_ISCSI_PERSONALITY(p_hwfn))\n+\t\teng = p_dev->fir_affin ? ECORE_ENG1 : ECORE_ENG0;\n+\telse /* L2_PERSONALITY */\n+\t\teng = ECORE_BOTH_ENG;\n+\n+\tfor (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {\n+\t\trc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);\n+\t\tif (rc != ECORE_SUCCESS) {\n+\t\t\tDP_NOTICE(p_dev, false,\n+\t\t\t\t  \"Failed to set the engine affinity of ppfid %d\\n\",\n+\t\t\t\t  ppfid);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\n+\tDP_VERBOSE(p_dev, ECORE_MSG_SP,\n+\t\t   \"LLH: Set the engine affinity of non-RoCE packets as %d\\n\",\n+\t\t   eng);\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_set_engine_affin(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t\t   bool avoid_eng_affin)\n+{\n+\tstruct ecore_dev *p_dev = p_hwfn->p_dev;\n+\tenum _ecore_status_t rc;\n+\n+\t/* Backwards compatible mode:\n+\t * - RoCE packets     - Use engine 0.\n+\t * - Non-RoCE packets - Use connection based classification for L2 PFs,\n+\t *                      and engine 0 otherwise.\n+\t */\n+\tif (avoid_eng_affin) {\n+\t\tenum ecore_eng eng;\n+\t\tu8 ppfid;\n+\n+\t\tif (ECORE_IS_ROCE_PERSONALITY(p_hwfn)) {\n+\t\t\teng = ECORE_ENG0;\n+\t\t\trc = ecore_llh_set_roce_affinity(p_dev, eng);\n+\t\t\tif (rc != ECORE_SUCCESS) {\n+\t\t\t\tDP_NOTICE(p_dev, false,\n+\t\t\t\t\t  \"Failed to set the RoCE engine affinity\\n\");\n+\t\t\t\treturn rc;\n+\t\t\t}\n+\n+\t\t\tDP_VERBOSE(p_dev, ECORE_MSG_SP,\n+\t\t\t\t   \"LLH [backwards compatible mode]: Set the engine affinity of RoCE packets as %d\\n\",\n+\t\t\t\t   eng);\n+\t\t}\n+\n+\t\teng = (ECORE_IS_FCOE_PERSONALITY(p_hwfn) ||\n+\t\t       ECORE_IS_ISCSI_PERSONALITY(p_hwfn)) ? ECORE_ENG0\n+\t\t\t\t\t\t\t   : ECORE_BOTH_ENG;\n+\t\tfor (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {\n+\t\t\trc = ecore_llh_set_ppfid_affinity(p_dev, ppfid, eng);\n+\t\t\tif (rc != ECORE_SUCCESS) {\n+\t\t\t\tDP_NOTICE(p_dev, false,\n+\t\t\t\t\t  \"Failed to set the engine affinity of ppfid %d\\n\",\n+\t\t\t\t\t  ppfid);\n+\t\t\t\treturn rc;\n+\t\t\t}\n+\t\t}\n+\n+\t\tDP_VERBOSE(p_dev, ECORE_MSG_SP,\n+\t\t\t   \"LLH [backwards compatible mode]: Set the engine affinity of non-RoCE packets as %d\\n\",\n+\t\t\t   eng);\n+\n+\t\treturn ECORE_SUCCESS;\n+\t}\n+\n+\treturn __ecore_llh_set_engine_affin(p_hwfn, p_ptt);\n+}\n+\n+static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\t struct ecore_ptt *p_ptt,\n+\t\t\t\t\t\t bool avoid_eng_affin)\n+{\n+\tstruct ecore_dev *p_dev = p_hwfn->p_dev;\n+\tu8 ppfid, abs_ppfid;\n+\tenum _ecore_status_t rc;\n+\n+\tfor (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {\n+\t\tu32 addr;\n+\n+\t\trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\treturn rc;\n+\n+\t\taddr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4;\n+\t\tecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);\n+\t}\n+\n+\tif (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&\n+\t    !ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {\n+\t\trc = ecore_llh_add_mac_filter(p_dev, 0,\n+\t\t\t\t\t      p_hwfn->hw_info.hw_mac_addr);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\tDP_NOTICE(p_dev, false,\n+\t\t\t\t  \"Failed to add an LLH filter with the primary MAC\\n\");\n+\t}\n+\n+\tif (ECORE_IS_CMT(p_dev)) {\n+\t\trc = ecore_llh_set_engine_affin(p_hwfn, p_ptt, avoid_eng_affin);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\treturn rc;\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev)\n+{\n+\treturn p_dev->p_llh_info->num_ppfid;\n+}\n+\n+enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev)\n+{\n+\treturn p_dev->l2_affin_hint ? ECORE_ENG1 : ECORE_ENG0;\n+}\n+\n+/* TBD - should be removed when these definitions are available in reg_addr.h */\n+#define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK\t\t0x3\n+#define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT\t\t0\n+#define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK\t\t0x3\n+#define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT\t2\n+\n+enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,\n+\t\t\t\t\t\t  u8 ppfid, enum ecore_eng eng)\n+{\n+\tstruct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);\n+\tstruct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);\n+\tu32 addr, val, eng_sel;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tu8 abs_ppfid;\n+\n+\tif (p_ptt == OSAL_NULL)\n+\t\treturn ECORE_AGAIN;\n+\n+\tif (!ECORE_IS_CMT(p_dev))\n+\t\tgoto out;\n+\n+\trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto out;\n+\n+\tswitch (eng) {\n+\tcase ECORE_ENG0:\n+\t\teng_sel = 0;\n+\t\tbreak;\n+\tcase ECORE_ENG1:\n+\t\teng_sel = 1;\n+\t\tbreak;\n+\tcase ECORE_BOTH_ENG:\n+\t\teng_sel = 2;\n+\t\tbreak;\n+\tdefault:\n+\t\tDP_NOTICE(p_dev, false,\n+\t\t\t  \"Invalid affinity value for ppfid [%d]\\n\", eng);\n+\t\trc = ECORE_INVAL;\n+\t\tgoto out;\n+\t}\n+\n+\taddr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;\n+\tval = ecore_rd(p_hwfn, p_ptt, addr);\n+\tSET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel);\n+\tecore_wr(p_hwfn, p_ptt, addr, val);\n+\n+\t/* The iWARP affinity is set as the affinity of ppfid 0 */\n+\tif (!ppfid && ECORE_IS_IWARP_PERSONALITY(p_hwfn))\n+\t\tp_dev->iwarp_affin = (eng == ECORE_ENG1) ? 1 : 0;\n+out:\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+\n+\treturn rc;\n+}\n+\n+enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,\n+\t\t\t\t\t\t enum ecore_eng eng)\n+{\n+\tstruct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);\n+\tstruct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);\n+\tu32 addr, val, eng_sel;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tu8 ppfid, abs_ppfid;\n+\n+\tif (p_ptt == OSAL_NULL)\n+\t\treturn ECORE_AGAIN;\n+\n+\tif (!ECORE_IS_CMT(p_dev))\n+\t\tgoto out;\n+\n+\tswitch (eng) {\n+\tcase ECORE_ENG0:\n+\t\teng_sel = 0;\n+\t\tbreak;\n+\tcase ECORE_ENG1:\n+\t\teng_sel = 1;\n+\t\tbreak;\n+\tcase ECORE_BOTH_ENG:\n+\t\teng_sel = 2;\n+\t\tecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL,\n+\t\t\t 0xf /* QP bit 15 */);\n+\t\tbreak;\n+\tdefault:\n+\t\tDP_NOTICE(p_dev, false,\n+\t\t\t  \"Invalid affinity value for RoCE [%d]\\n\", eng);\n+\t\trc = ECORE_INVAL;\n+\t\tgoto out;\n+\t}\n+\n+\tfor (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {\n+\t\trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\tgoto out;\n+\n+\t\taddr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;\n+\t\tval = ecore_rd(p_hwfn, p_ptt, addr);\n+\t\tSET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel);\n+\t\tecore_wr(p_hwfn, p_ptt, addr, val);\n+\t}\n+out:\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+\n+\treturn rc;\n+}\n+\n+struct ecore_llh_filter_e4_details {\n+\tu64 value;\n+\tu32 mode;\n+\tu32 protocol_type;\n+\tu32 hdr_sel;\n+\tu32 enable;\n+};\n+\n+static enum _ecore_status_t\n+ecore_llh_access_filter_e4(struct ecore_hwfn *p_hwfn,\n+\t\t\t   struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx,\n+\t\t\t   struct ecore_llh_filter_e4_details *p_details,\n+\t\t\t   bool b_write_access)\n+{\n+\tu8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);\n+\tstruct ecore_dmae_params params;\n+\tenum _ecore_status_t rc;\n+\tu32 addr;\n+\n+\t/* The NIG/LLH registers that are accessed in this function have only 16\n+\t * rows which are exposed to a PF. I.e. only the 16 filters of its\n+\t * default ppfid\n+\t * Accessing filters of other ppfids requires pretending to other PFs,\n+\t * and thus the usage of the ecore_ppfid_rd/wr() functions.\n+\t */\n+\n+\t/* Filter enable - should be done first when removing a filter */\n+\tif (b_write_access && !p_details->enable) {\n+\t\taddr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4;\n+\t\tecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,\n+\t\t\t       p_details->enable);\n+\t}\n+\n+\t/* Filter value */\n+\taddr = NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 + 2 * filter_idx * 0x4;\n+\tOSAL_MEMSET(&params, 0, sizeof(params));\n+\n+\tif (b_write_access) {\n+\t\tparams.flags = ECORE_DMAE_FLAG_PF_DST;\n+\t\tparams.dst_pfid = pfid;\n+\t\trc = ecore_dmae_host2grc(p_hwfn, p_ptt,\n+\t\t\t\t\t (u64)(osal_uintptr_t)&p_details->value,\n+\t\t\t\t\t addr, 2 /* size_in_dwords */, &params);\n+\t} else {\n+\t\tparams.flags = ECORE_DMAE_FLAG_PF_SRC |\n+\t\t\t       ECORE_DMAE_FLAG_COMPLETION_DST;\n+\t\tparams.src_pfid = pfid;\n+\t\trc = ecore_dmae_grc2host(p_hwfn, p_ptt, addr,\n+\t\t\t\t\t (u64)(osal_uintptr_t)&p_details->value,\n+\t\t\t\t\t 2 /* size_in_dwords */, &params);\n+\t}\n+\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\t/* Filter mode */\n+\taddr = NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 + filter_idx * 0x4;\n+\tif (b_write_access)\n+\t\tecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, p_details->mode);\n+\telse\n+\t\tp_details->mode = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,\n+\t\t\t\t\t\t addr);\n+\n+\t/* Filter protocol type */\n+\taddr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 + filter_idx * 0x4;\n+\tif (b_write_access)\n+\t\tecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,\n+\t\t\t       p_details->protocol_type);\n+\telse\n+\t\tp_details->protocol_type = ecore_ppfid_rd(p_hwfn, p_ptt,\n+\t\t\t\t\t\t\t  abs_ppfid, addr);\n+\n+\t/* Filter header select */\n+\taddr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 + filter_idx * 0x4;\n+\tif (b_write_access)\n+\t\tecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,\n+\t\t\t       p_details->hdr_sel);\n+\telse\n+\t\tp_details->hdr_sel = ecore_ppfid_rd(p_hwfn, p_ptt, abs_ppfid,\n+\t\t\t\t\t\t    addr);\n+\n+\t/* Filter enable - should be done last when adding a filter */\n+\tif (!b_write_access || p_details->enable) {\n+\t\taddr = NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + filter_idx * 0x4;\n+\t\tif (b_write_access)\n+\t\t\tecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr,\n+\t\t\t\t       p_details->enable);\n+\t\telse\n+\t\t\tp_details->enable = ecore_ppfid_rd(p_hwfn, p_ptt,\n+\t\t\t\t\t\t\t   abs_ppfid, addr);\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_add_filter_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t\tu8 abs_ppfid, u8 filter_idx, u8 filter_prot_type,\n+\t\t\tu32 high, u32 low)\n+{\n+\tstruct ecore_llh_filter_e4_details filter_details;\n+\n+\tfilter_details.enable = 1;\n+\tfilter_details.value = ((u64)high << 32) | low;\n+\tfilter_details.hdr_sel =\n+\t\tOSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?\n+\t\t1 : /* inner/encapsulated header */\n+\t\t0;  /* outer/tunnel header */\n+\tfilter_details.protocol_type = filter_prot_type;\n+\tfilter_details.mode = filter_prot_type ?\n+\t\t\t      1 : /* protocol-based classification */\n+\t\t\t      0;  /* MAC-address based classification */\n+\n+\treturn ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,\n+\t\t\t\t\t  &filter_details,\n+\t\t\t\t\t  true /* write access */);\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_remove_filter_e4(struct ecore_hwfn *p_hwfn,\n+\t\t\t   struct ecore_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx)\n+{\n+\tstruct ecore_llh_filter_e4_details filter_details;\n+\n+\tOSAL_MEMSET(&filter_details, 0, sizeof(filter_details));\n+\n+\treturn ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid, filter_idx,\n+\t\t\t\t\t  &filter_details,\n+\t\t\t\t\t  true /* write access */);\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t     u8 abs_ppfid, u8 filter_idx, u8 filter_prot_type, u32 high,\n+\t\t     u32 low)\n+{\n+\treturn ecore_llh_add_filter_e4(p_hwfn, p_ptt, abs_ppfid,\n+\t\t\t\t       filter_idx, filter_prot_type,\n+\t\t\t\t       high, low);\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_remove_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t\tu8 abs_ppfid, u8 filter_idx)\n+{\n+\treturn ecore_llh_remove_filter_e4(p_hwfn, p_ptt, abs_ppfid,\n+\t\t\t\t\t  filter_idx);\n+}\n+\n+enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t\t\t      u8 mac_addr[ETH_ALEN])\n+{\n+\tstruct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);\n+\tstruct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);\n+\tunion ecore_llh_filter filter;\n+\tu8 filter_idx, abs_ppfid;\n+\tu32 high, low, ref_cnt;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tif (p_ptt == OSAL_NULL)\n+\t\treturn ECORE_AGAIN;\n+\n+\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n+\t\tgoto out;\n+\n+\tOSAL_MEM_ZERO(&filter, sizeof(filter));\n+\tOSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);\n+\trc = ecore_llh_shadow_add_filter(p_dev, ppfid,\n+\t\t\t\t\t ECORE_LLH_FILTER_TYPE_MAC,\n+\t\t\t\t\t &filter, &filter_idx, &ref_cnt);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\t/* Configure the LLH only in case of a new the filter */\n+\tif (ref_cnt == 1) {\n+\t\thigh = mac_addr[1] | (mac_addr[0] << 8);\n+\t\tlow = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) |\n+\t\t      (mac_addr[2] << 24);\n+\t\trc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,\n+\t\t\t\t\t  0, high, low);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\tgoto err;\n+\t}\n+\n+\tDP_VERBOSE(p_dev, ECORE_MSG_SP,\n+\t\t   \"LLH: Added MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\\n\",\n+\t\t   mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],\n+\t\t   mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,\n+\t\t   ref_cnt);\n+\n+\tgoto out;\n+\n+err:\n+\tDP_NOTICE(p_dev, false,\n+\t\t  \"LLH: Failed to add MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] to ppfid %hhd\\n\",\n+\t\t  mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],\n+\t\t  mac_addr[4], mac_addr[5], ppfid);\n+out:\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+\n+\treturn rc;\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_protocol_filter_stringify(struct ecore_dev *p_dev,\n+\t\t\t\t    enum ecore_llh_prot_filter_type_t type,\n+\t\t\t\t    u16 source_port_or_eth_type, u16 dest_port,\n+\t\t\t\t    char *str, osal_size_t str_len)\n+{\n+\tswitch (type) {\n+\tcase ECORE_LLH_FILTER_ETHERTYPE:\n+\t\tOSAL_SNPRINTF(str, str_len, \"Ethertype 0x%04x\",\n+\t\t\t      source_port_or_eth_type);\n+\t\tbreak;\n+\tcase ECORE_LLH_FILTER_TCP_SRC_PORT:\n+\t\tOSAL_SNPRINTF(str, str_len, \"TCP src port 0x%04x\",\n+\t\t\t      source_port_or_eth_type);\n+\t\tbreak;\n+\tcase ECORE_LLH_FILTER_UDP_SRC_PORT:\n+\t\tOSAL_SNPRINTF(str, str_len, \"UDP src port 0x%04x\",\n+\t\t\t      source_port_or_eth_type);\n+\t\tbreak;\n+\tcase ECORE_LLH_FILTER_TCP_DEST_PORT:\n+\t\tOSAL_SNPRINTF(str, str_len, \"TCP dst port 0x%04x\", dest_port);\n+\t\tbreak;\n+\tcase ECORE_LLH_FILTER_UDP_DEST_PORT:\n+\t\tOSAL_SNPRINTF(str, str_len, \"UDP dst port 0x%04x\", dest_port);\n+\t\tbreak;\n+\tcase ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:\n+\t\tOSAL_SNPRINTF(str, str_len, \"TCP src/dst ports 0x%04x/0x%04x\",\n+\t\t\t      source_port_or_eth_type, dest_port);\n+\t\tbreak;\n+\tcase ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:\n+\t\tOSAL_SNPRINTF(str, str_len, \"UDP src/dst ports 0x%04x/0x%04x\",\n+\t\t\t      source_port_or_eth_type, dest_port);\n+\t\tbreak;\n+\tdefault:\n+\t\tDP_NOTICE(p_dev, true,\n+\t\t\t  \"Non valid LLH protocol filter type %d\\n\", type);\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_protocol_filter_to_hilo(struct ecore_dev *p_dev,\n+\t\t\t\t  enum ecore_llh_prot_filter_type_t type,\n+\t\t\t\t  u16 source_port_or_eth_type, u16 dest_port,\n+\t\t\t\t  u32 *p_high, u32 *p_low)\n+{\n+\t*p_high = 0;\n+\t*p_low = 0;\n+\n+\tswitch (type) {\n+\tcase ECORE_LLH_FILTER_ETHERTYPE:\n+\t\t*p_high = source_port_or_eth_type;\n+\t\tbreak;\n+\tcase ECORE_LLH_FILTER_TCP_SRC_PORT:\n+\tcase ECORE_LLH_FILTER_UDP_SRC_PORT:\n+\t\t*p_low = source_port_or_eth_type << 16;\n+\t\tbreak;\n+\tcase ECORE_LLH_FILTER_TCP_DEST_PORT:\n+\tcase ECORE_LLH_FILTER_UDP_DEST_PORT:\n+\t\t*p_low = dest_port;\n+\t\tbreak;\n+\tcase ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:\n+\tcase ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:\n+\t\t*p_low = (source_port_or_eth_type << 16) | dest_port;\n+\t\tbreak;\n+\tdefault:\n+\t\tDP_NOTICE(p_dev, true,\n+\t\t\t  \"Non valid LLH protocol filter type %d\\n\", type);\n+\t\treturn ECORE_INVAL;\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+enum _ecore_status_t\n+ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t      enum ecore_llh_prot_filter_type_t type,\n+\t\t\t      u16 source_port_or_eth_type, u16 dest_port)\n+{\n+\tstruct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);\n+\tstruct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);\n+\tu8 filter_idx, abs_ppfid, type_bitmap;\n+\tchar str[32];\n+\tunion ecore_llh_filter filter;\n+\tu32 high, low, ref_cnt;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tif (p_ptt == OSAL_NULL)\n+\t\treturn ECORE_AGAIN;\n+\n+\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))\n+\t\tgoto out;\n+\n+\trc = ecore_llh_protocol_filter_stringify(p_dev, type,\n+\t\t\t\t\t\t source_port_or_eth_type,\n+\t\t\t\t\t\t dest_port, str, sizeof(str));\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\tOSAL_MEM_ZERO(&filter, sizeof(filter));\n+\tfilter.protocol.type = type;\n+\tfilter.protocol.source_port_or_eth_type = source_port_or_eth_type;\n+\tfilter.protocol.dest_port = dest_port;\n+\trc = ecore_llh_shadow_add_filter(p_dev, ppfid,\n+\t\t\t\t\t ECORE_LLH_FILTER_TYPE_PROTOCOL,\n+\t\t\t\t\t &filter, &filter_idx, &ref_cnt);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\t/* Configure the LLH only in case of a new the filter */\n+\tif (ref_cnt == 1) {\n+\t\trc = ecore_llh_protocol_filter_to_hilo(p_dev, type,\n+\t\t\t\t\t\t       source_port_or_eth_type,\n+\t\t\t\t\t\t       dest_port, &high, &low);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\tgoto err;\n+\n+\t\ttype_bitmap = 0x1 << type;\n+\t\trc = ecore_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx,\n+\t\t\t\t\t  type_bitmap, high, low);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\tgoto err;\n+\t}\n+\n+\tDP_VERBOSE(p_dev, ECORE_MSG_SP,\n+\t\t   \"LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\\n\",\n+\t\t   str, ppfid, abs_ppfid, filter_idx, ref_cnt);\n+\n+\tgoto out;\n+\n+err:\n+\tDP_NOTICE(p_hwfn, false,\n+\t\t  \"LLH: Failed to add protocol filter [%s] to ppfid %hhd\\n\",\n+\t\t  str, ppfid);\n+out:\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+\n+\treturn rc;\n+}\n+\n+void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t\t u8 mac_addr[ETH_ALEN])\n+{\n+\tstruct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);\n+\tstruct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);\n+\tunion ecore_llh_filter filter;\n+\tu8 filter_idx, abs_ppfid;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tu32 ref_cnt;\n+\n+\tif (p_ptt == OSAL_NULL)\n+\t\treturn;\n+\n+\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n+\t\tgoto out;\n+\n+\tOSAL_MEM_ZERO(&filter, sizeof(filter));\n+\tOSAL_MEMCPY(filter.mac.addr, mac_addr, ETH_ALEN);\n+\trc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,\n+\t\t\t\t\t    &ref_cnt);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\t/* Remove from the LLH in case the filter is not in use */\n+\tif (!ref_cnt) {\n+\t\trc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,\n+\t\t\t\t\t     filter_idx);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\tgoto err;\n+\t}\n+\n+\tDP_VERBOSE(p_dev, ECORE_MSG_SP,\n+\t\t   \"LLH: Removed MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\\n\",\n+\t\t   mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],\n+\t\t   mac_addr[4], mac_addr[5], ppfid, abs_ppfid, filter_idx,\n+\t\t   ref_cnt);\n+\n+\tgoto out;\n+\n+err:\n+\tDP_NOTICE(p_dev, false,\n+\t\t  \"LLH: Failed to remove MAC filter [%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx] from ppfid %hhd\\n\",\n+\t\t  mac_addr[0], mac_addr[1], mac_addr[2], mac_addr[3],\n+\t\t  mac_addr[4], mac_addr[5], ppfid);\n+out:\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+}\n+\n+void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t\t      enum ecore_llh_prot_filter_type_t type,\n+\t\t\t\t      u16 source_port_or_eth_type,\n+\t\t\t\t      u16 dest_port)\n+{\n+\tstruct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);\n+\tstruct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);\n+\tu8 filter_idx, abs_ppfid;\n+\tchar str[32];\n+\tunion ecore_llh_filter filter;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\tu32 ref_cnt;\n+\n+\tif (p_ptt == OSAL_NULL)\n+\t\treturn;\n+\n+\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))\n+\t\tgoto out;\n+\n+\trc = ecore_llh_protocol_filter_stringify(p_dev, type,\n+\t\t\t\t\t\t source_port_or_eth_type,\n+\t\t\t\t\t\t dest_port, str, sizeof(str));\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\tOSAL_MEM_ZERO(&filter, sizeof(filter));\n+\tfilter.protocol.type = type;\n+\tfilter.protocol.source_port_or_eth_type = source_port_or_eth_type;\n+\tfilter.protocol.dest_port = dest_port;\n+\trc = ecore_llh_shadow_remove_filter(p_dev, ppfid, &filter, &filter_idx,\n+\t\t\t\t\t    &ref_cnt);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto err;\n+\n+\t/* Remove from the LLH in case the filter is not in use */\n+\tif (!ref_cnt) {\n+\t\trc = ecore_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid,\n+\t\t\t\t\t     filter_idx);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\tgoto err;\n+\t}\n+\n+\tDP_VERBOSE(p_dev, ECORE_MSG_SP,\n+\t\t   \"LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\\n\",\n+\t\t   str, ppfid, abs_ppfid, filter_idx, ref_cnt);\n+\n+\tgoto out;\n+\n+err:\n+\tDP_NOTICE(p_dev, false,\n+\t\t  \"LLH: Failed to remove protocol filter [%s] from ppfid %hhd\\n\",\n+\t\t  str, ppfid);\n+out:\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+}\n+\n+void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)\n+{\n+\tstruct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);\n+\tstruct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);\n+\tu8 filter_idx, abs_ppfid;\n+\tenum _ecore_status_t rc = ECORE_SUCCESS;\n+\n+\tif (p_ptt == OSAL_NULL)\n+\t\treturn;\n+\n+\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&\n+\t    !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n+\t\tgoto out;\n+\n+\trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto out;\n+\n+\trc = ecore_llh_shadow_remove_all_filters(p_dev, ppfid);\n+\tif (rc != ECORE_SUCCESS)\n+\t\tgoto out;\n+\n+\tfor (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;\n+\t     filter_idx++) {\n+\t\trc = ecore_llh_remove_filter_e4(p_hwfn, p_ptt,\n+\t\t\t\t\t\tabs_ppfid, filter_idx);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\tgoto out;\n+\t}\n+out:\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+}\n+\n+void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)\n+{\n+\tu8 ppfid;\n+\n+\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&\n+\t    !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))\n+\t\treturn;\n+\n+\tfor (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)\n+\t\tecore_llh_clear_ppfid_filters(p_dev, ppfid);\n+}\n+\n+enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t struct ecore_ptt *p_ptt, u32 addr,\n+\t\t\t\t\t u32 val)\n+{\n+\tstruct ecore_dev *p_dev = p_hwfn->p_dev;\n+\tu8 ppfid, abs_ppfid;\n+\tenum _ecore_status_t rc;\n+\n+\tfor (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {\n+\t\trc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\treturn rc;\n+\n+\t\tecore_ppfid_wr(p_hwfn, p_ptt, abs_ppfid, addr, val);\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+static enum _ecore_status_t\n+ecore_llh_dump_ppfid_e4(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t\tu8 ppfid)\n+{\n+\tstruct ecore_llh_filter_e4_details filter_details;\n+\tu8 abs_ppfid, filter_idx;\n+\tu32 addr;\n+\tenum _ecore_status_t rc;\n+\n+\trc = ecore_abs_ppfid(p_hwfn->p_dev, ppfid, &abs_ppfid);\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\taddr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4;\n+\tDP_NOTICE(p_hwfn, false,\n+\t\t  \"[rel_pf_id %hhd, ppfid={rel %hhd, abs %hhd}, engine_sel 0x%x]\\n\",\n+\t\t  p_hwfn->rel_pf_id, ppfid, abs_ppfid,\n+\t\t  ecore_rd(p_hwfn, p_ptt, addr));\n+\n+\tfor (filter_idx = 0; filter_idx < NIG_REG_LLH_FUNC_FILTER_EN_SIZE;\n+\t     filter_idx++) {\n+\t\tOSAL_MEMSET(&filter_details, 0, sizeof(filter_details));\n+\t\trc =  ecore_llh_access_filter_e4(p_hwfn, p_ptt, abs_ppfid,\n+\t\t\t\t\t\t filter_idx, &filter_details,\n+\t\t\t\t\t\t false /* read access */);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\treturn rc;\n+\n+\t\tDP_NOTICE(p_hwfn, false,\n+\t\t\t  \"filter %2hhd: enable %d, value 0x%016lx, mode %d, protocol_type 0x%x, hdr_sel 0x%x\\n\",\n+\t\t\t  filter_idx, filter_details.enable,\n+\t\t\t  (unsigned long)filter_details.value,\n+\t\t\t  filter_details.mode,\n+\t\t\t  filter_details.protocol_type, filter_details.hdr_sel);\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid)\n+{\n+\tstruct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);\n+\tstruct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);\n+\tenum _ecore_status_t rc;\n+\n+\tif (p_ptt == OSAL_NULL)\n+\t\treturn ECORE_AGAIN;\n+\n+\trc = ecore_llh_dump_ppfid_e4(p_hwfn, p_ptt, ppfid);\n+\n+\tecore_ptt_release(p_hwfn, p_ptt);\n+\n+\treturn rc;\n+}\n+\n+enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev)\n+{\n+\tu8 ppfid;\n+\tenum _ecore_status_t rc;\n+\n+\tfor (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++) {\n+\t\trc = ecore_llh_dump_ppfid(p_dev, ppfid);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\treturn rc;\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+/******************************* NIG LLH - End ********************************/\n+\n /* Configurable */\n #define ECORE_MIN_DPIS\t\t(4)\t/* The minimal num of DPIs required to\n \t\t\t\t\t * load the driver. The number was\n@@ -476,6 +1659,8 @@ void ecore_resc_free(struct ecore_dev *p_dev)\n \n \tOSAL_FREE(p_dev, p_dev->reset_stats);\n \n+\tecore_llh_free(p_dev);\n+\n \tfor_each_hwfn(p_dev, i) {\n \t\tstruct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];\n \n@@ -1349,6 +2534,13 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)\n \t\t}\n \t} /* hwfn loop */\n \n+\trc = ecore_llh_alloc(p_dev);\n+\tif (rc != ECORE_SUCCESS) {\n+\t\tDP_NOTICE(p_dev, true,\n+\t\t\t  \"Failed to allocate memory for the llh_info structure\\n\");\n+\t\tgoto alloc_err;\n+\t}\n+\n \tp_dev->reset_stats = OSAL_ZALLOC(p_dev, GFP_KERNEL,\n \t\t\t\t\t sizeof(*p_dev->reset_stats));\n \tif (!p_dev->reset_stats) {\n@@ -1489,8 +2681,7 @@ static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)\n \t\treturn ECORE_INVAL;\n \t}\n \n-\tif (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS,\n-\t\t\t  &p_hwfn->p_dev->mf_bits))\n+\tif (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))\n \t\thw_mode |= 1 << MODE_MF_SD;\n \telse\n \t\thw_mode |= 1 << MODE_MF_SI;\n@@ -2094,17 +3285,7 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t       struct ecore_ptt *p_ptt,\n \t\t\t\t\t       int hw_mode)\n {\n-\tu32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];\n-\tu32 val;\n \tenum _ecore_status_t rc\t= ECORE_SUCCESS;\n-\tu8 i;\n-\n-\t/* In CMT for non-RoCE packets - use connection based classification */\n-\tval = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;\n-\tfor (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)\n-\t\tppf_to_eng_sel[i] = val;\n-\tSTORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,\n-\t\t\t ppf_to_eng_sel);\n \n \t/* In CMT the gate should be cleared by the 2nd hwfn */\n \tif (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))\n@@ -2156,12 +3337,8 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,\n }\n \n static enum _ecore_status_t\n-ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,\n-\t\t struct ecore_ptt *p_ptt,\n-\t\t struct ecore_tunnel_info *p_tunn,\n-\t\t int hw_mode,\n-\t\t bool b_hw_start,\n-\t\t enum ecore_int_mode int_mode, bool allow_npar_tx_switch)\n+ecore_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t int hw_mode, struct ecore_hw_init_params *p_params)\n {\n \tu8 rel_pf_id = p_hwfn->rel_pf_id;\n \tu32 prs_reg;\n@@ -2249,17 +3426,18 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,\n \t*/\n \n \trc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);\n-\tif (rc)\n+\tif (rc != ECORE_SUCCESS)\n \t\treturn rc;\n-\tif (b_hw_start) {\n+\n+\tif (p_params->b_hw_start) {\n \t\t/* enable interrupts */\n-\t\trc = ecore_int_igu_enable(p_hwfn, p_ptt, int_mode);\n+\t\trc = ecore_int_igu_enable(p_hwfn, p_ptt, p_params->int_mode);\n \t\tif (rc != ECORE_SUCCESS)\n \t\t\treturn rc;\n \n \t\t/* send function start command */\n-\t\trc = ecore_sp_pf_start(p_hwfn, p_ptt, p_tunn,\n-\t\t\t\t       allow_npar_tx_switch);\n+\t\trc = ecore_sp_pf_start(p_hwfn, p_ptt, p_params->p_tunn,\n+\t\t\t\t       p_params->allow_npar_tx_switch);\n \t\tif (rc) {\n \t\t\tDP_NOTICE(p_hwfn, true,\n \t\t\t\t  \"Function start ramrod failed\\n\");\n@@ -2583,11 +3761,8 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,\n \t\t\t/* Fall into */\n \t\tcase FW_MSG_CODE_DRV_LOAD_FUNCTION:\n \t\t\trc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,\n-\t\t\t\t\t      p_params->p_tunn,\n \t\t\t\t\t      p_hwfn->hw_info.hw_mode,\n-\t\t\t\t\t      p_params->b_hw_start,\n-\t\t\t\t\t      p_params->int_mode,\n-\t\t\t\t\t      p_params->allow_npar_tx_switch);\n+\t\t\t\t\t      p_params);\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tDP_NOTICE(p_hwfn, false,\n@@ -2859,6 +4034,12 @@ enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)\n \t\t/* Need to wait 1ms to guarantee SBs are cleared */\n \t\tOSAL_MSLEEP(1);\n \n+\t\tif (IS_LEAD_HWFN(p_hwfn) &&\n+\t\t    OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&\n+\t\t    !ECORE_IS_FCOE_PERSONALITY(p_hwfn))\n+\t\t\tecore_llh_remove_mac_filter(p_dev, 0,\n+\t\t\t\t\t\t   p_hwfn->hw_info.hw_mac_addr);\n+\n \t\tif (!p_dev->recov_in_prog) {\n \t\t\tecore_verify_reg_val(p_hwfn, p_ptt,\n \t\t\t\t\t     QM_REG_USG_CNT_PF_TX, 0);\n@@ -3372,6 +4553,59 @@ static enum _ecore_status_t ecore_hw_set_resc_info(struct ecore_hwfn *p_hwfn,\n \treturn ECORE_SUCCESS;\n }\n \n+#define ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS\t0xaa\n+#define ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS\t0x55\n+#define ECORE_NONUSED_PPFID_MASK_AH_4P\t\t0xf0\n+\n+static enum _ecore_status_t ecore_hw_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\t      struct ecore_ptt *p_ptt)\n+{\n+\tu8 native_ppfid_idx = ECORE_PPFID_BY_PFID(p_hwfn), new_bitmap;\n+\tstruct ecore_dev *p_dev = p_hwfn->p_dev;\n+\tenum _ecore_status_t rc;\n+\n+\trc = ecore_mcp_get_ppfid_bitmap(p_hwfn, p_ptt);\n+\tif (rc != ECORE_SUCCESS && rc != ECORE_NOTIMPL)\n+\t\treturn rc;\n+\telse if (rc == ECORE_NOTIMPL)\n+\t\tp_dev->ppfid_bitmap = 0x1 << native_ppfid_idx;\n+\n+\t/* 4-ports mode has limitations that should be enforced:\n+\t * - BB: the MFW can access only PPFIDs which their corresponding PFIDs\n+\t *       belong to this certain port.\n+\t * - AH/E5: only 4 PPFIDs per port are available.\n+\t */\n+\tif (ecore_device_num_ports(p_dev) == 4) {\n+\t\tu8 mask;\n+\n+\t\tif (ECORE_IS_BB(p_dev))\n+\t\t\tmask = MFW_PORT(p_hwfn) > 1 ?\n+\t\t\t       ECORE_NONUSED_PPFID_MASK_BB_4P_HI_PORTS :\n+\t\t\t       ECORE_NONUSED_PPFID_MASK_BB_4P_LO_PORTS;\n+\t\telse\n+\t\t\tmask = ECORE_NONUSED_PPFID_MASK_AH_4P;\n+\n+\t\tif (p_dev->ppfid_bitmap & mask) {\n+\t\t\tnew_bitmap = p_dev->ppfid_bitmap & ~mask;\n+\t\t\tDP_INFO(p_hwfn,\n+\t\t\t\t\"Fix the PPFID bitmap for 4-ports mode: 0x%hhx -> 0x%hhx\\n\",\n+\t\t\t\tp_dev->ppfid_bitmap, new_bitmap);\n+\t\t\tp_dev->ppfid_bitmap = new_bitmap;\n+\t\t}\n+\t}\n+\n+\t/* The native PPFID is expected to be part of the allocated bitmap */\n+\tif (!(p_dev->ppfid_bitmap & (0x1 << native_ppfid_idx))) {\n+\t\tnew_bitmap = 0x1 << native_ppfid_idx;\n+\t\tDP_INFO(p_hwfn,\n+\t\t\t\"Fix the PPFID bitmap to inculde the native PPFID: %hhd -> 0x%hhx\\n\",\n+\t\t\tp_dev->ppfid_bitmap, new_bitmap);\n+\t\tp_dev->ppfid_bitmap = new_bitmap;\n+\t}\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t      struct ecore_ptt *p_ptt,\n \t\t\t\t\t      bool drv_resc_alloc)\n@@ -3446,6 +4680,13 @@ static enum _ecore_status_t ecore_hw_get_resc(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\"Failed to release the resource lock for the resource allocation commands\\n\");\n \t}\n \n+\t/* PPFID bitmap */\n+\tif (IS_LEAD_HWFN(p_hwfn)) {\n+\t\trc = ecore_hw_get_ppfid_bitmap(p_hwfn, p_ptt);\n+\t\tif (rc != ECORE_SUCCESS)\n+\t\t\treturn rc;\n+\t}\n+\n #ifndef ASIC_ONLY\n \tif (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {\n \t\t/* Reduced build contains less PQs */\n@@ -4236,9 +5477,8 @@ void ecore_prepare_hibernate(struct ecore_dev *p_dev)\n #endif\n \n static enum _ecore_status_t\n-ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn,\n-\t\t\tvoid OSAL_IOMEM * p_regview,\n-\t\t\tvoid OSAL_IOMEM * p_doorbells,\n+ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,\n+\t\t\tvoid OSAL_IOMEM *p_doorbells, u64 db_phys_addr,\n \t\t\tstruct ecore_hw_prepare_params *p_params)\n {\n \tstruct ecore_mdump_retain_data mdump_retain;\n@@ -4249,6 +5489,7 @@ void ecore_prepare_hibernate(struct ecore_dev *p_dev)\n \t/* Split PCI bars evenly between hwfns */\n \tp_hwfn->regview = p_regview;\n \tp_hwfn->doorbells = p_doorbells;\n+\tp_hwfn->db_phys_addr = db_phys_addr;\n \n \tif (IS_VF(p_dev))\n \t\treturn ecore_vf_hw_prepare(p_hwfn);\n@@ -4401,9 +5642,9 @@ enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,\n \t\tecore_init_iro_array(p_dev);\n \n \t/* Initialize the first hwfn - will learn number of hwfns */\n-\trc = ecore_hw_prepare_single(p_hwfn,\n-\t\t\t\t     p_dev->regview,\n-\t\t\t\t     p_dev->doorbells, p_params);\n+\trc = ecore_hw_prepare_single(p_hwfn, p_dev->regview,\n+\t\t\t\t     p_dev->doorbells, p_dev->db_phys_addr,\n+\t\t\t\t     p_params);\n \tif (rc != ECORE_SUCCESS)\n \t\treturn rc;\n \n@@ -4413,24 +5654,26 @@ enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,\n \tif (ECORE_IS_CMT(p_dev)) {\n \t\tvoid OSAL_IOMEM *p_regview, *p_doorbell;\n \t\tu8 OSAL_IOMEM *addr;\n+\t\tu64 db_phys_addr;\n+\t\tu32 offset;\n \n \t\t/* adjust bar offset for second engine */\n-\t\taddr = (u8 OSAL_IOMEM *)p_dev->regview +\n-\t\t\t\t\tecore_hw_bar_size(p_hwfn,\n-\t\t\t\t\t\t\t  p_hwfn->p_main_ptt,\n-\t\t\t\t\t\t\t  BAR_ID_0) / 2;\n+\t\toffset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t\t   BAR_ID_0) / 2;\n+\t\taddr = (u8 OSAL_IOMEM *)p_dev->regview + offset;\n \t\tp_regview = (void OSAL_IOMEM *)addr;\n \n-\t\taddr = (u8 OSAL_IOMEM *)p_dev->doorbells +\n-\t\t\t\t\tecore_hw_bar_size(p_hwfn,\n-\t\t\t\t\t\t\t  p_hwfn->p_main_ptt,\n-\t\t\t\t\t\t\t  BAR_ID_1) / 2;\n+\t\toffset = ecore_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt,\n+\t\t\t\t\t   BAR_ID_1) / 2;\n+\t\taddr = (u8 OSAL_IOMEM *)p_dev->doorbells + offset;\n \t\tp_doorbell = (void OSAL_IOMEM *)addr;\n+\t\tdb_phys_addr = p_dev->db_phys_addr + offset;\n \n \t\tp_dev->hwfns[1].b_en_pacing = p_params->b_en_pacing;\n \t\t/* prepare second hw function */\n \t\trc = ecore_hw_prepare_single(&p_dev->hwfns[1], p_regview,\n-\t\t\t\t\t     p_doorbell, p_params);\n+\t\t\t\t\t     p_doorbell, db_phys_addr,\n+\t\t\t\t\t     p_params);\n \n \t\t/* in case of error, need to free the previously\n \t\t * initiliazed hwfn 0.\n@@ -4827,419 +6070,6 @@ enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,\n \treturn ECORE_SUCCESS;\n }\n \n-static enum _ecore_status_t\n-ecore_llh_add_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,\n-\t\t\t       struct ecore_ptt *p_ptt, u32 high, u32 low,\n-\t\t\t       u32 *p_entry_num)\n-{\n-\tu32 en;\n-\tint i;\n-\n-\t/* Find a free entry and utilize it */\n-\tfor (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {\n-\t\ten = ecore_rd(p_hwfn, p_ptt,\n-\t\t\t      NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +\n-\t\t\t      i * sizeof(u32));\n-\t\tif (en)\n-\t\t\tcontinue;\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t 2 * i * sizeof(u32), low);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t (2 * i + 1) * sizeof(u32), high);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +\n-\t\t\t i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +\n-\t\t\t i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +\n-\t\t\t i * sizeof(u32), 1);\n-\t\tbreak;\n-\t}\n-\n-\tif (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)\n-\t\treturn ECORE_NORESOURCES;\n-\n-\t*p_entry_num = i;\n-\n-\treturn ECORE_SUCCESS;\n-}\n-\n-enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t  struct ecore_ptt *p_ptt, u8 *p_filter)\n-{\n-\tu32 high, low, entry_num;\n-\tenum _ecore_status_t rc = ECORE_SUCCESS;\n-\n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,\n-\t\t\t   &p_hwfn->p_dev->mf_bits))\n-\t\treturn ECORE_SUCCESS;\n-\n-\thigh = p_filter[1] | (p_filter[0] << 8);\n-\tlow = p_filter[5] | (p_filter[4] << 8) |\n-\t      (p_filter[3] << 16) | (p_filter[2] << 24);\n-\n-\tif (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))\n-\t\trc = ecore_llh_add_mac_filter_bb_ah(p_hwfn, p_ptt, high, low,\n-\t\t\t\t\t\t    &entry_num);\n-\tif (rc != ECORE_SUCCESS) {\n-\t\tDP_NOTICE(p_hwfn, false,\n-\t\t\t  \"Failed to find an empty LLH filter to utilize\\n\");\n-\t\treturn rc;\n-\t}\n-\n-\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t   \"MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx is added at %d\\n\",\n-\t\t   p_filter[0], p_filter[1], p_filter[2], p_filter[3],\n-\t\t   p_filter[4], p_filter[5], entry_num);\n-\n-\treturn rc;\n-}\n-\n-static enum _ecore_status_t\n-ecore_llh_remove_mac_filter_bb_ah(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t  struct ecore_ptt *p_ptt, u32 high, u32 low,\n-\t\t\t\t  u32 *p_entry_num)\n-{\n-\tint i;\n-\n-\t/* Find the entry and clean it */\n-\tfor (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {\n-\t\tif (ecore_rd(p_hwfn, p_ptt,\n-\t\t\t     NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t     2 * i * sizeof(u32)) != low)\n-\t\t\tcontinue;\n-\t\tif (ecore_rd(p_hwfn, p_ptt,\n-\t\t\t     NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t     (2 * i + 1) * sizeof(u32)) != high)\n-\t\t\tcontinue;\n-\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t 2 * i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t (2 * i + 1) * sizeof(u32), 0);\n-\t\tbreak;\n-\t}\n-\n-\tif (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)\n-\t\treturn ECORE_INVAL;\n-\n-\t*p_entry_num = i;\n-\n-\treturn ECORE_SUCCESS;\n-}\n-\n-void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t     struct ecore_ptt *p_ptt, u8 *p_filter)\n-{\n-\tu32 high, low, entry_num;\n-\tenum _ecore_status_t rc = ECORE_SUCCESS;\n-\n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,\n-\t\t\t   &p_hwfn->p_dev->mf_bits))\n-\t\treturn;\n-\n-\thigh = p_filter[1] | (p_filter[0] << 8);\n-\tlow = p_filter[5] | (p_filter[4] << 8) |\n-\t      (p_filter[3] << 16) | (p_filter[2] << 24);\n-\n-\tif (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))\n-\t\trc = ecore_llh_remove_mac_filter_bb_ah(p_hwfn, p_ptt, high,\n-\t\t\t\t\t\t       low, &entry_num);\n-\tif (rc != ECORE_SUCCESS) {\n-\t\tDP_NOTICE(p_hwfn, false,\n-\t\t\t  \"Tried to remove a non-configured filter\\n\");\n-\t\treturn;\n-\t}\n-\n-\n-\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t   \"MAC: %02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx was removed from %d\\n\",\n-\t\t   p_filter[0], p_filter[1], p_filter[2], p_filter[3],\n-\t\t   p_filter[4], p_filter[5], entry_num);\n-}\n-\n-static enum _ecore_status_t\n-ecore_llh_add_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t    struct ecore_ptt *p_ptt,\n-\t\t\t\t    enum ecore_llh_port_filter_type_t type,\n-\t\t\t\t    u32 high, u32 low, u32 *p_entry_num)\n-{\n-\tu32 en;\n-\tint i;\n-\n-\t/* Find a free entry and utilize it */\n-\tfor (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {\n-\t\ten = ecore_rd(p_hwfn, p_ptt,\n-\t\t\t      NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +\n-\t\t\t      i * sizeof(u32));\n-\t\tif (en)\n-\t\t\tcontinue;\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t 2 * i * sizeof(u32), low);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t (2 * i + 1) * sizeof(u32), high);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +\n-\t\t\t i * sizeof(u32), 1);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +\n-\t\t\t i * sizeof(u32), 1 << type);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 1);\n-\t\tbreak;\n-\t}\n-\n-\tif (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)\n-\t\treturn ECORE_NORESOURCES;\n-\n-\t*p_entry_num = i;\n-\n-\treturn ECORE_SUCCESS;\n-}\n-\n-enum _ecore_status_t\n-ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t      struct ecore_ptt *p_ptt,\n-\t\t\t      u16 source_port_or_eth_type,\n-\t\t\t      u16 dest_port,\n-\t\t\t      enum ecore_llh_port_filter_type_t type)\n-{\n-\tu32 high, low, entry_num;\n-\tenum _ecore_status_t rc = ECORE_SUCCESS;\n-\n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,\n-\t\t\t   &p_hwfn->p_dev->mf_bits))\n-\t\treturn rc;\n-\n-\thigh = 0;\n-\tlow = 0;\n-\n-\tswitch (type) {\n-\tcase ECORE_LLH_FILTER_ETHERTYPE:\n-\t\thigh = source_port_or_eth_type;\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_TCP_SRC_PORT:\n-\tcase ECORE_LLH_FILTER_UDP_SRC_PORT:\n-\t\tlow = source_port_or_eth_type << 16;\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_TCP_DEST_PORT:\n-\tcase ECORE_LLH_FILTER_UDP_DEST_PORT:\n-\t\tlow = dest_port;\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:\n-\tcase ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:\n-\t\tlow = (source_port_or_eth_type << 16) | dest_port;\n-\t\tbreak;\n-\tdefault:\n-\t\tDP_NOTICE(p_hwfn, true,\n-\t\t\t  \"Non valid LLH protocol filter type %d\\n\", type);\n-\t\treturn ECORE_INVAL;\n-\t}\n-\n-\tif (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))\n-\t\trc = ecore_llh_add_protocol_filter_bb_ah(p_hwfn, p_ptt, type,\n-\t\t\t\t\t\t\t high, low, &entry_num);\n-\tif (rc != ECORE_SUCCESS) {\n-\t\tDP_NOTICE(p_hwfn, false,\n-\t\t\t  \"Failed to find an empty LLH filter to utilize\\n\");\n-\t\treturn rc;\n-\t}\n-\tswitch (type) {\n-\tcase ECORE_LLH_FILTER_ETHERTYPE:\n-\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t\t   \"ETH type %x is added at %d\\n\",\n-\t\t\t   source_port_or_eth_type, entry_num);\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_TCP_SRC_PORT:\n-\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t\t   \"TCP src port %x is added at %d\\n\",\n-\t\t\t   source_port_or_eth_type, entry_num);\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_UDP_SRC_PORT:\n-\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t\t   \"UDP src port %x is added at %d\\n\",\n-\t\t\t   source_port_or_eth_type, entry_num);\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_TCP_DEST_PORT:\n-\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t\t   \"TCP dst port %x is added at %d\\n\", dest_port,\n-\t\t\t   entry_num);\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_UDP_DEST_PORT:\n-\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t\t   \"UDP dst port %x is added at %d\\n\", dest_port,\n-\t\t\t   entry_num);\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:\n-\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t\t   \"TCP src/dst ports %x/%x are added at %d\\n\",\n-\t\t\t   source_port_or_eth_type, dest_port, entry_num);\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:\n-\t\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t\t   \"UDP src/dst ports %x/%x are added at %d\\n\",\n-\t\t\t   source_port_or_eth_type, dest_port, entry_num);\n-\t\tbreak;\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static enum _ecore_status_t\n-ecore_llh_remove_protocol_filter_bb_ah(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t       struct ecore_ptt *p_ptt,\n-\t\t\t\t       enum ecore_llh_port_filter_type_t type,\n-\t\t\t\t       u32 high, u32 low, u32 *p_entry_num)\n-{\n-\tint i;\n-\n-\t/* Find the entry and clean it */\n-\tfor (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {\n-\t\tif (!ecore_rd(p_hwfn, p_ptt,\n-\t\t\t      NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 +\n-\t\t\t      i * sizeof(u32)))\n-\t\t\tcontinue;\n-\t\tif (!ecore_rd(p_hwfn, p_ptt,\n-\t\t\t      NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +\n-\t\t\t      i * sizeof(u32)))\n-\t\t\tcontinue;\n-\t\tif (!(ecore_rd(p_hwfn, p_ptt,\n-\t\t\t       NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +\n-\t\t\t       i * sizeof(u32)) & (1 << type)))\n-\t\t\tcontinue;\n-\t\tif (ecore_rd(p_hwfn, p_ptt,\n-\t\t\t     NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t     2 * i * sizeof(u32)) != low)\n-\t\t\tcontinue;\n-\t\tif (ecore_rd(p_hwfn, p_ptt,\n-\t\t\t     NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t     (2 * i + 1) * sizeof(u32)) != high)\n-\t\t\tcontinue;\n-\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_EN_BB_K2 + i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_MODE_BB_K2 +\n-\t\t\t i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_BB_K2 +\n-\t\t\t i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t 2 * i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t (2 * i + 1) * sizeof(u32), 0);\n-\t\tbreak;\n-\t}\n-\n-\tif (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE)\n-\t\treturn ECORE_INVAL;\n-\n-\t*p_entry_num = i;\n-\n-\treturn ECORE_SUCCESS;\n-}\n-\n-void\n-ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t struct ecore_ptt *p_ptt,\n-\t\t\t\t u16 source_port_or_eth_type,\n-\t\t\t\t u16 dest_port,\n-\t\t\t\t enum ecore_llh_port_filter_type_t type)\n-{\n-\tu32 high, low, entry_num;\n-\tenum _ecore_status_t rc = ECORE_SUCCESS;\n-\n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,\n-\t\t\t   &p_hwfn->p_dev->mf_bits))\n-\t\treturn;\n-\n-\thigh = 0;\n-\tlow = 0;\n-\n-\tswitch (type) {\n-\tcase ECORE_LLH_FILTER_ETHERTYPE:\n-\t\thigh = source_port_or_eth_type;\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_TCP_SRC_PORT:\n-\tcase ECORE_LLH_FILTER_UDP_SRC_PORT:\n-\t\tlow = source_port_or_eth_type << 16;\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_TCP_DEST_PORT:\n-\tcase ECORE_LLH_FILTER_UDP_DEST_PORT:\n-\t\tlow = dest_port;\n-\t\tbreak;\n-\tcase ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT:\n-\tcase ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT:\n-\t\tlow = (source_port_or_eth_type << 16) | dest_port;\n-\t\tbreak;\n-\tdefault:\n-\t\tDP_NOTICE(p_hwfn, true,\n-\t\t\t  \"Non valid LLH protocol filter type %d\\n\", type);\n-\t\treturn;\n-\t}\n-\n-\tif (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))\n-\t\trc = ecore_llh_remove_protocol_filter_bb_ah(p_hwfn, p_ptt, type,\n-\t\t\t\t\t\t\t    high, low,\n-\t\t\t\t\t\t\t    &entry_num);\n-\tif (rc != ECORE_SUCCESS) {\n-\t\tDP_NOTICE(p_hwfn, false,\n-\t\t\t  \"Tried to remove a non-configured filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x]\\n\",\n-\t\t\t  type, source_port_or_eth_type, dest_port);\n-\t\treturn;\n-\t}\n-\n-\tDP_VERBOSE(p_hwfn, ECORE_MSG_HW,\n-\t\t   \"Protocol filter [type %d, source_port_or_eth_type 0x%x, dest_port 0x%x] was removed from %d\\n\",\n-\t\t   type, source_port_or_eth_type, dest_port, entry_num);\n-}\n-\n-static void ecore_llh_clear_all_filters_bb_ah(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t      struct ecore_ptt *p_ptt)\n-{\n-\tint i;\n-\n-\tif (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn)))\n-\t\treturn;\n-\n-\tfor (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) {\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_EN_BB_K2  +\n-\t\t\t i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t 2 * i * sizeof(u32), 0);\n-\t\tecore_wr(p_hwfn, p_ptt,\n-\t\t\t NIG_REG_LLH_FUNC_FILTER_VALUE_BB_K2 +\n-\t\t\t (2 * i + 1) * sizeof(u32), 0);\n-\t}\n-}\n-\n-void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,\n-\t\t\t     struct ecore_ptt *p_ptt)\n-{\n-\tif (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS,\n-\t\t\t   &p_hwfn->p_dev->mf_bits) &&\n-\t    !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS,\n-\t\t\t   &p_hwfn->p_dev->mf_bits))\n-\t\treturn;\n-\n-\tif (ECORE_IS_BB(p_hwfn->p_dev) || ECORE_IS_AH(p_hwfn->p_dev))\n-\t\tecore_llh_clear_all_filters_bb_ah(p_hwfn, p_ptt);\n-}\n-\n enum _ecore_status_t\n ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,\n \t\t\t\t  struct ecore_ptt *p_ptt)\ndiff --git a/drivers/net/qede/base/ecore_dev_api.h b/drivers/net/qede/base/ecore_dev_api.h\nindex ab80b52..7308063 100644\n--- a/drivers/net/qede/base/ecore_dev_api.h\n+++ b/drivers/net/qede/base/ecore_dev_api.h\n@@ -114,6 +114,9 @@ struct ecore_hw_init_params {\n \t/* Driver load parameters */\n \tstruct ecore_drv_load_params *p_drv_load_params;\n \n+\t/* Avoid engine affinity for RoCE/storage in case of CMT mode */\n+\tbool avoid_eng_affin;\n+\n \t/* SPQ block timeout in msec */\n \tu32 spq_timeout_ms;\n };\n@@ -428,11 +431,17 @@ enum ecore_dmae_address_type_t {\n #define ECORE_DMAE_FLAG_VF_SRC\t\t0x00000002\n #define ECORE_DMAE_FLAG_VF_DST\t\t0x00000004\n #define ECORE_DMAE_FLAG_COMPLETION_DST\t0x00000008\n+#define ECORE_DMAE_FLAG_PORT\t\t0x00000010\n+#define ECORE_DMAE_FLAG_PF_SRC\t\t0x00000020\n+#define ECORE_DMAE_FLAG_PF_DST\t\t0x00000040\n \n struct ecore_dmae_params {\n \tu32 flags; /* consists of ECORE_DMAE_FLAG_* values */\n \tu8 src_vfid;\n \tu8 dst_vfid;\n+\tu8 port_id;\n+\tu8 src_pfid;\n+\tu8 dst_pfid;\n };\n \n /**\n@@ -444,7 +453,9 @@ struct ecore_dmae_params {\n  * @param source_addr\n  * @param grc_addr (dmae_data_offset)\n  * @param size_in_dwords\n- * @param flags (one of the flags defined above)\n+ * @param p_params (default parameters will be used in case of OSAL_NULL)\n+ *\n+ * @return enum _ecore_status_t\n  */\n enum _ecore_status_t\n ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,\n@@ -452,7 +463,7 @@ enum _ecore_status_t\n \t\t    u64 source_addr,\n \t\t    u32 grc_addr,\n \t\t    u32 size_in_dwords,\n-\t\t    u32 flags);\n+\t\t    struct ecore_dmae_params *p_params);\n \n /**\n  * @brief ecore_dmae_grc2host - Read data from dmae data offset\n@@ -462,7 +473,9 @@ enum _ecore_status_t\n  * @param grc_addr (dmae_data_offset)\n  * @param dest_addr\n  * @param size_in_dwords\n- * @param flags - one of the flags defined above\n+ * @param p_params (default parameters will be used in case of OSAL_NULL)\n+ *\n+ * @return enum _ecore_status_t\n  */\n enum _ecore_status_t\n ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,\n@@ -470,7 +483,7 @@ enum _ecore_status_t\n \t\t    u32 grc_addr,\n \t\t    dma_addr_t dest_addr,\n \t\t    u32 size_in_dwords,\n-\t\t    u32 flags);\n+\t\t    struct ecore_dmae_params *p_params);\n \n /**\n  * @brief ecore_dmae_host2host - copy data from to source address\n@@ -481,7 +494,9 @@ enum _ecore_status_t\n  * @param source_addr\n  * @param dest_addr\n  * @param size_in_dwords\n- * @param params\n+ * @param p_params (default parameters will be used in case of OSAL_NULL)\n+ *\n+ * @return enum _ecore_status_t\n  */\n enum _ecore_status_t\n ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,\n@@ -562,28 +577,79 @@ enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,\n \t\t\t\t      u8 *dst_id);\n \n /**\n- * @brief ecore_llh_add_mac_filter - configures a MAC filter in llh\n+ * @brief ecore_llh_get_num_ppfid - Return the allocated number of LLH filter\n+ *\tbanks that are allocated to the PF.\n  *\n- * @param p_hwfn\n- * @param p_ptt\n- * @param p_filter - MAC to add\n+ * @param p_dev\n+ *\n+ * @return u8 - Number of LLH filter banks\n  */\n-enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t\t  struct ecore_ptt *p_ptt,\n-\t\t\t\t\t  u8 *p_filter);\n+u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev);\n+\n+enum ecore_eng {\n+\tECORE_ENG0,\n+\tECORE_ENG1,\n+\tECORE_BOTH_ENG,\n+};\n \n /**\n- * @brief ecore_llh_remove_mac_filter - removes a MAC filtre from llh\n+ * @brief ecore_llh_get_l2_affinity_hint - Return the hint for the L2 affinity\n  *\n- * @param p_hwfn\n- * @param p_ptt\n- * @param p_filter - MAC to remove\n+ * @param p_dev\n+ *\n+ * @return enum ecore_eng - L2 affintiy hint\n+ */\n+enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev);\n+\n+/**\n+ * @brief ecore_llh_set_ppfid_affinity - Set the engine affinity for the given\n+ *\tLLH filter bank.\n+ *\n+ * @param p_dev\n+ * @param ppfid - relative within the allocated ppfids ('0' is the default one).\n+ * @param eng\n+ *\n+ * @return enum _ecore_status_t\n  */\n-void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t     struct ecore_ptt *p_ptt,\n-\t\t\t     u8 *p_filter);\n+enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,\n+\t\t\t\t\t\t  u8 ppfid, enum ecore_eng eng);\n \n-enum ecore_llh_port_filter_type_t {\n+/**\n+ * @brief ecore_llh_set_roce_affinity - Set the RoCE engine affinity\n+ *\n+ * @param p_dev\n+ * @param eng\n+ *\n+ * @return enum _ecore_status_t\n+ */\n+enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,\n+\t\t\t\t\t\t enum ecore_eng eng);\n+\n+/**\n+ * @brief ecore_llh_add_mac_filter - Add a LLH MAC filter into the given filter\n+ *\tbank.\n+ *\n+ * @param p_dev\n+ * @param ppfid - relative within the allocated ppfids ('0' is the default one).\n+ * @param mac_addr - MAC to add\n+ *\n+ * @return enum _ecore_status_t\n+ */\n+enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t\t\t      u8 mac_addr[ETH_ALEN]);\n+\n+/**\n+ * @brief ecore_llh_remove_mac_filter - Remove a LLH MAC filter from the given\n+ *\tfilter bank.\n+ *\n+ * @param p_dev\n+ * @param ppfid - relative within the allocated ppfids ('0' is the default one).\n+ * @param mac_addr - MAC to remove\n+ */\n+void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t\t u8 mac_addr[ETH_ALEN]);\n+\n+enum ecore_llh_prot_filter_type_t {\n \tECORE_LLH_FILTER_ETHERTYPE,\n \tECORE_LLH_FILTER_TCP_SRC_PORT,\n \tECORE_LLH_FILTER_TCP_DEST_PORT,\n@@ -594,45 +660,52 @@ enum ecore_llh_port_filter_type_t {\n };\n \n /**\n- * @brief ecore_llh_add_protocol_filter - configures a protocol filter in llh\n+ * @brief ecore_llh_add_protocol_filter - Add a LLH protocol filter into the\n+ *\tgiven filter bank.\n  *\n- * @param p_hwfn\n- * @param p_ptt\n+ * @param p_dev\n+ * @param ppfid - relative within the allocated ppfids ('0' is the default one).\n+ * @param type - type of filters and comparing\n  * @param source_port_or_eth_type - source port or ethertype to add\n  * @param dest_port - destination port to add\n- * @param type - type of filters and comparing\n+ *\n+ * @return enum _ecore_status_t\n  */\n enum _ecore_status_t\n-ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t      struct ecore_ptt *p_ptt,\n-\t\t\t      u16 source_port_or_eth_type,\n-\t\t\t      u16 dest_port,\n-\t\t\t      enum ecore_llh_port_filter_type_t type);\n+ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t      enum ecore_llh_prot_filter_type_t type,\n+\t\t\t      u16 source_port_or_eth_type, u16 dest_port);\n \n /**\n- * @brief ecore_llh_remove_protocol_filter - remove a protocol filter in llh\n+ * @brief ecore_llh_remove_protocol_filter - Remove a LLH protocol filter from\n+ *\tthe given filter bank.\n  *\n- * @param p_hwfn\n- * @param p_ptt\n+ * @param p_dev\n+ * @param ppfid - relative within the allocated ppfids ('0' is the default one).\n+ * @param type - type of filters and comparing\n  * @param source_port_or_eth_type - source port or ethertype to add\n  * @param dest_port - destination port to add\n- * @param type - type of filters and comparing\n  */\n-void\n-ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,\n-\t\t\t\t struct ecore_ptt *p_ptt,\n-\t\t\t\t u16 source_port_or_eth_type,\n-\t\t\t\t u16 dest_port,\n-\t\t\t\t enum ecore_llh_port_filter_type_t type);\n+void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,\n+\t\t\t\t      enum ecore_llh_prot_filter_type_t type,\n+\t\t\t\t      u16 source_port_or_eth_type,\n+\t\t\t\t      u16 dest_port);\n \n /**\n- * @brief ecore_llh_clear_all_filters - removes all MAC filters from llh\n+ * @brief ecore_llh_clear_ppfid_filters - Remove all LLH filters from the given\n+ *\tfilter bank.\n  *\n- * @param p_hwfn\n- * @param p_ptt\n+ * @param p_dev\n+ * @param ppfid - relative within the allocated ppfids ('0' is the default one).\n+ */\n+void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid);\n+\n+/**\n+ * @brief ecore_llh_clear_all_filters - Remove all LLH filters\n+ *\n+ * @param p_dev\n  */\n-void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,\n-\t\t\t     struct ecore_ptt *p_ptt);\n+void ecore_llh_clear_all_filters(struct ecore_dev *p_dev);\n \n /**\n  * @brief ecore_llh_set_function_as_default - set function as default per port\ndiff --git a/drivers/net/qede/base/ecore_hw.c b/drivers/net/qede/base/ecore_hw.c\nindex 6cfbbab..72cd7e9 100644\n--- a/drivers/net/qede/base/ecore_hw.c\n+++ b/drivers/net/qede/base/ecore_hw.c\n@@ -450,14 +450,17 @@ u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)\n  * If this changes, this needs to be revisted.\n  */\n \n-/* Ecore DMAE\n- * =============\n- */\n+/* DMAE */\n+\n+#define ECORE_DMAE_FLAGS_IS_SET(params, flag)\t\\\n+\t((params) != OSAL_NULL && ((params)->flags & ECORE_DMAE_FLAG_##flag))\n+\n static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,\n \t\t\t      const u8 is_src_type_grc,\n \t\t\t      const u8 is_dst_type_grc,\n \t\t\t      struct ecore_dmae_params *p_params)\n {\n+\tu8 src_pfid, dst_pfid, port_id;\n \tu16 opcode_b = 0;\n \tu32 opcode = 0;\n \n@@ -467,16 +470,20 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,\n \t */\n \topcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC\n \t\t   : DMAE_CMD_SRC_MASK_PCIE) << DMAE_CMD_SRC_SHIFT;\n-\topcode |= (p_hwfn->rel_pf_id & DMAE_CMD_SRC_PF_ID_MASK) <<\n-\t    DMAE_CMD_SRC_PF_ID_SHIFT;\n+\tsrc_pfid = ECORE_DMAE_FLAGS_IS_SET(p_params, PF_SRC) ?\n+\t\t   p_params->src_pfid : p_hwfn->rel_pf_id;\n+\topcode |= (src_pfid & DMAE_CMD_SRC_PF_ID_MASK) <<\n+\t\t  DMAE_CMD_SRC_PF_ID_SHIFT;\n \n \t/* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */\n \topcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC\n \t\t   : DMAE_CMD_DST_MASK_PCIE) << DMAE_CMD_DST_SHIFT;\n-\topcode |= (p_hwfn->rel_pf_id & DMAE_CMD_DST_PF_ID_MASK) <<\n-\t    DMAE_CMD_DST_PF_ID_SHIFT;\n+\tdst_pfid = ECORE_DMAE_FLAGS_IS_SET(p_params, PF_DST) ?\n+\t\t   p_params->dst_pfid : p_hwfn->rel_pf_id;\n+\topcode |= (dst_pfid & DMAE_CMD_DST_PF_ID_MASK) <<\n+\t\t  DMAE_CMD_DST_PF_ID_SHIFT;\n \n-\t/* DMAE_E4_TODO need to check which value to specifiy here. */\n+\t/* DMAE_E4_TODO need to check which value to specify here. */\n \t/* opcode |= (!b_complete_to_host)<< DMAE_CMD_C_DST_SHIFT; */\n \n \t/* Whether to write a completion word to the completion destination:\n@@ -486,7 +493,7 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,\n \topcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT;\n \topcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;\n \n-\tif (p_params->flags & ECORE_DMAE_FLAG_COMPLETION_DST)\n+\tif (ECORE_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST))\n \t\topcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT;\n \n \t/* swapping mode 3 - big endian there should be a define ifdefed in\n@@ -494,7 +501,9 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,\n \t */\n \topcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT;\n \n-\topcode |= p_hwfn->port_id << DMAE_CMD_PORT_ID_SHIFT;\n+\tport_id = (ECORE_DMAE_FLAGS_IS_SET(p_params, PORT)) ?\n+\t\t  p_params->port_id : p_hwfn->port_id;\n+\topcode |= port_id << DMAE_CMD_PORT_ID_SHIFT;\n \n \t/* reset source address in next go */\n \topcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;\n@@ -503,14 +512,14 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,\n \topcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT;\n \n \t/* SRC/DST VFID: all 1's - pf, otherwise VF id */\n-\tif (p_params->flags & ECORE_DMAE_FLAG_VF_SRC) {\n+\tif (ECORE_DMAE_FLAGS_IS_SET(p_params, VF_SRC)) {\n \t\topcode |= (1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT);\n \t\topcode_b |= (p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT);\n \t} else {\n \t\topcode_b |= (DMAE_CMD_SRC_VF_ID_MASK <<\n \t\t\t     DMAE_CMD_SRC_VF_ID_SHIFT);\n \t}\n-\tif (p_params->flags & ECORE_DMAE_FLAG_VF_DST) {\n+\tif (ECORE_DMAE_FLAGS_IS_SET(p_params, VF_DST)) {\n \t\topcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT;\n \t\topcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT;\n \t} else {\n@@ -855,7 +864,7 @@ static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)\n \tfor (i = 0; i <= cnt_split; i++) {\n \t\toffset = length_limit * i;\n \n-\t\tif (!(p_params->flags & ECORE_DMAE_FLAG_RW_REPL_SRC)) {\n+\t\tif (!ECORE_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) {\n \t\t\tif (src_type == ECORE_DMAE_ADDRESS_GRC)\n \t\t\t\tsrc_addr_split = src_addr + offset;\n \t\t\telse\n@@ -896,51 +905,45 @@ static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)\n \treturn ecore_status;\n }\n \n-enum _ecore_status_t\n-ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,\n-\t\t    struct ecore_ptt *p_ptt,\n-\t\t    u64 source_addr,\n-\t\t    u32 grc_addr, u32 size_in_dwords, u32 flags)\n+enum _ecore_status_t ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t struct ecore_ptt *p_ptt,\n+\t\t\t\t\t u64 source_addr,\n+\t\t\t\t\t u32 grc_addr,\n+\t\t\t\t\t u32 size_in_dwords,\n+\t\t\t\t\t struct ecore_dmae_params *p_params)\n {\n \tu32 grc_addr_in_dw = grc_addr / sizeof(u32);\n-\tstruct ecore_dmae_params params;\n \tenum _ecore_status_t rc;\n \n-\tOSAL_MEMSET(&params, 0, sizeof(struct ecore_dmae_params));\n-\tparams.flags = flags;\n-\n \tOSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);\n \n \trc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,\n \t\t\t\t\tgrc_addr_in_dw,\n \t\t\t\t\tECORE_DMAE_ADDRESS_HOST_VIRT,\n \t\t\t\t\tECORE_DMAE_ADDRESS_GRC,\n-\t\t\t\t\tsize_in_dwords, &params);\n+\t\t\t\t\tsize_in_dwords, p_params);\n \n \tOSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);\n \n \treturn rc;\n }\n \n-enum _ecore_status_t\n-ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,\n-\t\t    struct ecore_ptt *p_ptt,\n-\t\t    u32 grc_addr,\n-\t\t    dma_addr_t dest_addr, u32 size_in_dwords, u32 flags)\n+enum _ecore_status_t ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t struct ecore_ptt *p_ptt,\n+\t\t\t\t\t u32 grc_addr,\n+\t\t\t\t\t dma_addr_t dest_addr,\n+\t\t\t\t\t u32 size_in_dwords,\n+\t\t\t\t\t struct ecore_dmae_params *p_params)\n {\n \tu32 grc_addr_in_dw = grc_addr / sizeof(u32);\n-\tstruct ecore_dmae_params params;\n \tenum _ecore_status_t rc;\n \n-\tOSAL_MEMSET(&params, 0, sizeof(struct ecore_dmae_params));\n-\tparams.flags = flags;\n-\n \tOSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);\n \n \trc = ecore_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,\n \t\t\t\t\tdest_addr, ECORE_DMAE_ADDRESS_GRC,\n \t\t\t\t\tECORE_DMAE_ADDRESS_HOST_VIRT,\n-\t\t\t\t\tsize_in_dwords, &params);\n+\t\t\t\t\tsize_in_dwords, p_params);\n \n \tOSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);\n \n@@ -989,7 +992,6 @@ enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,\n \t\t\t\t       const char *phase)\n {\n \tu32 size = OSAL_PAGE_SIZE / 2, val;\n-\tstruct ecore_dmae_params params;\n \tenum _ecore_status_t rc = ECORE_SUCCESS;\n \tdma_addr_t p_phys;\n \tvoid *p_virt;\n@@ -1021,9 +1023,9 @@ enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,\n \t\t   (unsigned long)(p_phys + size),\n \t\t   (u8 *)p_virt + size, size);\n \n-\tOSAL_MEMSET(&params, 0, sizeof(params));\n \trc = ecore_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,\n-\t\t\t\t  size / 4 /* size_in_dwords */, &params);\n+\t\t\t\t  size / 4 /* size_in_dwords */,\n+\t\t\t\t  OSAL_NULL /* default parameters */);\n \tif (rc != ECORE_SUCCESS) {\n \t\tDP_NOTICE(p_hwfn, false,\n \t\t\t  \"DMAE sanity [%s]: ecore_dmae_host2host() failed. rc = %d.\\n\",\n@@ -1054,3 +1056,32 @@ enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,\n \tOSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_virt, p_phys, 2 * size);\n \treturn rc;\n }\n+\n+void ecore_ppfid_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t    u8 abs_ppfid, u32 hw_addr, u32 val)\n+{\n+\tu8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);\n+\n+\tecore_fid_pretend(p_hwfn, p_ptt,\n+\t\t\t  pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);\n+\tecore_wr(p_hwfn, p_ptt, hw_addr, val);\n+\tecore_fid_pretend(p_hwfn, p_ptt,\n+\t\t\t  p_hwfn->rel_pf_id <<\n+\t\t\t  PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);\n+}\n+\n+u32 ecore_ppfid_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t   u8 abs_ppfid, u32 hw_addr)\n+{\n+\tu8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);\n+\tu32 val;\n+\n+\tecore_fid_pretend(p_hwfn, p_ptt,\n+\t\t\t  pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);\n+\tval = ecore_rd(p_hwfn, p_ptt, hw_addr);\n+\tecore_fid_pretend(p_hwfn, p_ptt,\n+\t\t\t  p_hwfn->rel_pf_id <<\n+\t\t\t  PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);\n+\n+\treturn val;\n+}\ndiff --git a/drivers/net/qede/base/ecore_hw.h b/drivers/net/qede/base/ecore_hw.h\nindex a62ba39..0b5b40c 100644\n--- a/drivers/net/qede/base/ecore_hw.h\n+++ b/drivers/net/qede/base/ecore_hw.h\n@@ -134,8 +134,8 @@ struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn\t*p_hwfn,\n  *\n  * @param p_hwfn\n  * @param p_ptt\n- * @param val\n  * @param hw_addr\n+ * @param val\n  */\n void ecore_wr(struct ecore_hwfn\t*p_hwfn,\n \t      struct ecore_ptt\t*p_ptt,\n@@ -147,7 +147,6 @@ void ecore_wr(struct ecore_hwfn\t*p_hwfn,\n  *\n  * @param p_hwfn\n  * @param p_ptt\n- * @param val\n  * @param hw_addr\n  */\n u32 ecore_rd(struct ecore_hwfn\t*p_hwfn,\n@@ -269,4 +268,29 @@ enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,\n \t\t\t\t       struct ecore_ptt *p_ptt,\n \t\t\t\t       const char *phase);\n \n+/**\n+ * @brief ecore_ppfid_wr - Write value to BAR using the given ptt while\n+ *\tpretending to a PF to which the given PPFID pertains.\n+ *\n+ * @param p_hwfn\n+ * @param p_ptt\n+ * @param abs_ppfid\n+ * @param hw_addr\n+ * @param val\n+ */\n+void ecore_ppfid_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t    u8 abs_ppfid, u32 hw_addr, u32 val);\n+\n+/**\n+ * @brief ecore_ppfid_rd - Read value from BAR using the given ptt while\n+ *\t pretending to a PF to which the given PPFID pertains.\n+ *\n+ * @param p_hwfn\n+ * @param p_ptt\n+ * @param abs_ppfid\n+ * @param hw_addr\n+ */\n+u32 ecore_ppfid_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n+\t\t   u8 abs_ppfid, u32 hw_addr);\n+\n #endif /* __ECORE_HW_H__ */\ndiff --git a/drivers/net/qede/base/ecore_init_ops.c b/drivers/net/qede/base/ecore_init_ops.c\nindex b7636f3..47c1be2 100644\n--- a/drivers/net/qede/base/ecore_init_ops.c\n+++ b/drivers/net/qede/base/ecore_init_ops.c\n@@ -101,7 +101,8 @@ static enum _ecore_status_t ecore_init_rt(struct ecore_hwfn *p_hwfn,\n \n \t\trc = ecore_dmae_host2grc(p_hwfn, p_ptt,\n \t\t\t\t\t (osal_uintptr_t)(p_init_val + i),\n-\t\t\t\t\t addr + (i << 2), segment, 0);\n+\t\t\t\t\t addr + (i << 2), segment,\n+\t\t\t\t\t OSAL_NULL /* default parameters */);\n \t\tif (rc != ECORE_SUCCESS)\n \t\t\treturn rc;\n \n@@ -165,8 +166,9 @@ static enum _ecore_status_t ecore_init_array_dmae(struct ecore_hwfn *p_hwfn,\n \t} else {\n \t\trc = ecore_dmae_host2grc(p_hwfn, p_ptt,\n \t\t\t\t\t (osal_uintptr_t)(p_buf +\n-\t\t\t\t\t\t\t   dmae_data_offset),\n-\t\t\t\t\t addr, size, 0);\n+\t\t\t\t\t\t\t  dmae_data_offset),\n+\t\t\t\t\t addr, size,\n+\t\t\t\t\t OSAL_NULL /* default parameters */);\n \t}\n \n \treturn rc;\n@@ -177,13 +179,15 @@ static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn,\n \t\t\t\t\t\t u32 addr, u32 fill_count)\n {\n \tstatic u32 zero_buffer[DMAE_MAX_RW_SIZE];\n+\tstruct ecore_dmae_params params;\n \n \tOSAL_MEMSET(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);\n \n+\tOSAL_MEMSET(&params, 0, sizeof(params));\n+\tparams.flags = ECORE_DMAE_FLAG_RW_REPL_SRC;\n \treturn ecore_dmae_host2grc(p_hwfn, p_ptt,\n \t\t\t\t   (osal_uintptr_t)&zero_buffer[0],\n-\t\t\t\t   addr, fill_count,\n-\t\t\t\t   ECORE_DMAE_FLAG_RW_REPL_SRC);\n+\t\t\t\t   addr, fill_count, &params);\n }\n \n static void ecore_init_fill(struct ecore_hwfn *p_hwfn,\ndiff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecore_int.c\nindex fd8f657..e48a7bc 100644\n--- a/drivers/net/qede/base/ecore_int.c\n+++ b/drivers/net/qede/base/ecore_int.c\n@@ -1561,11 +1561,13 @@ void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,\n \t\tecore_dmae_host2grc(p_hwfn, p_ptt,\n \t\t\t\t    (u64)(osal_uintptr_t)&phys_addr,\n \t\t\t\t    CAU_REG_SB_ADDR_MEMORY +\n-\t\t\t\t    igu_sb_id * sizeof(u64), 2, 0);\n+\t\t\t\t    igu_sb_id * sizeof(u64), 2,\n+\t\t\t\t    OSAL_NULL /* default parameters */);\n \t\tecore_dmae_host2grc(p_hwfn, p_ptt,\n \t\t\t\t    (u64)(osal_uintptr_t)&sb_entry,\n \t\t\t\t    CAU_REG_SB_VAR_MEMORY +\n-\t\t\t\t    igu_sb_id * sizeof(u64), 2, 0);\n+\t\t\t\t    igu_sb_id * sizeof(u64), 2,\n+\t\t\t\t    OSAL_NULL /* default parameters */);\n \t} else {\n \t\t/* Initialize Status Block Address */\n \t\tSTORE_RT_REG_AGG(p_hwfn,\n@@ -2646,7 +2648,8 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,\n \n \trc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +\n \t\t\t\t sb_id * sizeof(u64),\n-\t\t\t\t (u64)(osal_uintptr_t)&sb_entry, 2, 0);\n+\t\t\t\t (u64)(osal_uintptr_t)&sb_entry, 2,\n+\t\t\t\t OSAL_NULL /* default parameters */);\n \tif (rc != ECORE_SUCCESS) {\n \t\tDP_ERR(p_hwfn, \"dmae_grc2host failed %d\\n\", rc);\n \t\treturn rc;\n@@ -2659,8 +2662,8 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,\n \n \trc = ecore_dmae_host2grc(p_hwfn, p_ptt,\n \t\t\t\t (u64)(osal_uintptr_t)&sb_entry,\n-\t\t\t\t CAU_REG_SB_VAR_MEMORY +\n-\t\t\t\t sb_id * sizeof(u64), 2, 0);\n+\t\t\t\t CAU_REG_SB_VAR_MEMORY + sb_id * sizeof(u64), 2,\n+\t\t\t\t OSAL_NULL /* default parameters */);\n \tif (rc != ECORE_SUCCESS) {\n \t\tDP_ERR(p_hwfn, \"dmae_host2grc failed %d\\n\", rc);\n \t\treturn rc;\ndiff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c\nindex c17082e..5a0905e 100644\n--- a/drivers/net/qede/base/ecore_l2.c\n+++ b/drivers/net/qede/base/ecore_l2.c\n@@ -2217,7 +2217,8 @@ int ecore_get_rxq_coalesce(struct ecore_hwfn *p_hwfn,\n \n \trc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +\n \t\t\t\t p_cid->sb_igu_id * sizeof(u64),\n-\t\t\t\t (u64)(osal_uintptr_t)&sb_entry, 2, 0);\n+\t\t\t\t (u64)(osal_uintptr_t)&sb_entry, 2,\n+\t\t\t\t OSAL_NULL /* default parameters */);\n \tif (rc != ECORE_SUCCESS) {\n \t\tDP_ERR(p_hwfn, \"dmae_grc2host failed %d\\n\", rc);\n \t\treturn rc;\n@@ -2251,7 +2252,8 @@ int ecore_get_txq_coalesce(struct ecore_hwfn *p_hwfn,\n \n \trc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +\n \t\t\t\t p_cid->sb_igu_id * sizeof(u64),\n-\t\t\t\t (u64)(osal_uintptr_t)&sb_entry, 2, 0);\n+\t\t\t\t (u64)(osal_uintptr_t)&sb_entry, 2,\n+\t\t\t\t OSAL_NULL /* default parameters */);\n \tif (rc != ECORE_SUCCESS) {\n \t\tDP_ERR(p_hwfn, \"dmae_grc2host failed %d\\n\", rc);\n \t\treturn rc;\ndiff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c\nindex 3811d27..202db13 100644\n--- a/drivers/net/qede/base/ecore_mcp.c\n+++ b/drivers/net/qede/base/ecore_mcp.c\n@@ -4144,6 +4144,75 @@ enum _ecore_status_t\n \treturn ECORE_SUCCESS;\n }\n \n+enum _ecore_status_t ecore_mcp_get_engine_config(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\t struct ecore_ptt *p_ptt)\n+{\n+\tstruct ecore_dev *p_dev = p_hwfn->p_dev;\n+\tstruct ecore_mcp_mb_params mb_params;\n+\tu8 fir_valid, l2_valid;\n+\tenum _ecore_status_t rc;\n+\n+\tOSAL_MEM_ZERO(&mb_params, sizeof(mb_params));\n+\tmb_params.cmd = DRV_MSG_CODE_GET_ENGINE_CONFIG;\n+\trc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\tif (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {\n+\t\tDP_INFO(p_hwfn,\n+\t\t\t\"The get_engine_config command is unsupported by the MFW\\n\");\n+\t\treturn ECORE_NOTIMPL;\n+\t}\n+\n+\tfir_valid = GET_MFW_FIELD(mb_params.mcp_param,\n+\t\t\t\t  FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID);\n+\tif (fir_valid)\n+\t\tp_dev->fir_affin =\n+\t\t\tGET_MFW_FIELD(mb_params.mcp_param,\n+\t\t\t\t      FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE);\n+\n+\tl2_valid = GET_MFW_FIELD(mb_params.mcp_param,\n+\t\t\t\t FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID);\n+\tif (l2_valid)\n+\t\tp_dev->l2_affin_hint =\n+\t\t\tGET_MFW_FIELD(mb_params.mcp_param,\n+\t\t\t\t      FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE);\n+\n+\tDP_INFO(p_hwfn,\n+\t\t\"Engine affinity config: FIR={valid %hhd, value %hhd}, L2_hint={valid %hhd, value %hhd}\\n\",\n+\t\tfir_valid, p_dev->fir_affin, l2_valid, p_dev->l2_affin_hint);\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n+enum _ecore_status_t ecore_mcp_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\tstruct ecore_ptt *p_ptt)\n+{\n+\tstruct ecore_dev *p_dev = p_hwfn->p_dev;\n+\tstruct ecore_mcp_mb_params mb_params;\n+\tenum _ecore_status_t rc;\n+\n+\tOSAL_MEM_ZERO(&mb_params, sizeof(mb_params));\n+\tmb_params.cmd = DRV_MSG_CODE_GET_PPFID_BITMAP;\n+\trc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);\n+\tif (rc != ECORE_SUCCESS)\n+\t\treturn rc;\n+\n+\tif (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {\n+\t\tDP_INFO(p_hwfn,\n+\t\t\t\"The get_ppfid_bitmap command is unsupported by the MFW\\n\");\n+\t\treturn ECORE_NOTIMPL;\n+\t}\n+\n+\tp_dev->ppfid_bitmap = GET_MFW_FIELD(mb_params.mcp_param,\n+\t\t\t\t\t    FW_MB_PARAM_PPFID_BITMAP);\n+\n+\tDP_VERBOSE(p_hwfn, ECORE_MSG_SP, \"PPFID bitmap 0x%hhx\\n\",\n+\t\t   p_dev->ppfid_bitmap);\n+\n+\treturn ECORE_SUCCESS;\n+}\n+\n void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \t\t      u32 offset, u32 val)\n {\ndiff --git a/drivers/net/qede/base/ecore_mcp.h b/drivers/net/qede/base/ecore_mcp.h\nindex 8e12531..2c052b7 100644\n--- a/drivers/net/qede/base/ecore_mcp.h\n+++ b/drivers/net/qede/base/ecore_mcp.h\n@@ -25,9 +25,6 @@\n \t\t\t\t\t     rel_pfid)\n #define MCP_PF_ID(p_hwfn)\tMCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id)\n \n-#define MFW_PORT(_p_hwfn)\t((_p_hwfn)->abs_pf_id % \\\n-\t\t\t\t ecore_device_num_ports((_p_hwfn)->p_dev))\n-\n struct ecore_mcp_info {\n \t/* List for mailbox commands which were sent and wait for a response */\n \tosal_list_t cmd_list;\n@@ -566,4 +563,22 @@ enum _ecore_status_t\n void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,\n \t\t      u32 offset, u32 val);\n \n+/**\n+ * @brief Get the engine affinity configuration.\n+ *\n+ * @param p_hwfn\n+ * @param p_ptt\n+ */\n+enum _ecore_status_t ecore_mcp_get_engine_config(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\t struct ecore_ptt *p_ptt);\n+\n+/**\n+ * @brief Get the PPFID bitmap.\n+ *\n+ * @param p_hwfn\n+ * @param p_ptt\n+ */\n+enum _ecore_status_t ecore_mcp_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,\n+\t\t\t\t\t\tstruct ecore_ptt *p_ptt);\n+\n #endif /* __ECORE_MCP_H__ */\ndiff --git a/drivers/net/qede/base/ecore_sriov.c b/drivers/net/qede/base/ecore_sriov.c\nindex 3ac1085..9e937e2 100644\n--- a/drivers/net/qede/base/ecore_sriov.c\n+++ b/drivers/net/qede/base/ecore_sriov.c\n@@ -979,10 +979,12 @@ static u8 ecore_iov_alloc_vf_igu_sbs(struct ecore_hwfn *p_hwfn,\n \t\tecore_init_cau_sb_entry(p_hwfn, &sb_entry,\n \t\t\t\t\tp_hwfn->rel_pf_id,\n \t\t\t\t\tvf->abs_vf_id, 1);\n+\n \t\tecore_dmae_host2grc(p_hwfn, p_ptt,\n \t\t\t\t    (u64)(osal_uintptr_t)&sb_entry,\n \t\t\t\t    CAU_REG_SB_VAR_MEMORY +\n-\t\t\t\t    p_block->igu_sb_id * sizeof(u64), 2, 0);\n+\t\t\t\t    p_block->igu_sb_id * sizeof(u64), 2,\n+\t\t\t\t    OSAL_NULL /* default parameters */);\n \t}\n \n \tvf->num_sbs = (u8)num_rx_queues;\ndiff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h\nindex 46ec984..13c2e2d 100644\n--- a/drivers/net/qede/base/mcp_public.h\n+++ b/drivers/net/qede/base/mcp_public.h\n@@ -1267,6 +1267,8 @@ struct public_drv_mb {\n #define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT\t0x3f000000\n #define DRV_MSG_CODE_OV_GET_CURR_CFG\t\t0x40000000\n #define DRV_MSG_CODE_GET_OEM_UPDATES\t\t0x41000000\n+/* params [31:8] - reserved, [7:0] - bitmap */\n+#define DRV_MSG_CODE_GET_PPFID_BITMAP\t\t0x43000000\n \n /*deprecated don't use*/\n #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED    0x02000000\n@@ -1476,6 +1478,7 @@ struct public_drv_mb {\n \n /* Param: Password len. Union: Plain Password */\n #define DRV_MSG_CODE_ENCRYPT_PASSWORD\t\t0x00360000\n+#define DRV_MSG_CODE_GET_ENGINE_CONFIG\t\t0x00370000 /* Param: None */\n \n #define DRV_MSG_SEQ_NUMBER_MASK                 0x0000ffff\n \n@@ -1812,6 +1815,18 @@ struct public_drv_mb {\n #define FW_MB_PARAM_OEM_UPDATE_S_TAG\t\t0x02\n #define FW_MB_PARAM_OEM_UPDATE_CFG\t\t0x04\n \n+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK   0x00000001\n+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0\n+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK   0x00000002\n+#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_OFFSET 1\n+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK    0x00000004\n+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_OFFSET  2\n+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK    0x00000008\n+#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_OFFSET  3\n+\n+#define FW_MB_PARAM_PPFID_BITMAP_MASK   0xFF\n+#define FW_MB_PARAM_PPFID_BITMAP_OFFSET    0\n+\n \tu32 drv_pulse_mb;\n #define DRV_PULSE_SEQ_MASK                      0x00007fff\n #define DRV_PULSE_SYSTEM_TIME_MASK              0xffff0000\ndiff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_addr.h\nindex c3e0bd2..612337f 100644\n--- a/drivers/net/qede/base/reg_addr.h\n+++ b/drivers/net/qede/base/reg_addr.h\n@@ -1235,3 +1235,7 @@\n #define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL\n #define DORQ_REG_PF_EXT_VID_BB_K2 0x1008c8UL\n #define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL\n+#define NIG_REG_LLH_PPFID2PFID_TBL_0 0x501970UL\n+#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL\n+#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL 0x501b98UL\n+#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 0x501b40UL\n",
    "prefixes": [
        "14/18"
    ]
}