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GET /api/patches/45629/?format=api
{ "id": 45629, "url": "http://patches.dpdk.org/api/patches/45629/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180929020006.71505-6-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180929020006.71505-6-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180929020006.71505-6-ajit.khaparde@broadcom.com", "date": "2018-09-29T01:59:56", "name": "[v3,05/15] net/bnxt: update HWRM version part 2", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6a5a53b3102f8385b9709ddaf20574fb7b830678", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180929020006.71505-6-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 1590, "url": "http://patches.dpdk.org/api/series/1590/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1590", "date": "2018-09-29T01:59:54", "name": "bnxt patchset", "version": 3, "mbox": "http://patches.dpdk.org/series/1590/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/45629/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/45629/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 95F9E1B434;\n\tSat, 29 Sep 2018 04:00:43 +0200 (CEST)", "from rnd-relay.smtp.broadcom.com (rnd-relay.smtp.broadcom.com\n\t[192.19.229.170]) by dpdk.org (Postfix) with ESMTP id EBB781B1D5\n\tfor <dev@dpdk.org>; Sat, 29 Sep 2018 04:00:16 +0200 (CEST)", "from nis-sj1-27.broadcom.com (nis-sj1-27.lvn.broadcom.net\n\t[10.75.144.136])\n\tby rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id 34E9A30C047;\n\tFri, 28 Sep 2018 19:00:14 -0700 (PDT)", "from C02VPB22HTD6.vpn.broadcom.net (unknown [10.10.118.196])\n\tby nis-sj1-27.broadcom.com (Postfix) with ESMTP id E5A7AAC0767;\n\tFri, 28 Sep 2018 19:00:13 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com 34E9A30C047", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n\ts=dkimrelay; t=1538186414;\n\tbh=d843YFW798NnhEtGR7YkLg07z4NPseve9nZdZiD9BXg=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=PubjWDtbqtZaA535Jad3qWKKAZJrVibhApiROvAM9CAH7oUAz1ONfrAf6hkNvt5uj\n\tei/2Wf4XeXCvikRhLPObXQgTSR/kVmzIyFs4tC/SFrZjOJoJfUGGqKqvDN6oimM2MV\n\ttyujAhCRE+hh4A6F7PjzRz42FFwTT8x/Wq2lHOIg=", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com", "Date": "Fri, 28 Sep 2018 18:59:56 -0700", "Message-Id": "<20180929020006.71505-6-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.17.1 (Apple Git-112)", "In-Reply-To": "<20180929020006.71505-1-ajit.khaparde@broadcom.com>", "References": "<95301884-14c8-bbfd-ade9-ded04bdb6a95@intel.com>\n\t<20180929020006.71505-1-ajit.khaparde@broadcom.com>", "Subject": "[dpdk-dev] [PATCH v3 05/15] net/bnxt: update HWRM version part 2", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update the HWRM API to version 1.9.2.53\nThis is second part of the patch.\n\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n--\nv1->v2:\nUpdate from 1.9.2.45 to version 1.9.2.53\nv2->v3:\nSplit the patch into smaller patches\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 1153 ++++++++++++++++++++++++\n 1 file changed, 1153 insertions(+)", "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex a433e6bfd..2fabb9ad6 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -17291,6 +17291,261 @@ struct hwrm_ring_reset_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n+/**************************\n+ * hwrm_ring_aggint_qcaps *\n+ **************************/\n+\n+\n+/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */\n+struct hwrm_ring_aggint_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */\n+struct hwrm_ring_aggint_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tcmpl_params;\n+\t/*\n+\t * When this bit is set to '1', int_lat_tmr_min can be configured\n+\t * on completion rings.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is set to '1', int_lat_tmr_max can be configured\n+\t * on completion rings.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is set to '1', timer_reset can be enabled\n+\t * on completion rings.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is set to '1', ring_idle can be enabled\n+\t * on completion rings.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is set to '1', num_cmpl_dma_aggr can be configured\n+\t * on completion rings.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured\n+\t * on completion rings.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured\n+\t * on completion rings.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured\n+\t * on completion rings.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * When this bit is set to '1', num_cmpl_aggr_int can be configured\n+\t * on completion rings.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \\\n+\t\tUINT32_C(0x100)\n+\tuint32_t\tnq_params;\n+\t/*\n+\t * When this bit is set to '1', int_lat_tmr_min can be configured\n+\t * on notification queues.\n+\t */\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \\\n+\t\tUINT32_C(0x1)\n+\t/* Minimum value for num_cmpl_dma_aggr */\n+\tuint16_t\tnum_cmpl_dma_aggr_min;\n+\t/* Maximum value for num_cmpl_dma_aggr */\n+\tuint16_t\tnum_cmpl_dma_aggr_max;\n+\t/* Minimum value for num_cmpl_dma_aggr_during_int */\n+\tuint16_t\tnum_cmpl_dma_aggr_during_int_min;\n+\t/* Maximum value for num_cmpl_dma_aggr_during_int */\n+\tuint16_t\tnum_cmpl_dma_aggr_during_int_max;\n+\t/* Minimum value for cmpl_aggr_dma_tmr */\n+\tuint16_t\tcmpl_aggr_dma_tmr_min;\n+\t/* Maximum value for cmpl_aggr_dma_tmr */\n+\tuint16_t\tcmpl_aggr_dma_tmr_max;\n+\t/* Minimum value for cmpl_aggr_dma_tmr_during_int */\n+\tuint16_t\tcmpl_aggr_dma_tmr_during_int_min;\n+\t/* Maximum value for cmpl_aggr_dma_tmr_during_int */\n+\tuint16_t\tcmpl_aggr_dma_tmr_during_int_max;\n+\t/* Minimum value for int_lat_tmr_min */\n+\tuint16_t\tint_lat_tmr_min_min;\n+\t/* Maximum value for int_lat_tmr_min */\n+\tuint16_t\tint_lat_tmr_min_max;\n+\t/* Minimum value for int_lat_tmr_max */\n+\tuint16_t\tint_lat_tmr_max_min;\n+\t/* Maximum value for int_lat_tmr_max */\n+\tuint16_t\tint_lat_tmr_max_max;\n+\t/* Minimum value for num_cmpl_aggr_int */\n+\tuint16_t\tnum_cmpl_aggr_int_min;\n+\t/* Maximum value for num_cmpl_aggr_int */\n+\tuint16_t\tnum_cmpl_aggr_int_max;\n+\t/* The units for timer parameters, in nanoseconds. */\n+\tuint16_t\ttimer_units;\n+\tuint8_t\tunused_0[1];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**************************************\n+ * hwrm_ring_cmpl_ring_qaggint_params *\n+ **************************************/\n+\n+\n+/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */\n+struct hwrm_ring_cmpl_ring_qaggint_params_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Physical number of completion ring. */\n+\tuint16_t\tring_id;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */\n+struct hwrm_ring_cmpl_ring_qaggint_params_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint16_t\tflags;\n+\t/*\n+\t * When this bit is set to '1', interrupt max\n+\t * timer is reset whenever a completion is received.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is set to '1', ring idle mode\n+\t * aggregation will be enabled.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Number of completions to aggregate before DMA\n+\t * during the normal mode.\n+\t */\n+\tuint16_t\tnum_cmpl_dma_aggr;\n+\t/*\n+\t * Number of completions to aggregate before DMA\n+\t * during the interrupt mode.\n+\t */\n+\tuint16_t\tnum_cmpl_dma_aggr_during_int;\n+\t/*\n+\t * Timer in unit of 80-nsec used to aggregate completions before\n+\t * DMA during the normal mode (not in interrupt mode).\n+\t */\n+\tuint16_t\tcmpl_aggr_dma_tmr;\n+\t/*\n+\t * Timer in unit of 80-nsec used to aggregate completions before\n+\t * DMA during the interrupt mode.\n+\t */\n+\tuint16_t\tcmpl_aggr_dma_tmr_during_int;\n+\t/* Minimum time (in unit of 80-nsec) between two interrupts. */\n+\tuint16_t\tint_lat_tmr_min;\n+\t/*\n+\t * Maximum wait time (in unit of 80-nsec) spent aggregating\n+\t * completions before signaling the interrupt after the\n+\t * interrupt is enabled.\n+\t */\n+\tuint16_t\tint_lat_tmr_max;\n+\t/*\n+\t * Minimum number of completions aggregated before signaling\n+\t * an interrupt.\n+\t */\n+\tuint16_t\tnum_cmpl_aggr_int;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n /*****************************************\n * hwrm_ring_cmpl_ring_cfg_aggint_params *\n *****************************************/\n@@ -18534,6 +18789,904 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n+/********************************\n+ * hwrm_cfa_tunnel_filter_alloc *\n+ ********************************/\n+\n+\n+/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */\n+struct hwrm_cfa_tunnel_filter_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n+\t\tUINT32_C(0x1)\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the l2_filter_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the l2_addr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the l2_ivlan field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the l3_addr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the l3_addr_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the t_l3_addr_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the t_l3_addr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the tunnel_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This bit must be '1' for the vni field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This bit must be '1' for the dst_vnic_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This bit must be '1' for the mirror_vnic_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * This value identifies a set of CFA data structures used for an L2\n+\t * context.\n+\t */\n+\tuint64_t\tl2_filter_id;\n+\t/*\n+\t * This value sets the match value for the inner L2\n+\t * MAC address.\n+\t * Destination MAC address for RX path.\n+\t * Source MAC address for TX path.\n+\t */\n+\tuint8_t\tl2_addr[6];\n+\t/*\n+\t * This value sets VLAN ID value for inner VLAN.\n+\t * Only 12-bits of VLAN ID are used in setting the filter.\n+\t */\n+\tuint16_t\tl2_ivlan;\n+\t/*\n+\t * The value of inner destination IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n+\t */\n+\tuint32_t\tl3_addr[4];\n+\t/*\n+\t * The value of tunnel destination IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n+\t */\n+\tuint32_t\tt_l3_addr[4];\n+\t/*\n+\t * This value indicates the type of inner IP address.\n+\t * 4 - IPv4\n+\t * 6 - IPv6\n+\t * All others are invalid.\n+\t */\n+\tuint8_t\tl3_addr_type;\n+\t/*\n+\t * This value indicates the type of tunnel IP address.\n+\t * 4 - IPv4\n+\t * 6 - IPv6\n+\t * All others are invalid.\n+\t */\n+\tuint8_t\tt_l3_addr_type;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\t/*\n+\t * tunnel_flags allows the user to indicate the tunnel tag detection\n+\t * for the tunnel type specified in tunnel_type.\n+\t */\n+\tuint8_t\ttunnel_flags;\n+\t/*\n+\t * If the tunnel_type is geneve, then this bit indicates if we\n+\t * need to match the geneve OAM packet.\n+\t * If the tunnel_type is nvgre or gre, then this bit indicates if\n+\t * we need to detect checksum present bit in geneve header.\n+\t * If the tunnel_type is mpls, then this bit indicates if we need\n+\t * to match mpls packet with explicit IPV4/IPV6 null header.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If the tunnel_type is geneve, then this bit indicates if we\n+\t * need to detect the critical option bit set in the oam packet.\n+\t * If the tunnel_type is nvgre or gre, then this bit indicates\n+\t * if we need to match nvgre packets with key present bit set in\n+\t * gre header.\n+\t * If the tunnel_type is mpls, then this bit indicates if we\n+\t * need to match mpls packet with S bit from inner/second label.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If the tunnel_type is geneve, then this bit indicates if we\n+\t * need to match geneve packet with extended header bit set in\n+\t * geneve header.\n+\t * If the tunnel_type is nvgre or gre, then this bit indicates\n+\t * if we need to match nvgre packets with sequence number\n+\t * present bit set in gre header.\n+\t * If the tunnel_type is mpls, then this bit indicates if we\n+\t * need to match mpls packet with S bit from out/first label.\n+\t */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * Virtual Network Identifier (VNI). Only valid with\n+\t * tunnel_types VXLAN, NVGRE, and Geneve.\n+\t * Only lower 24-bits of VNI field are used\n+\t * in setting up the filter.\n+\t */\n+\tuint32_t\tvni;\n+\t/* Logical VNIC ID of the destination VNIC. */\n+\tuint32_t\tdst_vnic_id;\n+\t/*\n+\t * Logical VNIC ID of the VNIC where traffic is\n+\t * mirrored.\n+\t */\n+\tuint32_t\tmirror_vnic_id;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */\n+struct hwrm_cfa_tunnel_filter_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint64_t\ttunnel_filter_id;\n+\t/*\n+\t * This is the ID of the flow associated with this\n+\t * filter.\n+\t * This value shall be used to match and associate the\n+\t * flow identifier returned in completion records.\n+\t * A value of 0xFFFFFFFF shall indicate no flow id.\n+\t */\n+\tuint32_t\tflow_id;\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*******************************\n+ * hwrm_cfa_tunnel_filter_free *\n+ *******************************/\n+\n+\n+/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */\n+struct hwrm_cfa_tunnel_filter_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint64_t\ttunnel_filter_id;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */\n+struct hwrm_cfa_tunnel_filter_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***************************************\n+ * hwrm_cfa_redirect_tunnel_type_alloc *\n+ ***************************************/\n+\n+\n+/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */\n+struct hwrm_cfa_redirect_tunnel_type_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The destination function id, to whom the traffic is redirected. */\n+\tuint16_t\tdest_fid;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\t/* Tunnel alloc flags. */\n+\tuint8_t\tflags;\n+\t/* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_redirect_tunnel_type_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**************************************\n+ * hwrm_cfa_redirect_tunnel_type_free *\n+ **************************************/\n+\n+\n+/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */\n+struct hwrm_cfa_redirect_tunnel_type_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The destination function id, to whom the traffic is redirected. */\n+\tuint16_t\tdest_fid;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\tuint8_t\tunused_0[5];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */\n+struct hwrm_cfa_redirect_tunnel_type_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**************************************\n+ * hwrm_cfa_redirect_tunnel_type_info *\n+ **************************************/\n+\n+\n+/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */\n+struct hwrm_cfa_redirect_tunnel_type_info_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The source function id. */\n+\tuint16_t\tsrc_fid;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\tuint8_t\tunused_0[5];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */\n+struct hwrm_cfa_redirect_tunnel_type_info_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The destination function id, to whom the traffic is redirected. */\n+\tuint16_t\tdest_fid;\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */\n+struct hwrm_vxlan_ipv4_hdr {\n+\t/* IPv4 version and header length. */\n+\tuint8_t\tver_hlen;\n+\t/* IPv4 header length */\n+\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)\n+\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0\n+\t/* Version */\n+\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)\n+\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4\n+\t/* IPv4 type of service. */\n+\tuint8_t\ttos;\n+\t/* IPv4 identification. */\n+\tuint16_t\tip_id;\n+\t/* IPv4 flags and offset. */\n+\tuint16_t\tflags_frag_offset;\n+\t/* IPv4 TTL. */\n+\tuint8_t\tttl;\n+\t/* IPv4 protocol. */\n+\tuint8_t\tprotocol;\n+\t/* IPv4 source address. */\n+\tuint32_t\tsrc_ip_addr;\n+\t/* IPv4 destination address. */\n+\tuint32_t\tdest_ip_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */\n+struct hwrm_vxlan_ipv6_hdr {\n+\t/* IPv6 version, traffic class and flow label. */\n+\tuint32_t\tver_tc_flow_label;\n+\t/* IPv6 version shift */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \\\n+\t\tUINT32_C(0x1c)\n+\t/* IPv6 version mask */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \\\n+\t\tUINT32_C(0xf0000000)\n+\t/* IPv6 TC shift */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \\\n+\t\tUINT32_C(0x14)\n+\t/* IPv6 TC mask */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \\\n+\t\tUINT32_C(0xff00000)\n+\t/* IPv6 flow label shift */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \\\n+\t\tUINT32_C(0x0)\n+\t/* IPv6 flow label mask */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \\\n+\t\tUINT32_C(0xfffff)\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \\\n+\t\tHWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK\n+\t/* IPv6 payload length. */\n+\tuint16_t\tpayload_len;\n+\t/* IPv6 next header. */\n+\tuint8_t\tnext_hdr;\n+\t/* IPv6 TTL. */\n+\tuint8_t\tttl;\n+\t/* IPv6 source address. */\n+\tuint32_t\tsrc_ip_addr[4];\n+\t/* IPv6 destination address. */\n+\tuint32_t\tdest_ip_addr[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */\n+struct hwrm_cfa_encap_data_vxlan {\n+\t/* Source MAC address. */\n+\tuint8_t\tsrc_mac_addr[6];\n+\t/* reserved. */\n+\tuint16_t\tunused_0;\n+\t/* Destination MAC address. */\n+\tuint8_t\tdst_mac_addr[6];\n+\t/* Number of VLAN tags. */\n+\tuint8_t\tnum_vlan_tags;\n+\t/* reserved. */\n+\tuint8_t\tunused_1;\n+\t/* Outer VLAN TPID. */\n+\tuint16_t\tovlan_tpid;\n+\t/* Outer VLAN TCI. */\n+\tuint16_t\tovlan_tci;\n+\t/* Inner VLAN TPID. */\n+\tuint16_t\tivlan_tpid;\n+\t/* Inner VLAN TCI. */\n+\tuint16_t\tivlan_tci;\n+\t/* L3 header fields. */\n+\tuint32_t\tl3[10];\n+\t/* IP version mask. */\n+\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)\n+\t/* IP version 4. */\n+\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)\n+\t/* IP version 6. */\n+\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)\n+\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \\\n+\t\tHWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6\n+\t/* UDP source port. */\n+\tuint16_t\tsrc_port;\n+\t/* UDP destination port. */\n+\tuint16_t\tdst_port;\n+\t/* VXLAN Network Identifier. */\n+\tuint32_t\tvni;\n+\t/* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */\n+\tuint8_t\thdr_rsvd0[3];\n+\t/* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */\n+\tuint8_t\thdr_rsvd1;\n+\t/* VXLAN header flags field. */\n+\tuint8_t\thdr_flags;\n+\tuint8_t\tunused[3];\n+} __attribute__((packed));\n+\n+/*******************************\n+ * hwrm_cfa_encap_record_alloc *\n+ *******************************/\n+\n+\n+/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */\n+struct hwrm_cfa_encap_record_alloc_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \\\n+\t\tUINT32_C(0x1)\n+\t/* Encapsulation Type. */\n+\tuint8_t\tencap_type;\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) after inside Ethernet payload */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* VLAN */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \\\n+\t\tHWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4\n+\tuint8_t\tunused_0[3];\n+\t/* This value is encap data used for the given encap type. */\n+\tuint32_t\tencap_data[20];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_encap_record_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint32_t\tencap_record_id;\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************************\n+ * hwrm_cfa_encap_record_free *\n+ ******************************/\n+\n+\n+/* hwrm_cfa_encap_record_free_input (size:192b/24B) */\n+struct hwrm_cfa_encap_record_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint32_t\tencap_record_id;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_encap_record_free_output (size:128b/16B) */\n+struct hwrm_cfa_encap_record_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n /********************************\n * hwrm_cfa_ntuple_filter_alloc *\n ********************************/\n", "prefixes": [ "v3", "05/15" ] }