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GET /api/patches/45179/?format=api
{ "id": 45179, "url": "http://patches.dpdk.org/api/patches/45179/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180922045559.27438-5-ajit.khaparde@broadcom.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180922045559.27438-5-ajit.khaparde@broadcom.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180922045559.27438-5-ajit.khaparde@broadcom.com", "date": "2018-09-22T04:55:51", "name": "[v2,04/12] net/bnxt: update HWRM version", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "d23c1f9c746af52fb2aaf68ea9efa2e984f2f285", "submitter": { "id": 501, "url": "http://patches.dpdk.org/api/people/501/?format=api", "name": "Ajit Khaparde", "email": "ajit.khaparde@broadcom.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180922045559.27438-5-ajit.khaparde@broadcom.com/mbox/", "series": [ { "id": 1450, "url": "http://patches.dpdk.org/api/series/1450/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1450", "date": "2018-09-22T04:55:49", "name": "bnxt patchset", "version": 2, "mbox": "http://patches.dpdk.org/series/1450/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/45179/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/45179/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 659CE2B8C;\n\tSun, 23 Sep 2018 12:53:19 +0200 (CEST)", "from rnd-relay.smtp.broadcom.com (rnd-relay.smtp.broadcom.com\n\t[192.19.229.170]) by dpdk.org (Postfix) with ESMTP id 26BF71041\n\tfor <dev@dpdk.org>; Sat, 22 Sep 2018 06:56:17 +0200 (CEST)", "from nis-sj1-27.broadcom.com (nis-sj1-27.lvn.broadcom.net\n\t[10.75.144.136])\n\tby rnd-relay.smtp.broadcom.com (Postfix) with ESMTP id CA59030C04D;\n\tFri, 21 Sep 2018 21:56:09 -0700 (PDT)", "from C02VPB22HTD6.vpn.broadcom.net (unknown [10.10.118.131])\n\tby nis-sj1-27.broadcom.com (Postfix) with ESMTP id A6BAAAC0741;\n\tFri, 21 Sep 2018 21:56:07 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.10.3 rnd-relay.smtp.broadcom.com CA59030C04D", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com;\n\ts=dkimrelay; t=1537592170;\n\tbh=OKV9ARCuqPF+pE+SmYTHew0DZaFqRxf+oeRZMsMnkwI=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=SAkWANhjyphaJP7PkOIk3ouuUMhB/ZMwXzjV+1EkVjn7qiPIlOcas13lig1ScZ81n\n\tfKd41hhntIaOWAoSekQ6BBu3J5MMmv3G+Kf489SBik4UgY/WD91wpi9UGmmhTTjtIu\n\tpEwkk0k9snZxxGu4+iqClTfW3hiGl4OX6swFBzlI=", "From": "Ajit Khaparde <ajit.khaparde@broadcom.com>", "To": "dev@dpdk.org", "Cc": "ferruh.yigit@intel.com", "Date": "Fri, 21 Sep 2018 21:55:51 -0700", "Message-Id": "<20180922045559.27438-5-ajit.khaparde@broadcom.com>", "X-Mailer": "git-send-email 2.17.1 (Apple Git-112)", "In-Reply-To": "<20180922045559.27438-1-ajit.khaparde@broadcom.com>", "References": "<f08457f7-5a78-c7e4-23ff-f4e253cd54c9@intel.com>\n\t<20180922045559.27438-1-ajit.khaparde@broadcom.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-Mailman-Approved-At": "Sun, 23 Sep 2018 12:53:17 +0200", "Subject": "[dpdk-dev] [PATCH v2 04/12] net/bnxt: update HWRM version", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update the HWRM API to version 1.9.2.53\nSigned-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n--\nv1->v2:\nUpdate from 1.9.2.45 to version 1.9.2.53\n---\n drivers/net/bnxt/bnxt_stats.c | 12 +-\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 24017 +++++++++++------------\n 2 files changed, 11540 insertions(+), 12489 deletions(-)", "diff": "diff --git a/drivers/net/bnxt/bnxt_stats.c b/drivers/net/bnxt/bnxt_stats.c\nindex a5d3c8660..f7e6ce4b2 100644\n--- a/drivers/net/bnxt/bnxt_stats.c\n+++ b/drivers/net/bnxt/bnxt_stats.c\n@@ -26,8 +26,8 @@ static const struct bnxt_xstats_name_off bnxt_rx_stats_strings[] = {\n \t\t\t\trx_256b_511b_frames)},\n \t{\"rx_512b_1023b_frames\", offsetof(struct rx_port_stats,\n \t\t\t\trx_512b_1023b_frames)},\n-\t{\"rx_1024b_1518_frames\", offsetof(struct rx_port_stats,\n-\t\t\t\trx_1024b_1518_frames)},\n+\t{\"rx_1024b_1518b_frames\", offsetof(struct rx_port_stats,\n+\t\t\t\trx_1024b_1518b_frames)},\n \t{\"rx_good_vlan_frames\", offsetof(struct rx_port_stats,\n \t\t\t\trx_good_vlan_frames)},\n \t{\"rx_1519b_2047b_frames\", offsetof(struct rx_port_stats,\n@@ -93,12 +93,12 @@ static const struct bnxt_xstats_name_off bnxt_tx_stats_strings[] = {\n \t\t\t\ttx_256b_511b_frames)},\n \t{\"tx_512b_1023b_frames\", offsetof(struct tx_port_stats,\n \t\t\t\ttx_512b_1023b_frames)},\n-\t{\"tx_1024b_1518_frames\", offsetof(struct tx_port_stats,\n-\t\t\t\ttx_1024b_1518_frames)},\n+\t{\"tx_1024b_1518b_frames\", offsetof(struct tx_port_stats,\n+\t\t\t\ttx_1024b_1518b_frames)},\n \t{\"tx_good_vlan_frames\", offsetof(struct tx_port_stats,\n \t\t\t\ttx_good_vlan_frames)},\n-\t{\"tx_1519b_2047_frames\", offsetof(struct tx_port_stats,\n-\t\t\t\ttx_1519b_2047_frames)},\n+\t{\"tx_1519b_2047b_frames\", offsetof(struct tx_port_stats,\n+\t\t\t\ttx_1519b_2047b_frames)},\n \t{\"tx_2048b_4095b_frames\", offsetof(struct tx_port_stats,\n \t\t\t\ttx_2048b_4095b_frames)},\n \t{\"tx_4096b_9216b_frames\", offsetof(struct tx_port_stats,\ndiff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex f5c7b4228..e80057936 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -67,6 +67,10 @@ struct hwrm_resp_hdr {\n #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)\n /* RoCE slow path command */\n #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)\n+/* RoCE slow path command to query CC Gen1 support. */\n+#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)\n+/* RoCE slow path command to modify CC Gen1 support. */\n+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)\n /* Engine CKV - The device's serial number. */\n #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)\n /* Engine CKV - Per-function random nonce data. */\n@@ -256,6 +260,7 @@ struct cmd_nums {\n \t */\n \tuint16_t\treq_type;\n \t#define HWRM_VER_GET UINT32_C(0x0)\n+\t#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)\n \t#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)\n \t#define HWRM_FUNC_VF_CFG UINT32_C(0xf)\n \t/* Reserved for future use. */\n@@ -328,6 +333,7 @@ struct cmd_nums {\n \t#define HWRM_RING_FREE UINT32_C(0x51)\n \t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS UINT32_C(0x52)\n \t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS UINT32_C(0x53)\n+\t#define HWRM_RING_AGGINT_QCAPS UINT32_C(0x54)\n \t#define HWRM_RING_RESET UINT32_C(0x5e)\n \t#define HWRM_RING_GRP_ALLOC UINT32_C(0x60)\n \t#define HWRM_RING_GRP_FREE UINT32_C(0x61)\n@@ -367,6 +373,8 @@ struct cmd_nums {\n \t#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)\n \t#define HWRM_FW_RESET UINT32_C(0xc0)\n \t#define HWRM_FW_QSTATUS UINT32_C(0xc1)\n+\t#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)\n+\t#define HWRM_FW_SYNC UINT32_C(0xc3)\n \t/* Experimental */\n \t#define HWRM_FW_SET_TIME UINT32_C(0xc8)\n \t/* Experimental */\n@@ -433,6 +441,7 @@ struct cmd_nums {\n \t/* Experimental */\n \t#define HWRM_FW_IPC_MSG UINT32_C(0x110)\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)\n \t/* Engine CKV - Ping the device and SRT firmware to get the public key. */\n \t#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)\n \t/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */\n@@ -515,6 +524,10 @@ struct cmd_nums {\n \t#define HWRM_FUNC_BACKING_STORE_CFG UINT32_C(0x193)\n \t/* Experimental */\n \t#define HWRM_FUNC_BACKING_STORE_QCFG UINT32_C(0x194)\n+\t/* Configures the BW of any VF */\n+\t#define HWRM_FUNC_VF_BW_CFG UINT32_C(0x195)\n+\t/* Queries the BW of any VF */\n+\t#define HWRM_FUNC_VF_BW_QCFG UINT32_C(0x196)\n \t/* Experimental */\n \t#define HWRM_SELFTEST_QLIST UINT32_C(0x200)\n \t/* Experimental */\n@@ -544,8 +557,12 @@ struct cmd_nums {\n \t#define HWRM_DBG_COREDUMP_INITIATE UINT32_C(0xff18)\n \t/* Experimental */\n \t#define HWRM_DBG_COREDUMP_RETRIEVE UINT32_C(0xff19)\n+\t/* Experimental */\n+\t#define HWRM_DBG_FW_CLI UINT32_C(0xff1a)\n \t/* */\n \t#define HWRM_DBG_I2C_CMD UINT32_C(0xff1b)\n+\t/* */\n+\t#define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)\n \t/* Experimental */\n \t#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)\n \t#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)\n@@ -615,6 +632,11 @@ struct ret_codes {\n \t * should retry the request.\n \t */\n \t#define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)\n+\t/*\n+\t * This error code is only reported by firmware when some\n+\t * sub-option of a supported HWRM command is unsupported.\n+\t */\n+\t#define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)\n \t/*\n \t * Generic HWRM execution error that represents an\n \t * internal error.\n@@ -686,8 +708,8 @@ struct hwrm_err_output {\n #define HWRM_VERSION_MINOR 9\n #define HWRM_VERSION_UPDATE 2\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 9\n-#define HWRM_VERSION_STR \"1.9.2.9\"\n+#define HWRM_VERSION_RSVD 53\n+#define HWRM_VERSION_STR \"1.9.2.53\"\n \n /****************\n * hwrm_ver_get *\n@@ -901,6 +923,42 @@ struct hwrm_ver_get_output {\n \t */\n \t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED \\\n \t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, then the KONG host mailbox channel is supported.\n+\t * If set to 0, then the KONG host mailbox channel is not supported.\n+\t * By default, this flag should be 0 for older version of core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * If set to 1, then the 64bit flow handle is supported in addition to the\n+\t * legacy 16bit flow handle. If set to 0, then the 64bit flow handle is not\n+\t * supported. By default, this flag should be 0 for older version of core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * If set to 1, then filter type can be provided in filter_alloc or filter_cfg\n+\t * filter types like L2 for l2 traffic and ROCE for roce & l2 traffic.\n+\t * If set to 0, then filter types not supported.\n+\t * By default, this flag should be 0 for older version of core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * If set to 1, firmware is capable to support virtio vSwitch offload model.\n+\t * If set to 0, firmware can't supported virtio vSwitch offload model.\n+\t * By default, this flag should be 0 for older version of core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * If set to 1, firmware is capable to support trusted VF.\n+\t * If set to 0, firmware is not capable to support trusted VF.\n+\t * By default, this flag should be 0 for older version of core firmware.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \\\n+\t\tUINT32_C(0x100)\n \t/*\n \t * This field represents the major version of RoCE firmware.\n \t * A change in major version represents a major release.\n@@ -1154,39 +1212,45 @@ struct hwrm_ver_get_output {\n struct bd_base {\n \tuint8_t\ttype;\n \t/* This value identifies the type of buffer descriptor. */\n-\t#define BD_BASE_TYPE_MASK UINT32_C(0x3f)\n-\t#define BD_BASE_TYPE_SFT 0\n+\t#define BD_BASE_TYPE_MASK UINT32_C(0x3f)\n+\t#define BD_BASE_TYPE_SFT 0\n \t/*\n \t * Indicates that this BD is 16B long and is used for\n \t * normal L2 packet transmission.\n \t */\n-\t#define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)\n+\t#define BD_BASE_TYPE_TX_BD_SHORT UINT32_C(0x0)\n \t/*\n \t * Indicates that this BD is 1BB long and is an empty\n \t * TX BD. Not valid for use by the driver.\n \t */\n-\t#define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)\n+\t#define BD_BASE_TYPE_TX_BD_EMPTY UINT32_C(0x1)\n \t/*\n \t * Indicates that this BD is 16B long and is an RX Producer\n \t * (ie. empty) buffer descriptor.\n \t */\n-\t#define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)\n+\t#define BD_BASE_TYPE_RX_PROD_PKT UINT32_C(0x4)\n \t/*\n \t * Indicates that this BD is 16B long and is an RX\n \t * Producer Buffer BD.\n \t */\n-\t#define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)\n+\t#define BD_BASE_TYPE_RX_PROD_BFR UINT32_C(0x5)\n \t/*\n \t * Indicates that this BD is 16B long and is an\n \t * RX Producer Assembly Buffer Descriptor.\n \t */\n-\t#define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)\n+\t#define BD_BASE_TYPE_RX_PROD_AGG UINT32_C(0x6)\n \t/*\n \t * Indicates that this BD is 32B long and is used for\n \t * normal L2 packet transmission.\n \t */\n-\t#define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)\n-\t#define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG\n+\t#define BD_BASE_TYPE_TX_BD_LONG UINT32_C(0x10)\n+\t/*\n+\t * Indicates that this BD is 32B long and is used for\n+\t * L2 packet transmission for small packets that require\n+\t * low latency.\n+\t */\n+\t#define BD_BASE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)\n+\t#define BD_BASE_TYPE_LAST BD_BASE_TYPE_TX_BD_LONG_INLINE\n \tuint8_t\tunused_1[7];\n } __attribute__((packed));\n \n@@ -1406,6 +1470,7 @@ struct tx_bd_long {\n \tuint64_t\taddress;\n } __attribute__((packed));\n \n+/* Last 16 bytes of tx_bd_long. */\n /* tx_bd_long_hi (size:128b/16B) */\n struct tx_bd_long_hi {\n \t/*\n@@ -1595,6 +1660,219 @@ struct tx_bd_long_hi {\n \t\tTX_BD_LONG_CFA_META_KEY_VLAN_TAG\n } __attribute__((packed));\n \n+/*\n+ * This structure is used to inform the NIC of packet data that needs to be\n+ * transmitted with additional processing that requires extra data such as\n+ * VLAN insertion plus attached inline data. This BD type may be used to\n+ * improve latency for small packets needing the additional extended features\n+ * supported by long BDs.\n+ */\n+/* tx_bd_long_inline (size:256b/32B) */\n+struct tx_bd_long_inline {\n+\tuint16_t\tflags_type;\n+\t/* This value identifies the type of buffer descriptor. */\n+\t#define TX_BD_LONG_INLINE_TYPE_MASK UINT32_C(0x3f)\n+\t#define TX_BD_LONG_INLINE_TYPE_SFT 0\n+\t/*\n+\t * This type of BD is 32B long and is used for inline L2 packet\n+\t * transmission.\n+\t */\n+\t#define TX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE UINT32_C(0x11)\n+\t#define TX_BD_LONG_INLINE_TYPE_LAST \\\n+\t\tTX_BD_LONG_INLINE_TYPE_TX_BD_LONG_INLINE\n+\t/*\n+\t * All bits in this field may be set on the first BD of a packet.\n+\t * Only the packet_end bit may be set in non-first BDs.\n+\t */\n+\t#define TX_BD_LONG_INLINE_FLAGS_MASK UINT32_C(0xffc0)\n+\t#define TX_BD_LONG_INLINE_FLAGS_SFT 6\n+\t/*\n+\t * If set to 1, the packet ends with the data in the buffer\n+\t * pointed to by this descriptor. This flag must be\n+\t * valid on every BD.\n+\t */\n+\t#define TX_BD_LONG_INLINE_FLAGS_PACKET_END UINT32_C(0x40)\n+\t/*\n+\t * If set to 1, the device will not generate a completion for\n+\t * this transmit packet unless there is an error in its processing.\n+\t * If this bit is set to 0, then the packet will be completed\n+\t * normally.\n+\t *\n+\t * This bit may be set only on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_INLINE_FLAGS_NO_CMPL UINT32_C(0x80)\n+\t/*\n+\t * This value indicates how many 16B BD locations are consumed\n+\t * in the ring by this packet, including the BD and inline\n+\t * data.\n+\t */\n+\t#define TX_BD_LONG_INLINE_FLAGS_BD_CNT_MASK UINT32_C(0x1f00)\n+\t#define TX_BD_LONG_INLINE_FLAGS_BD_CNT_SFT 8\n+\t/* This field is deprecated. */\n+\t#define TX_BD_LONG_INLINE_FLAGS_LHINT_MASK UINT32_C(0x6000)\n+\t#define TX_BD_LONG_INLINE_FLAGS_LHINT_SFT 13\n+\t/*\n+\t * If set to 1, the device immediately updates the Send Consumer\n+\t * Index after the buffer associated with this descriptor has\n+\t * been transferred via DMA to NIC memory from host memory. An\n+\t * interrupt may or may not be generated according to the state\n+\t * of the interrupt avoidance mechanisms. If this bit\n+\t * is set to 0, then the Consumer Index is only updated as soon\n+\t * as one of the host interrupt coalescing conditions has been met.\n+\t *\n+\t * This bit must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_INLINE_FLAGS_COAL_NOW UINT32_C(0x8000)\n+\t/*\n+\t * This is the length of the inline data, not including BD length, in\n+\t * bytes.\n+\t * The maximum value is 480.\n+\t *\n+\t * This field must be valid on all BDs of a packet.\n+\t */\n+\tuint16_t\tlen;\n+\t/*\n+\t * The opaque data field is passed through to the completion and can be\n+\t * used for any data that the driver wants to associate with the transmit\n+\t * BD.\n+\t *\n+\t * This field must be valid on the first BD of a packet.\n+\t */\n+\tuint32_t\topaque;\n+\tuint64_t\tunused1;\n+\t/*\n+\t * All bits in this field must be valid on the first BD of a packet.\n+\t * Their value on other BDs of the packet is ignored.\n+\t */\n+\tuint16_t\tlflags;\n+\t/*\n+\t * If set to 1, the controller replaces the TCP/UPD checksum\n+\t * fields of normal TCP/UPD checksum, or the inner TCP/UDP\n+\t * checksum field of the encapsulated TCP/UDP packets with the\n+\t * hardware calculated TCP/UDP checksum for the packet associated\n+\t * with this descriptor. The flag is ignored if the LSO flag is set.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_TCP_UDP_CHKSUM UINT32_C(0x1)\n+\t/*\n+\t * If set to 1, the controller replaces the IP checksum of the\n+\t * normal packets, or the inner IP checksum of the encapsulated\n+\t * packets with the hardware calculated IP checksum for the\n+\t * packet associated with this descriptor.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_IP_CHKSUM UINT32_C(0x2)\n+\t/*\n+\t * If set to 1, the controller will not append an Ethernet CRC\n+\t * to the end of the frame.\n+\t *\n+\t * Packet must be 64B or longer when this flag is set. It is not\n+\t * useful to use this bit with any form of TX offload such as\n+\t * CSO or LSO. The intent is that the packet from the host already\n+\t * has a valid Ethernet CRC on the packet.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_NOCRC UINT32_C(0x4)\n+\t/*\n+\t * If set to 1, the device will record the time at which the packet\n+\t * was actually transmitted at the TX MAC.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_STAMP UINT32_C(0x8)\n+\t/*\n+\t * If set to 1, the controller replaces the tunnel IP checksum\n+\t * field with hardware calculated IP checksum for the IP header\n+\t * of the packet associated with this descriptor. The hardware\n+\t * updates an outer UDP checksum if it is non-zero.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_T_IP_CHKSUM UINT32_C(0x10)\n+\t/*\n+\t * This bit must be 0 for BDs of this type. LSO is not supported with\n+\t * inline BDs.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_LSO UINT32_C(0x20)\n+\t/* Since LSO is not supported with inline BDs, this bit is not used. */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_IPID_FMT UINT32_C(0x40)\n+\t/* Since LSO is not supported with inline BDs, this bit is not used. */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_T_IPID UINT32_C(0x80)\n+\t/*\n+\t * If set to '1', then the RoCE ICRC will be appended to the\n+\t * packet. Packet must be a valid RoCE format packet.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_ROCE_CRC UINT32_C(0x100)\n+\t/*\n+\t * If set to '1', then the FCoE CRC will be appended to the\n+\t * packet. Packet must be a valid FCoE format packet.\n+\t */\n+\t#define TX_BD_LONG_INLINE_LFLAGS_FCOE_CRC UINT32_C(0x200)\n+\tuint16_t\tunused2;\n+\tuint32_t\tunused3;\n+\tuint16_t\tunused4;\n+\t/*\n+\t * This value selects a CFA action to perform on the packet.\n+\t * Set this value to zero if no CFA action is desired.\n+\t *\n+\t * This value must be valid on the first BD of a packet.\n+\t */\n+\tuint16_t\tcfa_action;\n+\t/*\n+\t * This value is action meta-data that defines CFA edit operations\n+\t * that are done in addition to any action editing.\n+\t */\n+\tuint32_t\tcfa_meta;\n+\t/* When key = 1, this is the VLAN tag VID value. */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK UINT32_C(0xfff)\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT 0\n+\t/* When key = 1, this is the VLAN tag DE value. */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_DE UINT32_C(0x1000)\n+\t/* When key = 1, this is the VLAN tag PRI value. */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK UINT32_C(0xe000)\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT 13\n+\t/* When key = 1, this is the VLAN tag TPID select value. */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK UINT32_C(0x70000)\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT 16\n+\t/* 0x88a8 */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \\\n+\t\t(UINT32_C(0x0) << 16)\n+\t/* 0x8100 */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID8100 \\\n+\t\t(UINT32_C(0x1) << 16)\n+\t/* 0x9100 */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9100 \\\n+\t\t(UINT32_C(0x2) << 16)\n+\t/* 0x9200 */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9200 \\\n+\t\t(UINT32_C(0x3) << 16)\n+\t/* 0x9300 */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID9300 \\\n+\t\t(UINT32_C(0x4) << 16)\n+\t/* Value programmed in CFA VLANTPID register. */\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG \\\n+\t\t(UINT32_C(0x5) << 16)\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_LAST \\\n+\t\tTX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \\\n+\t\tUINT32_C(0xff80000)\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19\n+\t/*\n+\t * This field identifies the type of edit to be performed\n+\t * on the packet.\n+\t *\n+\t * This value must be valid on the first BD of a packet.\n+\t */\n+\t#define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \\\n+\t\tUINT32_C(0xf0000000)\n+\t#define TX_BD_LONG_INLINE_CFA_META_KEY_SFT 28\n+\t/* No editing */\n+\t#define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/*\n+\t * - meta[17:16] - TPID select value (0 = 0x8100).\n+\t * - meta[15:12] - PRI/DE value.\n+\t * - meta[11:0] - VID value.\n+\t */\n+\t#define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \\\n+\t\tTX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG\n+} __attribute__((packed));\n+\n /* tx_bd_empty (size:128b/16B) */\n struct tx_bd_empty {\n \t/* This value identifies the type of buffer descriptor. */\n@@ -2121,6 +2399,7 @@ struct rx_pkt_cmpl {\n \tuint32_t\trss_hash;\n } __attribute__((packed));\n \n+/* Last 16 bytes of rx_pkt_cmpl. */\n /* rx_pkt_cmpl_hi (size:128b/16B) */\n struct rx_pkt_cmpl_hi {\n \tuint32_t\tflags2;\n@@ -2566,6 +2845,7 @@ struct rx_tpa_start_cmpl {\n \tuint32_t\trss_hash;\n } __attribute__((packed));\n \n+/* Last 16 bytes of rx_tpq_start_cmpl. */\n /* rx_tpa_start_cmpl_hi (size:128b/16B) */\n struct rx_tpa_start_cmpl_hi {\n \tuint32_t\tflags2;\n@@ -2830,6 +3110,7 @@ struct rx_tpa_end_cmpl {\n \tuint32_t\ttsdelta;\n } __attribute__((packed));\n \n+/* Last 16 bytes of rx_tpa_end_cmpl. */\n /* rx_tpa_end_cmpl_hi (size:128b/16B) */\n struct rx_tpa_end_cmpl_hi {\n \t/*\n@@ -3153,6 +3434,9 @@ struct hwrm_async_event_cmpl {\n \t/* Port PHY configuration change */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE \\\n \t\tUINT32_C(0x7)\n+\t/* Reset notification to clients */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \\\n+\t\tUINT32_C(0x8)\n \t/* Function driver unloaded */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \\\n \t\tUINT32_C(0x10)\n@@ -3790,6 +4074,96 @@ struct hwrm_async_event_cmpl_port_phy_cfg_change {\n \t\tUINT32_C(0x40000)\n } __attribute__((packed));\n \n+/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */\n+struct hwrm_async_event_cmpl_reset_notify {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/* Notify clients of imminent reset. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY \\\n+\t\tUINT32_C(0x8)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY\n+\t/* Event specific data */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_V UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data */\n+\tuint32_t\tevent_data1;\n+\t/* Indicates driver action requested */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT \\\n+\t\t0\n+\t/*\n+\t * If set to 1, it indicates that the l2 client should\n+\t * stop sending in band traffic to Nitro.\n+\t * if set to 0, there is no change in L2 client behavior.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, it indicates that the L2 client should\n+\t * bring down the interface.\n+\t * If set to 0, then there is no change in L2 client behavior.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN\n+\t/* Indicates reason for reset. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK \\\n+\t\tUINT32_C(0xff00)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT \\\n+\t\t8\n+\t/* A management client has requested reset. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST \\\n+\t\t(UINT32_C(0x1) << 8)\n+\t/* A fatal firmware exception has occurred. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL \\\n+\t\t(UINT32_C(0x2) << 8)\n+\t/* A non-fatal firmware exception has occurred. */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \\\n+\t\t(UINT32_C(0x3) << 8)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL\n+\t/*\n+\t * Minimum time before driver should attempt access - units 100ms ticks.\n+\t * Range 0-65535\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK \\\n+\t\tUINT32_C(0xffff0000)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT \\\n+\t\t16\n+} __attribute__((packed));\n+\n /* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */\n struct hwrm_async_event_cmpl_func_drvr_unload {\n \tuint16_t\ttype;\n@@ -4285,6 +4659,13 @@ struct hwrm_async_event_cmpl_vf_cfg_change {\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE \\\n \t\tUINT32_C(0x8)\n+\t/*\n+\t * If this bit is set to 1, then the value of trusted VF enable\n+\t * was changed on this VF.\n+\t * If set to 0, then this bit should be ignored.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE \\\n+\t\tUINT32_C(0x10)\n } __attribute__((packed));\n \n /* hwrm_async_event_cmpl_llfc_pfc_change (size:128b/16B) */\n@@ -5305,6 +5686,20 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \\\n \t\tUINT32_C(0x40000)\n+\t/*\n+\t * If the query is for a VF, then this flag shall be ignored.\n+\t * If this query is for a PF and this flag is set to 1, then\n+\t * the PF will know that the firmware has the capability to track\n+\t * the virtual link status.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED \\\n+\t\tUINT32_C(0x80000)\n+\t/*\n+\t * If 1, then this function supports the push mode that uses\n+\t * write combine buffers and the long inline tx buffer descriptor.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \\\n+\t\tUINT32_C(0x100000)\n \t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n@@ -5547,6 +5942,15 @@ struct hwrm_func_qcfg_output {\n \t */\n \t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST \\\n \t\tUINT32_C(0x20)\n+\t/*\n+\t * If the function that is being queried is a PF, then the HWRM shall\n+\t * set this field to 0 and the HWRM client shall ignore this field.\n+\t * If the function that is being queried is a VF, then the HWRM shall\n+\t * set this field to 1 if the queried VF is trusted, otherwise the HWRM\n+\t * shall set this field to 0.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \\\n+\t\tUINT32_C(0x40)\n \t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n@@ -5755,7 +6159,7 @@ struct hwrm_func_qcfg_output {\n \t */\n \t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_MASK \\\n \t\tUINT32_C(0x3)\n-\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0\n+\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SFT 0\n \t/* Cache Line Size 64 bytes */\n \t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \\\n \t\tUINT32_C(0x0)\n@@ -5764,10 +6168,25 @@ struct hwrm_func_qcfg_output {\n \t\tUINT32_C(0x1)\n \t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_LAST \\\n \t\tHWRM_FUNC_QCFG_OUTPUT_OPTIONS_CACHE_LINESIZE_SIZE_128\n+\t/* This value is the virtual link admin state setting. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_MASK \\\n+\t\tUINT32_C(0xc)\n+\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2\n+\t/* Admin link state is in forced down mode. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \\\n+\t\t(UINT32_C(0x0) << 2)\n+\t/* Admin link state is in forced up mode. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \\\n+\t\t(UINT32_C(0x1) << 2)\n+\t/* Admin link state is in auto mode - follows the physical link state. */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \\\n+\t\t(UINT32_C(0x2) << 2)\n+\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_LAST \\\n+\t\tHWRM_FUNC_QCFG_OUTPUT_OPTIONS_LINK_ADMIN_STATE_AUTO\n \t/* Reserved for future. */\n \t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_MASK \\\n-\t\tUINT32_C(0xfc)\n-\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 2\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_FUNC_QCFG_OUTPUT_OPTIONS_RSVD_SFT 4\n \t/*\n \t * The number of VFs that are allocated to the function.\n \t * This is valid only on the PF with SR-IOV enabled.\n@@ -5814,13 +6233,13 @@ struct hwrm_func_qcfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_func_vlan_qcfg *\n- ***********************/\n+/*****************\n+ * hwrm_func_cfg *\n+ *****************/\n \n \n-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n-struct hwrm_func_vlan_qcfg_input {\n+/* hwrm_func_cfg_input (size:704b/88B) */\n+struct hwrm_func_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -5851,236 +6270,25 @@ struct hwrm_func_vlan_qcfg_input {\n \t/*\n \t * Function ID of the function that is being\n \t * configured.\n-\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * If set to 0xFF... (All Fs), then the the configuration is\n \t * for the requesting function.\n \t */\n \tuint16_t\tfid;\n-\tuint8_t\tunused_0[6];\n-} __attribute__((packed));\n-\n-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n-struct hwrm_func_vlan_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This field specifies how many NQs will be reserved for the PF.\n+\t * Remaining NQs that belong to the PF become available for VFs.\n+\t * Once a PF has created VFs, it cannot change how many NQs are\n+\t * reserved for itself (since the NQs must be contiguous in HW).\n \t */\n-\tuint8_t\tvalid;\n-\t/* S-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tstag_vid;\n-\t/* S-TAG PCP value configured for the function. */\n-\tuint8_t\tstag_pcp;\n-\tuint8_t\tunused_1;\n+\tuint16_t\tnum_msix;\n+\tuint32_t\tflags;\n \t/*\n-\t * S-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n-\t */\n-\tuint16_t\tstag_tpid;\n-\t/* C-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tctag_vid;\n-\t/* C-TAG PCP value configured for the function. */\n-\tuint8_t\tctag_pcp;\n-\tuint8_t\tunused_2;\n-\t/*\n-\t * C-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n-\t */\n-\tuint16_t\tctag_tpid;\n-\t/* Future use. */\n-\tuint32_t\trsvd2;\n-\t/* Future use. */\n-\tuint32_t\trsvd3;\n-\tuint32_t\tunused_3;\n-} __attribute__((packed));\n-\n-/**********************\n- * hwrm_func_vlan_cfg *\n- **********************/\n-\n-\n-/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n-struct hwrm_func_vlan_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/*\n-\t * Function ID of the function that is being\n-\t * configured.\n-\t * If set to 0xFF... (All Fs), then the configuration is\n-\t * for the requesting function.\n-\t */\n-\tuint16_t\tfid;\n-\tuint8_t\tunused_0[2];\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the stag_vid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the ctag_vid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)\n-\t/*\n-\t * This bit must be '1' for the stag_pcp field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)\n-\t/*\n-\t * This bit must be '1' for the ctag_pcp field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)\n-\t/*\n-\t * This bit must be '1' for the stag_tpid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)\n-\t/*\n-\t * This bit must be '1' for the ctag_tpid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)\n-\t/* S-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tstag_vid;\n-\t/* S-TAG PCP value configured for the function. */\n-\tuint8_t\tstag_pcp;\n-\tuint8_t\tunused_1;\n-\t/*\n-\t * S-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n-\t */\n-\tuint16_t\tstag_tpid;\n-\t/* C-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tctag_vid;\n-\t/* C-TAG PCP value configured for the function. */\n-\tuint8_t\tctag_pcp;\n-\tuint8_t\tunused_2;\n-\t/*\n-\t * C-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n-\t */\n-\tuint16_t\tctag_tpid;\n-\t/* Future use. */\n-\tuint32_t\trsvd1;\n-\t/* Future use. */\n-\tuint32_t\trsvd2;\n-\tuint8_t\tunused_3[4];\n-} __attribute__((packed));\n-\n-/* hwrm_func_vlan_cfg_output (size:128b/16B) */\n-struct hwrm_func_vlan_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/*****************\n- * hwrm_func_cfg *\n- *****************/\n-\n-\n-/* hwrm_func_cfg_input (size:704b/88B) */\n-struct hwrm_func_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/*\n-\t * Function ID of the function that is being\n-\t * configured.\n-\t * If set to 0xFF... (All Fs), then the the configuration is\n-\t * for the requesting function.\n-\t */\n-\tuint16_t\tfid;\n-\t/*\n-\t * This field specifies how many NQs will be reserved for the PF.\n-\t * Remaining NQs that belong to the PF become available for VFs.\n-\t * Once a PF has created VFs, it cannot change how many NQs are\n-\t * reserved for itself (since the NQs must be contiguous in HW).\n-\t */\n-\tuint16_t\tnum_msix;\n-\tuint32_t\tflags;\n-\t/*\n-\t * When this bit is '1', the function is disabled with\n-\t * source MAC address check.\n-\t * This is an anti-spoofing check. If this flag is set,\n-\t * then the function shall be configured to disallow\n-\t * transmission of frames with the source MAC address that\n-\t * is configured for this function.\n+\t * When this bit is '1', the function is disabled with\n+\t * source MAC address check.\n+\t * This is an anti-spoofing check. If this flag is set,\n+\t * then the function shall be configured to disallow\n+\t * transmission of frames with the source MAC address that\n+\t * is configured for this function.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE \\\n \t\tUINT32_C(0x1)\n@@ -6205,6 +6413,17 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \\\n \t\tUINT32_C(0x100000)\n+\t/*\n+\t * This configuration change can be initiated by a PF driver. This\n+\t * configuration request shall be targeted to a VF. From local host\n+\t * resident HWRM clients, only the parent PF driver shall be allowed\n+\t * to initiate this change on one of its children VFs. If this bit is\n+\t * set to 1, then the VF that is being configured is requested to be\n+\t * trusted. If this bit is set to 0, then the VF that is being configured\n+\t * is requested to be not trusted.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \\\n+\t\tUINT32_C(0x200000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the mtu field to be\n@@ -6338,6 +6557,12 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX \\\n \t\tUINT32_C(0x200000)\n+\t/*\n+\t * This bit must be '1' for the link admin state field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_ENABLES_ADMIN_LINK_STATE \\\n+\t\tUINT32_C(0x400000)\n \t/*\n \t * The maximum transmission unit of the function.\n \t * The HWRM should make sure that the mtu of\n@@ -6569,7 +6794,7 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_MASK \\\n \t\tUINT32_C(0x3)\n-\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0\n+\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SFT 0\n \t/* Cache Line Size 64 bytes */\n \t#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_64 \\\n \t\tUINT32_C(0x0)\n@@ -6578,10 +6803,25 @@ struct hwrm_func_cfg_input {\n \t\tUINT32_C(0x1)\n \t#define HWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_LAST \\\n \t\tHWRM_FUNC_CFG_INPUT_OPTIONS_CACHE_LINESIZE_SIZE_128\n+\t/* This value is the virtual link admin state setting. */\n+\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_MASK \\\n+\t\tUINT32_C(0xc)\n+\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_SFT 2\n+\t/* Admin state is forced down. */\n+\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN \\\n+\t\t(UINT32_C(0x0) << 2)\n+\t/* Admin state is forced up. */\n+\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_FORCED_UP \\\n+\t\t(UINT32_C(0x1) << 2)\n+\t/* Admin state is in auto mode - is to follow the physical link state. */\n+\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO \\\n+\t\t(UINT32_C(0x2) << 2)\n+\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_LAST \\\n+\t\tHWRM_FUNC_CFG_INPUT_OPTIONS_LINK_ADMIN_STATE_AUTO\n \t/* Reserved for future. */\n \t#define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_MASK \\\n-\t\tUINT32_C(0xfc)\n-\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 2\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_FUNC_CFG_INPUT_OPTIONS_RSVD_SFT 4\n \t/*\n \t * The number of multicast filters that should\n \t * be reserved for this function on the RX side.\n@@ -6862,13 +7102,13 @@ struct hwrm_func_vf_resc_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************************\n- * hwrm_func_vf_vnic_ids_query *\n- *******************************/\n+/**********************\n+ * hwrm_func_drv_rgtr *\n+ **********************/\n \n \n-/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */\n-struct hwrm_func_vf_vnic_ids_query_input {\n+/* hwrm_func_drv_rgtr_input (size:896b/112B) */\n+struct hwrm_func_drv_rgtr_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -6896,98 +7136,27 @@ struct hwrm_func_vf_vnic_ids_query_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n \t/*\n-\t * This value is used to identify a Virtual Function (VF).\n-\t * The scope of VF ID is local within a PF.\n+\t * When this bit is '1', the function driver is requesting\n+\t * all requests from its children VF drivers to be\n+\t * forwarded to itself.\n+\t * This flag can only be set by the PF driver.\n+\t * If a VF driver sets this flag, it should be ignored\n+\t * by the HWRM.\n \t */\n-\tuint16_t\tvf_id;\n-\tuint8_t\tunused_0[2];\n-\t/* Max number of vnic ids in vnic id table */\n-\tuint32_t\tmax_vnic_id_cnt;\n-\t/* This is the address for VF VNIC ID table */\n-\tuint64_t\tvnic_id_tbl_addr;\n-} __attribute__((packed));\n-\n-/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */\n-struct hwrm_func_vf_vnic_ids_query_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n+\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * Actual number of vnic ids\n-\t *\n-\t * Each VNIC ID is written as a 32-bit number.\n+\t * When this bit is '1', the function is requesting none of\n+\t * the requests from its children VF drivers to be\n+\t * forwarded to itself.\n+\t * This flag can only be set by the PF driver.\n+\t * If a VF driver sets this flag, it should be ignored\n+\t * by the HWRM.\n \t */\n-\tuint32_t\tvnic_id_cnt;\n-\tuint8_t\tunused_0[3];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**********************\n- * hwrm_func_drv_rgtr *\n- **********************/\n-\n-\n-/* hwrm_func_drv_rgtr_input (size:896b/112B) */\n-struct hwrm_func_drv_rgtr_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/*\n-\t * When this bit is '1', the function driver is requesting\n-\t * all requests from its children VF drivers to be\n-\t * forwarded to itself.\n-\t * This flag can only be set by the PF driver.\n-\t * If a VF driver sets this flag, it should be ignored\n-\t * by the HWRM.\n-\t */\n-\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_ALL_MODE UINT32_C(0x1)\n-\t/*\n-\t * When this bit is '1', the function is requesting none of\n-\t * the requests from its children VF drivers to be\n-\t * forwarded to itself.\n-\t * This flag can only be set by the PF driver.\n-\t * If a VF driver sets this flag, it should be ignored\n-\t * by the HWRM.\n-\t */\n-\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE UINT32_C(0x2)\n+\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE \\\n+\t\tUINT32_C(0x2)\n \t/*\n \t * When this bit is '1', then ver_maj_8b, ver_min_8b, ver_upd_8b\n \t * fields shall be ignored and ver_maj, ver_min, ver_upd\n@@ -6996,7 +7165,22 @@ struct hwrm_func_drv_rgtr_input {\n \t * fields shall be used for the driver version information and\n \t * ver_maj, ver_min, ver_upd and ver_patch shall be ignored.\n \t */\n-\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE UINT32_C(0x4)\n+\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_16BIT_VER_MODE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', the function is indicating support of\n+\t * 64bit flow handle. The firmware that only supports 64bit flow\n+\t * handle should check this bit before allowing processing of\n+\t * HWRM_CFA_FLOW_XXX commands from the requesting function as firmware\n+\t * with 64bit flow handle support can only be compatible with drivers\n+\t * that support 64bit flow handle. The legacy drivers that don't support\n+\t * 64bit flow handle won't be able to use HWRM_CFA_FLOW_XXX commands when\n+\t * running with new firmware that only supports 64bit flow handle. The new\n+\t * firmware support 64bit flow handle returns HWRM_ERR_CODE_CMD_NOT_SUPPORTED\n+\t * status to the legacy driver when encounters these commands.\n+\t */\n+\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \\\n+\t\tUINT32_C(0x8)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the os_type field to be\n@@ -7117,7 +7301,14 @@ struct hwrm_func_drv_rgtr_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint32_t\tflags;\n+\t/*\n+\t * When this bit is '1', it indicates that the\n+\t * HWRM_FUNC_DRV_IF_CHANGE call is supported.\n+\t */\n+\t#define HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -7441,7 +7632,7 @@ struct hwrm_func_drv_qver_input {\n \tuint8_t\tunused_0[2];\n } __attribute__((packed));\n \n-/* hwrm_func_drv_qver_output (size:192b/24B) */\n+/* hwrm_func_drv_qver_output (size:256b/32B) */\n struct hwrm_func_drv_qver_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -7483,15 +7674,7 @@ struct hwrm_func_drv_qver_output {\n \tuint8_t\tver_min_8b;\n \t/* This is the 8bit update version of the driver. */\n \tuint8_t\tver_upd_8b;\n-\tuint8_t\tunused_0[2];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n+\tuint8_t\tunused_0[3];\n \t/* This is the 16bit major version of the driver. */\n \tuint16_t\tver_maj;\n \t/* This is the 16bit minor version of the driver. */\n@@ -7500,6 +7683,15 @@ struct hwrm_func_drv_qver_output {\n \tuint16_t\tver_upd;\n \t/* This is the 16bit patch version of the driver. */\n \tuint16_t\tver_patch;\n+\tuint8_t\tunused_1[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n } __attribute__((packed));\n \n /****************************\n@@ -7612,117 +7804,15 @@ struct hwrm_func_resource_qcaps_output {\n \t * The number of TX rings assigned to the function cannot exceed this value.\n \t */\n \tuint16_t\tmax_tx_scheduler_inputs;\n-\tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/*****************************\n- * hwrm_func_vf_resource_cfg *\n- *****************************/\n-\n-\n-/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */\n-struct hwrm_func_vf_resource_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n+\tuint16_t\tflags;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * When this bit is '1', it indicates that VF_RESOURCE_CFG supports\n+\t * feature to reserve all minimum resources when minimum >= 1, otherwise\n+\t * returns an error.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* VF ID that is being configured by PF */\n-\tuint16_t\tvf_id;\n-\t/* Maximum guaranteed number of MSI-X vectors for the function */\n-\tuint16_t\tmax_msix;\n-\t/* Minimum guaranteed number of RSS/COS contexts */\n-\tuint16_t\tmin_rsscos_ctx;\n-\t/* Maximum non-guaranteed number of RSS/COS contexts */\n-\tuint16_t\tmax_rsscos_ctx;\n-\t/* Minimum guaranteed number of completion rings */\n-\tuint16_t\tmin_cmpl_rings;\n-\t/* Maximum non-guaranteed number of completion rings */\n-\tuint16_t\tmax_cmpl_rings;\n-\t/* Minimum guaranteed number of transmit rings */\n-\tuint16_t\tmin_tx_rings;\n-\t/* Maximum non-guaranteed number of transmit rings */\n-\tuint16_t\tmax_tx_rings;\n-\t/* Minimum guaranteed number of receive rings */\n-\tuint16_t\tmin_rx_rings;\n-\t/* Maximum non-guaranteed number of receive rings */\n-\tuint16_t\tmax_rx_rings;\n-\t/* Minimum guaranteed number of L2 contexts */\n-\tuint16_t\tmin_l2_ctxs;\n-\t/* Maximum non-guaranteed number of L2 contexts */\n-\tuint16_t\tmax_l2_ctxs;\n-\t/* Minimum guaranteed number of VNICs */\n-\tuint16_t\tmin_vnics;\n-\t/* Maximum non-guaranteed number of VNICs */\n-\tuint16_t\tmax_vnics;\n-\t/* Minimum guaranteed number of statistic contexts */\n-\tuint16_t\tmin_stat_ctx;\n-\t/* Maximum non-guaranteed number of statistic contexts */\n-\tuint16_t\tmax_stat_ctx;\n-\t/* Minimum guaranteed number of ring groups */\n-\tuint16_t\tmin_hw_ring_grps;\n-\t/* Maximum non-guaranteed number of ring groups */\n-\tuint16_t\tmax_hw_ring_grps;\n-\tuint8_t\tunused_0[4];\n-} __attribute__((packed));\n-\n-/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */\n-struct hwrm_func_vf_resource_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* Reserved number of RSS/COS contexts */\n-\tuint16_t\treserved_rsscos_ctx;\n-\t/* Reserved number of completion rings */\n-\tuint16_t\treserved_cmpl_rings;\n-\t/* Reserved number of transmit rings */\n-\tuint16_t\treserved_tx_rings;\n-\t/* Reserved number of receive rings */\n-\tuint16_t\treserved_rx_rings;\n-\t/* Reserved number of L2 contexts */\n-\tuint16_t\treserved_l2_ctxs;\n-\t/* Reserved number of VNICs */\n-\tuint16_t\treserved_vnics;\n-\t/* Reserved number of statistic contexts */\n-\tuint16_t\treserved_stat_ctx;\n-\t/* Reserved number of ring groups */\n-\tuint16_t\treserved_hw_ring_grps;\n-\tuint8_t\tunused_0[7];\n+\t#define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -7769,7 +7859,7 @@ struct hwrm_func_backing_store_qcaps_input {\n \tuint64_t\tresp_addr;\n } __attribute__((packed));\n \n-/* hwrm_func_backing_store_qcaps_output (size:512b/64B) */\n+/* hwrm_func_backing_store_qcaps_output (size:576b/72B) */\n struct hwrm_func_backing_store_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -7813,19 +7903,51 @@ struct hwrm_func_backing_store_qcaps_output {\n \tuint32_t\tstat_max_entries;\n \t/* Number of bytes that must be allocated for each context entry. */\n \tuint16_t\tstat_entry_size;\n-\t/* Maximum number of TQM context entries supported per ring. */\n-\tuint16_t\ttqm_max_entries_per_ring;\n \t/* Number of bytes that must be allocated for each context entry. */\n \tuint16_t\ttqm_entry_size;\n-\t/* Number of bytes that must be allocated for each context entry. */\n-\tuint16_t\tmrav_entry_size;\n+\t/* Minimum number of TQM context entries required per ring. */\n+\tuint32_t\ttqm_min_entries_per_ring;\n+\t/*\n+\t * Maximum number of TQM context entries supported per ring. This is\n+\t * actually a recommended TQM queue size based on worst case usage of\n+\t * the TQM queue.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * TQM slowpath rings should be sized as follows:\n+\t *\n+\t * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size\n+\t *\n+\t * Where:\n+\t * num_vnics is the number of VNICs allocated in the VNIC backing store\n+\t * num_l2_tx_rings is the number of L2 rings in the QP backing store\n+\t * num_roce_qps is the number of RoCE QPs in the QP backing store\n+\t * tqm_min_size is tqm_min_entries_per_ring reported by\n+\t * HWRM_FUNC_BACKING_STORE_QCAPS\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n+\tuint32_t\ttqm_max_entries_per_ring;\n \t/* Maximum number of MR/AV context entries supported for this function. */\n \tuint32_t\tmrav_max_entries;\n-\t/* Maximum number of Timer context entries supported for this function. */\n-\tuint32_t\ttim_max_entries;\n+\t/* Number of bytes that must be allocated for each context entry. */\n+\tuint16_t\tmrav_entry_size;\n \t/* Number of bytes that must be allocated for each context entry. */\n \tuint16_t\ttim_entry_size;\n-\tuint8_t\tunused_0;\n+\t/* Maximum number of Timer context entries supported for this function. */\n+\tuint32_t\ttim_max_entries;\n+\tuint8_t\tunused_0[2];\n+\t/*\n+\t * The number of entries specified for any TQM ring must be a\n+\t * multiple of this value to prevent any resource allocation\n+\t * limitations.\n+\t */\n+\tuint8_t\ttqm_entries_multiple;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -8672,23 +8794,129 @@ struct hwrm_func_backing_store_cfg_input {\n \tuint32_t\tcq_num_entries;\n \t/* Number of Stats. */\n \tuint32_t\tstat_num_entries;\n-\t/* Number of TQM slowpath entries. */\n+\t/*\n+\t * Number of TQM slowpath entries.\n+\t *\n+\t * TQM slowpath rings should be sized as follows:\n+\t *\n+\t * num_entries = num_vnics + num_l2_tx_rings + num_roce_qps + tqm_min_size\n+\t *\n+\t * Where:\n+\t * num_vnics is the number of VNICs allocated in the VNIC backing store\n+\t * num_l2_tx_rings is the number of L2 rings in the QP backing store\n+\t * num_roce_qps is the number of RoCE QPs in the QP backing store\n+\t * tqm_min_size is tqm_min_entries_per_ring reported by\n+\t * HWRM_FUNC_BACKING_STORE_QCAPS\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n \tuint32_t\ttqm_sp_num_entries;\n-\t/* Number of TQM ring 0 entries. */\n+\t/*\n+\t * Number of TQM ring 0 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n \tuint32_t\ttqm_ring0_num_entries;\n-\t/* Number of TQM ring 1 entries. */\n+\t/*\n+\t * Number of TQM ring 1 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n \tuint32_t\ttqm_ring1_num_entries;\n-\t/* Number of TQM ring 2 entries. */\n+\t/*\n+\t * Number of TQM ring 2 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n \tuint32_t\ttqm_ring2_num_entries;\n-\t/* Number of TQM ring 3 entries. */\n+\t/*\n+\t * Number of TQM ring 3 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n \tuint32_t\ttqm_ring3_num_entries;\n-\t/* Number of TQM ring 4 entries. */\n+\t/*\n+\t * Number of TQM ring 4 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n \tuint32_t\ttqm_ring4_num_entries;\n-\t/* Number of TQM ring 5 entries. */\n+\t/*\n+\t * Number of TQM ring 5 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n \tuint32_t\ttqm_ring5_num_entries;\n-\t/* Number of TQM ring 6 entries. */\n+\t/*\n+\t * Number of TQM ring 6 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n \tuint32_t\ttqm_ring6_num_entries;\n-\t/* Number of TQM ring 7 entries. */\n+\t/*\n+\t * Number of TQM ring 7 entries.\n+\t *\n+\t * TQM fastpath rings should be sized large enough to accommodate the\n+\t * maximum number of QPs (either L2 or RoCE, or both if shared)\n+\t * that can be enqueued to the TQM ring.\n+\t *\n+\t * Note that TQM ring sizes cannot be extended while the system is\n+\t * operational. If a PF driver needs to extend a TQM ring, it needs\n+\t * to reset the function (e.g. HWRM_FUNC_RESET) and then reallocate\n+\t * the backing store.\n+\t */\n \tuint32_t\ttqm_ring7_num_entries;\n \t/* Number of MR/AV entries. */\n \tuint32_t\tmrav_num_entries;\n@@ -9638,13 +9866,13 @@ struct hwrm_func_backing_store_qcfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*********************\n- * hwrm_port_phy_cfg *\n- *********************/\n+/***********************\n+ * hwrm_func_vlan_qcfg *\n+ ***********************/\n \n \n-/* hwrm_port_phy_cfg_input (size:448b/56B) */\n-struct hwrm_port_phy_cfg_input {\n+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n+struct hwrm_func_vlan_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -9672,508 +9900,430 @@ struct hwrm_port_phy_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n \t/*\n-\t * When this bit is set to '1', the PHY for the port shall\n-\t * be reset.\n-\t *\n-\t * # If this bit is set to 1, then the HWRM shall reset the\n-\t * PHY after applying PHY configuration changes specified\n-\t * in this command.\n-\t * # In order to guarantee that PHY configuration changes\n-\t * specified in this command take effect, the HWRM\n-\t * client should set this flag to 1.\n-\t * # If this bit is not set to 1, then the HWRM may reset\n-\t * the PHY depending on the current PHY configuration and\n-\t * settings specified in this command.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \\\n-\t\tUINT32_C(0x1)\n-\t/* deprecated bit. Do not use!!! */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * When this bit is set to '1', the link shall be forced to\n-\t * the force_link_speed value.\n-\t *\n-\t * When this bit is set to '1', the HWRM client should\n-\t * not enable any of the auto negotiation related\n-\t * fields represented by auto_XXX fields in this command.\n-\t * When this bit is set to '1' and the HWRM client has\n-\t * enabled a auto_XXX field in this command, then the\n-\t * HWRM shall ignore the enabled auto_XXX field.\n-\t *\n-\t * When this bit is set to zero, the link\n-\t * shall be allowed to autoneg.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * When this bit is set to '1', the auto-negotiation process\n-\t * shall be restarted on the link.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * When this bit is set to '1', Energy Efficient Ethernet\n-\t * (EEE) is requested to be enabled on this link.\n-\t * If EEE is not supported on this port, then this flag\n-\t * shall be ignored by the HWRM.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * When this bit is set to '1', Energy Efficient Ethernet\n-\t * (EEE) is requested to be disabled on this link.\n-\t * If EEE is not supported on this port, then this flag\n-\t * shall be ignored by the HWRM.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * When this bit is set to '1' and EEE is enabled on this\n-\t * link, then TX LPI is requested to be enabled on the link.\n-\t * If EEE is not supported on this port, then this flag\n-\t * shall be ignored by the HWRM.\n-\t * If EEE is disabled on this port, then this flag shall be\n-\t * ignored by the HWRM.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * When this bit is set to '1' and EEE is enabled on this\n-\t * link, then TX LPI is requested to be disabled on the link.\n-\t * If EEE is not supported on this port, then this flag\n-\t * shall be ignored by the HWRM.\n-\t * If EEE is disabled on this port, then this flag shall be\n-\t * ignored by the HWRM.\n+\t * Function ID of the function that is being\n+\t * configured.\n+\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * for the requesting function.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \\\n-\t\tUINT32_C(0x80)\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n+struct hwrm_func_vlan_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint64_t\tunused_0;\n+\t/* S-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tstag_vid;\n+\t/* S-TAG PCP value configured for the function. */\n+\tuint8_t\tstag_pcp;\n+\tuint8_t\tunused_1;\n \t/*\n-\t * When set to 1, then the HWRM shall enable FEC autonegotitation\n-\t * on this port if supported.\n-\t * When set to 0, then this flag shall be ignored.\n-\t * If FEC autonegotiation is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * S-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \\\n-\t\tUINT32_C(0x100)\n+\tuint16_t\tstag_tpid;\n+\t/* C-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tctag_vid;\n+\t/* C-TAG PCP value configured for the function. */\n+\tuint8_t\tctag_pcp;\n+\tuint8_t\tunused_2;\n \t/*\n-\t * When set to 1, then the HWRM shall disable FEC autonegotiation\n-\t * on this port if supported.\n-\t * When set to 0, then this flag shall be ignored.\n-\t * If FEC autonegotiation is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * C-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \\\n-\t\tUINT32_C(0x200)\n+\tuint16_t\tctag_tpid;\n+\t/* Future use. */\n+\tuint32_t\trsvd2;\n+\t/* Future use. */\n+\tuint32_t\trsvd3;\n+\tuint8_t\tunused_3[3];\n \t/*\n-\t * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)\n-\t * on this port if supported.\n-\t * When set to 0, then this flag shall be ignored.\n-\t * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \\\n-\t\tUINT32_C(0x400)\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**********************\n+ * hwrm_func_vlan_cfg *\n+ **********************/\n+\n+\n+/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n+struct hwrm_func_vlan_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)\n-\t * on this port if supported.\n-\t * When set to 0, then this flag shall be ignored.\n-\t * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \\\n-\t\tUINT32_C(0x800)\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)\n-\t * on this port if supported.\n-\t * When set to 0, then this flag shall be ignored.\n-\t * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \\\n-\t\tUINT32_C(0x1000)\n+\tuint16_t\tseq_id;\n \t/*\n-\t * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)\n-\t * on this port if supported.\n-\t * When set to 0, then this flag shall be ignored.\n-\t * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this\n-\t * flag.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \\\n-\t\tUINT32_C(0x2000)\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * When this bit is set to '1', the link shall be forced to\n-\t * be taken down.\n-\t *\n-\t * # When this bit is set to '1\", all other\n-\t * command input settings related to the link speed shall\n-\t * be ignored.\n-\t * Once the link state is forced down, it can be\n-\t * explicitly cleared from that state by setting this flag\n-\t * to '0'.\n-\t * # If this flag is set to '0', then the link shall be\n-\t * cleared from forced down state if the link is in forced\n-\t * down state.\n-\t * There may be conditions (e.g. out-of-band or sideband\n-\t * configuration changes for the link) outside the scope\n-\t * of the HWRM implementation that may clear forced down\n-\t * link state.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \\\n-\t\tUINT32_C(0x4000)\n-\tuint32_t\tenables;\n+\tuint64_t\tresp_addr;\n \t/*\n-\t * This bit must be '1' for the auto_mode field to be\n+\t * Function ID of the function that is being\n \t * configured.\n+\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * for the requesting function.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \\\n-\t\tUINT32_C(0x1)\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[2];\n+\tuint32_t\tenables;\n \t/*\n-\t * This bit must be '1' for the auto_duplex field to be\n+\t * This bit must be '1' for the stag_vid field to be\n \t * configured.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID UINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the auto_pause field to be\n+\t * This bit must be '1' for the ctag_vid field to be\n \t * configured.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \\\n-\t\tUINT32_C(0x4)\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID UINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the auto_link_speed field to be\n+\t * This bit must be '1' for the stag_pcp field to be\n \t * configured.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \\\n-\t\tUINT32_C(0x8)\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP UINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the auto_link_speed_mask field to be\n+\t * This bit must be '1' for the ctag_pcp field to be\n \t * configured.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \\\n-\t\tUINT32_C(0x10)\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP UINT32_C(0x8)\n \t/*\n-\t * This bit must be '1' for the wirespeed field to be\n+\t * This bit must be '1' for the stag_tpid field to be\n \t * configured.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \\\n-\t\tUINT32_C(0x20)\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID UINT32_C(0x10)\n \t/*\n-\t * This bit must be '1' for the lpbk field to be\n+\t * This bit must be '1' for the ctag_tpid field to be\n \t * configured.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \\\n-\t\tUINT32_C(0x40)\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID UINT32_C(0x20)\n+\t/* S-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tstag_vid;\n+\t/* S-TAG PCP value configured for the function. */\n+\tuint8_t\tstag_pcp;\n+\tuint8_t\tunused_1;\n \t/*\n-\t * This bit must be '1' for the preemphasis field to be\n-\t * configured.\n+\t * S-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \\\n-\t\tUINT32_C(0x80)\n-\t/*\n-\t * This bit must be '1' for the force_pause field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \\\n-\t\tUINT32_C(0x100)\n+\tuint16_t\tstag_tpid;\n+\t/* C-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tctag_vid;\n+\t/* C-TAG PCP value configured for the function. */\n+\tuint8_t\tctag_pcp;\n+\tuint8_t\tunused_2;\n \t/*\n-\t * This bit must be '1' for the eee_link_speed_mask field to be\n-\t * configured.\n+\t * C-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \\\n-\t\tUINT32_C(0x200)\n+\tuint16_t\tctag_tpid;\n+\t/* Future use. */\n+\tuint32_t\trsvd1;\n+\t/* Future use. */\n+\tuint32_t\trsvd2;\n+\tuint8_t\tunused_3[4];\n+} __attribute__((packed));\n+\n+/* hwrm_func_vlan_cfg_output (size:128b/16B) */\n+struct hwrm_func_vlan_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * This bit must be '1' for the tx_lpi_timer field to be\n-\t * configured.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \\\n-\t\tUINT32_C(0x400)\n-\t/* Port ID of port that is to be configured. */\n-\tuint16_t\tport_id;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*******************************\n+ * hwrm_func_vf_vnic_ids_query *\n+ *******************************/\n+\n+\n+/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */\n+struct hwrm_func_vf_vnic_ids_query_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * This is the speed that will be used if the force\n-\t * bit is '1'. If unsupported speed is selected, an error\n-\t * will be generated.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint16_t\tforce_link_speed;\n-\t/* 100Mb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)\n-\t/* 1Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)\n-\t/* 20Mb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)\n-\t/* 10Mb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \\\n-\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * This value is used to identify what autoneg mode is\n-\t * used when the link speed is not being forced.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint8_t\tauto_mode;\n-\t/* Disable autoneg or autoneg disabled. No speeds are selected. */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)\n-\t/* Select all possible speeds for autoneg mode. */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)\n+\tuint16_t\tseq_id;\n \t/*\n-\t * Select only the auto_link_speed speed for autoneg mode. This mode has\n-\t * been DEPRECATED. An HWRM client should not use this mode.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * Select the auto_link_speed or any speed below that speed for autoneg.\n-\t * This mode has been DEPRECATED. An HWRM client should not use this mode.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)\n+\tuint64_t\tresp_addr;\n \t/*\n-\t * Select the speeds based on the corresponding link speed mask value\n-\t * that is provided.\n+\t * This value is used to identify a Virtual Function (VF).\n+\t * The scope of VF ID is local within a PF.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \\\n-\t\tHWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK\n+\tuint16_t\tvf_id;\n+\tuint8_t\tunused_0[2];\n+\t/* Max number of vnic ids in vnic id table */\n+\tuint32_t\tmax_vnic_id_cnt;\n+\t/* This is the address for VF VNIC ID table */\n+\tuint64_t\tvnic_id_tbl_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */\n+struct hwrm_func_vf_vnic_ids_query_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n \t/*\n-\t * This is the duplex setting that will be used if the autoneg_mode\n-\t * is \"one_speed\" or \"one_or_below\".\n+\t * Actual number of vnic ids\n+\t *\n+\t * Each VNIC ID is written as a 32-bit number.\n \t */\n-\tuint8_t\tauto_duplex;\n-\t/* Half Duplex will be requested. */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)\n-\t/* Full duplex will be requested. */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)\n-\t/* Both Half and Full dupex will be requested. */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \\\n-\t\tHWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH\n+\tuint32_t\tvnic_id_cnt;\n+\tuint8_t\tunused_0[3];\n \t/*\n-\t * This value is used to configure the pause that will be\n-\t * used for autonegotiation.\n-\t * Add text on the usage of auto_pause and force_pause.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\tauto_pause;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***********************\n+ * hwrm_func_vf_bw_cfg *\n+ ***********************/\n+\n+\n+/* hwrm_func_vf_bw_cfg_input (size:960b/120B) */\n+struct hwrm_func_vf_bw_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * When this bit is '1', Generation of tx pause messages\n-\t * has been requested. Disabled otherwise.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \\\n-\t\tUINT32_C(0x1)\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * When this bit is '1', Reception of rx pause messages\n-\t * has been requested. Disabled otherwise.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \\\n-\t\tUINT32_C(0x2)\n+\tuint16_t\tseq_id;\n \t/*\n-\t * When set to 1, the advertisement of pause is enabled.\n-\t *\n-\t * # When the auto_mode is not set to none and this flag is\n-\t * set to 1, then the auto_pause bits on this port are being\n-\t * advertised and autoneg pause results are being interpreted.\n-\t * # When the auto_mode is not set to none and this\n-\t * flag is set to 0, the pause is forced as indicated in\n-\t * force_pause, and also advertised as auto_pause bits, but\n-\t * the autoneg results are not interpreted since the pause\n-\t * configuration is being forced.\n-\t * # When the auto_mode is set to none and this flag is set to\n-\t * 1, auto_pause bits should be ignored and should be set to 0.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \\\n-\t\tUINT32_C(0x4)\n-\tuint8_t\tunused_0;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * This is the speed that will be used if the autoneg_mode\n-\t * is \"one_speed\" or \"one_or_below\". If an unsupported speed\n-\t * is selected, an error will be generated.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint16_t\tauto_link_speed;\n-\t/* 100Mb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)\n-\t/* 1Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)\n-\t/* 20Mb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)\n-\t/* 10Mb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \\\n-\t\tHWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB\n+\tuint64_t\tresp_addr;\n \t/*\n-\t * This is a mask of link speeds that will be used if\n-\t * autoneg_mode is \"mask\". If unsupported speed is enabled\n-\t * an error will be generated.\n+\t * The number of VF functions that are being configured.\n+\t * The cmd space allows up to 50 VFs' BW to be configured with one cmd.\n \t */\n-\tuint16_t\tauto_link_speed_mask;\n-\t/* 100Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \\\n-\t\tUINT32_C(0x1)\n-\t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \\\n-\t\tUINT32_C(0x2)\n-\t/* 1Gb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \\\n-\t\tUINT32_C(0x4)\n-\t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \\\n-\t\tUINT32_C(0x8)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \\\n-\t\tUINT32_C(0x10)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \\\n-\t\tUINT32_C(0x20)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \\\n-\t\tUINT32_C(0x40)\n-\t/* 20Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \\\n-\t\tUINT32_C(0x80)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \\\n-\t\tUINT32_C(0x100)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \\\n-\t\tUINT32_C(0x200)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \\\n-\t\tUINT32_C(0x400)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \\\n-\t\tUINT32_C(0x800)\n-\t/* 10Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \\\n-\t\tUINT32_C(0x1000)\n-\t/* 10Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \\\n-\t\tUINT32_C(0x2000)\n-\t/* This value controls the wirespeed feature. */\n-\tuint8_t\twirespeed;\n-\t/* Wirespeed feature is disabled. */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)\n-\t/* Wirespeed feature is enabled. */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)\n-\t#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \\\n-\t\tHWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON\n-\t/* This value controls the loopback setting for the PHY. */\n-\tuint8_t\tlpbk;\n-\t/* No loopback is selected. Normal operation. */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)\n-\t/*\n-\t * The HW will be configured with local loopback such that\n-\t * host data is sent back to the host without modification.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)\n-\t/*\n-\t * The HW will be configured with remote loopback such that\n-\t * port logic will send packets back out the transmitter that\n-\t * are received.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)\n-\t/*\n-\t * The HW will be configured with external loopback such that\n-\t * host data is sent on the trasmitter and based on the external\n-\t * loopback connection the data will be received without modification.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)\n-\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \\\n-\t\tHWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL\n+\tuint16_t\tnum_vfs;\n+\tuint16_t\tunused[3];\n+\t/* These 16-bit fields contain the VF fid and the rate scale percentage. */\n+\tuint16_t\tvfn[48];\n+\t/* The physical VF id the adjustment will be made to. */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_VFID_SFT 0\n+\t/*\n+\t * This field configures the rate scale percentage of the VF as specified\n+\t * by the physical VF id.\n+\t */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_MASK UINT32_C(0xf000)\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_SFT 12\n+\t/* 0% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_0 \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/* 6.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_6_66 \\\n+\t\t(UINT32_C(0x1) << 12)\n+\t/* 13.33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_13_33 \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t/* 20% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_20 \\\n+\t\t(UINT32_C(0x3) << 12)\n+\t/* 26.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_26_66 \\\n+\t\t(UINT32_C(0x4) << 12)\n+\t/* 33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_33_33 \\\n+\t\t(UINT32_C(0x5) << 12)\n+\t/* 40% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_40 \\\n+\t\t(UINT32_C(0x6) << 12)\n+\t/* 46.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_46_66 \\\n+\t\t(UINT32_C(0x7) << 12)\n+\t/* 53.33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_53_33 \\\n+\t\t(UINT32_C(0x8) << 12)\n+\t/* 60% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_60 \\\n+\t\t(UINT32_C(0x9) << 12)\n+\t/* 66.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_66_66 \\\n+\t\t(UINT32_C(0xa) << 12)\n+\t/* 53.33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_73_33 \\\n+\t\t(UINT32_C(0xb) << 12)\n+\t/* 80% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_80 \\\n+\t\t(UINT32_C(0xc) << 12)\n+\t/* 86.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_86_66 \\\n+\t\t(UINT32_C(0xd) << 12)\n+\t/* 93.33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_93_33 \\\n+\t\t(UINT32_C(0xe) << 12)\n+\t/* 100% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100 \\\n+\t\t(UINT32_C(0xf) << 12)\n+\t#define HWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_LAST \\\n+\t\tHWRM_FUNC_VF_BW_CFG_INPUT_VFN_RATE_PCT_100\n+} __attribute__((packed));\n+\n+/* hwrm_func_vf_bw_cfg_output (size:128b/16B) */\n+struct hwrm_func_vf_bw_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * This value is used to configure the pause that will be\n-\t * used for force mode.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\tforce_pause;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/************************\n+ * hwrm_func_vf_bw_qcfg *\n+ ************************/\n+\n+\n+/* hwrm_func_vf_bw_qcfg_input (size:960b/120B) */\n+struct hwrm_func_vf_bw_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * When this bit is '1', Generation of tx pause messages\n-\t * is supported. Disabled otherwise.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * When this bit is '1', Reception of rx pause messages\n-\t * is supported. Disabled otherwise.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)\n-\tuint8_t\tunused_1;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * This value controls the pre-emphasis to be used for the\n-\t * link. Driver should not set this value (use\n-\t * enable.preemphasis = 0) unless driver is sure of setting.\n-\t * Normally HWRM FW will determine proper pre-emphasis.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint32_t\tpreemphasis;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * Setting for link speed mask that is used to\n-\t * advertise speeds during autonegotiation when EEE is enabled.\n-\t * This field is valid only when EEE is enabled.\n-\t * The speeds specified in this field shall be a subset of\n-\t * speeds specified in auto_link_speed_mask.\n-\t * If EEE is enabled,then at least one speed shall be provided\n-\t * in this mask.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint16_t\teee_link_speed_mask;\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \\\n-\t\tUINT32_C(0x1)\n-\t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \\\n-\t\tUINT32_C(0x2)\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \\\n-\t\tUINT32_C(0x4)\n-\t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \\\n-\t\tUINT32_C(0x8)\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \\\n-\t\tUINT32_C(0x10)\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \\\n-\t\tUINT32_C(0x20)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \\\n-\t\tUINT32_C(0x40)\n-\tuint8_t\tunused_2[2];\n+\tuint64_t\tresp_addr;\n \t/*\n-\t * Reuested setting of TX LPI timer in microseconds.\n-\t * This field is valid only when EEE is enabled and TX LPI is\n-\t * enabled.\n+\t * The number of VF functions that are being queried.\n+\t * The inline response space allows the host to query up to 50 VFs'\n+\t * rate scale percentage\n \t */\n-\tuint32_t\ttx_lpi_timer;\n-\t#define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)\n-\t#define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0\n-\tuint32_t\tunused_3;\n+\tuint16_t\tnum_vfs;\n+\tuint16_t\tunused[3];\n+\t/* These 16-bit fields contain the VF fid */\n+\tuint16_t\tvfn[48];\n+\t/* The physical VF id of interest */\n+\t#define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_MASK UINT32_C(0xfff)\n+\t#define HWRM_FUNC_VF_BW_QCFG_INPUT_VFN_VFID_SFT 0\n } __attribute__((packed));\n \n-/* hwrm_port_phy_cfg_output (size:128b/16B) */\n-struct hwrm_port_phy_cfg_output {\n+/* hwrm_func_vf_bw_qcfg_output (size:960b/120B) */\n+struct hwrm_func_vf_bw_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -10182,6 +10332,74 @@ struct hwrm_port_phy_cfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/*\n+\t * The number of VF functions that are being queried.\n+\t * The inline response space allows the host to query up to 50 VFs' rate\n+\t * scale percentage\n+\t */\n+\tuint16_t\tnum_vfs;\n+\tuint16_t\tunused[3];\n+\t/* These 16-bit fields contain the VF fid and the rate scale percentage. */\n+\tuint16_t\tvfn[48];\n+\t/* The physical VF id the adjustment will be made to. */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_MASK UINT32_C(0xfff)\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_VFID_SFT 0\n+\t/*\n+\t * This field configures the rate scale percentage of the VF as specified\n+\t * by the physical VF id.\n+\t */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_MASK UINT32_C(0xf000)\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_SFT 12\n+\t/* 0% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_0 \\\n+\t\t(UINT32_C(0x0) << 12)\n+\t/* 6.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_6_66 \\\n+\t\t(UINT32_C(0x1) << 12)\n+\t/* 13.33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_13_33 \\\n+\t\t(UINT32_C(0x2) << 12)\n+\t/* 20% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_20 \\\n+\t\t(UINT32_C(0x3) << 12)\n+\t/* 26.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_26_66 \\\n+\t\t(UINT32_C(0x4) << 12)\n+\t/* 33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_33_33 \\\n+\t\t(UINT32_C(0x5) << 12)\n+\t/* 40% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_40 \\\n+\t\t(UINT32_C(0x6) << 12)\n+\t/* 46.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_46_66 \\\n+\t\t(UINT32_C(0x7) << 12)\n+\t/* 53.33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_53_33 \\\n+\t\t(UINT32_C(0x8) << 12)\n+\t/* 60% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_60 \\\n+\t\t(UINT32_C(0x9) << 12)\n+\t/* 66.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_66_66 \\\n+\t\t(UINT32_C(0xa) << 12)\n+\t/* 53.33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_73_33 \\\n+\t\t(UINT32_C(0xb) << 12)\n+\t/* 80% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_80 \\\n+\t\t(UINT32_C(0xc) << 12)\n+\t/* 86.66% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_86_66 \\\n+\t\t(UINT32_C(0xd) << 12)\n+\t/* 93.33% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_93_33 \\\n+\t\t(UINT32_C(0xe) << 12)\n+\t/* 100% of the max tx rate */\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100 \\\n+\t\t(UINT32_C(0xf) << 12)\n+\t#define HWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_LAST \\\n+\t\tHWRM_FUNC_VF_BW_QCFG_OUTPUT_VFN_RATE_PCT_100\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -10193,42 +10411,13 @@ struct hwrm_port_phy_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */\n-struct hwrm_port_phy_cfg_cmd_err {\n-\t/*\n-\t * command specific error codes that goes to\n-\t * the cmd_err field in Common HWRM Error Response.\n-\t */\n-\tuint8_t\tcode;\n-\t/* Unknown error */\n-\t#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n-\t/* Unable to complete operation due to invalid speed */\n-\t#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)\n-\t/*\n-\t * retry the command since the phy is not ready.\n-\t * retry count is returned in opaque_0.\n-\t * This is only valid for the first command and\n-\t * this value will not change for successive calls.\n-\t * but if a 0 is returned at any time then this should\n-\t * be treated as an un recoverable failure,\n-\t *\n-\t * retry interval in milli seconds is returned in opaque_1.\n-\t * This specifies the time that user should wait before\n-\t * issuing the next port_phy_cfg command.\n-\t */\n-\t#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)\n-\t#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY\n-\tuint8_t\tunused_0[7];\n-} __attribute__((packed));\n-\n-/**********************\n- * hwrm_port_phy_qcfg *\n- **********************/\n+/***************************\n+ * hwrm_func_drv_if_change *\n+ ***************************/\n \n \n-/* hwrm_port_phy_qcfg_input (size:192b/24B) */\n-struct hwrm_port_phy_qcfg_input {\n+/* hwrm_func_drv_if_change_input (size:192b/24B) */\n+struct hwrm_func_drv_if_change_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -10256,13 +10445,26 @@ struct hwrm_port_phy_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Port ID of port that is to be queried. */\n-\tuint16_t\tport_id;\n-\tuint8_t\tunused_0[6];\n+\tuint32_t\tflags;\n+\t/*\n+\t * When this bit is '1', the function driver is indicating\n+\t * that the IF state is changing to UP state. The call should\n+\t * be made at the beginning of the driver's open call before\n+\t * resources are allocated. After making the call, the driver\n+\t * should check the response to see if any resources may have\n+\t * changed (see the response below). If the driver fails\n+\t * the open call, the driver should make this call again with\n+\t * this bit cleared to indicate that the IF state is not UP.\n+\t * During the driver's close call when the IF state is changing\n+\t * to DOWN, the driver should make this call with the bit cleared\n+\t * after all resources have been freed.\n+\t */\n+\t#define HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP UINT32_C(0x1)\n+\tuint32_t\tunused;\n } __attribute__((packed));\n \n-/* hwrm_port_phy_qcfg_output (size:768b/96B) */\n-struct hwrm_port_phy_qcfg_output {\n+/* hwrm_func_drv_if_change_output (size:128b/16B) */\n+struct hwrm_func_drv_if_change_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -10271,826 +10473,617 @@ struct hwrm_port_phy_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This value indicates the current link status. */\n-\tuint8_t\tlink;\n-\t/* There is no link or cable detected. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)\n-\t/* There is no link, but a cable has been detected. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)\n-\t/* There is a link. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK\n-\tuint8_t\tunused_0;\n-\t/* This value indicates the current link speed of the connection. */\n-\tuint16_t\tlink_speed;\n-\t/* 100Mb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)\n-\t/* 1Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)\n-\t/* 20Mb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)\n-\t/* 10Mb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB\n+\tuint32_t\tflags;\n \t/*\n-\t * This value is indicates the duplex of the current\n-\t * configuration.\n+\t * When this bit is '1', it indicates that the resources reserved\n+\t * for this function may have changed. The driver should check\n+\t * resource capabilities and reserve resources again before\n+\t * allocating resources.\n \t */\n-\tuint8_t\tduplex_cfg;\n-\t/* Half Duplex connection. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)\n-\t/* Full duplex connection. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL\n+\t#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[3];\n \t/*\n-\t * This value is used to indicate the current\n-\t * pause configuration. When autoneg is enabled, this value\n-\t * represents the autoneg results of pause configuration.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\tpause;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*********************\n+ * hwrm_port_phy_cfg *\n+ *********************/\n+\n+\n+/* hwrm_port_phy_cfg_input (size:448b/56B) */\n+struct hwrm_port_phy_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * When this bit is '1', Generation of tx pause messages\n-\t * is supported. Disabled otherwise.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * When this bit is '1', Reception of rx pause messages\n-\t * is supported. Disabled otherwise.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)\n+\tuint16_t\tseq_id;\n \t/*\n-\t * The supported speeds for the port. This is a bit mask.\n-\t * For each speed that is supported, the corrresponding\n-\t * bit will be set to '1'.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint16_t\tsupport_speeds;\n-\t/* 100Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \\\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/*\n+\t * When this bit is set to '1', the PHY for the port shall\n+\t * be reset.\n+\t *\n+\t * # If this bit is set to 1, then the HWRM shall reset the\n+\t * PHY after applying PHY configuration changes specified\n+\t * in this command.\n+\t * # In order to guarantee that PHY configuration changes\n+\t * specified in this command take effect, the HWRM\n+\t * client should set this flag to 1.\n+\t * # If this bit is not set to 1, then the HWRM may reset\n+\t * the PHY depending on the current PHY configuration and\n+\t * settings specified in this command.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY \\\n \t\tUINT32_C(0x1)\n-\t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \\\n+\t/* deprecated bit. Do not use!!! */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_DEPRECATED \\\n \t\tUINT32_C(0x2)\n-\t/* 1Gb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \\\n+\t/*\n+\t * When this bit is set to '1', the link shall be forced to\n+\t * the force_link_speed value.\n+\t *\n+\t * When this bit is set to '1', the HWRM client should\n+\t * not enable any of the auto negotiation related\n+\t * fields represented by auto_XXX fields in this command.\n+\t * When this bit is set to '1' and the HWRM client has\n+\t * enabled a auto_XXX field in this command, then the\n+\t * HWRM shall ignore the enabled auto_XXX field.\n+\t *\n+\t * When this bit is set to zero, the link\n+\t * shall be allowed to autoneg.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE \\\n \t\tUINT32_C(0x4)\n-\t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \\\n-\t\tUINT32_C(0x8)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \\\n-\t\tUINT32_C(0x10)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \\\n-\t\tUINT32_C(0x20)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \\\n-\t\tUINT32_C(0x40)\n-\t/* 20Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \\\n-\t\tUINT32_C(0x80)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \\\n-\t\tUINT32_C(0x100)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \\\n-\t\tUINT32_C(0x200)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \\\n-\t\tUINT32_C(0x400)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \\\n-\t\tUINT32_C(0x800)\n-\t/* 10Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \\\n-\t\tUINT32_C(0x1000)\n-\t/* 10Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \\\n-\t\tUINT32_C(0x2000)\n \t/*\n-\t * Current setting of forced link speed.\n-\t * When the link speed is not being forced, this\n-\t * value shall be set to 0.\n+\t * When this bit is set to '1', the auto-negotiation process\n+\t * shall be restarted on the link.\n \t */\n-\tuint16_t\tforce_link_speed;\n-\t/* 100Mb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)\n-\t/* 1Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)\n-\t/* 20Mb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \\\n-\t\tUINT32_C(0x190)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \\\n-\t\tUINT32_C(0x1f4)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \\\n-\t\tUINT32_C(0x3e8)\n-\t/* 10Mb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB\n-\t/* Current setting of auto negotiation mode. */\n-\tuint8_t\tauto_mode;\n-\t/* Disable autoneg or autoneg disabled. No speeds are selected. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)\n-\t/* Select all possible speeds for autoneg mode. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * Select only the auto_link_speed speed for autoneg mode. This mode has\n-\t * been DEPRECATED. An HWRM client should not use this mode.\n+\t * When this bit is set to '1', Energy Efficient Ethernet\n+\t * (EEE) is requested to be enabled on this link.\n+\t * If EEE is not supported on this port, then this flag\n+\t * shall be ignored by the HWRM.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * Select the auto_link_speed or any speed below that speed for autoneg.\n-\t * This mode has been DEPRECATED. An HWRM client should not use this mode.\n+\t * When this bit is set to '1', Energy Efficient Ethernet\n+\t * (EEE) is requested to be disabled on this link.\n+\t * If EEE is not supported on this port, then this flag\n+\t * shall be ignored by the HWRM.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * Select the speeds based on the corresponding link speed mask value\n-\t * that is provided.\n+\t * When this bit is set to '1' and EEE is enabled on this\n+\t * link, then TX LPI is requested to be enabled on the link.\n+\t * If EEE is not supported on this port, then this flag\n+\t * shall be ignored by the HWRM.\n+\t * If EEE is disabled on this port, then this flag shall be\n+\t * ignored by the HWRM.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_ENABLE \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * Current setting of pause autonegotiation.\n-\t * Move autoneg_pause flag here.\n+\t * When this bit is set to '1' and EEE is enabled on this\n+\t * link, then TX LPI is requested to be disabled on the link.\n+\t * If EEE is not supported on this port, then this flag\n+\t * shall be ignored by the HWRM.\n+\t * If EEE is disabled on this port, then this flag shall be\n+\t * ignored by the HWRM.\n \t */\n-\tuint8_t\tauto_pause;\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI_DISABLE \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * When this bit is '1', Generation of tx pause messages\n-\t * has been requested. Disabled otherwise.\n+\t * When set to 1, then the HWRM shall enable FEC autonegotitation\n+\t * on this port if supported.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC autonegotiation is not supported, then the HWRM shall ignore this\n+\t * flag.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_ENABLE \\\n+\t\tUINT32_C(0x100)\n \t/*\n-\t * When this bit is '1', Reception of rx pause messages\n-\t * has been requested. Disabled otherwise.\n+\t * When set to 1, then the HWRM shall disable FEC autonegotiation\n+\t * on this port if supported.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC autonegotiation is not supported, then the HWRM shall ignore this\n+\t * flag.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_AUTONEG_DISABLE \\\n+\t\tUINT32_C(0x200)\n \t/*\n-\t * When set to 1, the advertisement of pause is enabled.\n-\t *\n-\t * # When the auto_mode is not set to none and this flag is\n-\t * set to 1, then the auto_pause bits on this port are being\n-\t * advertised and autoneg pause results are being interpreted.\n-\t * # When the auto_mode is not set to none and this\n-\t * flag is set to 0, the pause is forced as indicated in\n-\t * force_pause, and also advertised as auto_pause bits, but\n-\t * the autoneg results are not interpreted since the pause\n-\t * configuration is being forced.\n-\t * # When the auto_mode is set to none and this flag is set to\n-\t * 1, auto_pause bits should be ignored and should be set to 0.\n+\t * When set to 1, then the HWRM shall enable FEC CLAUSE 74 (Fire Code)\n+\t * on this port if supported.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this\n+\t * flag.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \\\n-\t\tUINT32_C(0x4)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_ENABLE \\\n+\t\tUINT32_C(0x400)\n \t/*\n-\t * Current setting for auto_link_speed. This field is only\n-\t * valid when auto_mode is set to \"one_speed\" or \"one_or_below\".\n+\t * When set to 1, then the HWRM shall disable FEC CLAUSE 74 (Fire Code)\n+\t * on this port if supported.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC CLAUSE 74 is not supported, then the HWRM shall ignore this\n+\t * flag.\n \t */\n-\tuint16_t\tauto_link_speed;\n-\t/* 100Mb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)\n-\t/* 1Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)\n-\t/* 20Mb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)\n-\t/* 10Mb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE74_DISABLE \\\n+\t\tUINT32_C(0x800)\n \t/*\n-\t * Current setting for auto_link_speed_mask that is used to\n-\t * advertise speeds during autonegotiation.\n-\t * This field is only valid when auto_mode is set to \"mask\".\n-\t * The speeds specified in this field shall be a subset of\n-\t * supported speeds on this port.\n+\t * When set to 1, then the HWRM shall enable FEC CLAUSE 91 (Reed Solomon)\n+\t * on this port if supported.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this\n+\t * flag.\n \t */\n-\tuint16_t\tauto_link_speed_mask;\n-\t/* 100Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_ENABLE \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * When set to 1, then the HWRM shall disable FEC CLAUSE 91 (Reed Solomon)\n+\t * on this port if supported.\n+\t * When set to 0, then this flag shall be ignored.\n+\t * If FEC CLAUSE 91 is not supported, then the HWRM shall ignore this\n+\t * flag.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FEC_CLAUSE91_DISABLE \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * When this bit is set to '1', the link shall be forced to\n+\t * be taken down.\n+\t *\n+\t * # When this bit is set to '1\", all other\n+\t * command input settings related to the link speed shall\n+\t * be ignored.\n+\t * Once the link state is forced down, it can be\n+\t * explicitly cleared from that state by setting this flag\n+\t * to '0'.\n+\t * # If this flag is set to '0', then the link shall be\n+\t * cleared from forced down state if the link is in forced\n+\t * down state.\n+\t * There may be conditions (e.g. out-of-band or sideband\n+\t * configuration changes for the link) outside the scope\n+\t * of the HWRM implementation that may clear forced down\n+\t * link state.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN \\\n+\t\tUINT32_C(0x4000)\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the auto_mode field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE \\\n \t\tUINT32_C(0x1)\n-\t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \\\n+\t/*\n+\t * This bit must be '1' for the auto_duplex field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX \\\n \t\tUINT32_C(0x2)\n-\t/* 1Gb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \\\n+\t/*\n+\t * This bit must be '1' for the auto_pause field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE \\\n \t\tUINT32_C(0x4)\n-\t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \\\n+\t/*\n+\t * This bit must be '1' for the auto_link_speed field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED \\\n \t\tUINT32_C(0x8)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \\\n+\t/*\n+\t * This bit must be '1' for the auto_link_speed_mask field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \\\n \t\tUINT32_C(0x10)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \\\n+\t/*\n+\t * This bit must be '1' for the wirespeed field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED \\\n \t\tUINT32_C(0x20)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \\\n+\t/*\n+\t * This bit must be '1' for the lpbk field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK \\\n \t\tUINT32_C(0x40)\n-\t/* 20Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \\\n+\t/*\n+\t * This bit must be '1' for the preemphasis field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS \\\n \t\tUINT32_C(0x80)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \\\n-\t\tUINT32_C(0x100)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \\\n-\t\tUINT32_C(0x200)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \\\n-\t\tUINT32_C(0x400)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \\\n-\t\tUINT32_C(0x800)\n-\t/* 10Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \\\n-\t\tUINT32_C(0x1000)\n-\t/* 10Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \\\n-\t\tUINT32_C(0x2000)\n-\t/* Current setting for wirespeed. */\n-\tuint8_t\twirespeed;\n-\t/* Wirespeed feature is disabled. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)\n-\t/* Wirespeed feature is enabled. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON\n-\t/* Current setting for loopback. */\n-\tuint8_t\tlpbk;\n-\t/* No loopback is selected. Normal operation. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)\n \t/*\n-\t * The HW will be configured with local loopback such that\n-\t * host data is sent back to the host without modification.\n+\t * This bit must be '1' for the force_pause field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE \\\n+\t\tUINT32_C(0x100)\n \t/*\n-\t * The HW will be configured with remote loopback such that\n-\t * port logic will send packets back out the transmitter that\n-\t * are received.\n+\t * This bit must be '1' for the eee_link_speed_mask field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \\\n+\t\tUINT32_C(0x200)\n \t/*\n-\t * The HW will be configured with external loopback such that\n-\t * host data is sent on the trasmitter and based on the external\n-\t * loopback connection the data will be received without modification.\n+\t * This bit must be '1' for the tx_lpi_timer field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL\n+\t#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER \\\n+\t\tUINT32_C(0x400)\n+\t/* Port ID of port that is to be configured. */\n+\tuint16_t\tport_id;\n \t/*\n-\t * Current setting of forced pause.\n-\t * When the pause configuration is not being forced, then\n-\t * this value shall be set to 0.\n+\t * This is the speed that will be used if the force\n+\t * bit is '1'. If unsupported speed is selected, an error\n+\t * will be generated.\n \t */\n-\tuint8_t\tforce_pause;\n+\tuint16_t\tforce_link_speed;\n+\t/* 100Mb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)\n+\t/* 20Mb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB UINT32_C(0x190)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)\n+\t/* 10Mb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \\\n+\t\tHWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB\n \t/*\n-\t * When this bit is '1', Generation of tx pause messages\n-\t * is supported. Disabled otherwise.\n+\t * This value is used to identify what autoneg mode is\n+\t * used when the link speed is not being forced.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)\n+\tuint8_t\tauto_mode;\n+\t/* Disable autoneg or autoneg disabled. No speeds are selected. */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE UINT32_C(0x0)\n+\t/* Select all possible speeds for autoneg mode. */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)\n \t/*\n-\t * When this bit is '1', Reception of rx pause messages\n-\t * is supported. Disabled otherwise.\n+\t * Select only the auto_link_speed speed for autoneg mode. This mode has\n+\t * been DEPRECATED. An HWRM client should not use this mode.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)\n \t/*\n-\t * This value indicates the current status of the optics module on\n-\t * this port.\n+\t * Select the auto_link_speed or any speed below that speed for autoneg.\n+\t * This mode has been DEPRECATED. An HWRM client should not use this mode.\n \t */\n-\tuint8_t\tmodule_status;\n-\t/* Module is inserted and accepted */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \\\n-\t\tUINT32_C(0x0)\n-\t/* Module is rejected and transmit side Laser is disabled. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \\\n-\t\tUINT32_C(0x1)\n-\t/* Module mismatch warning. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \\\n-\t\tUINT32_C(0x2)\n-\t/* Module is rejected and powered down. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \\\n-\t\tUINT32_C(0x3)\n-\t/* Module is not inserted. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \\\n-\t\tUINT32_C(0x4)\n-\t/* Module status is not applicable. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE\n-\t/* Current setting for preemphasis. */\n-\tuint32_t\tpreemphasis;\n-\t/* This field represents the major version of the PHY. */\n-\tuint8_t\tphy_maj;\n-\t/* This field represents the minor version of the PHY. */\n-\tuint8_t\tphy_min;\n-\t/* This field represents the build version of the PHY. */\n-\tuint8_t\tphy_bld;\n-\t/* This value represents a PHY type. */\n-\tuint8_t\tphy_type;\n-\t/* Unknown */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \\\n-\t\tUINT32_C(0x0)\n-\t/* BASE-CR */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \\\n-\t\tUINT32_C(0x1)\n-\t/* BASE-KR4 (Deprecated) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \\\n-\t\tUINT32_C(0x2)\n-\t/* BASE-LR */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \\\n-\t\tUINT32_C(0x3)\n-\t/* BASE-SR */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \\\n-\t\tUINT32_C(0x4)\n-\t/* BASE-KR2 (Deprecated) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \\\n-\t\tUINT32_C(0x5)\n-\t/* BASE-KX */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \\\n-\t\tUINT32_C(0x6)\n-\t/* BASE-KR */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \\\n-\t\tUINT32_C(0x7)\n-\t/* BASE-T */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \\\n-\t\tUINT32_C(0x8)\n-\t/* EEE capable BASE-T */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \\\n-\t\tUINT32_C(0x9)\n-\t/* SGMII connected external PHY */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \\\n-\t\tUINT32_C(0xa)\n-\t/* 25G_BASECR_CA_L */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \\\n-\t\tUINT32_C(0xb)\n-\t/* 25G_BASECR_CA_S */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \\\n-\t\tUINT32_C(0xc)\n-\t/* 25G_BASECR_CA_N */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \\\n-\t\tUINT32_C(0xd)\n-\t/* 25G_BASESR */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \\\n-\t\tUINT32_C(0xe)\n-\t/* 100G_BASECR4 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \\\n-\t\tUINT32_C(0xf)\n-\t/* 100G_BASESR4 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \\\n-\t\tUINT32_C(0x10)\n-\t/* 100G_BASELR4 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \\\n-\t\tUINT32_C(0x11)\n-\t/* 100G_BASEER4 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \\\n-\t\tUINT32_C(0x12)\n-\t/* 100G_BASESR10 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \\\n-\t\tUINT32_C(0x13)\n-\t/* 40G_BASECR4 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \\\n-\t\tUINT32_C(0x14)\n-\t/* 40G_BASESR4 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \\\n-\t\tUINT32_C(0x15)\n-\t/* 40G_BASELR4 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \\\n-\t\tUINT32_C(0x16)\n-\t/* 40G_BASEER4 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \\\n-\t\tUINT32_C(0x17)\n-\t/* 40G_ACTIVE_CABLE */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \\\n-\t\tUINT32_C(0x18)\n-\t/* 1G_baseT */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \\\n-\t\tUINT32_C(0x19)\n-\t/* 1G_baseSX */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \\\n-\t\tUINT32_C(0x1a)\n-\t/* 1G_baseCX */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \\\n-\t\tUINT32_C(0x1b)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX\n-\t/* This value represents a media type. */\n-\tuint8_t\tmedia_type;\n-\t/* Unknown */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)\n-\t/* Twisted Pair */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)\n-\t/* Direct Attached Copper */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)\n-\t/* Fiber */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE\n-\t/* This value represents a transceiver type. */\n-\tuint8_t\txcvr_pkg_type;\n-\t/* PHY and MAC are in the same package */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \\\n-\t\tUINT32_C(0x1)\n-\t/* PHY and MAC are in different packages */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \\\n-\t\tUINT32_C(0x2)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL\n-\tuint8_t\teee_config_phy_addr;\n-\t/* This field represents PHY address. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \\\n-\t\tUINT32_C(0x1f)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)\n \t/*\n-\t * This field represents flags related to EEE configuration.\n-\t * These EEE configuration flags are valid only when the\n-\t * auto_mode is not set to none (in other words autonegotiation\n-\t * is enabled).\n+\t * Select the speeds based on the corresponding link speed mask value\n+\t * that is provided.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \\\n-\t\tUINT32_C(0xe0)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_LAST \\\n+\t\tHWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK\n \t/*\n-\t * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.\n-\t * Speeds for autoneg with EEE mode enabled\n-\t * are based on eee_link_speed_mask.\n+\t * This is the duplex setting that will be used if the autoneg_mode\n+\t * is \"one_speed\" or \"one_or_below\".\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \\\n-\t\tUINT32_C(0x20)\n+\tuint8_t\tauto_duplex;\n+\t/* Half Duplex will be requested. */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF UINT32_C(0x0)\n+\t/* Full duplex will be requested. */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL UINT32_C(0x1)\n+\t/* Both Half and Full dupex will be requested. */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH UINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_LAST \\\n+\t\tHWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH\n \t/*\n-\t * This flag is valid only when eee_enabled is set to 1.\n-\t *\n-\t * # If eee_enabled is set to 0, then EEE mode is disabled\n-\t * and this flag shall be ignored.\n-\t * # If eee_enabled is set to 1 and this flag is set to 1,\n-\t * then Energy Efficient Ethernet (EEE) mode is enabled\n-\t * and in use.\n-\t * # If eee_enabled is set to 1 and this flag is set to 0,\n-\t * then Energy Efficient Ethernet (EEE) mode is enabled\n-\t * but is currently not in use.\n+\t * This value is used to configure the pause that will be\n+\t * used for autonegotiation.\n+\t * Add text on the usage of auto_pause and force_pause.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \\\n-\t\tUINT32_C(0x40)\n+\tuint8_t\tauto_pause;\n \t/*\n-\t * This flag is valid only when eee_enabled is set to 1.\n-\t *\n-\t * # If eee_enabled is set to 0, then EEE mode is disabled\n-\t * and this flag shall be ignored.\n-\t * # If eee_enabled is set to 1 and this flag is set to 1,\n-\t * then Energy Efficient Ethernet (EEE) mode is enabled\n-\t * and TX LPI is enabled.\n-\t * # If eee_enabled is set to 1 and this flag is set to 0,\n-\t * then Energy Efficient Ethernet (EEE) mode is enabled\n-\t * but TX LPI is disabled.\n+\t * When this bit is '1', Generation of tx pause messages\n+\t * has been requested. Disabled otherwise.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \\\n-\t\tUINT32_C(0x80)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * When set to 1, the parallel detection is used to determine\n-\t * the speed of the link partner.\n-\t *\n-\t * Parallel detection is used when a autonegotiation capable\n-\t * device is connected to a link parter that is not capable\n-\t * of autonegotiation.\n+\t * When this bit is '1', Reception of rx pause messages\n+\t * has been requested. Disabled otherwise.\n \t */\n-\tuint8_t\tparallel_detect;\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * When set to 1, the parallel detection is used to determine\n-\t * the speed of the link partner.\n+\t * When set to 1, the advertisement of pause is enabled.\n \t *\n-\t * Parallel detection is used when a autonegotiation capable\n-\t * device is connected to a link parter that is not capable\n-\t * of autonegotiation.\n+\t * # When the auto_mode is not set to none and this flag is\n+\t * set to 1, then the auto_pause bits on this port are being\n+\t * advertised and autoneg pause results are being interpreted.\n+\t * # When the auto_mode is not set to none and this\n+\t * flag is set to 0, the pause is forced as indicated in\n+\t * force_pause, and also advertised as auto_pause bits, but\n+\t * the autoneg results are not interpreted since the pause\n+\t * configuration is being forced.\n+\t * # When the auto_mode is set to none and this flag is set to\n+\t * 1, auto_pause bits should be ignored and should be set to 0.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE \\\n+\t\tUINT32_C(0x4)\n+\tuint8_t\tunused_0;\n \t/*\n-\t * The advertised speeds for the port by the link partner.\n-\t * Each advertised speed will be set to '1'.\n+\t * This is the speed that will be used if the autoneg_mode\n+\t * is \"one_speed\" or \"one_or_below\". If an unsupported speed\n+\t * is selected, an error will be generated.\n \t */\n-\tuint16_t\tlink_partner_adv_speeds;\n-\t/* 100Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \\\n-\t\tUINT32_C(0x1)\n-\t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \\\n-\t\tUINT32_C(0x2)\n-\t/* 1Gb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \\\n-\t\tUINT32_C(0x4)\n-\t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \\\n+\tuint16_t\tauto_link_speed;\n+\t/* 100Mb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)\n+\t/* 20Mb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)\n+\t/* 10Mb link speed */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \\\n+\t\tHWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB\n+\t/*\n+\t * This is a mask of link speeds that will be used if\n+\t * autoneg_mode is \"mask\". If unsupported speed is enabled\n+\t * an error will be generated.\n+\t */\n+\tuint16_t\tauto_link_speed_mask;\n+\t/* 100Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \\\n+\t\tUINT32_C(0x1)\n+\t/* 100Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \\\n+\t\tUINT32_C(0x2)\n+\t/* 1Gb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \\\n+\t\tUINT32_C(0x4)\n+\t/* 1Gb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \\\n \t\tUINT32_C(0x8)\n \t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \\\n \t\tUINT32_C(0x10)\n \t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \\\n \t\tUINT32_C(0x20)\n \t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \\\n \t\tUINT32_C(0x40)\n \t/* 20Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \\\n \t\tUINT32_C(0x80)\n \t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \\\n \t\tUINT32_C(0x100)\n \t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \\\n \t\tUINT32_C(0x200)\n \t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \\\n \t\tUINT32_C(0x400)\n \t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \\\n \t\tUINT32_C(0x800)\n \t/* 10Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \\\n \t\tUINT32_C(0x1000)\n \t/* 10Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \\\n \t\tUINT32_C(0x2000)\n+\t/* This value controls the wirespeed feature. */\n+\tuint8_t\twirespeed;\n+\t/* Wirespeed feature is disabled. */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF UINT32_C(0x0)\n+\t/* Wirespeed feature is enabled. */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_LAST \\\n+\t\tHWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON\n+\t/* This value controls the loopback setting for the PHY. */\n+\tuint8_t\tlpbk;\n+\t/* No loopback is selected. Normal operation. */\n+\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE UINT32_C(0x0)\n \t/*\n-\t * The advertised autoneg for the port by the link partner.\n-\t * This field is deprecated and should be set to 0.\n+\t * The HW will be configured with local loopback such that\n+\t * host data is sent back to the host without modification.\n \t */\n-\tuint8_t\tlink_partner_adv_auto_mode;\n-\t/* Disable autoneg or autoneg disabled. No speeds are selected. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \\\n-\t\tUINT32_C(0x0)\n-\t/* Select all possible speeds for autoneg mode. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)\n \t/*\n-\t * Select only the auto_link_speed speed for autoneg mode. This mode has\n-\t * been DEPRECATED. An HWRM client should not use this mode.\n+\t * The HW will be configured with remote loopback such that\n+\t * port logic will send packets back out the transmitter that\n+\t * are received.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)\n \t/*\n-\t * Select the auto_link_speed or any speed below that speed for autoneg.\n-\t * This mode has been DEPRECATED. An HWRM client should not use this mode.\n+\t * The HW will be configured with external loopback such that\n+\t * host data is sent on the trasmitter and based on the external\n+\t * loopback connection the data will be received without modification.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \\\n-\t\tUINT32_C(0x3)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL UINT32_C(0x3)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_LPBK_LAST \\\n+\t\tHWRM_PORT_PHY_CFG_INPUT_LPBK_EXTERNAL\n \t/*\n-\t * Select the speeds based on the corresponding link speed mask value\n-\t * that is provided.\n+\t * This value is used to configure the pause that will be\n+\t * used for force mode.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \\\n-\t\tUINT32_C(0x4)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK\n-\t/* The advertised pause settings on the port by the link partner. */\n-\tuint8_t\tlink_partner_adv_pause;\n+\tuint8_t\tforce_pause;\n \t/*\n \t * When this bit is '1', Generation of tx pause messages\n \t * is supported. Disabled otherwise.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)\n \t/*\n \t * When this bit is '1', Reception of rx pause messages\n \t * is supported. Disabled otherwise.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)\n+\tuint8_t\tunused_1;\n \t/*\n-\t * Current setting for link speed mask that is used to\n+\t * This value controls the pre-emphasis to be used for the\n+\t * link. Driver should not set this value (use\n+\t * enable.preemphasis = 0) unless driver is sure of setting.\n+\t * Normally HWRM FW will determine proper pre-emphasis.\n+\t */\n+\tuint32_t\tpreemphasis;\n+\t/*\n+\t * Setting for link speed mask that is used to\n \t * advertise speeds during autonegotiation when EEE is enabled.\n-\t * This field is valid only when eee_enabled flags is set to 1.\n+\t * This field is valid only when EEE is enabled.\n \t * The speeds specified in this field shall be a subset of\n \t * speeds specified in auto_link_speed_mask.\n+\t * If EEE is enabled,then at least one speed shall be provided\n+\t * in this mask.\n \t */\n-\tuint16_t\tadv_eee_link_speed_mask;\n+\tuint16_t\teee_link_speed_mask;\n \t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 \\\n \t\tUINT32_C(0x1)\n \t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB \\\n \t\tUINT32_C(0x2)\n \t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 \\\n \t\tUINT32_C(0x4)\n \t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB \\\n \t\tUINT32_C(0x8)\n \t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \\\n \t\tUINT32_C(0x10)\n \t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \\\n \t\tUINT32_C(0x20)\n \t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \\\n+\t#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \\\n \t\tUINT32_C(0x40)\n+\tuint8_t\tunused_2[2];\n \t/*\n-\t * Current setting for link speed mask that is advertised by\n-\t * the link partner when EEE is enabled.\n-\t * This field is valid only when eee_enabled flags is set to 1.\n+\t * Reuested setting of TX LPI timer in microseconds.\n+\t * This field is valid only when EEE is enabled and TX LPI is\n+\t * enabled.\n \t */\n-\tuint16_t\tlink_partner_adv_eee_link_speed_mask;\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \\\n-\t\tUINT32_C(0x1)\n-\t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \\\n-\t\tUINT32_C(0x2)\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \\\n-\t\tUINT32_C(0x4)\n-\t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \\\n-\t\tUINT32_C(0x8)\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \\\n-\t\tUINT32_C(0x10)\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \\\n-\t\tUINT32_C(0x20)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \\\n-\t\tUINT32_C(0x40)\n-\tuint32_t\txcvr_identifier_type_tx_lpi_timer;\n+\tuint32_t\ttx_lpi_timer;\n+\t#define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK UINT32_C(0xffffff)\n+\t#define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0\n+\tuint32_t\tunused_3;\n+} __attribute__((packed));\n+\n+/* hwrm_port_phy_cfg_output (size:128b/16B) */\n+struct hwrm_port_phy_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * Current setting of TX LPI timer in microseconds.\n-\t * This field is valid only when_eee_enabled flag is set to 1\n-\t * and tx_lpi_enabled is set to 1.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \\\n-\t\tUINT32_C(0xffffff)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0\n-\t/* This value represents transceiver identifier type. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \\\n-\t\tUINT32_C(0xff000000)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24\n-\t/* Unknown */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \\\n-\t\t(UINT32_C(0x0) << 24)\n-\t/* SFP/SFP+/SFP28 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \\\n-\t\t(UINT32_C(0x3) << 24)\n-\t/* QSFP+ */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \\\n-\t\t(UINT32_C(0xc) << 24)\n-\t/* QSFP+ */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \\\n-\t\t(UINT32_C(0xd) << 24)\n-\t/* QSFP28 */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \\\n-\t\t(UINT32_C(0x11) << 24)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */\n+struct hwrm_port_phy_cfg_cmd_err {\n \t/*\n-\t * This value represents the current configuration of\n-\t * Forward Error Correction (FEC) on the port.\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n \t */\n-\tuint16_t\tfec_cfg;\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)\n+\t/* Unable to complete operation due to invalid speed */\n+\t#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED UINT32_C(0x1)\n \t/*\n-\t * When set to 1, then FEC is not supported on this port. If this flag\n-\t * is set to 1, then all other FEC configuration flags shall be ignored.\n-\t * When set to 0, then FEC is supported as indicated by other\n-\t * configuration flags.\n-\t * If no cable is attached and the HWRM does not yet know the FEC\n-\t * capability, then the HWRM shall set this flag to 1 when reporting\n-\t * FEC capability.\n-\t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * When set to 1, then FEC autonegotiation is supported on this port.\n-\t * When set to 0, then FEC autonegotiation is not supported on this port.\n-\t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * When set to 1, then FEC autonegotiation is enabled on this port.\n-\t * When set to 0, then FEC autonegotiation is disabled if supported.\n-\t * This flag should be ignored if FEC autonegotiation is not supported on this port.\n-\t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.\n-\t * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.\n-\t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.\n-\t * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.\n-\t * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.\n-\t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.\n-\t * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.\n-\t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.\n-\t * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.\n-\t * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.\n-\t */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * This value is indicates the duplex of the current\n-\t * connection state.\n-\t */\n-\tuint8_t\tduplex_state;\n-\t/* Half Duplex connection. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)\n-\t/* Full duplex connection. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \\\n-\t\tHWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL\n-\t/* Option flags fields. */\n-\tuint8_t\toption_flags;\n-\t/* When this bit is '1', Media auto detect is enabled. */\n-\t#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * Up to 16 bytes of null padded ASCII string representing\n-\t * PHY vendor.\n-\t * If the string is set to null, then the vendor name is not\n-\t * available.\n-\t */\n-\tchar\tphy_vendor_name[16];\n-\t/*\n-\t * Up to 16 bytes of null padded ASCII string that\n-\t * identifies vendor specific part number of the PHY.\n-\t * If the string is set to null, then the vendor specific\n-\t * part number is not available.\n-\t */\n-\tchar\tphy_vendor_partnumber[16];\n-\tuint8_t\tunused_2[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * retry the command since the phy is not ready.\n+\t * retry count is returned in opaque_0.\n+\t * This is only valid for the first command and\n+\t * this value will not change for successive calls.\n+\t * but if a 0 is returned at any time then this should\n+\t * be treated as an un recoverable failure,\n+\t *\n+\t * retry interval in milli seconds is returned in opaque_1.\n+\t * This specifies the time that user should wait before\n+\t * issuing the next port_phy_cfg command.\n \t */\n-\tuint8_t\tvalid;\n+\t#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY UINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_CFG_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_PORT_PHY_CFG_CMD_ERR_CODE_RETRY\n+\tuint8_t\tunused_0[7];\n } __attribute__((packed));\n \n-/*********************\n- * hwrm_port_mac_cfg *\n- *********************/\n+/**********************\n+ * hwrm_port_phy_qcfg *\n+ **********************/\n \n \n-/* hwrm_port_mac_cfg_input (size:320b/40B) */\n-struct hwrm_port_mac_cfg_input {\n+/* hwrm_port_phy_qcfg_input (size:192b/24B) */\n+struct hwrm_port_phy_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -11118,1000 +11111,1217 @@ struct hwrm_port_mac_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Port ID of port that is to be queried. */\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_port_phy_qcfg_output (size:768b/96B) */\n+struct hwrm_port_phy_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* This value indicates the current link status. */\n+\tuint8_t\tlink;\n+\t/* There is no link or cable detected. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_NO_LINK UINT32_C(0x0)\n+\t/* There is no link, but a cable has been detected. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SIGNAL UINT32_C(0x1)\n+\t/* There is a link. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK UINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK\n+\tuint8_t\tunused_0;\n+\t/* This value indicates the current link speed of the connection. */\n+\tuint16_t\tlink_speed;\n+\t/* 100Mb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB UINT32_C(0x1)\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB UINT32_C(0xa)\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB UINT32_C(0x14)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB UINT32_C(0x19)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB UINT32_C(0x64)\n+\t/* 20Mb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB UINT32_C(0xc8)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB UINT32_C(0xfa)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB UINT32_C(0x190)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)\n+\t/* 10Mb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB\n \t/*\n-\t * In this field, there are a number of CoS mappings related flags\n-\t * that are used to configure CoS mappings and their corresponding\n-\t * priorities in the hardware.\n-\t * For the priorities of CoS mappings, the HWRM uses the following\n-\t * priority order (high to low) by default:\n-\t * # vlan pri\n-\t * # ip_dscp\n-\t * # tunnel_vlan_pri\n-\t * # default cos\n-\t *\n-\t * A subset of CoS mappings can be enabled.\n-\t * If a priority is not specified for an enabled CoS mapping, the\n-\t * priority will be assigned in the above order for the enabled CoS\n-\t * mappings. For example, if vlan_pri and ip_dscp CoS mappings are\n-\t * enabled and their priorities are not specified, the following\n-\t * priority order (high to low) will be used by the HWRM:\n-\t * # vlan_pri\n-\t * # ip_dscp\n-\t * # default cos\n-\t *\n-\t * vlan_pri CoS mapping together with default CoS with lower priority\n-\t * are enabled by default by the HWRM.\n+\t * This value is indicates the duplex of the current\n+\t * configuration.\n \t */\n-\tuint32_t\tflags;\n+\tuint8_t\tduplex_cfg;\n+\t/* Half Duplex connection. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_HALF UINT32_C(0x0)\n+\t/* Full duplex connection. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_CFG_FULL\n \t/*\n-\t * When this bit is '1', this command will configure\n-\t * the MAC to match the current link state of the PHY.\n-\t * If the link is not established on the PHY, then this\n-\t * bit has no effect.\n+\t * This value is used to indicate the current\n+\t * pause configuration. When autoneg is enabled, this value\n+\t * represents the autoneg results of pause configuration.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \\\n-\t\tUINT32_C(0x1)\n+\tuint8_t\tpause;\n \t/*\n-\t * When this bit is set to '1', the inner VLAN PRI to CoS mapping\n-\t * is requested to be enabled.\n+\t * When this bit is '1', Generation of tx pause messages\n+\t * is supported. Disabled otherwise.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX UINT32_C(0x1)\n \t/*\n-\t * When this bit is set to '1', tunnel VLAN PRI field to\n-\t * CoS mapping is requested to be enabled.\n+\t * When this bit is '1', Reception of rx pause messages\n+\t * is supported. Disabled otherwise.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \\\n-\t\tUINT32_C(0x4)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX UINT32_C(0x2)\n \t/*\n-\t * When this bit is set to '1', the IP DSCP to CoS mapping is\n-\t * requested to be enabled.\n+\t * The supported speeds for the port. This is a bit mask.\n+\t * For each speed that is supported, the corrresponding\n+\t * bit will be set to '1'.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \\\n+\tuint16_t\tsupport_speeds;\n+\t/* 100Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD \\\n+\t\tUINT32_C(0x1)\n+\t/* 100Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MB \\\n+\t\tUINT32_C(0x2)\n+\t/* 1Gb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GBHD \\\n+\t\tUINT32_C(0x4)\n+\t/* 1Gb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB \\\n \t\tUINT32_C(0x8)\n-\t/*\n-\t * When this bit is '1', the HWRM is requested to\n-\t * enable timestamp capture capability on the receive side\n-\t * of this port.\n-\t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \\\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2GB \\\n \t\tUINT32_C(0x10)\n-\t/*\n-\t * When this bit is '1', the HWRM is requested to\n-\t * disable timestamp capture capability on the receive side\n-\t * of this port.\n-\t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \\\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB \\\n \t\tUINT32_C(0x20)\n-\t/*\n-\t * When this bit is '1', the HWRM is requested to\n-\t * enable timestamp capture capability on the transmit side\n-\t * of this port.\n-\t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \\\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB \\\n \t\tUINT32_C(0x40)\n-\t/*\n-\t * When this bit is '1', the HWRM is requested to\n-\t * disable timestamp capture capability on the transmit side\n-\t * of this port.\n-\t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \\\n+\t/* 20Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB \\\n \t\tUINT32_C(0x80)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB \\\n+\t\tUINT32_C(0x100)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB \\\n+\t\tUINT32_C(0x200)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB \\\n+\t\tUINT32_C(0x400)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB \\\n+\t\tUINT32_C(0x800)\n+\t/* 10Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MBHD \\\n+\t\tUINT32_C(0x1000)\n+\t/* 10Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \\\n+\t\tUINT32_C(0x2000)\n \t/*\n-\t * When this bit is '1', the Out-Of-Box WoL is requested to\n-\t * be enabled on this port.\n+\t * Current setting of forced link speed.\n+\t * When the link speed is not being forced, this\n+\t * value shall be set to 0.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \\\n-\t\tUINT32_C(0x100)\n+\tuint16_t\tforce_link_speed;\n+\t/* 100Mb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100MB UINT32_C(0x1)\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_1GB UINT32_C(0xa)\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2GB UINT32_C(0x14)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_2_5GB UINT32_C(0x19)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10GB UINT32_C(0x64)\n+\t/* 20Mb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_20GB UINT32_C(0xc8)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_25GB UINT32_C(0xfa)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_40GB \\\n+\t\tUINT32_C(0x190)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_50GB \\\n+\t\tUINT32_C(0x1f4)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \\\n+\t\tUINT32_C(0x3e8)\n+\t/* 10Mb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB\n+\t/* Current setting of auto negotiation mode. */\n+\tuint8_t\tauto_mode;\n+\t/* Disable autoneg or autoneg disabled. No speeds are selected. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE UINT32_C(0x0)\n+\t/* Select all possible speeds for autoneg mode. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ALL_SPEEDS UINT32_C(0x1)\n \t/*\n-\t * When this bit is '1', the the Out-Of-Box WoL is requested to\n-\t * be disabled on this port.\n+\t * Select only the auto_link_speed speed for autoneg mode. This mode has\n+\t * been DEPRECATED. An HWRM client should not use this mode.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \\\n-\t\tUINT32_C(0x200)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_SPEED UINT32_C(0x2)\n \t/*\n-\t * When this bit is set to '1', the inner VLAN PRI to CoS mapping\n-\t * is requested to be disabled.\n+\t * Select the auto_link_speed or any speed below that speed for autoneg.\n+\t * This mode has been DEPRECATED. An HWRM client should not use this mode.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \\\n-\t\tUINT32_C(0x400)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_ONE_OR_BELOW UINT32_C(0x3)\n \t/*\n-\t * When this bit is set to '1', tunnel VLAN PRI field to\n-\t * CoS mapping is requested to be disabled.\n+\t * Select the speeds based on the corresponding link speed mask value\n+\t * that is provided.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \\\n-\t\tUINT32_C(0x800)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK UINT32_C(0x4)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_SPEED_MASK\n \t/*\n-\t * When this bit is set to '1', the IP DSCP to CoS mapping is\n-\t * requested to be disabled.\n+\t * Current setting of pause autonegotiation.\n+\t * Move autoneg_pause flag here.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \\\n-\t\tUINT32_C(0x1000)\n-\tuint32_t\tenables;\n+\tuint8_t\tauto_pause;\n \t/*\n-\t * This bit must be '1' for the ipg field to be\n-\t * configured.\n+\t * When this bit is '1', Generation of tx pause messages\n+\t * has been requested. Disabled otherwise.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \\\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_TX \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the lpbk field to be\n-\t * configured.\n+\t * When this bit is '1', Reception of rx pause messages\n+\t * has been requested. Disabled otherwise.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \\\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_RX \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the vlan_pri2cos_map_pri field to be\n-\t * configured.\n+\t * When set to 1, the advertisement of pause is enabled.\n+\t *\n+\t * # When the auto_mode is not set to none and this flag is\n+\t * set to 1, then the auto_pause bits on this port are being\n+\t * advertised and autoneg pause results are being interpreted.\n+\t * # When the auto_mode is not set to none and this\n+\t * flag is set to 0, the pause is forced as indicated in\n+\t * force_pause, and also advertised as auto_pause bits, but\n+\t * the autoneg results are not interpreted since the pause\n+\t * configuration is being forced.\n+\t * # When the auto_mode is set to none and this flag is set to\n+\t * 1, auto_pause bits should be ignored and should be set to 0.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \\\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_PAUSE_AUTONEG_PAUSE \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the tunnel_pri2cos_map_pri field to be\n-\t * configured.\n+\t * Current setting for auto_link_speed. This field is only\n+\t * valid when auto_mode is set to \"one_speed\" or \"one_or_below\".\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \\\n-\t\tUINT32_C(0x10)\n+\tuint16_t\tauto_link_speed;\n+\t/* 100Mb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100MB UINT32_C(0x1)\n+\t/* 1Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_1GB UINT32_C(0xa)\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2GB UINT32_C(0x14)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_2_5GB UINT32_C(0x19)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10GB UINT32_C(0x64)\n+\t/* 20Mb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_20GB UINT32_C(0xc8)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_25GB UINT32_C(0xfa)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_40GB UINT32_C(0x190)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)\n+\t/* 10Mb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB\n \t/*\n-\t * This bit must be '1' for the dscp2cos_map_pri field to be\n-\t * configured.\n+\t * Current setting for auto_link_speed_mask that is used to\n+\t * advertise speeds during autonegotiation.\n+\t * This field is only valid when auto_mode is set to \"mask\".\n+\t * The speeds specified in this field shall be a subset of\n+\t * supported speeds on this port.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \\\n+\tuint16_t\tauto_link_speed_mask;\n+\t/* 100Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MBHD \\\n+\t\tUINT32_C(0x1)\n+\t/* 100Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100MB \\\n+\t\tUINT32_C(0x2)\n+\t/* 1Gb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GBHD \\\n+\t\tUINT32_C(0x4)\n+\t/* 1Gb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_1GB \\\n+\t\tUINT32_C(0x8)\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2GB \\\n+\t\tUINT32_C(0x10)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_2_5GB \\\n \t\tUINT32_C(0x20)\n-\t/*\n-\t * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \\\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10GB \\\n \t\tUINT32_C(0x40)\n-\t/*\n-\t * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \\\n+\t/* 20Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_20GB \\\n \t\tUINT32_C(0x80)\n-\t/*\n-\t * This bit must be '1' for the cos_field_cfg field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \\\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_25GB \\\n \t\tUINT32_C(0x100)\n-\t/* Port ID of port that is to be configured. */\n-\tuint16_t\tport_id;\n-\t/*\n-\t * This value is used to configure the minimum IPG that will\n-\t * be sent between packets by this port.\n-\t */\n-\tuint8_t\tipg;\n-\t/* This value controls the loopback setting for the MAC. */\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_40GB \\\n+\t\tUINT32_C(0x200)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_50GB \\\n+\t\tUINT32_C(0x400)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_100GB \\\n+\t\tUINT32_C(0x800)\n+\t/* 10Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MBHD \\\n+\t\tUINT32_C(0x1000)\n+\t/* 10Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \\\n+\t\tUINT32_C(0x2000)\n+\t/* Current setting for wirespeed. */\n+\tuint8_t\twirespeed;\n+\t/* Wirespeed feature is disabled. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_OFF UINT32_C(0x0)\n+\t/* Wirespeed feature is enabled. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_WIRESPEED_ON\n+\t/* Current setting for loopback. */\n \tuint8_t\tlpbk;\n \t/* No loopback is selected. Normal operation. */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)\n \t/*\n \t * The HW will be configured with local loopback such that\n \t * host data is sent back to the host without modification.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)\n \t/*\n \t * The HW will be configured with remote loopback such that\n \t * port logic will send packets back out the transmitter that\n \t * are received.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)\n-\t#define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \\\n-\t\tHWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)\n \t/*\n-\t * This value controls the priority setting of VLAN PRI to CoS\n-\t * mapping based on VLAN Tags of inner packet headers of\n-\t * tunneled packets or packet headers of non-tunneled packets.\n-\t *\n-\t * # Each XXX_pri variable shall have a unique priority value\n-\t * when it is being specified.\n-\t * # When comparing priorities of mappings, higher value\n-\t * indicates higher priority.\n-\t * For example, a value of 0-3 is returned where 0 is being\n-\t * the lowest priority and 3 is being the highest priority.\n+\t * The HW will be configured with external loopback such that\n+\t * host data is sent on the trasmitter and based on the external\n+\t * loopback connection the data will be received without modification.\n \t */\n-\tuint8_t\tvlan_pri2cos_map_pri;\n-\t/* Reserved field. */\n-\tuint8_t\treserved1;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL UINT32_C(0x3)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LPBK_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LPBK_EXTERNAL\n \t/*\n-\t * This value controls the priority setting of VLAN PRI to CoS\n-\t * mapping based on VLAN Tags of tunneled header.\n-\t * This mapping only applies when tunneled headers\n-\t * are present.\n-\t *\n-\t * # Each XXX_pri variable shall have a unique priority value\n-\t * when it is being specified.\n-\t * # When comparing priorities of mappings, higher value\n-\t * indicates higher priority.\n-\t * For example, a value of 0-3 is returned where 0 is being\n-\t * the lowest priority and 3 is being the highest priority.\n+\t * Current setting of forced pause.\n+\t * When the pause configuration is not being forced, then\n+\t * this value shall be set to 0.\n \t */\n-\tuint8_t\ttunnel_pri2cos_map_pri;\n+\tuint8_t\tforce_pause;\n \t/*\n-\t * This value controls the priority setting of IP DSCP to CoS\n-\t * mapping based on inner IP header of tunneled packets or\n-\t * IP header of non-tunneled packets.\n-\t *\n-\t * # Each XXX_pri variable shall have a unique priority value\n-\t * when it is being specified.\n-\t * # When comparing priorities of mappings, higher value\n-\t * indicates higher priority.\n-\t * For example, a value of 0-3 is returned where 0 is being\n-\t * the lowest priority and 3 is being the highest priority.\n+\t * When this bit is '1', Generation of tx pause messages\n+\t * is supported. Disabled otherwise.\n \t */\n-\tuint8_t\tdscp2pri_map_pri;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_TX UINT32_C(0x1)\n \t/*\n-\t * This is a 16-bit bit mask that is used to request a\n-\t * specific configuration of time stamp capture of PTP messages\n-\t * on the receive side of this port.\n-\t * This field shall be ignored if the ptp_rx_ts_capture_enable\n-\t * flag is not set in this command.\n-\t * Otherwise, if bit 'i' is set, then the HWRM is being\n-\t * requested to configure the receive side of the port to\n-\t * capture the time stamp of every received PTP message\n-\t * with messageType field value set to i.\n+\t * When this bit is '1', Reception of rx pause messages\n+\t * is supported. Disabled otherwise.\n \t */\n-\tuint16_t\trx_ts_capture_ptp_msg_type;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_PAUSE_RX UINT32_C(0x2)\n \t/*\n-\t * This is a 16-bit bit mask that is used to request a\n-\t * specific configuration of time stamp capture of PTP messages\n-\t * on the transmit side of this port.\n-\t * This field shall be ignored if the ptp_tx_ts_capture_enable\n-\t * flag is not set in this command.\n-\t * Otherwise, if bit 'i' is set, then the HWRM is being\n-\t * requested to configure the transmit sied of the port to\n-\t * capture the time stamp of every transmitted PTP message\n-\t * with messageType field value set to i.\n+\t * This value indicates the current status of the optics module on\n+\t * this port.\n \t */\n-\tuint16_t\ttx_ts_capture_ptp_msg_type;\n-\t/* Configuration of CoS fields. */\n-\tuint8_t\tcos_field_cfg;\n-\t/* Reserved */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \\\n+\tuint8_t\tmodule_status;\n+\t/* Module is inserted and accepted */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NONE \\\n+\t\tUINT32_C(0x0)\n+\t/* Module is rejected and transmit side Laser is disabled. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_DISABLETX \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * This field is used to specify selection of VLAN PRI value\n-\t * based on whether one or two VLAN Tags are present in\n-\t * the inner packet headers of tunneled packets or\n-\t * non-tunneled packets.\n-\t * This field is valid only if inner VLAN PRI to CoS mapping\n-\t * is enabled.\n-\t * If VLAN PRI to CoS mapping is not enabled, then this\n-\t * field shall be ignored.\n-\t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \\\n+\t/* Module mismatch warning. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG \\\n+\t\tUINT32_C(0x2)\n+\t/* Module is rejected and powered down. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_PWRDOWN \\\n+\t\tUINT32_C(0x3)\n+\t/* Module is not inserted. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTINSERTED \\\n+\t\tUINT32_C(0x4)\n+\t/* Module status is not applicable. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_NOTAPPLICABLE\n+\t/* Current setting for preemphasis. */\n+\tuint32_t\tpreemphasis;\n+\t/* This field represents the major version of the PHY. */\n+\tuint8_t\tphy_maj;\n+\t/* This field represents the minor version of the PHY. */\n+\tuint8_t\tphy_min;\n+\t/* This field represents the build version of the PHY. */\n+\tuint8_t\tphy_bld;\n+\t/* This value represents a PHY type. */\n+\tuint8_t\tphy_type;\n+\t/* Unknown */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_UNKNOWN \\\n+\t\tUINT32_C(0x0)\n+\t/* BASE-CR */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASECR \\\n+\t\tUINT32_C(0x1)\n+\t/* BASE-KR4 (Deprecated) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR4 \\\n+\t\tUINT32_C(0x2)\n+\t/* BASE-LR */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASELR \\\n+\t\tUINT32_C(0x3)\n+\t/* BASE-SR */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASESR \\\n+\t\tUINT32_C(0x4)\n+\t/* BASE-KR2 (Deprecated) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR2 \\\n+\t\tUINT32_C(0x5)\n+\t/* BASE-KX */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKX \\\n \t\tUINT32_C(0x6)\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \\\n-\t\t1\n+\t/* BASE-KR */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASEKR \\\n+\t\tUINT32_C(0x7)\n+\t/* BASE-T */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET \\\n+\t\tUINT32_C(0x8)\n+\t/* EEE capable BASE-T */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE \\\n+\t\tUINT32_C(0x9)\n+\t/* SGMII connected external PHY */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_SGMIIEXTPHY \\\n+\t\tUINT32_C(0xa)\n+\t/* 25G_BASECR_CA_L */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_L \\\n+\t\tUINT32_C(0xb)\n+\t/* 25G_BASECR_CA_S */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_S \\\n+\t\tUINT32_C(0xc)\n+\t/* 25G_BASECR_CA_N */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASECR_CA_N \\\n+\t\tUINT32_C(0xd)\n+\t/* 25G_BASESR */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_25G_BASESR \\\n+\t\tUINT32_C(0xe)\n+\t/* 100G_BASECR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASECR4 \\\n+\t\tUINT32_C(0xf)\n+\t/* 100G_BASESR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR4 \\\n+\t\tUINT32_C(0x10)\n+\t/* 100G_BASELR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASELR4 \\\n+\t\tUINT32_C(0x11)\n+\t/* 100G_BASEER4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASEER4 \\\n+\t\tUINT32_C(0x12)\n+\t/* 100G_BASESR10 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_100G_BASESR10 \\\n+\t\tUINT32_C(0x13)\n+\t/* 40G_BASECR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASECR4 \\\n+\t\tUINT32_C(0x14)\n+\t/* 40G_BASESR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASESR4 \\\n+\t\tUINT32_C(0x15)\n+\t/* 40G_BASELR4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASELR4 \\\n+\t\tUINT32_C(0x16)\n+\t/* 40G_BASEER4 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_BASEER4 \\\n+\t\tUINT32_C(0x17)\n+\t/* 40G_ACTIVE_CABLE */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_40G_ACTIVE_CABLE \\\n+\t\tUINT32_C(0x18)\n+\t/* 1G_baseT */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASET \\\n+\t\tUINT32_C(0x19)\n+\t/* 1G_baseSX */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASESX \\\n+\t\tUINT32_C(0x1a)\n+\t/* 1G_baseCX */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \\\n+\t\tUINT32_C(0x1b)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX\n+\t/* This value represents a media type. */\n+\tuint8_t\tmedia_type;\n+\t/* Unknown */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_UNKNOWN UINT32_C(0x0)\n+\t/* Twisted Pair */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP UINT32_C(0x1)\n+\t/* Direct Attached Copper */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_DAC UINT32_C(0x2)\n+\t/* Fiber */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE UINT32_C(0x3)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_FIBRE\n+\t/* This value represents a transceiver type. */\n+\tuint8_t\txcvr_pkg_type;\n+\t/* PHY and MAC are in the same package */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_INTERNAL \\\n+\t\tUINT32_C(0x1)\n+\t/* PHY and MAC are in different packages */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_XCVR_PKG_TYPE_XCVR_EXTERNAL\n+\tuint8_t\teee_config_phy_addr;\n+\t/* This field represents PHY address. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_MASK \\\n+\t\tUINT32_C(0x1f)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_ADDR_SFT 0\n \t/*\n-\t * Select inner VLAN PRI when 1 or 2 VLAN Tags are\n-\t * present in the inner packet headers\n+\t * This field represents flags related to EEE configuration.\n+\t * These EEE configuration flags are valid only when the\n+\t * auto_mode is not set to none (in other words autonegotiation\n+\t * is enabled).\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \\\n-\t\t(UINT32_C(0x0) << 1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_MASK \\\n+\t\tUINT32_C(0xe0)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_SFT 5\n \t/*\n-\t * Select outer VLAN Tag PRI when 2 VLAN Tags are\n-\t * present in the inner packet headers.\n-\t * No VLAN PRI shall be selected for this configuration\n-\t * if only one VLAN Tag is present in the inner\n-\t * packet headers.\n+\t * When set to 1, Energy Efficient Ethernet (EEE) mode is enabled.\n+\t * Speeds for autoneg with EEE mode enabled\n+\t * are based on eee_link_speed_mask.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \\\n-\t\t(UINT32_C(0x1) << 1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ENABLED \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * Select outermost VLAN PRI when 1 or 2 VLAN Tags\n-\t * are present in the inner packet headers\n+\t * This flag is valid only when eee_enabled is set to 1.\n+\t *\n+\t * # If eee_enabled is set to 0, then EEE mode is disabled\n+\t * and this flag shall be ignored.\n+\t * # If eee_enabled is set to 1 and this flag is set to 1,\n+\t * then Energy Efficient Ethernet (EEE) mode is enabled\n+\t * and in use.\n+\t * # If eee_enabled is set to 1 and this flag is set to 0,\n+\t * then Energy Efficient Ethernet (EEE) mode is enabled\n+\t * but is currently not in use.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \\\n-\t\t(UINT32_C(0x2) << 1)\n-\t/* Unspecified */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \\\n-\t\t(UINT32_C(0x3) << 1)\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \\\n-\t\tHWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED\n-\t/*\n-\t * This field is used to specify selection of tunnel VLAN\n-\t * PRI value based on whether one or two VLAN Tags are\n-\t * present in tunnel headers.\n-\t * This field is valid only if tunnel VLAN PRI to CoS mapping\n-\t * is enabled.\n-\t * If tunnel VLAN PRI to CoS mapping is not enabled, then this\n-\t * field shall be ignored.\n-\t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \\\n-\t\tUINT32_C(0x18)\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \\\n-\t\t3\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_ACTIVE \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * Select inner VLAN PRI when 1 or 2 VLAN Tags are\n-\t * present in the tunnel packet headers\n+\t * This flag is valid only when eee_enabled is set to 1.\n+\t *\n+\t * # If eee_enabled is set to 0, then EEE mode is disabled\n+\t * and this flag shall be ignored.\n+\t * # If eee_enabled is set to 1 and this flag is set to 1,\n+\t * then Energy Efficient Ethernet (EEE) mode is enabled\n+\t * and TX LPI is enabled.\n+\t * # If eee_enabled is set to 1 and this flag is set to 0,\n+\t * then Energy Efficient Ethernet (EEE) mode is enabled\n+\t * but TX LPI is disabled.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \\\n-\t\t(UINT32_C(0x0) << 3)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_EEE_CONFIG_EEE_TX_LPI \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * Select outer VLAN Tag PRI when 2 VLAN Tags are\n-\t * present in the tunnel packet headers.\n-\t * No tunnel VLAN PRI shall be selected for this\n-\t * configuration if only one VLAN Tag is present in\n-\t * the tunnel packet headers.\n+\t * When set to 1, the parallel detection is used to determine\n+\t * the speed of the link partner.\n+\t *\n+\t * Parallel detection is used when a autonegotiation capable\n+\t * device is connected to a link parter that is not capable\n+\t * of autonegotiation.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \\\n-\t\t(UINT32_C(0x1) << 3)\n+\tuint8_t\tparallel_detect;\n \t/*\n-\t * Select outermost VLAN PRI when 1 or 2 VLAN Tags\n-\t * are present in the tunnel packet headers\n+\t * When set to 1, the parallel detection is used to determine\n+\t * the speed of the link partner.\n+\t *\n+\t * Parallel detection is used when a autonegotiation capable\n+\t * device is connected to a link parter that is not capable\n+\t * of autonegotiation.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \\\n-\t\t(UINT32_C(0x2) << 3)\n-\t/* Unspecified */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \\\n-\t\t(UINT32_C(0x3) << 3)\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \\\n-\t\tHWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_PARALLEL_DETECT UINT32_C(0x1)\n \t/*\n-\t * This field shall be used to provide default CoS value\n-\t * that has been configured on this port.\n-\t * This field is valid only if default CoS mapping\n-\t * is enabled.\n-\t * If default CoS mapping is not enabled, then this\n-\t * field shall be ignored.\n+\t * The advertised speeds for the port by the link partner.\n+\t * Each advertised speed will be set to '1'.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \\\n-\t\tUINT32_C(0xe0)\n-\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \\\n-\t\t5\n-\tuint8_t\tunused_0[3];\n-} __attribute__((packed));\n-\n-/* hwrm_port_mac_cfg_output (size:128b/16B) */\n-struct hwrm_port_mac_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n+\tuint16_t\tlink_partner_adv_speeds;\n+\t/* 100Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MBHD \\\n+\t\tUINT32_C(0x1)\n+\t/* 100Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100MB \\\n+\t\tUINT32_C(0x2)\n+\t/* 1Gb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GBHD \\\n+\t\tUINT32_C(0x4)\n+\t/* 1Gb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_1GB \\\n+\t\tUINT32_C(0x8)\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2GB \\\n+\t\tUINT32_C(0x10)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_2_5GB \\\n+\t\tUINT32_C(0x20)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10GB \\\n+\t\tUINT32_C(0x40)\n+\t/* 20Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_20GB \\\n+\t\tUINT32_C(0x80)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_25GB \\\n+\t\tUINT32_C(0x100)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_40GB \\\n+\t\tUINT32_C(0x200)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_50GB \\\n+\t\tUINT32_C(0x400)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_100GB \\\n+\t\tUINT32_C(0x800)\n+\t/* 10Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MBHD \\\n+\t\tUINT32_C(0x1000)\n+\t/* 10Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_SPEEDS_10MB \\\n+\t\tUINT32_C(0x2000)\n \t/*\n-\t * This is the configured maximum length of Ethernet packet\n-\t * payload that is allowed to be received on the port.\n-\t * This value does not include the number of bytes used by\n-\t * Ethernet header and trailer (CRC).\n+\t * The advertised autoneg for the port by the link partner.\n+\t * This field is deprecated and should be set to 0.\n \t */\n-\tuint16_t\tmru;\n+\tuint8_t\tlink_partner_adv_auto_mode;\n+\t/* Disable autoneg or autoneg disabled. No speeds are selected. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_NONE \\\n+\t\tUINT32_C(0x0)\n+\t/* Select all possible speeds for autoneg mode. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * This is the configured maximum length of Ethernet packet\n-\t * payload that is allowed to be transmitted on the port.\n-\t * This value does not include the number of bytes used by\n-\t * Ethernet header and trailer (CRC).\n+\t * Select only the auto_link_speed speed for autoneg mode. This mode has\n+\t * been DEPRECATED. An HWRM client should not use this mode.\n \t */\n-\tuint16_t\tmtu;\n-\t/* Current configuration of the IPG value. */\n-\tuint8_t\tipg;\n-\t/* Current value of the loopback value. */\n-\tuint8_t\tlpbk;\n-\t/* No loopback is selected. Normal operation. */\n-\t#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * The HW will be configured with local loopback such that\n-\t * host data is sent back to the host without modification.\n+\t * Select the auto_link_speed or any speed below that speed for autoneg.\n+\t * This mode has been DEPRECATED. An HWRM client should not use this mode.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW \\\n+\t\tUINT32_C(0x3)\n \t/*\n-\t * The HW will be configured with remote loopback such that\n-\t * port logic will send packets back out the transmitter that\n-\t * are received.\n+\t * Select the speeds based on the corresponding link speed mask value\n+\t * that is provided.\n \t */\n-\t#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)\n-\t#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \\\n-\t\tHWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE\n-\tuint8_t\tunused_0;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK \\\n+\t\tUINT32_C(0x4)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK\n+\t/* The advertised pause settings on the port by the link partner. */\n+\tuint8_t\tlink_partner_adv_pause;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When this bit is '1', Generation of tx pause messages\n+\t * is supported. Disabled otherwise.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**********************\n- * hwrm_port_mac_qcfg *\n- **********************/\n-\n-\n-/* hwrm_port_mac_qcfg_input (size:192b/24B) */\n-struct hwrm_port_mac_qcfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_TX \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * When this bit is '1', Reception of rx pause messages\n+\t * is supported. Disabled otherwise.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_PAUSE_RX \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Current setting for link speed mask that is used to\n+\t * advertise speeds during autonegotiation when EEE is enabled.\n+\t * This field is valid only when eee_enabled flags is set to 1.\n+\t * The speeds specified in this field shall be a subset of\n+\t * speeds specified in auto_link_speed_mask.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint16_t\tadv_eee_link_speed_mask;\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD1 \\\n+\t\tUINT32_C(0x1)\n+\t/* 100Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_100MB \\\n+\t\tUINT32_C(0x2)\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD2 \\\n+\t\tUINT32_C(0x4)\n+\t/* 1Gb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_1GB \\\n+\t\tUINT32_C(0x8)\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD3 \\\n+\t\tUINT32_C(0x10)\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_RSVD4 \\\n+\t\tUINT32_C(0x20)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_ADV_EEE_LINK_SPEED_MASK_10GB \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * Current setting for link speed mask that is advertised by\n+\t * the link partner when EEE is enabled.\n+\t * This field is valid only when eee_enabled flags is set to 1.\n \t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\tuint16_t\tlink_partner_adv_eee_link_speed_mask;\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 \\\n+\t\tUINT32_C(0x1)\n+\t/* 100Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB \\\n+\t\tUINT32_C(0x2)\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 \\\n+\t\tUINT32_C(0x4)\n+\t/* 1Gb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB \\\n+\t\tUINT32_C(0x8)\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 \\\n+\t\tUINT32_C(0x10)\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 \\\n+\t\tUINT32_C(0x20)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB \\\n+\t\tUINT32_C(0x40)\n+\tuint32_t\txcvr_identifier_type_tx_lpi_timer;\n+\t/*\n+\t * Current setting of TX LPI timer in microseconds.\n+\t * This field is valid only when_eee_enabled flag is set to 1\n+\t * and tx_lpi_enabled is set to 1.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Port ID of port that is to be configured. */\n-\tuint16_t\tport_id;\n-\tuint8_t\tunused_0[6];\n-} __attribute__((packed));\n-\n-/* hwrm_port_mac_qcfg_output (size:192b/24B) */\n-struct hwrm_port_mac_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_MASK \\\n+\t\tUINT32_C(0xffffff)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_TX_LPI_TIMER_SFT 0\n+\t/* This value represents transceiver identifier type. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_MASK \\\n+\t\tUINT32_C(0xff000000)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFT 24\n+\t/* Unknown */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_UNKNOWN \\\n+\t\t(UINT32_C(0x0) << 24)\n+\t/* SFP/SFP+/SFP28 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_SFP \\\n+\t\t(UINT32_C(0x3) << 24)\n+\t/* QSFP+ */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP \\\n+\t\t(UINT32_C(0xc) << 24)\n+\t/* QSFP+ */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFPPLUS \\\n+\t\t(UINT32_C(0xd) << 24)\n+\t/* QSFP28 */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28 \\\n+\t\t(UINT32_C(0x11) << 24)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_XCVR_IDENTIFIER_TYPE_QSFP28\n \t/*\n-\t * This is the configured maximum length of Ethernet packet\n-\t * payload that is allowed to be received on the port.\n-\t * This value does not include the number of bytes used by the\n-\t * Ethernet header and trailer (CRC).\n+\t * This value represents the current configuration of\n+\t * Forward Error Correction (FEC) on the port.\n \t */\n-\tuint16_t\tmru;\n+\tuint16_t\tfec_cfg;\n \t/*\n-\t * This is the configured maximum length of Ethernet packet\n-\t * payload that is allowed to be transmitted on the port.\n-\t * This value does not include the number of bytes used by the\n-\t * Ethernet header and trailer (CRC).\n+\t * When set to 1, then FEC is not supported on this port. If this flag\n+\t * is set to 1, then all other FEC configuration flags shall be ignored.\n+\t * When set to 0, then FEC is supported as indicated by other\n+\t * configuration flags.\n+\t * If no cable is attached and the HWRM does not yet know the FEC\n+\t * capability, then the HWRM shall set this flag to 1 when reporting\n+\t * FEC capability.\n \t */\n-\tuint16_t\tmtu;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_NONE_SUPPORTED \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * The minimum IPG that will\n-\t * be sent between packets by this port.\n+\t * When set to 1, then FEC autonegotiation is supported on this port.\n+\t * When set to 0, then FEC autonegotiation is not supported on this port.\n \t */\n-\tuint8_t\tipg;\n-\t/* The loopback setting for the MAC. */\n-\tuint8_t\tlpbk;\n-\t/* No loopback is selected. Normal operation. */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * The HW will be configured with local loopback such that\n-\t * host data is sent back to the host without modification.\n+\t * When set to 1, then FEC autonegotiation is enabled on this port.\n+\t * When set to 0, then FEC autonegotiation is disabled if supported.\n+\t * This flag should be ignored if FEC autonegotiation is not supported on this port.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_AUTONEG_ENABLED \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * The HW will be configured with remote loopback such that\n-\t * port logic will send packets back out the transmitter that\n-\t * are received.\n+\t * When set to 1, then FEC CLAUSE 74 (Fire Code) is supported on this port.\n+\t * When set to 0, then FEC CLAUSE 74 (Fire Code) is not supported on this port.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \\\n-\t\tHWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * Priority setting for VLAN PRI to CoS mapping.\n-\t * # Each XXX_pri variable shall have a unique priority value\n-\t * when it is being used.\n-\t * # When comparing priorities of mappings, higher value\n-\t * indicates higher priority.\n-\t * For example, a value of 0-3 is returned where 0 is being\n-\t * the lowest priority and 3 is being the highest priority.\n-\t * # If the correspoding CoS mapping is not enabled, then this\n-\t * field should be ignored.\n-\t * # This value indicates the normalized priority value retained\n-\t * in the HWRM.\n+\t * When set to 1, then FEC CLAUSE 74 (Fire Code) is enabled on this port.\n+\t * When set to 0, then FEC CLAUSE 74 (Fire Code) is disabled if supported.\n+\t * This flag should be ignored if FEC CLAUSE 74 is not supported on this port.\n \t */\n-\tuint8_t\tvlan_pri2cos_map_pri;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE74_ENABLED \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * In this field, a number of CoS mappings related flags\n-\t * are used to indicate configured CoS mappings.\n+\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is supported on this port.\n+\t * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is not supported on this port.\n \t */\n-\tuint8_t\tflags;\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_SUPPORTED \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * When this bit is set to '1', the inner VLAN PRI to CoS mapping\n-\t * is enabled.\n+\t * When set to 1, then FEC CLAUSE 91 (Reed Solomon) is enabled on this port.\n+\t * When set to 0, then FEC CLAUSE 91 (Reed Solomon) is disabled if supported.\n+\t * This flag should be ignored if FEC CLAUSE 91 is not supported on this port.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_FEC_CFG_FEC_CLAUSE91_ENABLED \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * When this bit is set to '1', tunnel VLAN PRI field to\n-\t * CoS mapping is enabled.\n+\t * This value is indicates the duplex of the current\n+\t * connection state.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \\\n-\t\tUINT32_C(0x2)\n+\tuint8_t\tduplex_state;\n+\t/* Half Duplex connection. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_HALF UINT32_C(0x0)\n+\t/* Full duplex connection. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL UINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_LAST \\\n+\t\tHWRM_PORT_PHY_QCFG_OUTPUT_DUPLEX_STATE_FULL\n+\t/* Option flags fields. */\n+\tuint8_t\toption_flags;\n+\t/* When this bit is '1', Media auto detect is enabled. */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * When this bit is set to '1', the IP DSCP to CoS mapping is\n-\t * enabled.\n+\t * Up to 16 bytes of null padded ASCII string representing\n+\t * PHY vendor.\n+\t * If the string is set to null, then the vendor name is not\n+\t * available.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \\\n-\t\tUINT32_C(0x4)\n+\tchar\tphy_vendor_name[16];\n \t/*\n-\t * When this bit is '1', the Out-Of-Box WoL is enabled on this\n-\t * port.\n+\t * Up to 16 bytes of null padded ASCII string that\n+\t * identifies vendor specific part number of the PHY.\n+\t * If the string is set to null, then the vendor specific\n+\t * part number is not available.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \\\n-\t\tUINT32_C(0x8)\n-\t/* When this bit is '1', PTP is enabled for RX on this port. */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \\\n-\t\tUINT32_C(0x10)\n-\t/* When this bit is '1', PTP is enabled for TX on this port. */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \\\n-\t\tUINT32_C(0x20)\n+\tchar\tphy_vendor_partnumber[16];\n+\tuint8_t\tunused_2[7];\n \t/*\n-\t * Priority setting for tunnel VLAN PRI to CoS mapping.\n-\t * # Each XXX_pri variable shall have a unique priority value\n-\t * when it is being used.\n-\t * # When comparing priorities of mappings, higher value\n-\t * indicates higher priority.\n-\t * For example, a value of 0-3 is returned where 0 is being\n-\t * the lowest priority and 3 is being the highest priority.\n-\t * # If the correspoding CoS mapping is not enabled, then this\n-\t * field should be ignored.\n-\t * # This value indicates the normalized priority value retained\n-\t * in the HWRM.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\ttunnel_pri2cos_map_pri;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*********************\n+ * hwrm_port_mac_cfg *\n+ *********************/\n+\n+\n+/* hwrm_port_mac_cfg_input (size:320b/40B) */\n+struct hwrm_port_mac_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * Priority setting for DSCP to PRI mapping.\n-\t * # Each XXX_pri variable shall have a unique priority value\n-\t * when it is being used.\n-\t * # When comparing priorities of mappings, higher value\n-\t * indicates higher priority.\n-\t * For example, a value of 0-3 is returned where 0 is being\n-\t * the lowest priority and 3 is being the highest priority.\n-\t * # If the correspoding CoS mapping is not enabled, then this\n-\t * field should be ignored.\n-\t * # This value indicates the normalized priority value retained\n-\t * in the HWRM.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint8_t\tdscp2pri_map_pri;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * This is a 16-bit bit mask that represents the\n-\t * current configuration of time stamp capture of PTP messages\n-\t * on the receive side of this port.\n-\t * If bit 'i' is set, then the receive side of the port\n-\t * is configured to capture the time stamp of every\n-\t * received PTP message with messageType field value set\n-\t * to i.\n-\t * If all bits are set to 0 (i.e. field value set 0),\n-\t * then the receive side of the port is not configured\n-\t * to capture timestamp for PTP messages.\n-\t * If all bits are set to 1, then the receive side of the\n-\t * port is configured to capture timestamp for all PTP\n-\t * messages.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint16_t\trx_ts_capture_ptp_msg_type;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * This is a 16-bit bit mask that represents the\n-\t * current configuration of time stamp capture of PTP messages\n-\t * on the transmit side of this port.\n-\t * If bit 'i' is set, then the transmit side of the port\n-\t * is configured to capture the time stamp of every\n-\t * received PTP message with messageType field value set\n-\t * to i.\n-\t * If all bits are set to 0 (i.e. field value set 0),\n-\t * then the transmit side of the port is not configured\n-\t * to capture timestamp for PTP messages.\n-\t * If all bits are set to 1, then the transmit side of the\n-\t * port is configured to capture timestamp for all PTP\n-\t * messages.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint16_t\ttx_ts_capture_ptp_msg_type;\n-\t/* Configuration of CoS fields. */\n-\tuint8_t\tcos_field_cfg;\n-\t/* Reserved */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \\\n-\t\tUINT32_C(0x1)\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * This field is used for selecting VLAN PRI value\n-\t * based on whether one or two VLAN Tags are present in\n-\t * the inner packet headers of tunneled packets or\n-\t * non-tunneled packets.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \\\n-\t\tUINT32_C(0x6)\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \\\n-\t\t1\n+\tuint64_t\tresp_addr;\n \t/*\n-\t * Select inner VLAN PRI when 1 or 2 VLAN Tags are\n-\t * present in the inner packet headers\n+\t * In this field, there are a number of CoS mappings related flags\n+\t * that are used to configure CoS mappings and their corresponding\n+\t * priorities in the hardware.\n+\t * For the priorities of CoS mappings, the HWRM uses the following\n+\t * priority order (high to low) by default:\n+\t * # vlan pri\n+\t * # ip_dscp\n+\t * # tunnel_vlan_pri\n+\t * # default cos\n+\t *\n+\t * A subset of CoS mappings can be enabled.\n+\t * If a priority is not specified for an enabled CoS mapping, the\n+\t * priority will be assigned in the above order for the enabled CoS\n+\t * mappings. For example, if vlan_pri and ip_dscp CoS mappings are\n+\t * enabled and their priorities are not specified, the following\n+\t * priority order (high to low) will be used by the HWRM:\n+\t * # vlan_pri\n+\t * # ip_dscp\n+\t * # default cos\n+\t *\n+\t * vlan_pri CoS mapping together with default CoS with lower priority\n+\t * are enabled by default by the HWRM.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \\\n-\t\t(UINT32_C(0x0) << 1)\n+\tuint32_t\tflags;\n \t/*\n-\t * Select outer VLAN Tag PRI when 2 VLAN Tags are\n-\t * present in the inner packet headers.\n-\t * No VLAN PRI is selected for this configuration\n-\t * if only one VLAN Tag is present in the inner\n-\t * packet headers.\n+\t * When this bit is '1', this command will configure\n+\t * the MAC to match the current link state of the PHY.\n+\t * If the link is not established on the PHY, then this\n+\t * bit has no effect.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \\\n-\t\t(UINT32_C(0x1) << 1)\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_MATCH_LINK \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * Select outermost VLAN PRI when 1 or 2 VLAN Tags\n-\t * are present in the inner packet headers\n+\t * When this bit is set to '1', the inner VLAN PRI to CoS mapping\n+\t * is requested to be enabled.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \\\n-\t\t(UINT32_C(0x2) << 1)\n-\t/* Unspecified */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \\\n-\t\t(UINT32_C(0x3) << 1)\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \\\n-\t\tHWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_ENABLE \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * This field is used for selecting tunnel VLAN PRI value\n-\t * based on whether one or two VLAN Tags are present in\n-\t * the tunnel headers of tunneled packets. This selection\n-\t * does not apply to non-tunneled packets.\n+\t * When this bit is set to '1', tunnel VLAN PRI field to\n+\t * CoS mapping is requested to be enabled.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \\\n-\t\tUINT32_C(0x18)\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \\\n-\t\t3\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * Select inner VLAN PRI when 1 or 2 VLAN Tags are\n-\t * present in the tunnel packet headers\n+\t * When this bit is set to '1', the IP DSCP to CoS mapping is\n+\t * requested to be enabled.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \\\n-\t\t(UINT32_C(0x0) << 3)\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_ENABLE \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * Select outer VLAN Tag PRI when 2 VLAN Tags are\n-\t * present in the tunnel packet headers.\n-\t * No VLAN PRI is selected for this configuration\n-\t * if only one VLAN Tag is present in the tunnel\n-\t * packet headers.\n+\t * When this bit is '1', the HWRM is requested to\n+\t * enable timestamp capture capability on the receive side\n+\t * of this port.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \\\n-\t\t(UINT32_C(0x1) << 3)\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * Select outermost VLAN PRI when 1 or 2 VLAN Tags\n-\t * are present in the tunnel packet headers\n+\t * When this bit is '1', the HWRM is requested to\n+\t * disable timestamp capture capability on the receive side\n+\t * of this port.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \\\n-\t\t(UINT32_C(0x2) << 3)\n-\t/* Unspecified */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \\\n-\t\t(UINT32_C(0x3) << 3)\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \\\n-\t\tHWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * This field is used to provide default CoS value that\n-\t * has been configured on this port.\n+\t * When this bit is '1', the HWRM is requested to\n+\t * enable timestamp capture capability on the transmit side\n+\t * of this port.\n \t */\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \\\n-\t\tUINT32_C(0xe0)\n-\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \\\n-\t\t5\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When this bit is '1', the HWRM is requested to\n+\t * disable timestamp capture capability on the transmit side\n+\t * of this port.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**************************\n- * hwrm_port_mac_ptp_qcfg *\n- **************************/\n-\n-\n-/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */\n-struct hwrm_port_mac_ptp_qcfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * When this bit is '1', the Out-Of-Box WoL is requested to\n+\t * be enabled on this port.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_ENABLE \\\n+\t\tUINT32_C(0x100)\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * When this bit is '1', the the Out-Of-Box WoL is requested to\n+\t * be disabled on this port.\n \t */\n-\tuint16_t\tseq_id;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_OOB_WOL_DISABLE \\\n+\t\tUINT32_C(0x200)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * When this bit is set to '1', the inner VLAN PRI to CoS mapping\n+\t * is requested to be disabled.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_VLAN_PRI2COS_DISABLE \\\n+\t\tUINT32_C(0x400)\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * When this bit is set to '1', tunnel VLAN PRI field to\n+\t * CoS mapping is requested to be disabled.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Port ID of port that is being queried. */\n-\tuint16_t\tport_id;\n-\tuint8_t\tunused_0[6];\n-} __attribute__((packed));\n-\n-/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */\n-struct hwrm_port_mac_ptp_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_TUNNEL_PRI2COS_DISABLE \\\n+\t\tUINT32_C(0x800)\n \t/*\n-\t * In this field, a number of PTP related flags\n-\t * are used to indicate configured PTP capabilities.\n+\t * When this bit is set to '1', the IP DSCP to CoS mapping is\n+\t * requested to be disabled.\n \t */\n-\tuint8_t\tflags;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \\\n+\t\tUINT32_C(0x1000)\n+\tuint32_t\tenables;\n \t/*\n-\t * When this bit is set to '1', the PTP related registers are\n-\t * directly accessible by the host.\n+\t * This bit must be '1' for the ipg field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \\\n+\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_IPG \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * When this bit is set to '1', the PTP information is accessible\n-\t * via HWRM commands.\n+\t * This bit must be '1' for the lpbk field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \\\n+\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_LPBK \\\n \t\tUINT32_C(0x2)\n-\tuint8_t\tunused_0[3];\n-\t/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */\n-\tuint32_t\trx_ts_reg_off_lower;\n-\t/* Offset of the PTP register for the upper 32 bits of timestamp for RX. */\n-\tuint32_t\trx_ts_reg_off_upper;\n-\t/* Offset of the PTP register for the sequence ID for RX. */\n-\tuint32_t\trx_ts_reg_off_seq_id;\n-\t/* Offset of the first PTP source ID for RX. */\n-\tuint32_t\trx_ts_reg_off_src_id_0;\n-\t/* Offset of the second PTP source ID for RX. */\n-\tuint32_t\trx_ts_reg_off_src_id_1;\n-\t/* Offset of the third PTP source ID for RX. */\n-\tuint32_t\trx_ts_reg_off_src_id_2;\n-\t/* Offset of the domain ID for RX. */\n-\tuint32_t\trx_ts_reg_off_domain_id;\n-\t/* Offset of the PTP FIFO register for RX. */\n-\tuint32_t\trx_ts_reg_off_fifo;\n-\t/* Offset of the PTP advance FIFO register for RX. */\n-\tuint32_t\trx_ts_reg_off_fifo_adv;\n-\t/* PTP timestamp granularity for RX. */\n-\tuint32_t\trx_ts_reg_off_granularity;\n-\t/* Offset of the PTP register for the lower 32 bits of timestamp for TX. */\n-\tuint32_t\ttx_ts_reg_off_lower;\n-\t/* Offset of the PTP register for the upper 32 bits of timestamp for TX. */\n-\tuint32_t\ttx_ts_reg_off_upper;\n-\t/* Offset of the PTP register for the sequence ID for TX. */\n-\tuint32_t\ttx_ts_reg_off_seq_id;\n-\t/* Offset of the PTP FIFO register for TX. */\n-\tuint32_t\ttx_ts_reg_off_fifo;\n-\t/* PTP timestamp granularity for TX. */\n-\tuint32_t\ttx_ts_reg_off_granularity;\n-\tuint8_t\tunused_1[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This bit must be '1' for the vlan_pri2cos_map_pri field to be\n+\t * configured.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/********************\n- * hwrm_port_qstats *\n- ********************/\n-\n-\n-/* hwrm_port_qstats_input (size:320b/40B) */\n-struct hwrm_port_qstats_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_VLAN_PRI2COS_MAP_PRI \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * This bit must be '1' for the tunnel_pri2cos_map_pri field to be\n+\t * configured.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TUNNEL_PRI2COS_MAP_PRI \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * This bit must be '1' for the dscp2cos_map_pri field to be\n+\t * configured.\n \t */\n-\tuint16_t\tseq_id;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_DSCP2COS_MAP_PRI \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * This bit must be '1' for the rx_ts_capture_ptp_msg_type field to be\n+\t * configured.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * This bit must be '1' for the tx_ts_capture_ptp_msg_type field to be\n+\t * configured.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Port ID of port that is being queried. */\n+\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This bit must be '1' for the cos_field_cfg field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \\\n+\t\tUINT32_C(0x100)\n+\t/* Port ID of port that is to be configured. */\n \tuint16_t\tport_id;\n-\tuint8_t\tunused_0[6];\n \t/*\n-\t * This is the host address where\n-\t * Tx port statistics will be stored\n+\t * This value is used to configure the minimum IPG that will\n+\t * be sent between packets by this port.\n \t */\n-\tuint64_t\ttx_stat_host_addr;\n+\tuint8_t\tipg;\n+\t/* This value controls the loopback setting for the MAC. */\n+\tuint8_t\tlpbk;\n+\t/* No loopback is selected. Normal operation. */\n+\t#define HWRM_PORT_MAC_CFG_INPUT_LPBK_NONE UINT32_C(0x0)\n \t/*\n-\t * This is the host address where\n-\t * Rx port statistics will be stored\n+\t * The HW will be configured with local loopback such that\n+\t * host data is sent back to the host without modification.\n \t */\n-\tuint64_t\trx_stat_host_addr;\n-} __attribute__((packed));\n-\n-/* hwrm_port_qstats_output (size:128b/16B) */\n-struct hwrm_port_qstats_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* The size of TX port statistics block in bytes. */\n-\tuint16_t\ttx_stat_size;\n-\t/* The size of RX port statistics block in bytes. */\n-\tuint16_t\trx_stat_size;\n-\tuint8_t\tunused_0[3];\n+\t#define HWRM_PORT_MAC_CFG_INPUT_LPBK_LOCAL UINT32_C(0x1)\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * The HW will be configured with remote loopback such that\n+\t * port logic will send packets back out the transmitter that\n+\t * are received.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/************************\n- * hwrm_port_qstats_ext *\n- ************************/\n-\n-\n-/* hwrm_port_qstats_ext_input (size:320b/40B) */\n-struct hwrm_port_qstats_ext_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE UINT32_C(0x2)\n+\t#define HWRM_PORT_MAC_CFG_INPUT_LPBK_LAST \\\n+\t\tHWRM_PORT_MAC_CFG_INPUT_LPBK_REMOTE\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * This value controls the priority setting of VLAN PRI to CoS\n+\t * mapping based on VLAN Tags of inner packet headers of\n+\t * tunneled packets or packet headers of non-tunneled packets.\n+\t *\n+\t * # Each XXX_pri variable shall have a unique priority value\n+\t * when it is being specified.\n+\t * # When comparing priorities of mappings, higher value\n+\t * indicates higher priority.\n+\t * For example, a value of 0-3 is returned where 0 is being\n+\t * the lowest priority and 3 is being the highest priority.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint8_t\tvlan_pri2cos_map_pri;\n+\t/* Reserved field. */\n+\tuint8_t\treserved1;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * This value controls the priority setting of VLAN PRI to CoS\n+\t * mapping based on VLAN Tags of tunneled header.\n+\t * This mapping only applies when tunneled headers\n+\t * are present.\n+\t *\n+\t * # Each XXX_pri variable shall have a unique priority value\n+\t * when it is being specified.\n+\t * # When comparing priorities of mappings, higher value\n+\t * indicates higher priority.\n+\t * For example, a value of 0-3 is returned where 0 is being\n+\t * the lowest priority and 3 is being the highest priority.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint8_t\ttunnel_pri2cos_map_pri;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * This value controls the priority setting of IP DSCP to CoS\n+\t * mapping based on inner IP header of tunneled packets or\n+\t * IP header of non-tunneled packets.\n+\t *\n+\t * # Each XXX_pri variable shall have a unique priority value\n+\t * when it is being specified.\n+\t * # When comparing priorities of mappings, higher value\n+\t * indicates higher priority.\n+\t * For example, a value of 0-3 is returned where 0 is being\n+\t * the lowest priority and 3 is being the highest priority.\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint8_t\tdscp2pri_map_pri;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * This is a 16-bit bit mask that is used to request a\n+\t * specific configuration of time stamp capture of PTP messages\n+\t * on the receive side of this port.\n+\t * This field shall be ignored if the ptp_rx_ts_capture_enable\n+\t * flag is not set in this command.\n+\t * Otherwise, if bit 'i' is set, then the HWRM is being\n+\t * requested to configure the receive side of the port to\n+\t * capture the time stamp of every received PTP message\n+\t * with messageType field value set to i.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Port ID of port that is being queried. */\n-\tuint16_t\tport_id;\n+\tuint16_t\trx_ts_capture_ptp_msg_type;\n \t/*\n-\t * The size of TX port extended\n-\t * statistics block in bytes.\n+\t * This is a 16-bit bit mask that is used to request a\n+\t * specific configuration of time stamp capture of PTP messages\n+\t * on the transmit side of this port.\n+\t * This field shall be ignored if the ptp_tx_ts_capture_enable\n+\t * flag is not set in this command.\n+\t * Otherwise, if bit 'i' is set, then the HWRM is being\n+\t * requested to configure the transmit sied of the port to\n+\t * capture the time stamp of every transmitted PTP message\n+\t * with messageType field value set to i.\n \t */\n-\tuint16_t\ttx_stat_size;\n+\tuint16_t\ttx_ts_capture_ptp_msg_type;\n+\t/* Configuration of CoS fields. */\n+\tuint8_t\tcos_field_cfg;\n+\t/* Reserved */\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_RSVD1 \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * The size of RX port extended\n-\t * statistics block in bytes\n+\t * This field is used to specify selection of VLAN PRI value\n+\t * based on whether one or two VLAN Tags are present in\n+\t * the inner packet headers of tunneled packets or\n+\t * non-tunneled packets.\n+\t * This field is valid only if inner VLAN PRI to CoS mapping\n+\t * is enabled.\n+\t * If VLAN PRI to CoS mapping is not enabled, then this\n+\t * field shall be ignored.\n \t */\n-\tuint16_t\trx_stat_size;\n-\tuint8_t\tunused_0[2];\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \\\n+\t\tUINT32_C(0x6)\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \\\n+\t\t1\n \t/*\n-\t * This is the host address where\n-\t * Tx port statistics will be stored\n+\t * Select inner VLAN PRI when 1 or 2 VLAN Tags are\n+\t * present in the inner packet headers\n \t */\n-\tuint64_t\ttx_stat_host_addr;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \\\n+\t\t(UINT32_C(0x0) << 1)\n \t/*\n-\t * This is the host address where\n-\t * Rx port statistics will be stored\n+\t * Select outer VLAN Tag PRI when 2 VLAN Tags are\n+\t * present in the inner packet headers.\n+\t * No VLAN PRI shall be selected for this configuration\n+\t * if only one VLAN Tag is present in the inner\n+\t * packet headers.\n \t */\n-\tuint64_t\trx_stat_host_addr;\n-} __attribute__((packed));\n-\n-/* hwrm_port_qstats_ext_output (size:128b/16B) */\n-struct hwrm_port_qstats_ext_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* The size of TX port statistics block in bytes. */\n-\tuint16_t\ttx_stat_size;\n-\t/* The size of RX port statistics block in bytes. */\n-\tuint16_t\trx_stat_size;\n-\tuint8_t\tunused_0[3];\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \\\n+\t\t(UINT32_C(0x1) << 1)\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * Select outermost VLAN PRI when 1 or 2 VLAN Tags\n+\t * are present in the inner packet headers\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/*************************\n- * hwrm_port_lpbk_qstats *\n- *************************/\n-\n-\n-/* hwrm_port_lpbk_qstats_input (size:128b/16B) */\n-struct hwrm_port_lpbk_qstats_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \\\n+\t\t(UINT32_C(0x2) << 1)\n+\t/* Unspecified */\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \\\n+\t\t(UINT32_C(0x3) << 1)\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \\\n+\t\tHWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * This field is used to specify selection of tunnel VLAN\n+\t * PRI value based on whether one or two VLAN Tags are\n+\t * present in tunnel headers.\n+\t * This field is valid only if tunnel VLAN PRI to CoS mapping\n+\t * is enabled.\n+\t * If tunnel VLAN PRI to CoS mapping is not enabled, then this\n+\t * field shall be ignored.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \\\n+\t\tUINT32_C(0x18)\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \\\n+\t\t3\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Select inner VLAN PRI when 1 or 2 VLAN Tags are\n+\t * present in the tunnel packet headers\n \t */\n-\tuint16_t\tseq_id;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \\\n+\t\t(UINT32_C(0x0) << 3)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * Select outer VLAN Tag PRI when 2 VLAN Tags are\n+\t * present in the tunnel packet headers.\n+\t * No tunnel VLAN PRI shall be selected for this\n+\t * configuration if only one VLAN Tag is present in\n+\t * the tunnel packet headers.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \\\n+\t\t(UINT32_C(0x1) << 3)\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Select outermost VLAN PRI when 1 or 2 VLAN Tags\n+\t * are present in the tunnel packet headers\n \t */\n-\tuint64_t\tresp_addr;\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \\\n+\t\t(UINT32_C(0x2) << 3)\n+\t/* Unspecified */\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \\\n+\t\t(UINT32_C(0x3) << 3)\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \\\n+\t\tHWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED\n+\t/*\n+\t * This field shall be used to provide default CoS value\n+\t * that has been configured on this port.\n+\t * This field is valid only if default CoS mapping\n+\t * is enabled.\n+\t * If default CoS mapping is not enabled, then this\n+\t * field shall be ignored.\n+\t */\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \\\n+\t\tUINT32_C(0xe0)\n+\t#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \\\n+\t\t5\n+\tuint8_t\tunused_0[3];\n } __attribute__((packed));\n \n-/* hwrm_port_lpbk_qstats_output (size:768b/96B) */\n-struct hwrm_port_lpbk_qstats_output {\n+/* hwrm_port_mac_cfg_output (size:128b/16B) */\n+struct hwrm_port_mac_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -12120,87 +12330,40 @@ struct hwrm_port_lpbk_qstats_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Number of transmitted unicast frames */\n-\tuint64_t\tlpbk_ucast_frames;\n-\t/* Number of transmitted multicast frames */\n-\tuint64_t\tlpbk_mcast_frames;\n-\t/* Number of transmitted broadcast frames */\n-\tuint64_t\tlpbk_bcast_frames;\n-\t/* Number of transmitted bytes for unicast traffic */\n-\tuint64_t\tlpbk_ucast_bytes;\n-\t/* Number of transmitted bytes for multicast traffic */\n-\tuint64_t\tlpbk_mcast_bytes;\n-\t/* Number of transmitted bytes for broadcast traffic */\n-\tuint64_t\tlpbk_bcast_bytes;\n-\t/* Total Tx Drops for loopback traffic reported by STATS block */\n-\tuint64_t\ttx_stat_discard;\n-\t/* Total Tx Error Drops for loopback traffic reported by STATS block */\n-\tuint64_t\ttx_stat_error;\n-\t/* Total Rx Drops for loopback traffic reported by STATS block */\n-\tuint64_t\trx_stat_discard;\n-\t/* Total Rx Error Drops for loopback traffic reported by STATS block */\n-\tuint64_t\trx_stat_error;\n-\tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/***********************\n- * hwrm_port_clr_stats *\n- ***********************/\n-\n-\n-/* hwrm_port_clr_stats_input (size:192b/24B) */\n-struct hwrm_port_clr_stats_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * This is the configured maximum length of Ethernet packet\n+\t * payload that is allowed to be received on the port.\n+\t * This value does not include the number of bytes used by\n+\t * Ethernet header and trailer (CRC).\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint16_t\tmru;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * This is the configured maximum length of Ethernet packet\n+\t * payload that is allowed to be transmitted on the port.\n+\t * This value does not include the number of bytes used by\n+\t * Ethernet header and trailer (CRC).\n \t */\n-\tuint16_t\tseq_id;\n+\tuint16_t\tmtu;\n+\t/* Current configuration of the IPG value. */\n+\tuint8_t\tipg;\n+\t/* Current value of the loopback value. */\n+\tuint8_t\tlpbk;\n+\t/* No loopback is selected. Normal operation. */\n+\t#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_NONE UINT32_C(0x0)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * The HW will be configured with local loopback such that\n+\t * host data is sent back to the host without modification.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * The HW will be configured with remote loopback such that\n+\t * port logic will send packets back out the transmitter that\n+\t * are received.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Port ID of port that is being queried. */\n-\tuint16_t\tport_id;\n-\tuint8_t\tunused_0[6];\n-} __attribute__((packed));\n-\n-/* hwrm_port_clr_stats_output (size:128b/16B) */\n-struct hwrm_port_clr_stats_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)\n+\t#define HWRM_PORT_MAC_CFG_OUTPUT_LPBK_LAST \\\n+\t\tHWRM_PORT_MAC_CFG_OUTPUT_LPBK_REMOTE\n+\tuint8_t\tunused_0;\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -12211,13 +12374,13 @@ struct hwrm_port_clr_stats_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/****************************\n- * hwrm_port_lpbk_clr_stats *\n- ****************************/\n+/**********************\n+ * hwrm_port_mac_qcfg *\n+ **********************/\n \n \n-/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */\n-struct hwrm_port_lpbk_clr_stats_input {\n+/* hwrm_port_mac_qcfg_input (size:192b/24B) */\n+struct hwrm_port_mac_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -12245,10 +12408,13 @@ struct hwrm_port_lpbk_clr_stats_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* Port ID of port that is to be configured. */\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */\n-struct hwrm_port_lpbk_clr_stats_output {\n+/* hwrm_port_mac_qcfg_output (size:192b/24B) */\n+struct hwrm_port_mac_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -12257,84 +12423,236 @@ struct hwrm_port_lpbk_clr_stats_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This is the configured maximum length of Ethernet packet\n+\t * payload that is allowed to be received on the port.\n+\t * This value does not include the number of bytes used by the\n+\t * Ethernet header and trailer (CRC).\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**********************\n- * hwrm_port_ts_query *\n- **********************/\n-\n-\n-/* hwrm_port_ts_query_input (size:192b/24B) */\n-struct hwrm_port_ts_query_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint16_t\tmru;\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * This is the configured maximum length of Ethernet packet\n+\t * payload that is allowed to be transmitted on the port.\n+\t * This value does not include the number of bytes used by the\n+\t * Ethernet header and trailer (CRC).\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint16_t\tmtu;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * The minimum IPG that will\n+\t * be sent between packets by this port.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint8_t\tipg;\n+\t/* The loopback setting for the MAC. */\n+\tuint8_t\tlpbk;\n+\t/* No loopback is selected. Normal operation. */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_NONE UINT32_C(0x0)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * The HW will be configured with local loopback such that\n+\t * host data is sent back to the host without modification.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LOCAL UINT32_C(0x1)\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * The HW will be configured with remote loopback such that\n+\t * port logic will send packets back out the transmitter that\n+\t * are received.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE UINT32_C(0x2)\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_LPBK_LAST \\\n+\t\tHWRM_PORT_MAC_QCFG_OUTPUT_LPBK_REMOTE\n \t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n+\t * Priority setting for VLAN PRI to CoS mapping.\n+\t * # Each XXX_pri variable shall have a unique priority value\n+\t * when it is being used.\n+\t * # When comparing priorities of mappings, higher value\n+\t * indicates higher priority.\n+\t * For example, a value of 0-3 is returned where 0 is being\n+\t * the lowest priority and 3 is being the highest priority.\n+\t * # If the correspoding CoS mapping is not enabled, then this\n+\t * field should be ignored.\n+\t * # This value indicates the normalized priority value retained\n+\t * in the HWRM.\n \t */\n-\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t#define HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX\n-\t/* Port ID of port that is being queried. */\n-\tuint16_t\tport_id;\n-\tuint8_t\tunused_0[2];\n-} __attribute__((packed));\n-\n-/* hwrm_port_ts_query_output (size:192b/24B) */\n-struct hwrm_port_ts_query_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* Timestamp value of PTP message captured. */\n-\tuint64_t\tptp_msg_ts;\n-\t/* Sequence ID of the PTP message captured. */\n-\tuint16_t\tptp_msg_seqid;\n-\tuint8_t\tunused_0[5];\n+\tuint8_t\tvlan_pri2cos_map_pri;\n+\t/*\n+\t * In this field, a number of CoS mappings related flags\n+\t * are used to indicate configured CoS mappings.\n+\t */\n+\tuint8_t\tflags;\n+\t/*\n+\t * When this bit is set to '1', the inner VLAN PRI to CoS mapping\n+\t * is enabled.\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_VLAN_PRI2COS_ENABLE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is set to '1', tunnel VLAN PRI field to\n+\t * CoS mapping is enabled.\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_TUNNEL_PRI2COS_ENABLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is set to '1', the IP DSCP to CoS mapping is\n+\t * enabled.\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_IP_DSCP2COS_ENABLE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', the Out-Of-Box WoL is enabled on this\n+\t * port.\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_OOB_WOL_ENABLE \\\n+\t\tUINT32_C(0x8)\n+\t/* When this bit is '1', PTP is enabled for RX on this port. */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE \\\n+\t\tUINT32_C(0x10)\n+\t/* When this bit is '1', PTP is enabled for TX on this port. */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * Priority setting for tunnel VLAN PRI to CoS mapping.\n+\t * # Each XXX_pri variable shall have a unique priority value\n+\t * when it is being used.\n+\t * # When comparing priorities of mappings, higher value\n+\t * indicates higher priority.\n+\t * For example, a value of 0-3 is returned where 0 is being\n+\t * the lowest priority and 3 is being the highest priority.\n+\t * # If the correspoding CoS mapping is not enabled, then this\n+\t * field should be ignored.\n+\t * # This value indicates the normalized priority value retained\n+\t * in the HWRM.\n+\t */\n+\tuint8_t\ttunnel_pri2cos_map_pri;\n+\t/*\n+\t * Priority setting for DSCP to PRI mapping.\n+\t * # Each XXX_pri variable shall have a unique priority value\n+\t * when it is being used.\n+\t * # When comparing priorities of mappings, higher value\n+\t * indicates higher priority.\n+\t * For example, a value of 0-3 is returned where 0 is being\n+\t * the lowest priority and 3 is being the highest priority.\n+\t * # If the correspoding CoS mapping is not enabled, then this\n+\t * field should be ignored.\n+\t * # This value indicates the normalized priority value retained\n+\t * in the HWRM.\n+\t */\n+\tuint8_t\tdscp2pri_map_pri;\n+\t/*\n+\t * This is a 16-bit bit mask that represents the\n+\t * current configuration of time stamp capture of PTP messages\n+\t * on the receive side of this port.\n+\t * If bit 'i' is set, then the receive side of the port\n+\t * is configured to capture the time stamp of every\n+\t * received PTP message with messageType field value set\n+\t * to i.\n+\t * If all bits are set to 0 (i.e. field value set 0),\n+\t * then the receive side of the port is not configured\n+\t * to capture timestamp for PTP messages.\n+\t * If all bits are set to 1, then the receive side of the\n+\t * port is configured to capture timestamp for all PTP\n+\t * messages.\n+\t */\n+\tuint16_t\trx_ts_capture_ptp_msg_type;\n+\t/*\n+\t * This is a 16-bit bit mask that represents the\n+\t * current configuration of time stamp capture of PTP messages\n+\t * on the transmit side of this port.\n+\t * If bit 'i' is set, then the transmit side of the port\n+\t * is configured to capture the time stamp of every\n+\t * received PTP message with messageType field value set\n+\t * to i.\n+\t * If all bits are set to 0 (i.e. field value set 0),\n+\t * then the transmit side of the port is not configured\n+\t * to capture timestamp for PTP messages.\n+\t * If all bits are set to 1, then the transmit side of the\n+\t * port is configured to capture timestamp for all PTP\n+\t * messages.\n+\t */\n+\tuint16_t\ttx_ts_capture_ptp_msg_type;\n+\t/* Configuration of CoS fields. */\n+\tuint8_t\tcos_field_cfg;\n+\t/* Reserved */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_RSVD \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This field is used for selecting VLAN PRI value\n+\t * based on whether one or two VLAN Tags are present in\n+\t * the inner packet headers of tunneled packets or\n+\t * non-tunneled packets.\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_MASK \\\n+\t\tUINT32_C(0x6)\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_SFT \\\n+\t\t1\n+\t/*\n+\t * Select inner VLAN PRI when 1 or 2 VLAN Tags are\n+\t * present in the inner packet headers\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/*\n+\t * Select outer VLAN Tag PRI when 2 VLAN Tags are\n+\t * present in the inner packet headers.\n+\t * No VLAN PRI is selected for this configuration\n+\t * if only one VLAN Tag is present in the inner\n+\t * packet headers.\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t/*\n+\t * Select outermost VLAN PRI when 1 or 2 VLAN Tags\n+\t * are present in the inner packet headers\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST \\\n+\t\t(UINT32_C(0x2) << 1)\n+\t/* Unspecified */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED \\\n+\t\t(UINT32_C(0x3) << 1)\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_LAST \\\n+\t\tHWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED\n+\t/*\n+\t * This field is used for selecting tunnel VLAN PRI value\n+\t * based on whether one or two VLAN Tags are present in\n+\t * the tunnel headers of tunneled packets. This selection\n+\t * does not apply to non-tunneled packets.\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK \\\n+\t\tUINT32_C(0x18)\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT \\\n+\t\t3\n+\t/*\n+\t * Select inner VLAN PRI when 1 or 2 VLAN Tags are\n+\t * present in the tunnel packet headers\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST \\\n+\t\t(UINT32_C(0x0) << 3)\n+\t/*\n+\t * Select outer VLAN Tag PRI when 2 VLAN Tags are\n+\t * present in the tunnel packet headers.\n+\t * No VLAN PRI is selected for this configuration\n+\t * if only one VLAN Tag is present in the tunnel\n+\t * packet headers.\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER \\\n+\t\t(UINT32_C(0x1) << 3)\n+\t/*\n+\t * Select outermost VLAN PRI when 1 or 2 VLAN Tags\n+\t * are present in the tunnel packet headers\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST \\\n+\t\t(UINT32_C(0x2) << 3)\n+\t/* Unspecified */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED \\\n+\t\t(UINT32_C(0x3) << 3)\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST \\\n+\t\tHWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED\n+\t/*\n+\t * This field is used to provide default CoS value that\n+\t * has been configured on this port.\n+\t */\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_MASK \\\n+\t\tUINT32_C(0xe0)\n+\t#define HWRM_PORT_MAC_QCFG_OUTPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \\\n+\t\t5\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -12345,13 +12663,13 @@ struct hwrm_port_ts_query_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_port_phy_qcaps *\n- ***********************/\n+/**************************\n+ * hwrm_port_mac_ptp_qcfg *\n+ **************************/\n \n \n-/* hwrm_port_phy_qcaps_input (size:192b/24B) */\n-struct hwrm_port_phy_qcaps_input {\n+/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */\n+struct hwrm_port_mac_ptp_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -12384,8 +12702,8 @@ struct hwrm_port_phy_qcaps_input {\n \tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_port_phy_qcaps_output (size:192b/24B) */\n-struct hwrm_port_phy_qcaps_output {\n+/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */\n+struct hwrm_port_mac_ptp_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -12394,193 +12712,55 @@ struct hwrm_port_phy_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* PHY capability flags */\n+\t/*\n+\t * In this field, a number of PTP related flags\n+\t * are used to indicate configured PTP capabilities.\n+\t */\n \tuint8_t\tflags;\n \t/*\n-\t * If set to 1, then this field indicates that the\n-\t * link is capable of supporting EEE.\n+\t * When this bit is set to '1', the PTP related registers are\n+\t * directly accessible by the host.\n \t */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \\\n+\t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * If set to 1, then this field indicates that the\n-\t * PHY is capable of supporting external loopback.\n+\t * When this bit is set to '1', the PTP information is accessible\n+\t * via HWRM commands.\n \t */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \\\n+\t#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \\\n \t\tUINT32_C(0x2)\n-\t/*\n-\t * Reserved field. The HWRM shall set this field to 0.\n-\t * An HWRM client shall ignore this field.\n-\t */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \\\n-\t\tUINT32_C(0xfc)\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2\n-\t/* Number of front panel ports for this device. */\n-\tuint8_t\tport_cnt;\n-\t/* Not supported or unknown */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)\n-\t/* single port device */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)\n-\t/* 2-port device */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)\n-\t/* 3-port device */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)\n-\t/* 4-port device */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \\\n-\t\tHWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4\n-\t/*\n-\t * This is a bit mask to indicate what speeds are supported\n-\t * as forced speeds on this link.\n-\t * For each speed that can be forced on this link, the\n-\t * corresponding mask bit shall be set to '1'.\n-\t */\n-\tuint16_t\tsupported_speeds_force_mode;\n-\t/* 100Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \\\n-\t\tUINT32_C(0x1)\n-\t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \\\n-\t\tUINT32_C(0x2)\n-\t/* 1Gb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \\\n-\t\tUINT32_C(0x4)\n-\t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \\\n-\t\tUINT32_C(0x8)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \\\n-\t\tUINT32_C(0x10)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \\\n-\t\tUINT32_C(0x20)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \\\n-\t\tUINT32_C(0x40)\n-\t/* 20Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \\\n-\t\tUINT32_C(0x80)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \\\n-\t\tUINT32_C(0x100)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \\\n-\t\tUINT32_C(0x200)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \\\n-\t\tUINT32_C(0x400)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \\\n-\t\tUINT32_C(0x800)\n-\t/* 10Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \\\n-\t\tUINT32_C(0x1000)\n-\t/* 10Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \\\n-\t\tUINT32_C(0x2000)\n-\t/*\n-\t * This is a bit mask to indicate what speeds are supported\n-\t * for autonegotiation on this link.\n-\t * For each speed that can be autonegotiated on this link, the\n-\t * corresponding mask bit shall be set to '1'.\n-\t */\n-\tuint16_t\tsupported_speeds_auto_mode;\n-\t/* 100Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \\\n-\t\tUINT32_C(0x1)\n-\t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \\\n-\t\tUINT32_C(0x2)\n-\t/* 1Gb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \\\n-\t\tUINT32_C(0x4)\n-\t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \\\n-\t\tUINT32_C(0x8)\n-\t/* 2Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \\\n-\t\tUINT32_C(0x10)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \\\n-\t\tUINT32_C(0x20)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \\\n-\t\tUINT32_C(0x40)\n-\t/* 20Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \\\n-\t\tUINT32_C(0x80)\n-\t/* 25Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \\\n-\t\tUINT32_C(0x100)\n-\t/* 40Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \\\n-\t\tUINT32_C(0x200)\n-\t/* 50Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \\\n-\t\tUINT32_C(0x400)\n-\t/* 100Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \\\n-\t\tUINT32_C(0x800)\n-\t/* 10Mb link speed (Half-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \\\n-\t\tUINT32_C(0x1000)\n-\t/* 10Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \\\n-\t\tUINT32_C(0x2000)\n-\t/*\n-\t * This is a bit mask to indicate what speeds are supported\n-\t * for EEE on this link.\n-\t * For each speed that can be autonegotiated when EEE is enabled\n-\t * on this link, the corresponding mask bit shall be set to '1'.\n-\t * This field is only valid when the eee_suppotred is set to '1'.\n-\t */\n-\tuint16_t\tsupported_speeds_eee_mode;\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \\\n-\t\tUINT32_C(0x1)\n-\t/* 100Mb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \\\n-\t\tUINT32_C(0x2)\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \\\n-\t\tUINT32_C(0x4)\n-\t/* 1Gb link speed (Full-duplex) */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \\\n-\t\tUINT32_C(0x8)\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \\\n-\t\tUINT32_C(0x10)\n-\t/* Reserved */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \\\n-\t\tUINT32_C(0x20)\n-\t/* 10Gb link speed */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \\\n-\t\tUINT32_C(0x40)\n-\tuint32_t\ttx_lpi_timer_low;\n-\t/*\n-\t * The lowest value of TX LPI timer that can be set on this link\n-\t * when EEE is enabled. This value is in microseconds.\n-\t * This field is valid only when_eee_supported is set to '1'.\n-\t */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \\\n-\t\tUINT32_C(0xffffff)\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0\n-\t/*\n-\t * Reserved field. The HWRM shall set this field to 0.\n-\t * An HWRM client shall ignore this field.\n-\t */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \\\n-\t\tUINT32_C(0xff000000)\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24\n-\tuint32_t\tvalid_tx_lpi_timer_high;\n-\t/*\n-\t * The highest value of TX LPI timer that can be set on this link\n-\t * when EEE is enabled. This value is in microseconds.\n-\t * This field is valid only when_eee_supported is set to '1'.\n-\t */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \\\n-\t\tUINT32_C(0xffffff)\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0\n+\tuint8_t\tunused_0[3];\n+\t/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */\n+\tuint32_t\trx_ts_reg_off_lower;\n+\t/* Offset of the PTP register for the upper 32 bits of timestamp for RX. */\n+\tuint32_t\trx_ts_reg_off_upper;\n+\t/* Offset of the PTP register for the sequence ID for RX. */\n+\tuint32_t\trx_ts_reg_off_seq_id;\n+\t/* Offset of the first PTP source ID for RX. */\n+\tuint32_t\trx_ts_reg_off_src_id_0;\n+\t/* Offset of the second PTP source ID for RX. */\n+\tuint32_t\trx_ts_reg_off_src_id_1;\n+\t/* Offset of the third PTP source ID for RX. */\n+\tuint32_t\trx_ts_reg_off_src_id_2;\n+\t/* Offset of the domain ID for RX. */\n+\tuint32_t\trx_ts_reg_off_domain_id;\n+\t/* Offset of the PTP FIFO register for RX. */\n+\tuint32_t\trx_ts_reg_off_fifo;\n+\t/* Offset of the PTP advance FIFO register for RX. */\n+\tuint32_t\trx_ts_reg_off_fifo_adv;\n+\t/* PTP timestamp granularity for RX. */\n+\tuint32_t\trx_ts_reg_off_granularity;\n+\t/* Offset of the PTP register for the lower 32 bits of timestamp for TX. */\n+\tuint32_t\ttx_ts_reg_off_lower;\n+\t/* Offset of the PTP register for the upper 32 bits of timestamp for TX. */\n+\tuint32_t\ttx_ts_reg_off_upper;\n+\t/* Offset of the PTP register for the sequence ID for TX. */\n+\tuint32_t\ttx_ts_reg_off_seq_id;\n+\t/* Offset of the PTP FIFO register for TX. */\n+\tuint32_t\ttx_ts_reg_off_fifo;\n+\t/* PTP timestamp granularity for TX. */\n+\tuint32_t\ttx_ts_reg_off_granularity;\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -12588,581 +12768,416 @@ struct hwrm_port_phy_qcaps_output {\n \t * When writing a command completion or response to an internal processor,\n \t * the order of writes has to be such that this field is written last.\n \t */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \\\n-\t\tUINT32_C(0xff000000)\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24\n+\tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***************************\n- * hwrm_port_phy_i2c_write *\n- ***************************/\n-\n-\n-/* hwrm_port_phy_i2c_write_input (size:832b/104B) */\n-struct hwrm_port_phy_i2c_write_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+/* Port Tx Statistics Formats */\n+/* tx_port_stats (size:3264b/408B) */\n+struct tx_port_stats {\n+\t/* Total Number of 64 Bytes frames transmitted */\n+\tuint64_t\ttx_64b_frames;\n+\t/* Total Number of 65-127 Bytes frames transmitted */\n+\tuint64_t\ttx_65b_127b_frames;\n+\t/* Total Number of 128-255 Bytes frames transmitted */\n+\tuint64_t\ttx_128b_255b_frames;\n+\t/* Total Number of 256-511 Bytes frames transmitted */\n+\tuint64_t\ttx_256b_511b_frames;\n+\t/* Total Number of 512-1023 Bytes frames transmitted */\n+\tuint64_t\ttx_512b_1023b_frames;\n+\t/* Total Number of 1024-1518 Bytes frames transmitted */\n+\tuint64_t\ttx_1024b_1518b_frames;\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * Total Number of each good VLAN (exludes FCS errors)\n+\t * frame transmitted which is 1519 to 1522 bytes in length\n+\t * inclusive (excluding framing bits but including FCS bytes).\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint64_t\ttx_good_vlan_frames;\n+\t/* Total Number of 1519-2047 Bytes frames transmitted */\n+\tuint64_t\ttx_1519b_2047b_frames;\n+\t/* Total Number of 2048-4095 Bytes frames transmitted */\n+\tuint64_t\ttx_2048b_4095b_frames;\n+\t/* Total Number of 4096-9216 Bytes frames transmitted */\n+\tuint64_t\ttx_4096b_9216b_frames;\n+\t/* Total Number of 9217-16383 Bytes frames transmitted */\n+\tuint64_t\ttx_9217b_16383b_frames;\n+\t/* Total Number of good frames transmitted */\n+\tuint64_t\ttx_good_frames;\n+\t/* Total Number of frames transmitted */\n+\tuint64_t\ttx_total_frames;\n+\t/* Total number of unicast frames transmitted */\n+\tuint64_t\ttx_ucast_frames;\n+\t/* Total number of multicast frames transmitted */\n+\tuint64_t\ttx_mcast_frames;\n+\t/* Total number of broadcast frames transmitted */\n+\tuint64_t\ttx_bcast_frames;\n+\t/* Total number of PAUSE control frames transmitted */\n+\tuint64_t\ttx_pause_frames;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Total number of PFC/per-priority PAUSE\n+\t * control frames transmitted\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\tuint32_t\tenables;\n+\tuint64_t\ttx_pfc_frames;\n+\t/* Total number of jabber frames transmitted */\n+\tuint64_t\ttx_jabber_frames;\n+\t/* Total number of frames transmitted with FCS error */\n+\tuint64_t\ttx_fcs_err_frames;\n+\t/* Total number of control frames transmitted */\n+\tuint64_t\ttx_control_frames;\n+\t/* Total number of over-sized frames transmitted */\n+\tuint64_t\ttx_oversz_frames;\n+\t/* Total number of frames with single deferral */\n+\tuint64_t\ttx_single_dfrl_frames;\n+\t/* Total number of frames with multiple deferrals */\n+\tuint64_t\ttx_multi_dfrl_frames;\n+\t/* Total number of frames with single collision */\n+\tuint64_t\ttx_single_coll_frames;\n+\t/* Total number of frames with multiple collisions */\n+\tuint64_t\ttx_multi_coll_frames;\n+\t/* Total number of frames with late collisions */\n+\tuint64_t\ttx_late_coll_frames;\n+\t/* Total number of frames with excessive collisions */\n+\tuint64_t\ttx_excessive_coll_frames;\n+\t/* Total number of fragmented frames transmitted */\n+\tuint64_t\ttx_frag_frames;\n+\t/* Total number of transmit errors */\n+\tuint64_t\ttx_err;\n+\t/* Total number of single VLAN tagged frames transmitted */\n+\tuint64_t\ttx_tagged_frames;\n+\t/* Total number of double VLAN tagged frames transmitted */\n+\tuint64_t\ttx_dbl_tagged_frames;\n+\t/* Total number of runt frames transmitted */\n+\tuint64_t\ttx_runt_frames;\n+\t/* Total number of TX FIFO under runs */\n+\tuint64_t\ttx_fifo_underruns;\n \t/*\n-\t * This bit must be '1' for the page_offset field to be\n-\t * configured.\n+\t * Total number of PFC frames with PFC enabled bit for\n+\t * Pri 0 transmitted\n \t */\n-\t#define HWRM_PORT_PHY_I2C_WRITE_INPUT_ENABLES_PAGE_OFFSET \\\n-\t\tUINT32_C(0x1)\n-\t/* Port ID of port. */\n-\tuint16_t\tport_id;\n-\t/* 8-bit I2C slave address. */\n-\tuint8_t\ti2c_slave_addr;\n-\tuint8_t\tunused_0;\n-\t/* The page number that is being accessed over I2C. */\n-\tuint16_t\tpage_number;\n-\t/* Offset within the page that is being accessed over I2C. */\n-\tuint16_t\tpage_offset;\n+\tuint64_t\ttx_pfc_ena_frames_pri0;\n \t/*\n-\t * Length of data to write, in bytes starting at the offset\n-\t * specified above. If the offset is not specified, then\n-\t * the data shall be written from the beginning of the page.\n+\t * Total number of PFC frames with PFC enabled bit for\n+\t * Pri 1 transmitted\n \t */\n-\tuint8_t\tdata_length;\n-\tuint8_t\tunused_1[7];\n-\t/* Up to 64B of data. */\n-\tuint32_t\tdata[16];\n-} __attribute__((packed));\n-\n-/* hwrm_port_phy_i2c_write_output (size:128b/16B) */\n-struct hwrm_port_phy_i2c_write_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint64_t\ttx_pfc_ena_frames_pri1;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * Total number of PFC frames with PFC enabled bit for\n+\t * Pri 2 transmitted\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**************************\n- * hwrm_port_phy_i2c_read *\n- **************************/\n-\n-\n-/* hwrm_port_phy_i2c_read_input (size:320b/40B) */\n-struct hwrm_port_phy_i2c_read_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint64_t\ttx_pfc_ena_frames_pri2;\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * Total number of PFC frames with PFC enabled bit for\n+\t * Pri 3 transmitted\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint64_t\ttx_pfc_ena_frames_pri3;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Total number of PFC frames with PFC enabled bit for\n+\t * Pri 4 transmitted\n \t */\n-\tuint16_t\tseq_id;\n+\tuint64_t\ttx_pfc_ena_frames_pri4;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * Total number of PFC frames with PFC enabled bit for\n+\t * Pri 5 transmitted\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint64_t\ttx_pfc_ena_frames_pri5;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Total number of PFC frames with PFC enabled bit for\n+\t * Pri 6 transmitted\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\tuint32_t\tenables;\n+\tuint64_t\ttx_pfc_ena_frames_pri6;\n \t/*\n-\t * This bit must be '1' for the page_offset field to be\n-\t * configured.\n+\t * Total number of PFC frames with PFC enabled bit for\n+\t * Pri 7 transmitted\n \t */\n-\t#define HWRM_PORT_PHY_I2C_READ_INPUT_ENABLES_PAGE_OFFSET \\\n-\t\tUINT32_C(0x1)\n-\t/* Port ID of port. */\n-\tuint16_t\tport_id;\n-\t/* 8-bit I2C slave address. */\n-\tuint8_t\ti2c_slave_addr;\n-\tuint8_t\tunused_0;\n-\t/* The page number that is being accessed over I2C. */\n-\tuint16_t\tpage_number;\n-\t/* Offset within the page that is being accessed over I2C. */\n-\tuint16_t\tpage_offset;\n+\tuint64_t\ttx_pfc_ena_frames_pri7;\n+\t/* Total number of EEE LPI Events on TX */\n+\tuint64_t\ttx_eee_lpi_events;\n+\t/* EEE LPI Duration Counter on TX */\n+\tuint64_t\ttx_eee_lpi_duration;\n \t/*\n-\t * Length of data to read, in bytes starting at the offset\n-\t * specified above. If the offset is not specified, then\n-\t * the data shall be read from the beginning of the page.\n+\t * Total number of Link Level Flow Control (LLFC) messages\n+\t * transmitted\n \t */\n-\tuint8_t\tdata_length;\n-\tuint8_t\tunused_1[7];\n+\tuint64_t\ttx_llfc_logical_msgs;\n+\t/* Total number of HCFC messages transmitted */\n+\tuint64_t\ttx_hcfc_msgs;\n+\t/* Total number of TX collisions */\n+\tuint64_t\ttx_total_collisions;\n+\t/* Total number of transmitted bytes */\n+\tuint64_t\ttx_bytes;\n+\t/* Total number of end-to-end HOL frames */\n+\tuint64_t\ttx_xthol_frames;\n+\t/* Total Tx Drops per Port reported by STATS block */\n+\tuint64_t\ttx_stat_discard;\n+\t/* Total Tx Error Drops per Port reported by STATS block */\n+\tuint64_t\ttx_stat_error;\n } __attribute__((packed));\n \n-/* hwrm_port_phy_i2c_read_output (size:640b/80B) */\n-struct hwrm_port_phy_i2c_read_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* Up to 64B of data. */\n-\tuint32_t\tdata[16];\n-\tuint8_t\tunused_0[7];\n+/* Port Rx Statistics Formats */\n+/* rx_port_stats (size:4224b/528B) */\n+struct rx_port_stats {\n+\t/* Total Number of 64 Bytes frames received */\n+\tuint64_t\trx_64b_frames;\n+\t/* Total Number of 65-127 Bytes frames received */\n+\tuint64_t\trx_65b_127b_frames;\n+\t/* Total Number of 128-255 Bytes frames received */\n+\tuint64_t\trx_128b_255b_frames;\n+\t/* Total Number of 256-511 Bytes frames received */\n+\tuint64_t\trx_256b_511b_frames;\n+\t/* Total Number of 512-1023 Bytes frames received */\n+\tuint64_t\trx_512b_1023b_frames;\n+\t/* Total Number of 1024-1518 Bytes frames received */\n+\tuint64_t\trx_1024b_1518b_frames;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * Total Number of each good VLAN (exludes FCS errors)\n+\t * frame received which is 1519 to 1522 bytes in length\n+\t * inclusive (excluding framing bits but including FCS bytes).\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/*********************\n- * hwrm_port_led_cfg *\n- *********************/\n-\n-\n-/* hwrm_port_led_cfg_input (size:512b/64B) */\n-struct hwrm_port_led_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint64_t\trx_good_vlan_frames;\n+\t/* Total Number of 1519-2047 Bytes frames received */\n+\tuint64_t\trx_1519b_2047b_frames;\n+\t/* Total Number of 2048-4095 Bytes frames received */\n+\tuint64_t\trx_2048b_4095b_frames;\n+\t/* Total Number of 4096-9216 Bytes frames received */\n+\tuint64_t\trx_4096b_9216b_frames;\n+\t/* Total Number of 9217-16383 Bytes frames received */\n+\tuint64_t\trx_9217b_16383b_frames;\n+\t/* Total number of frames received */\n+\tuint64_t\trx_total_frames;\n+\t/* Total number of unicast frames received */\n+\tuint64_t\trx_ucast_frames;\n+\t/* Total number of multicast frames received */\n+\tuint64_t\trx_mcast_frames;\n+\t/* Total number of broadcast frames received */\n+\tuint64_t\trx_bcast_frames;\n+\t/* Total number of received frames with FCS error */\n+\tuint64_t\trx_fcs_err_frames;\n+\t/* Total number of control frames received */\n+\tuint64_t\trx_ctrl_frames;\n+\t/* Total number of PAUSE frames received */\n+\tuint64_t\trx_pause_frames;\n+\t/* Total number of PFC frames received */\n+\tuint64_t\trx_pfc_frames;\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * Total number of frames received with an unsupported\n+\t * opcode\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint64_t\trx_unsupported_opcode_frames;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Total number of frames received with an unsupported\n+\t * DA for pause and PFC\n \t */\n-\tuint16_t\tseq_id;\n+\tuint64_t\trx_unsupported_da_pausepfc_frames;\n+\t/* Total number of frames received with an unsupported SA */\n+\tuint64_t\trx_wrong_sa_frames;\n+\t/* Total number of received packets with alignment error */\n+\tuint64_t\trx_align_err_frames;\n+\t/* Total number of received frames with out-of-range length */\n+\tuint64_t\trx_oor_len_frames;\n+\t/* Total number of received frames with error termination */\n+\tuint64_t\trx_code_err_frames;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * Total number of received frames with a false carrier is\n+\t * detected during idle, as defined by RX_ER samples active\n+\t * and RXD is 0xE. The event is reported along with the\n+\t * statistics generated on the next received frame. Only\n+\t * one false carrier condition can be detected and logged\n+\t * between frames.\n+\t *\n+\t * Carrier event, valid for 10M/100M speed modes only.\n \t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n+\tuint64_t\trx_false_carrier_frames;\n+\t/* Total number of over-sized frames received */\n+\tuint64_t\trx_ovrsz_frames;\n+\t/* Total number of jabber packets received */\n+\tuint64_t\trx_jbr_frames;\n+\t/* Total number of received frames with MTU error */\n+\tuint64_t\trx_mtu_err_frames;\n+\t/* Total number of received frames with CRC match */\n+\tuint64_t\trx_match_crc_frames;\n+\t/* Total number of frames received promiscuously */\n+\tuint64_t\trx_promiscuous_frames;\n \t/*\n-\t * This bit must be '1' for the led0_id field to be\n-\t * configured.\n+\t * Total number of received frames with one or two VLAN\n+\t * tags\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \\\n-\t\tUINT32_C(0x1)\n+\tuint64_t\trx_tagged_frames;\n+\t/* Total number of received frames with two VLAN tags */\n+\tuint64_t\trx_double_tagged_frames;\n+\t/* Total number of truncated frames received */\n+\tuint64_t\trx_trunc_frames;\n+\t/* Total number of good frames (without errors) received */\n+\tuint64_t\trx_good_frames;\n \t/*\n-\t * This bit must be '1' for the led0_state field to be\n-\t * configured.\n+\t * Total number of received PFC frames with transition from\n+\t * XON to XOFF on Pri 0\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \\\n-\t\tUINT32_C(0x2)\n+\tuint64_t\trx_pfc_xon2xoff_frames_pri0;\n \t/*\n-\t * This bit must be '1' for the led0_color field to be\n-\t * configured.\n+\t * Total number of received PFC frames with transition from\n+\t * XON to XOFF on Pri 1\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \\\n-\t\tUINT32_C(0x4)\n+\tuint64_t\trx_pfc_xon2xoff_frames_pri1;\n \t/*\n-\t * This bit must be '1' for the led0_blink_on field to be\n-\t * configured.\n+\t * Total number of received PFC frames with transition from\n+\t * XON to XOFF on Pri 2\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \\\n-\t\tUINT32_C(0x8)\n+\tuint64_t\trx_pfc_xon2xoff_frames_pri2;\n \t/*\n-\t * This bit must be '1' for the led0_blink_off field to be\n-\t * configured.\n+\t * Total number of received PFC frames with transition from\n+\t * XON to XOFF on Pri 3\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \\\n-\t\tUINT32_C(0x10)\n+\tuint64_t\trx_pfc_xon2xoff_frames_pri3;\n \t/*\n-\t * This bit must be '1' for the led0_group_id field to be\n-\t * configured.\n+\t * Total number of received PFC frames with transition from\n+\t * XON to XOFF on Pri 4\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \\\n-\t\tUINT32_C(0x20)\n+\tuint64_t\trx_pfc_xon2xoff_frames_pri4;\n \t/*\n-\t * This bit must be '1' for the led1_id field to be\n-\t * configured.\n+\t * Total number of received PFC frames with transition from\n+\t * XON to XOFF on Pri 5\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \\\n-\t\tUINT32_C(0x40)\n+\tuint64_t\trx_pfc_xon2xoff_frames_pri5;\n \t/*\n-\t * This bit must be '1' for the led1_state field to be\n-\t * configured.\n+\t * Total number of received PFC frames with transition from\n+\t * XON to XOFF on Pri 6\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \\\n-\t\tUINT32_C(0x80)\n+\tuint64_t\trx_pfc_xon2xoff_frames_pri6;\n \t/*\n-\t * This bit must be '1' for the led1_color field to be\n-\t * configured.\n+\t * Total number of received PFC frames with transition from\n+\t * XON to XOFF on Pri 7\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \\\n-\t\tUINT32_C(0x100)\n+\tuint64_t\trx_pfc_xon2xoff_frames_pri7;\n \t/*\n-\t * This bit must be '1' for the led1_blink_on field to be\n-\t * configured.\n+\t * Total number of received PFC frames with PFC enabled\n+\t * bit for Pri 0\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \\\n-\t\tUINT32_C(0x200)\n+\tuint64_t\trx_pfc_ena_frames_pri0;\n \t/*\n-\t * This bit must be '1' for the led1_blink_off field to be\n-\t * configured.\n+\t * Total number of received PFC frames with PFC enabled\n+\t * bit for Pri 1\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \\\n-\t\tUINT32_C(0x400)\n+\tuint64_t\trx_pfc_ena_frames_pri1;\n \t/*\n-\t * This bit must be '1' for the led1_group_id field to be\n-\t * configured.\n+\t * Total number of received PFC frames with PFC enabled\n+\t * bit for Pri 2\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \\\n-\t\tUINT32_C(0x800)\n+\tuint64_t\trx_pfc_ena_frames_pri2;\n \t/*\n-\t * This bit must be '1' for the led2_id field to be\n-\t * configured.\n+\t * Total number of received PFC frames with PFC enabled\n+\t * bit for Pri 3\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \\\n-\t\tUINT32_C(0x1000)\n+\tuint64_t\trx_pfc_ena_frames_pri3;\n \t/*\n-\t * This bit must be '1' for the led2_state field to be\n-\t * configured.\n+\t * Total number of received PFC frames with PFC enabled\n+\t * bit for Pri 4\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \\\n-\t\tUINT32_C(0x2000)\n+\tuint64_t\trx_pfc_ena_frames_pri4;\n \t/*\n-\t * This bit must be '1' for the led2_color field to be\n-\t * configured.\n+\t * Total number of received PFC frames with PFC enabled\n+\t * bit for Pri 5\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \\\n-\t\tUINT32_C(0x4000)\n+\tuint64_t\trx_pfc_ena_frames_pri5;\n \t/*\n-\t * This bit must be '1' for the led2_blink_on field to be\n-\t * configured.\n+\t * Total number of received PFC frames with PFC enabled\n+\t * bit for Pri 6\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \\\n-\t\tUINT32_C(0x8000)\n+\tuint64_t\trx_pfc_ena_frames_pri6;\n \t/*\n-\t * This bit must be '1' for the led2_blink_off field to be\n-\t * configured.\n+\t * Total number of received PFC frames with PFC enabled\n+\t * bit for Pri 7\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \\\n-\t\tUINT32_C(0x10000)\n+\tuint64_t\trx_pfc_ena_frames_pri7;\n+\t/* Total Number of frames received with SCH CRC error */\n+\tuint64_t\trx_sch_crc_err_frames;\n+\t/* Total Number of under-sized frames received */\n+\tuint64_t\trx_undrsz_frames;\n+\t/* Total Number of fragmented frames received */\n+\tuint64_t\trx_frag_frames;\n+\t/* Total number of RX EEE LPI Events */\n+\tuint64_t\trx_eee_lpi_events;\n+\t/* EEE LPI Duration Counter on RX */\n+\tuint64_t\trx_eee_lpi_duration;\n \t/*\n-\t * This bit must be '1' for the led2_group_id field to be\n-\t * configured.\n+\t * Total number of physical type Link Level Flow Control\n+\t * (LLFC) messages received\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \\\n-\t\tUINT32_C(0x20000)\n+\tuint64_t\trx_llfc_physical_msgs;\n \t/*\n-\t * This bit must be '1' for the led3_id field to be\n-\t * configured.\n+\t * Total number of logical type Link Level Flow Control\n+\t * (LLFC) messages received\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \\\n-\t\tUINT32_C(0x40000)\n+\tuint64_t\trx_llfc_logical_msgs;\n \t/*\n-\t * This bit must be '1' for the led3_state field to be\n-\t * configured.\n+\t * Total number of logical type Link Level Flow Control\n+\t * (LLFC) messages received with CRC error\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \\\n-\t\tUINT32_C(0x80000)\n+\tuint64_t\trx_llfc_msgs_with_crc_err;\n+\t/* Total number of HCFC messages received */\n+\tuint64_t\trx_hcfc_msgs;\n+\t/* Total number of HCFC messages received with CRC error */\n+\tuint64_t\trx_hcfc_msgs_with_crc_err;\n+\t/* Total number of received bytes */\n+\tuint64_t\trx_bytes;\n+\t/* Total number of bytes received in runt frames */\n+\tuint64_t\trx_runt_bytes;\n+\t/* Total number of runt frames received */\n+\tuint64_t\trx_runt_frames;\n+\t/* Total Rx Discards per Port reported by STATS block */\n+\tuint64_t\trx_stat_discard;\n+\tuint64_t\trx_stat_err;\n+} __attribute__((packed));\n+\n+/********************\n+ * hwrm_port_qstats *\n+ ********************/\n+\n+\n+/* hwrm_port_qstats_input (size:320b/40B) */\n+struct hwrm_port_qstats_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * This bit must be '1' for the led3_color field to be\n-\t * configured.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \\\n-\t\tUINT32_C(0x100000)\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * This bit must be '1' for the led3_blink_on field to be\n-\t * configured.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \\\n-\t\tUINT32_C(0x200000)\n+\tuint16_t\tseq_id;\n \t/*\n-\t * This bit must be '1' for the led3_blink_off field to be\n-\t * configured.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \\\n-\t\tUINT32_C(0x400000)\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * This bit must be '1' for the led3_group_id field to be\n-\t * configured.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \\\n-\t\tUINT32_C(0x800000)\n-\t/* Port ID of port whose LEDs are configured. */\n+\tuint64_t\tresp_addr;\n+\t/* Port ID of port that is being queried. */\n \tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n \t/*\n-\t * The number of LEDs that are being configured.\n-\t * Up to 4 LEDs can be configured with this command.\n+\t * This is the host address where\n+\t * Tx port statistics will be stored\n \t */\n-\tuint8_t\tnum_leds;\n-\t/* Reserved field. */\n-\tuint8_t\trsvd;\n-\t/* An identifier for the LED #0. */\n-\tuint8_t\tled0_id;\n-\t/* The requested state of the LED #0. */\n-\tuint8_t\tled0_state;\n-\t/* Default state of the LED */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)\n-\t/* Off */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)\n-\t/* On */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)\n-\t/* Blink */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)\n-\t/* Blink Alternately */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \\\n-\t\tHWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT\n-\t/* The requested color of LED #0. */\n-\tuint8_t\tled0_color;\n-\t/* Default */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)\n-\t/* Amber */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)\n-\t/* Green */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)\n-\t/* Green or Amber */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \\\n-\t\tHWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER\n-\tuint8_t\tunused_0;\n-\t/*\n-\t * If the LED #0 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED on between cycles.\n-\t */\n-\tuint16_t\tled0_blink_on;\n-\t/*\n-\t * If the LED #0 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED off between cycles.\n-\t */\n-\tuint16_t\tled0_blink_off;\n-\t/*\n-\t * An identifier for the group of LEDs that LED #0 belongs\n-\t * to.\n-\t * If set to 0, then the LED #0 shall not be grouped and\n-\t * shall be treated as an individual resource.\n-\t * For all other non-zero values of this field, LED #0 shall\n-\t * be grouped together with the LEDs with the same group ID\n-\t * value.\n-\t */\n-\tuint8_t\tled0_group_id;\n-\t/* Reserved field. */\n-\tuint8_t\trsvd0;\n-\t/* An identifier for the LED #1. */\n-\tuint8_t\tled1_id;\n-\t/* The requested state of the LED #1. */\n-\tuint8_t\tled1_state;\n-\t/* Default state of the LED */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)\n-\t/* Off */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)\n-\t/* On */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)\n-\t/* Blink */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)\n-\t/* Blink Alternately */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \\\n-\t\tHWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT\n-\t/* The requested color of LED #1. */\n-\tuint8_t\tled1_color;\n-\t/* Default */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)\n-\t/* Amber */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)\n-\t/* Green */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)\n-\t/* Green or Amber */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \\\n-\t\tHWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER\n-\tuint8_t\tunused_1;\n-\t/*\n-\t * If the LED #1 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED on between cycles.\n-\t */\n-\tuint16_t\tled1_blink_on;\n-\t/*\n-\t * If the LED #1 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED off between cycles.\n-\t */\n-\tuint16_t\tled1_blink_off;\n-\t/*\n-\t * An identifier for the group of LEDs that LED #1 belongs\n-\t * to.\n-\t * If set to 0, then the LED #1 shall not be grouped and\n-\t * shall be treated as an individual resource.\n-\t * For all other non-zero values of this field, LED #1 shall\n-\t * be grouped together with the LEDs with the same group ID\n-\t * value.\n-\t */\n-\tuint8_t\tled1_group_id;\n-\t/* Reserved field. */\n-\tuint8_t\trsvd1;\n-\t/* An identifier for the LED #2. */\n-\tuint8_t\tled2_id;\n-\t/* The requested state of the LED #2. */\n-\tuint8_t\tled2_state;\n-\t/* Default state of the LED */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)\n-\t/* Off */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)\n-\t/* On */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)\n-\t/* Blink */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)\n-\t/* Blink Alternately */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \\\n-\t\tHWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT\n-\t/* The requested color of LED #2. */\n-\tuint8_t\tled2_color;\n-\t/* Default */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)\n-\t/* Amber */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)\n-\t/* Green */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)\n-\t/* Green or Amber */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \\\n-\t\tHWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER\n-\tuint8_t\tunused_2;\n-\t/*\n-\t * If the LED #2 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED on between cycles.\n-\t */\n-\tuint16_t\tled2_blink_on;\n-\t/*\n-\t * If the LED #2 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED off between cycles.\n-\t */\n-\tuint16_t\tled2_blink_off;\n-\t/*\n-\t * An identifier for the group of LEDs that LED #2 belongs\n-\t * to.\n-\t * If set to 0, then the LED #2 shall not be grouped and\n-\t * shall be treated as an individual resource.\n-\t * For all other non-zero values of this field, LED #2 shall\n-\t * be grouped together with the LEDs with the same group ID\n-\t * value.\n-\t */\n-\tuint8_t\tled2_group_id;\n-\t/* Reserved field. */\n-\tuint8_t\trsvd2;\n-\t/* An identifier for the LED #3. */\n-\tuint8_t\tled3_id;\n-\t/* The requested state of the LED #3. */\n-\tuint8_t\tled3_state;\n-\t/* Default state of the LED */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)\n-\t/* Off */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)\n-\t/* On */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)\n-\t/* Blink */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)\n-\t/* Blink Alternately */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \\\n-\t\tHWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT\n-\t/* The requested color of LED #3. */\n-\tuint8_t\tled3_color;\n-\t/* Default */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)\n-\t/* Amber */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)\n-\t/* Green */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)\n-\t/* Green or Amber */\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)\n-\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \\\n-\t\tHWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER\n-\tuint8_t\tunused_3;\n-\t/*\n-\t * If the LED #3 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED on between cycles.\n-\t */\n-\tuint16_t\tled3_blink_on;\n-\t/*\n-\t * If the LED #3 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED off between cycles.\n-\t */\n-\tuint16_t\tled3_blink_off;\n+\tuint64_t\ttx_stat_host_addr;\n \t/*\n-\t * An identifier for the group of LEDs that LED #3 belongs\n-\t * to.\n-\t * If set to 0, then the LED #3 shall not be grouped and\n-\t * shall be treated as an individual resource.\n-\t * For all other non-zero values of this field, LED #3 shall\n-\t * be grouped together with the LEDs with the same group ID\n-\t * value.\n+\t * This is the host address where\n+\t * Rx port statistics will be stored\n \t */\n-\tuint8_t\tled3_group_id;\n-\t/* Reserved field. */\n-\tuint8_t\trsvd3;\n+\tuint64_t\trx_stat_host_addr;\n } __attribute__((packed));\n \n-/* hwrm_port_led_cfg_output (size:128b/16B) */\n-struct hwrm_port_led_cfg_output {\n+/* hwrm_port_qstats_output (size:128b/16B) */\n+struct hwrm_port_qstats_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -13171,7 +13186,11 @@ struct hwrm_port_led_cfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* The size of TX port statistics block in bytes. */\n+\tuint16_t\ttx_stat_size;\n+\t/* The size of RX port statistics block in bytes. */\n+\tuint16_t\trx_stat_size;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -13182,13 +13201,161 @@ struct hwrm_port_led_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**********************\n- * hwrm_port_led_qcfg *\n- **********************/\n+/* Port Tx Statistics extended Formats */\n+/* tx_port_stats_ext (size:2048b/256B) */\n+struct tx_port_stats_ext {\n+\t/* Total number of tx bytes count on cos queue 0 */\n+\tuint64_t\ttx_bytes_cos0;\n+\t/* Total number of tx bytes count on cos queue 1 */\n+\tuint64_t\ttx_bytes_cos1;\n+\t/* Total number of tx bytes count on cos queue 2 */\n+\tuint64_t\ttx_bytes_cos2;\n+\t/* Total number of tx bytes count on cos queue 3 */\n+\tuint64_t\ttx_bytes_cos3;\n+\t/* Total number of tx bytes count on cos queue 4 */\n+\tuint64_t\ttx_bytes_cos4;\n+\t/* Total number of tx bytes count on cos queue 5 */\n+\tuint64_t\ttx_bytes_cos5;\n+\t/* Total number of tx bytes count on cos queue 6 */\n+\tuint64_t\ttx_bytes_cos6;\n+\t/* Total number of tx bytes count on cos queue 7 */\n+\tuint64_t\ttx_bytes_cos7;\n+\t/* Total number of tx packets count on cos queue 0 */\n+\tuint64_t\ttx_packets_cos0;\n+\t/* Total number of tx packets count on cos queue 1 */\n+\tuint64_t\ttx_packets_cos1;\n+\t/* Total number of tx packets count on cos queue 2 */\n+\tuint64_t\ttx_packets_cos2;\n+\t/* Total number of tx packets count on cos queue 3 */\n+\tuint64_t\ttx_packets_cos3;\n+\t/* Total number of tx packets count on cos queue 4 */\n+\tuint64_t\ttx_packets_cos4;\n+\t/* Total number of tx packets count on cos queue 5 */\n+\tuint64_t\ttx_packets_cos5;\n+\t/* Total number of tx packets count on cos queue 6 */\n+\tuint64_t\ttx_packets_cos6;\n+\t/* Total number of tx packets count on cos queue 7 */\n+\tuint64_t\ttx_packets_cos7;\n+\t/* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */\n+\tuint64_t\tpfc_pri0_tx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */\n+\tuint64_t\tpfc_pri0_tx_transitions;\n+\t/* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */\n+\tuint64_t\tpfc_pri1_tx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */\n+\tuint64_t\tpfc_pri1_tx_transitions;\n+\t/* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */\n+\tuint64_t\tpfc_pri2_tx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */\n+\tuint64_t\tpfc_pri2_tx_transitions;\n+\t/* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */\n+\tuint64_t\tpfc_pri3_tx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */\n+\tuint64_t\tpfc_pri3_tx_transitions;\n+\t/* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */\n+\tuint64_t\tpfc_pri4_tx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */\n+\tuint64_t\tpfc_pri4_tx_transitions;\n+\t/* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */\n+\tuint64_t\tpfc_pri5_tx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */\n+\tuint64_t\tpfc_pri5_tx_transitions;\n+\t/* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */\n+\tuint64_t\tpfc_pri6_tx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */\n+\tuint64_t\tpfc_pri6_tx_transitions;\n+\t/* time duration between transmitting a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */\n+\tuint64_t\tpfc_pri7_tx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */\n+\tuint64_t\tpfc_pri7_tx_transitions;\n+} __attribute__((packed));\n+\n+/* Port Rx Statistics extended Formats */\n+/* rx_port_stats_ext (size:2368b/296B) */\n+struct rx_port_stats_ext {\n+\t/* Number of times link state changed to down */\n+\tuint64_t\tlink_down_events;\n+\t/* Number of times the idle rings with pause bit are found */\n+\tuint64_t\tcontinuous_pause_events;\n+\t/* Number of times the active rings pause bit resumed back */\n+\tuint64_t\tresume_pause_events;\n+\t/* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */\n+\tuint64_t\tcontinuous_roce_pause_events;\n+\t/* Number of times, the ROCE cos queue PFC is enabled back */\n+\tuint64_t\tresume_roce_pause_events;\n+\t/* Total number of rx bytes count on cos queue 0 */\n+\tuint64_t\trx_bytes_cos0;\n+\t/* Total number of rx bytes count on cos queue 1 */\n+\tuint64_t\trx_bytes_cos1;\n+\t/* Total number of rx bytes count on cos queue 2 */\n+\tuint64_t\trx_bytes_cos2;\n+\t/* Total number of rx bytes count on cos queue 3 */\n+\tuint64_t\trx_bytes_cos3;\n+\t/* Total number of rx bytes count on cos queue 4 */\n+\tuint64_t\trx_bytes_cos4;\n+\t/* Total number of rx bytes count on cos queue 5 */\n+\tuint64_t\trx_bytes_cos5;\n+\t/* Total number of rx bytes count on cos queue 6 */\n+\tuint64_t\trx_bytes_cos6;\n+\t/* Total number of rx bytes count on cos queue 7 */\n+\tuint64_t\trx_bytes_cos7;\n+\t/* Total number of rx packets count on cos queue 0 */\n+\tuint64_t\trx_packets_cos0;\n+\t/* Total number of rx packets count on cos queue 1 */\n+\tuint64_t\trx_packets_cos1;\n+\t/* Total number of rx packets count on cos queue 2 */\n+\tuint64_t\trx_packets_cos2;\n+\t/* Total number of rx packets count on cos queue 3 */\n+\tuint64_t\trx_packets_cos3;\n+\t/* Total number of rx packets count on cos queue 4 */\n+\tuint64_t\trx_packets_cos4;\n+\t/* Total number of rx packets count on cos queue 5 */\n+\tuint64_t\trx_packets_cos5;\n+\t/* Total number of rx packets count on cos queue 6 */\n+\tuint64_t\trx_packets_cos6;\n+\t/* Total number of rx packets count on cos queue 7 */\n+\tuint64_t\trx_packets_cos7;\n+\t/* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 0 */\n+\tuint64_t\tpfc_pri0_rx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 0 */\n+\tuint64_t\tpfc_pri0_rx_transitions;\n+\t/* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 1 */\n+\tuint64_t\tpfc_pri1_rx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 1 */\n+\tuint64_t\tpfc_pri1_rx_transitions;\n+\t/* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 2 */\n+\tuint64_t\tpfc_pri2_rx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 2 */\n+\tuint64_t\tpfc_pri2_rx_transitions;\n+\t/* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 3 */\n+\tuint64_t\tpfc_pri3_rx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 3 */\n+\tuint64_t\tpfc_pri3_rx_transitions;\n+\t/* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 4 */\n+\tuint64_t\tpfc_pri4_rx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 4 */\n+\tuint64_t\tpfc_pri4_rx_transitions;\n+\t/* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 5 */\n+\tuint64_t\tpfc_pri5_rx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 5 */\n+\tuint64_t\tpfc_pri5_rx_transitions;\n+\t/* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 6 */\n+\tuint64_t\tpfc_pri6_rx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 6 */\n+\tuint64_t\tpfc_pri6_rx_transitions;\n+\t/* time duration receiving a XON -> XOFF and a subsequent XOFF -> XON for priority 7 */\n+\tuint64_t\tpfc_pri7_rx_duration_us;\n+\t/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */\n+\tuint64_t\tpfc_pri7_rx_transitions;\n+} __attribute__((packed));\n+\n+/************************\n+ * hwrm_port_qstats_ext *\n+ ************************/\n \n \n-/* hwrm_port_led_qcfg_input (size:192b/24B) */\n-struct hwrm_port_led_qcfg_input {\n+/* hwrm_port_qstats_ext_input (size:320b/40B) */\n+struct hwrm_port_qstats_ext_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -13216,267 +13383,131 @@ struct hwrm_port_led_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Port ID of port whose LED configuration is being queried. */\n+\t/* Port ID of port that is being queried. */\n \tuint16_t\tport_id;\n-\tuint8_t\tunused_0[6];\n-} __attribute__((packed));\n-\n-/* hwrm_port_led_qcfg_output (size:448b/56B) */\n-struct hwrm_port_led_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n \t/*\n-\t * The number of LEDs that are configured on this port.\n-\t * Up to 4 LEDs can be returned in the response.\n+\t * The size of TX port extended\n+\t * statistics block in bytes.\n \t */\n-\tuint8_t\tnum_leds;\n-\t/* An identifier for the LED #0. */\n-\tuint8_t\tled0_id;\n-\t/* The type of LED #0. */\n-\tuint8_t\tled0_type;\n-\t/* Speed LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)\n-\t/* Activity LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)\n-\t/* Invalid */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID\n-\t/* The current state of the LED #0. */\n-\tuint8_t\tled0_state;\n-\t/* Default state of the LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)\n-\t/* Off */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)\n-\t/* On */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)\n-\t/* Blink */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)\n-\t/* Blink Alternately */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT\n-\t/* The color of LED #0. */\n-\tuint8_t\tled0_color;\n-\t/* Default */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)\n-\t/* Amber */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)\n-\t/* Green */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)\n-\t/* Green or Amber */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER\n-\tuint8_t\tunused_0;\n+\tuint16_t\ttx_stat_size;\n \t/*\n-\t * If the LED #0 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED on between cycles.\n+\t * The size of RX port extended\n+\t * statistics block in bytes\n \t */\n-\tuint16_t\tled0_blink_on;\n+\tuint16_t\trx_stat_size;\n+\tuint8_t\tunused_0[2];\n \t/*\n-\t * If the LED #0 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED off between cycles.\n+\t * This is the host address where\n+\t * Tx port statistics will be stored\n \t */\n-\tuint16_t\tled0_blink_off;\n+\tuint64_t\ttx_stat_host_addr;\n \t/*\n-\t * An identifier for the group of LEDs that LED #0 belongs\n-\t * to.\n-\t * If set to 0, then the LED #0 is not grouped.\n-\t * For all other non-zero values of this field, LED #0 is\n-\t * grouped together with the LEDs with the same group ID\n-\t * value.\n+\t * This is the host address where\n+\t * Rx port statistics will be stored\n \t */\n-\tuint8_t\tled0_group_id;\n-\t/* An identifier for the LED #1. */\n-\tuint8_t\tled1_id;\n-\t/* The type of LED #1. */\n-\tuint8_t\tled1_type;\n-\t/* Speed LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)\n-\t/* Activity LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)\n-\t/* Invalid */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID\n-\t/* The current state of the LED #1. */\n-\tuint8_t\tled1_state;\n-\t/* Default state of the LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)\n-\t/* Off */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)\n-\t/* On */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)\n-\t/* Blink */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)\n-\t/* Blink Alternately */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT\n-\t/* The color of LED #1. */\n-\tuint8_t\tled1_color;\n-\t/* Default */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)\n-\t/* Amber */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)\n-\t/* Green */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)\n-\t/* Green or Amber */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER\n-\tuint8_t\tunused_1;\n+\tuint64_t\trx_stat_host_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_port_qstats_ext_output (size:128b/16B) */\n+struct hwrm_port_qstats_ext_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The size of TX port statistics block in bytes. */\n+\tuint16_t\ttx_stat_size;\n+\t/* The size of RX port statistics block in bytes. */\n+\tuint16_t\trx_stat_size;\n+\t/* Total number of active cos queues available. */\n+\tuint16_t\ttotal_active_cos_queues;\n+\tuint8_t\tflags;\n \t/*\n-\t * If the LED #1 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED on between cycles.\n+\t * If set to 1, then this field indicates that clear\n+\t * roce specific counters is supported.\n \t */\n-\tuint16_t\tled1_blink_on;\n+\t#define HWRM_PORT_QSTATS_EXT_OUTPUT_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * If the LED #1 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED off between cycles.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint16_t\tled1_blink_off;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*************************\n+ * hwrm_port_lpbk_qstats *\n+ *************************/\n+\n+\n+/* hwrm_port_lpbk_qstats_input (size:128b/16B) */\n+struct hwrm_port_lpbk_qstats_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * An identifier for the group of LEDs that LED #1 belongs\n-\t * to.\n-\t * If set to 0, then the LED #1 is not grouped.\n-\t * For all other non-zero values of this field, LED #1 is\n-\t * grouped together with the LEDs with the same group ID\n-\t * value.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint8_t\tled1_group_id;\n-\t/* An identifier for the LED #2. */\n-\tuint8_t\tled2_id;\n-\t/* The type of LED #2. */\n-\tuint8_t\tled2_type;\n-\t/* Speed LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)\n-\t/* Activity LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)\n-\t/* Invalid */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID\n-\t/* The current state of the LED #2. */\n-\tuint8_t\tled2_state;\n-\t/* Default state of the LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)\n-\t/* Off */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)\n-\t/* On */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)\n-\t/* Blink */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)\n-\t/* Blink Alternately */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT\n-\t/* The color of LED #2. */\n-\tuint8_t\tled2_color;\n-\t/* Default */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)\n-\t/* Amber */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)\n-\t/* Green */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)\n-\t/* Green or Amber */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER\n-\tuint8_t\tunused_2;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * If the LED #2 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED on between cycles.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint16_t\tled2_blink_on;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * If the LED #2 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED off between cycles.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint16_t\tled2_blink_off;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * An identifier for the group of LEDs that LED #2 belongs\n-\t * to.\n-\t * If set to 0, then the LED #2 is not grouped.\n-\t * For all other non-zero values of this field, LED #2 is\n-\t * grouped together with the LEDs with the same group ID\n-\t * value.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint8_t\tled2_group_id;\n-\t/* An identifier for the LED #3. */\n-\tuint8_t\tled3_id;\n-\t/* The type of LED #3. */\n-\tuint8_t\tled3_type;\n-\t/* Speed LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)\n-\t/* Activity LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)\n-\t/* Invalid */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID\n-\t/* The current state of the LED #3. */\n-\tuint8_t\tled3_state;\n-\t/* Default state of the LED */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)\n-\t/* Off */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)\n-\t/* On */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)\n-\t/* Blink */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)\n-\t/* Blink Alternately */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT\n-\t/* The color of LED #3. */\n-\tuint8_t\tled3_color;\n-\t/* Default */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)\n-\t/* Amber */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)\n-\t/* Green */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)\n-\t/* Green or Amber */\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)\n-\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \\\n-\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER\n-\tuint8_t\tunused_3;\n-\t/*\n-\t * If the LED #3 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED on between cycles.\n-\t */\n-\tuint16_t\tled3_blink_on;\n-\t/*\n-\t * If the LED #3 state is \"blink\" or \"blinkalt\", then\n-\t * this field represents the requested time in milliseconds\n-\t * to keep LED off between cycles.\n-\t */\n-\tuint16_t\tled3_blink_off;\n-\t/*\n-\t * An identifier for the group of LEDs that LED #3 belongs\n-\t * to.\n-\t * If set to 0, then the LED #3 is not grouped.\n-\t * For all other non-zero values of this field, LED #3 is\n-\t * grouped together with the LEDs with the same group ID\n-\t * value.\n-\t */\n-\tuint8_t\tled3_group_id;\n-\tuint8_t\tunused_4[6];\n+\tuint64_t\tresp_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_port_lpbk_qstats_output (size:768b/96B) */\n+struct hwrm_port_lpbk_qstats_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Number of transmitted unicast frames */\n+\tuint64_t\tlpbk_ucast_frames;\n+\t/* Number of transmitted multicast frames */\n+\tuint64_t\tlpbk_mcast_frames;\n+\t/* Number of transmitted broadcast frames */\n+\tuint64_t\tlpbk_bcast_frames;\n+\t/* Number of transmitted bytes for unicast traffic */\n+\tuint64_t\tlpbk_ucast_bytes;\n+\t/* Number of transmitted bytes for multicast traffic */\n+\tuint64_t\tlpbk_mcast_bytes;\n+\t/* Number of transmitted bytes for broadcast traffic */\n+\tuint64_t\tlpbk_bcast_bytes;\n+\t/* Total Tx Drops for loopback traffic reported by STATS block */\n+\tuint64_t\ttx_stat_discard;\n+\t/* Total Tx Error Drops for loopback traffic reported by STATS block */\n+\tuint64_t\ttx_stat_error;\n+\t/* Total Rx Drops for loopback traffic reported by STATS block */\n+\tuint64_t\trx_stat_discard;\n+\t/* Total Rx Error Drops for loopback traffic reported by STATS block */\n+\tuint64_t\trx_stat_error;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -13488,12 +13519,12 @@ struct hwrm_port_led_qcfg_output {\n } __attribute__((packed));\n \n /***********************\n- * hwrm_port_led_qcaps *\n+ * hwrm_port_clr_stats *\n ***********************/\n \n \n-/* hwrm_port_led_qcaps_input (size:192b/24B) */\n-struct hwrm_port_led_qcaps_input {\n+/* hwrm_port_clr_stats_input (size:192b/24B) */\n+struct hwrm_port_clr_stats_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -13521,13 +13552,24 @@ struct hwrm_port_led_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Port ID of port whose LED configuration is being queried. */\n+\t/* Port ID of port that is being queried. */\n \tuint16_t\tport_id;\n-\tuint8_t\tunused_0[6];\n+\tuint8_t\tflags;\n+\t/*\n+\t * If set to 1, then this field indicates clear the following RoCE\n+\t * specific counters.\n+\t * RoCE associated TX/RX cos counters\n+\t * CNP associated TX/RX cos counters\n+\t * RoCE/CNP specific TX/RX flow counters\n+\t * Firmware will determine the RoCE/CNP cos queue based on qos profile.\n+\t * This flag is honored only when RoCE is enabled on that port.\n+\t */\n+\t#define HWRM_PORT_CLR_STATS_INPUT_FLAGS_ROCE_COUNTERS UINT32_C(0x1)\n+\tuint8_t\tunused_0[5];\n } __attribute__((packed));\n \n-/* hwrm_port_led_qcaps_output (size:384b/48B) */\n-struct hwrm_port_led_qcaps_output {\n+/* hwrm_port_clr_stats_output (size:128b/16B) */\n+struct hwrm_port_clr_stats_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -13536,750 +13578,678 @@ struct hwrm_port_led_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * The number of LEDs that are configured on this port.\n-\t * Up to 4 LEDs can be returned in the response.\n-\t */\n-\tuint8_t\tnum_leds;\n-\t/* Reserved for future use. */\n-\tuint8_t\tunused[3];\n-\t/* An identifier for the LED #0. */\n-\tuint8_t\tled0_id;\n-\t/* The type of LED #0. */\n-\tuint8_t\tled0_type;\n-\t/* Speed LED */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)\n-\t/* Activity LED */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)\n-\t/* Invalid */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \\\n-\t\tHWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID\n-\t/*\n-\t * An identifier for the group of LEDs that LED #0 belongs\n-\t * to.\n-\t * If set to 0, then the LED #0 cannot be grouped.\n-\t * For all other non-zero values of this field, LED #0 is\n-\t * grouped together with the LEDs with the same group ID\n-\t * value.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\tled0_group_id;\n-\tuint8_t\tunused_0;\n-\t/* The states supported by LED #0. */\n-\tuint16_t\tled0_state_caps;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***********************\n+ * hwrm_port_phy_qcaps *\n+ ***********************/\n+\n+\n+/* hwrm_port_phy_qcaps_input (size:192b/24B) */\n+struct hwrm_port_phy_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * If set to 1, this LED is enabled.\n-\t * If set to 0, this LED is disabled.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \\\n-\t\tUINT32_C(0x1)\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * If set to 1, off state is supported on this LED.\n-\t * If set to 0, off state is not supported on this LED.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \\\n-\t\tUINT32_C(0x2)\n+\tuint16_t\tseq_id;\n \t/*\n-\t * If set to 1, on state is supported on this LED.\n-\t * If set to 0, on state is not supported on this LED.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \\\n-\t\tUINT32_C(0x4)\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * If set to 1, blink state is supported on this LED.\n-\t * If set to 0, blink state is not supported on this LED.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \\\n-\t\tUINT32_C(0x8)\n+\tuint64_t\tresp_addr;\n+\t/* Port ID of port that is being queried. */\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_port_phy_qcaps_output (size:192b/24B) */\n+struct hwrm_port_phy_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* PHY capability flags */\n+\tuint8_t\tflags;\n \t/*\n-\t * If set to 1, blink_alt state is supported on this LED.\n-\t * If set to 0, blink_alt state is not supported on this LED.\n+\t * If set to 1, then this field indicates that the\n+\t * link is capable of supporting EEE.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \\\n-\t\tUINT32_C(0x10)\n-\t/* The colors supported by LED #0. */\n-\tuint16_t\tled0_color_caps;\n-\t/* reserved. */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \\\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * If set to 1, Amber color is supported on this LED.\n-\t * If set to 0, Amber color is not supported on this LED.\n+\t * If set to 1, then this field indicates that the\n+\t * PHY is capable of supporting external loopback.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \\\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * If set to 1, Green color is supported on this LED.\n-\t * If set to 0, Green color is not supported on this LED.\n-\t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \\\n-\t\tUINT32_C(0x4)\n-\t/* An identifier for the LED #1. */\n-\tuint8_t\tled1_id;\n-\t/* The type of LED #1. */\n-\tuint8_t\tled1_type;\n-\t/* Speed LED */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)\n-\t/* Activity LED */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)\n-\t/* Invalid */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \\\n-\t\tHWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID\n-\t/*\n-\t * An identifier for the group of LEDs that LED #1 belongs\n-\t * to.\n-\t * If set to 0, then the LED #0 cannot be grouped.\n-\t * For all other non-zero values of this field, LED #0 is\n-\t * grouped together with the LEDs with the same group ID\n-\t * value.\n+\t * Reserved field. The HWRM shall set this field to 0.\n+\t * An HWRM client shall ignore this field.\n \t */\n-\tuint8_t\tled1_group_id;\n-\tuint8_t\tunused_1;\n-\t/* The states supported by LED #1. */\n-\tuint16_t\tled1_state_caps;\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \\\n+\t\tUINT32_C(0xfc)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT 2\n+\t/* Number of front panel ports for this device. */\n+\tuint8_t\tport_cnt;\n+\t/* Not supported or unknown */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_UNKNOWN UINT32_C(0x0)\n+\t/* single port device */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_1 UINT32_C(0x1)\n+\t/* 2-port device */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_2 UINT32_C(0x2)\n+\t/* 3-port device */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_3 UINT32_C(0x3)\n+\t/* 4-port device */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4 UINT32_C(0x4)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_LAST \\\n+\t\tHWRM_PORT_PHY_QCAPS_OUTPUT_PORT_CNT_4\n \t/*\n-\t * If set to 1, this LED is enabled.\n-\t * If set to 0, this LED is disabled.\n+\t * This is a bit mask to indicate what speeds are supported\n+\t * as forced speeds on this link.\n+\t * For each speed that can be forced on this link, the\n+\t * corresponding mask bit shall be set to '1'.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \\\n+\tuint16_t\tsupported_speeds_force_mode;\n+\t/* 100Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * If set to 1, off state is supported on this LED.\n-\t * If set to 0, off state is not supported on this LED.\n-\t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \\\n+\t/* 100Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100MB \\\n \t\tUINT32_C(0x2)\n-\t/*\n-\t * If set to 1, on state is supported on this LED.\n-\t * If set to 0, on state is not supported on this LED.\n-\t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \\\n+\t/* 1Gb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD \\\n \t\tUINT32_C(0x4)\n+\t/* 1Gb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_1GB \\\n+\t\tUINT32_C(0x8)\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2GB \\\n+\t\tUINT32_C(0x10)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB \\\n+\t\tUINT32_C(0x20)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10GB \\\n+\t\tUINT32_C(0x40)\n+\t/* 20Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_20GB \\\n+\t\tUINT32_C(0x80)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_25GB \\\n+\t\tUINT32_C(0x100)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_40GB \\\n+\t\tUINT32_C(0x200)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_50GB \\\n+\t\tUINT32_C(0x400)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_100GB \\\n+\t\tUINT32_C(0x800)\n+\t/* 10Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD \\\n+\t\tUINT32_C(0x1000)\n+\t/* 10Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \\\n+\t\tUINT32_C(0x2000)\n \t/*\n-\t * If set to 1, blink state is supported on this LED.\n-\t * If set to 0, blink state is not supported on this LED.\n+\t * This is a bit mask to indicate what speeds are supported\n+\t * for autonegotiation on this link.\n+\t * For each speed that can be autonegotiated on this link, the\n+\t * corresponding mask bit shall be set to '1'.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \\\n+\tuint16_t\tsupported_speeds_auto_mode;\n+\t/* 100Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD \\\n+\t\tUINT32_C(0x1)\n+\t/* 100Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100MB \\\n+\t\tUINT32_C(0x2)\n+\t/* 1Gb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD \\\n+\t\tUINT32_C(0x4)\n+\t/* 1Gb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_1GB \\\n \t\tUINT32_C(0x8)\n+\t/* 2Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2GB \\\n+\t\tUINT32_C(0x10)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB \\\n+\t\tUINT32_C(0x20)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10GB \\\n+\t\tUINT32_C(0x40)\n+\t/* 20Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_20GB \\\n+\t\tUINT32_C(0x80)\n+\t/* 25Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_25GB \\\n+\t\tUINT32_C(0x100)\n+\t/* 40Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_40GB \\\n+\t\tUINT32_C(0x200)\n+\t/* 50Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_50GB \\\n+\t\tUINT32_C(0x400)\n+\t/* 100Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_100GB \\\n+\t\tUINT32_C(0x800)\n+\t/* 10Mb link speed (Half-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD \\\n+\t\tUINT32_C(0x1000)\n+\t/* 10Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \\\n+\t\tUINT32_C(0x2000)\n \t/*\n-\t * If set to 1, blink_alt state is supported on this LED.\n-\t * If set to 0, blink_alt state is not supported on this LED.\n+\t * This is a bit mask to indicate what speeds are supported\n+\t * for EEE on this link.\n+\t * For each speed that can be autonegotiated when EEE is enabled\n+\t * on this link, the corresponding mask bit shall be set to '1'.\n+\t * This field is only valid when the eee_suppotred is set to '1'.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \\\n-\t\tUINT32_C(0x10)\n-\t/* The colors supported by LED #1. */\n-\tuint16_t\tled1_color_caps;\n-\t/* reserved. */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \\\n+\tuint16_t\tsupported_speeds_eee_mode;\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 \\\n \t\tUINT32_C(0x1)\n+\t/* 100Mb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_100MB \\\n+\t\tUINT32_C(0x2)\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 \\\n+\t\tUINT32_C(0x4)\n+\t/* 1Gb link speed (Full-duplex) */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_1GB \\\n+\t\tUINT32_C(0x8)\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 \\\n+\t\tUINT32_C(0x10)\n+\t/* Reserved */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 \\\n+\t\tUINT32_C(0x20)\n+\t/* 10Gb link speed */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_EEE_MODE_10GB \\\n+\t\tUINT32_C(0x40)\n+\tuint32_t\ttx_lpi_timer_low;\n \t/*\n-\t * If set to 1, Amber color is supported on this LED.\n-\t * If set to 0, Amber color is not supported on this LED.\n+\t * The lowest value of TX LPI timer that can be set on this link\n+\t * when EEE is enabled. This value is in microseconds.\n+\t * This field is valid only when_eee_supported is set to '1'.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_MASK \\\n+\t\tUINT32_C(0xffffff)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_LOW_SFT 0\n \t/*\n-\t * If set to 1, Green color is supported on this LED.\n-\t * If set to 0, Green color is not supported on this LED.\n+\t * Reserved field. The HWRM shall set this field to 0.\n+\t * An HWRM client shall ignore this field.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \\\n-\t\tUINT32_C(0x4)\n-\t/* An identifier for the LED #2. */\n-\tuint8_t\tled2_id;\n-\t/* The type of LED #2. */\n-\tuint8_t\tled2_type;\n-\t/* Speed LED */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)\n-\t/* Activity LED */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)\n-\t/* Invalid */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \\\n-\t\tHWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_MASK \\\n+\t\tUINT32_C(0xff000000)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_RSVD2_SFT 24\n+\tuint32_t\tvalid_tx_lpi_timer_high;\n \t/*\n-\t * An identifier for the group of LEDs that LED #0 belongs\n-\t * to.\n-\t * If set to 0, then the LED #0 cannot be grouped.\n-\t * For all other non-zero values of this field, LED #0 is\n-\t * grouped together with the LEDs with the same group ID\n-\t * value.\n+\t * The highest value of TX LPI timer that can be set on this link\n+\t * when EEE is enabled. This value is in microseconds.\n+\t * This field is valid only when_eee_supported is set to '1'.\n \t */\n-\tuint8_t\tled2_group_id;\n-\tuint8_t\tunused_2;\n-\t/* The states supported by LED #2. */\n-\tuint16_t\tled2_state_caps;\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_MASK \\\n+\t\tUINT32_C(0xffffff)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_TX_LPI_TIMER_HIGH_SFT 0\n \t/*\n-\t * If set to 1, this LED is enabled.\n-\t * If set to 0, this LED is disabled.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_MASK \\\n+\t\tUINT32_C(0xff000000)\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24\n+} __attribute__((packed));\n+\n+/*********************\n+ * hwrm_port_led_cfg *\n+ *********************/\n+\n+\n+/* hwrm_port_led_cfg_input (size:512b/64B) */\n+struct hwrm_port_led_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * If set to 1, off state is supported on this LED.\n-\t * If set to 0, off state is not supported on this LED.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \\\n-\t\tUINT32_C(0x2)\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * If set to 1, on state is supported on this LED.\n-\t * If set to 0, on state is not supported on this LED.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \\\n-\t\tUINT32_C(0x4)\n+\tuint16_t\tseq_id;\n \t/*\n-\t * If set to 1, blink state is supported on this LED.\n-\t * If set to 0, blink state is not supported on this LED.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \\\n-\t\tUINT32_C(0x8)\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * If set to 1, blink_alt state is supported on this LED.\n-\t * If set to 0, blink_alt state is not supported on this LED.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \\\n-\t\tUINT32_C(0x10)\n-\t/* The colors supported by LED #2. */\n-\tuint16_t\tled2_color_caps;\n-\t/* reserved. */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \\\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the led0_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * If set to 1, Amber color is supported on this LED.\n-\t * If set to 0, Amber color is not supported on this LED.\n+\t * This bit must be '1' for the led0_state field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \\\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * If set to 1, Green color is supported on this LED.\n-\t * If set to 0, Green color is not supported on this LED.\n+\t * This bit must be '1' for the led0_color field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \\\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \\\n \t\tUINT32_C(0x4)\n-\t/* An identifier for the LED #3. */\n-\tuint8_t\tled3_id;\n-\t/* The type of LED #3. */\n-\tuint8_t\tled3_type;\n-\t/* Speed LED */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)\n-\t/* Activity LED */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)\n-\t/* Invalid */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \\\n-\t\tHWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID\n \t/*\n-\t * An identifier for the group of LEDs that LED #3 belongs\n-\t * to.\n-\t * If set to 0, then the LED #0 cannot be grouped.\n-\t * For all other non-zero values of this field, LED #0 is\n-\t * grouped together with the LEDs with the same group ID\n-\t * value.\n+\t * This bit must be '1' for the led0_blink_on field to be\n+\t * configured.\n \t */\n-\tuint8_t\tled3_group_id;\n-\tuint8_t\tunused_3;\n-\t/* The states supported by LED #3. */\n-\tuint16_t\tled3_state_caps;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * If set to 1, this LED is enabled.\n-\t * If set to 0, this LED is disabled.\n+\t * This bit must be '1' for the led0_blink_off field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * If set to 1, off state is supported on this LED.\n-\t * If set to 0, off state is not supported on this LED.\n+\t * This bit must be '1' for the led0_group_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * If set to 1, on state is supported on this LED.\n-\t * If set to 0, on state is not supported on this LED.\n+\t * This bit must be '1' for the led1_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \\\n-\t\tUINT32_C(0x4)\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * If set to 1, blink state is supported on this LED.\n-\t * If set to 0, blink state is not supported on this LED.\n+\t * This bit must be '1' for the led1_state field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \\\n-\t\tUINT32_C(0x8)\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_STATE \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * If set to 1, blink_alt state is supported on this LED.\n-\t * If set to 0, blink_alt state is not supported on this LED.\n+\t * This bit must be '1' for the led1_color field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \\\n-\t\tUINT32_C(0x10)\n-\t/* The colors supported by LED #3. */\n-\tuint16_t\tled3_color_caps;\n-\t/* reserved. */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_COLOR \\\n+\t\tUINT32_C(0x100)\n \t/*\n-\t * If set to 1, Amber color is supported on this LED.\n-\t * If set to 0, Amber color is not supported on this LED.\n+\t * This bit must be '1' for the led1_blink_on field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_ON \\\n+\t\tUINT32_C(0x200)\n \t/*\n-\t * If set to 1, Green color is supported on this LED.\n-\t * If set to 0, Green color is not supported on this LED.\n+\t * This bit must be '1' for the led1_blink_off field to be\n+\t * configured.\n \t */\n-\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \\\n-\t\tUINT32_C(0x4)\n-\tuint8_t\tunused_4[3];\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_BLINK_OFF \\\n+\t\tUINT32_C(0x400)\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This bit must be '1' for the led1_group_id field to be\n+\t * configured.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/***********************\n- * hwrm_queue_qportcfg *\n- ***********************/\n-\n-\n-/* hwrm_queue_qportcfg_input (size:192b/24B) */\n-struct hwrm_queue_qportcfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_GROUP_ID \\\n+\t\tUINT32_C(0x800)\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * This bit must be '1' for the led2_id field to be\n+\t * configured.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_ID \\\n+\t\tUINT32_C(0x1000)\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * This bit must be '1' for the led2_state field to be\n+\t * configured.\n \t */\n-\tuint16_t\tseq_id;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_STATE \\\n+\t\tUINT32_C(0x2000)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * This bit must be '1' for the led2_color field to be\n+\t * configured.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_COLOR \\\n+\t\tUINT32_C(0x4000)\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * This bit must be '1' for the led2_blink_on field to be\n+\t * configured.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_ON \\\n+\t\tUINT32_C(0x8000)\n \t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n+\t * This bit must be '1' for the led2_blink_off field to be\n+\t * configured.\n \t */\n-\t#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_BLINK_OFF \\\n+\t\tUINT32_C(0x10000)\n \t/*\n-\t * Port ID of port for which the queue configuration is being\n-\t * queried. This field is only required when sent by IPC.\n+\t * This bit must be '1' for the led2_group_id field to be\n+\t * configured.\n \t */\n-\tuint16_t\tport_id;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED2_GROUP_ID \\\n+\t\tUINT32_C(0x20000)\n \t/*\n-\t * Drivers will set this capability when it can use\n-\t * queue_idx_service_profile to map the queues to application.\n+\t * This bit must be '1' for the led3_id field to be\n+\t * configured.\n \t */\n-\tuint8_t\tdrv_qmap_cap;\n-\t/* disabled */\n-\t#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)\n-\t/* enabled */\n-\t#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)\n-\t#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED\n-\tuint8_t\tunused_0;\n-} __attribute__((packed));\n-\n-/* hwrm_queue_qportcfg_output (size:256b/32B) */\n-struct hwrm_queue_qportcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_ID \\\n+\t\tUINT32_C(0x40000)\n \t/*\n-\t * The maximum number of queues that can be configured on this\n-\t * port.\n-\t * Valid values range from 1 through 8.\n+\t * This bit must be '1' for the led3_state field to be\n+\t * configured.\n \t */\n-\tuint8_t\tmax_configurable_queues;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_STATE \\\n+\t\tUINT32_C(0x80000)\n \t/*\n-\t * The maximum number of lossless queues that can be configured\n-\t * on this port.\n-\t * Valid values range from 0 through 8.\n+\t * This bit must be '1' for the led3_color field to be\n+\t * configured.\n \t */\n-\tuint8_t\tmax_configurable_lossless_queues;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_COLOR \\\n+\t\tUINT32_C(0x100000)\n \t/*\n-\t * Bitmask indicating which queues can be configured by the\n-\t * hwrm_queue_cfg command.\n-\t *\n-\t * Each bit represents a specific queue where bit 0 represents\n-\t * queue 0 and bit 7 represents queue 7.\n-\t * # A value of 0 indicates that the queue is not configurable\n-\t * by the hwrm_queue_cfg command.\n-\t * # A value of 1 indicates that the queue is configurable.\n-\t * # A hwrm_queue_cfg command shall return error when trying to\n-\t * configure a queue not configurable.\n+\t * This bit must be '1' for the led3_blink_on field to be\n+\t * configured.\n \t */\n-\tuint8_t\tqueue_cfg_allowed;\n-\t/* Information about queue configuration. */\n-\tuint8_t\tqueue_cfg_info;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_ON \\\n+\t\tUINT32_C(0x200000)\n \t/*\n-\t * If this flag is set to '1', then the queues are\n-\t * configured asymmetrically on TX and RX sides.\n-\t * If this flag is set to '0', then the queues are\n-\t * configured symmetrically on TX and RX sides. For\n-\t * symmetric configuration, the queue configuration\n-\t * including queue ids and service profiles on the\n-\t * TX side is the same as the corresponding queue\n-\t * configuration on the RX side.\n+\t * This bit must be '1' for the led3_blink_off field to be\n+\t * configured.\n \t */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_BLINK_OFF \\\n+\t\tUINT32_C(0x400000)\n \t/*\n-\t * Bitmask indicating which queues can be configured by the\n-\t * hwrm_queue_pfcenable_cfg command.\n-\t *\n-\t * Each bit represents a specific priority where bit 0 represents\n-\t * priority 0 and bit 7 represents priority 7.\n-\t * # A value of 0 indicates that the priority is not configurable by\n-\t * the hwrm_queue_pfcenable_cfg command.\n-\t * # A value of 1 indicates that the priority is configurable.\n-\t * # A hwrm_queue_pfcenable_cfg command shall return error when\n-\t * trying to configure a priority that is not configurable.\n+\t * This bit must be '1' for the led3_group_id field to be\n+\t * configured.\n \t */\n-\tuint8_t\tqueue_pfcenable_cfg_allowed;\n+\t#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED3_GROUP_ID \\\n+\t\tUINT32_C(0x800000)\n+\t/* Port ID of port whose LEDs are configured. */\n+\tuint16_t\tport_id;\n \t/*\n-\t * Bitmask indicating which queues can be configured by the\n-\t * hwrm_queue_pri2cos_cfg command.\n-\t *\n-\t * Each bit represents a specific queue where bit 0 represents\n-\t * queue 0 and bit 7 represents queue 7.\n-\t * # A value of 0 indicates that the queue is not configurable\n-\t * by the hwrm_queue_pri2cos_cfg command.\n-\t * # A value of 1 indicates that the queue is configurable.\n-\t * # A hwrm_queue_pri2cos_cfg command shall return error when\n-\t * trying to configure a queue that is not configurable.\n+\t * The number of LEDs that are being configured.\n+\t * Up to 4 LEDs can be configured with this command.\n \t */\n-\tuint8_t\tqueue_pri2cos_cfg_allowed;\n+\tuint8_t\tnum_leds;\n+\t/* Reserved field. */\n+\tuint8_t\trsvd;\n+\t/* An identifier for the LED #0. */\n+\tuint8_t\tled0_id;\n+\t/* The requested state of the LED #0. */\n+\tuint8_t\tled0_state;\n+\t/* Default state of the LED */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_DEFAULT UINT32_C(0x0)\n+\t/* Off */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_OFF UINT32_C(0x1)\n+\t/* On */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_ON UINT32_C(0x2)\n+\t/* Blink */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINK UINT32_C(0x3)\n+\t/* Blink Alternately */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT UINT32_C(0x4)\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_STATE_LAST \\\n+\t\tHWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT\n+\t/* The requested color of LED #0. */\n+\tuint8_t\tled0_color;\n+\t/* Default */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)\n+\t/* Amber */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_AMBER UINT32_C(0x1)\n+\t/* Green */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREEN UINT32_C(0x2)\n+\t/* Green or Amber */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED0_COLOR_LAST \\\n+\t\tHWRM_PORT_LED_CFG_INPUT_LED0_COLOR_GREENAMBER\n+\tuint8_t\tunused_0;\n \t/*\n-\t * Bitmask indicating which queues can be configured by the\n-\t * hwrm_queue_pri2cos_cfg command.\n-\t *\n-\t * Each bit represents a specific queue where bit 0 represents\n-\t * queue 0 and bit 7 represents queue 7.\n-\t * # A value of 0 indicates that the queue is not configurable\n-\t * by the hwrm_queue_pri2cos_cfg command.\n-\t * # A value of 1 indicates that the queue is configurable.\n-\t * # A hwrm_queue_pri2cos_cfg command shall return error when\n-\t * trying to configure a queue not configurable.\n+\t * If the LED #0 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED on between cycles.\n \t */\n-\tuint8_t\tqueue_cos2bw_cfg_allowed;\n+\tuint16_t\tled0_blink_on;\n \t/*\n-\t * ID of CoS Queue 0.\n-\t * FF - Invalid id\n-\t *\n-\t * # This ID can be used on any subsequent call to an hwrm command\n-\t * that takes a queue id.\n-\t * # IDs must always be queried by this command before any use\n-\t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n-\t * # A value of 0xff indicates that the queue is not available.\n-\t * # Available queues may not be in sequential order.\n+\t * If the LED #0 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED off between cycles.\n \t */\n-\tuint8_t\tqueue_id0;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tqueue_id0_service_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \\\n-\t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n-\t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \\\n-\t\tUINT32_C(0x3)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN\n+\tuint16_t\tled0_blink_off;\n \t/*\n-\t * ID of CoS Queue 1.\n-\t * FF - Invalid id\n-\t *\n-\t * # This ID can be used on any subsequent call to an hwrm command\n-\t * that takes a queue id.\n-\t * # IDs must always be queried by this command before any use\n-\t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n-\t * # A value of 0xff indicates that the queue is not available.\n-\t * # Available queues may not be in sequential order.\n+\t * An identifier for the group of LEDs that LED #0 belongs\n+\t * to.\n+\t * If set to 0, then the LED #0 shall not be grouped and\n+\t * shall be treated as an individual resource.\n+\t * For all other non-zero values of this field, LED #0 shall\n+\t * be grouped together with the LEDs with the same group ID\n+\t * value.\n \t */\n-\tuint8_t\tqueue_id1;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tqueue_id1_service_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \\\n-\t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n-\t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \\\n-\t\tUINT32_C(0x3)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN\n+\tuint8_t\tled0_group_id;\n+\t/* Reserved field. */\n+\tuint8_t\trsvd0;\n+\t/* An identifier for the LED #1. */\n+\tuint8_t\tled1_id;\n+\t/* The requested state of the LED #1. */\n+\tuint8_t\tled1_state;\n+\t/* Default state of the LED */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_DEFAULT UINT32_C(0x0)\n+\t/* Off */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_OFF UINT32_C(0x1)\n+\t/* On */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_ON UINT32_C(0x2)\n+\t/* Blink */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINK UINT32_C(0x3)\n+\t/* Blink Alternately */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT UINT32_C(0x4)\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_STATE_LAST \\\n+\t\tHWRM_PORT_LED_CFG_INPUT_LED1_STATE_BLINKALT\n+\t/* The requested color of LED #1. */\n+\tuint8_t\tled1_color;\n+\t/* Default */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)\n+\t/* Amber */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_AMBER UINT32_C(0x1)\n+\t/* Green */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREEN UINT32_C(0x2)\n+\t/* Green or Amber */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED1_COLOR_LAST \\\n+\t\tHWRM_PORT_LED_CFG_INPUT_LED1_COLOR_GREENAMBER\n+\tuint8_t\tunused_1;\n \t/*\n-\t * ID of CoS Queue 2.\n-\t * FF - Invalid id\n-\t *\n-\t * # This ID can be used on any subsequent call to an hwrm command\n-\t * that takes a queue id.\n-\t * # IDs must always be queried by this command before any use\n-\t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n-\t * # A value of 0xff indicates that the queue is not available.\n-\t * # Available queues may not be in sequential order.\n+\t * If the LED #1 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED on between cycles.\n \t */\n-\tuint8_t\tqueue_id2;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tqueue_id2_service_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \\\n-\t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n-\t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \\\n-\t\tUINT32_C(0x3)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN\n+\tuint16_t\tled1_blink_on;\n \t/*\n-\t * ID of CoS Queue 3.\n-\t * FF - Invalid id\n-\t *\n-\t * # This ID can be used on any subsequent call to an hwrm command\n-\t * that takes a queue id.\n-\t * # IDs must always be queried by this command before any use\n-\t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n-\t * # A value of 0xff indicates that the queue is not available.\n-\t * # Available queues may not be in sequential order.\n+\t * If the LED #1 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED off between cycles.\n \t */\n-\tuint8_t\tqueue_id3;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tqueue_id3_service_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \\\n-\t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n-\t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \\\n-\t\tUINT32_C(0x3)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN\n+\tuint16_t\tled1_blink_off;\n \t/*\n-\t * ID of CoS Queue 4.\n-\t * FF - Invalid id\n-\t *\n-\t * # This ID can be used on any subsequent call to an hwrm command\n-\t * that takes a queue id.\n-\t * # IDs must always be queried by this command before any use\n-\t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n-\t * # A value of 0xff indicates that the queue is not available.\n-\t * # Available queues may not be in sequential order.\n+\t * An identifier for the group of LEDs that LED #1 belongs\n+\t * to.\n+\t * If set to 0, then the LED #1 shall not be grouped and\n+\t * shall be treated as an individual resource.\n+\t * For all other non-zero values of this field, LED #1 shall\n+\t * be grouped together with the LEDs with the same group ID\n+\t * value.\n \t */\n-\tuint8_t\tqueue_id4;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tqueue_id4_service_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \\\n-\t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n-\t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \\\n-\t\tUINT32_C(0x3)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN\n+\tuint8_t\tled1_group_id;\n+\t/* Reserved field. */\n+\tuint8_t\trsvd1;\n+\t/* An identifier for the LED #2. */\n+\tuint8_t\tled2_id;\n+\t/* The requested state of the LED #2. */\n+\tuint8_t\tled2_state;\n+\t/* Default state of the LED */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_DEFAULT UINT32_C(0x0)\n+\t/* Off */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_OFF UINT32_C(0x1)\n+\t/* On */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_ON UINT32_C(0x2)\n+\t/* Blink */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINK UINT32_C(0x3)\n+\t/* Blink Alternately */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT UINT32_C(0x4)\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_STATE_LAST \\\n+\t\tHWRM_PORT_LED_CFG_INPUT_LED2_STATE_BLINKALT\n+\t/* The requested color of LED #2. */\n+\tuint8_t\tled2_color;\n+\t/* Default */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)\n+\t/* Amber */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_AMBER UINT32_C(0x1)\n+\t/* Green */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREEN UINT32_C(0x2)\n+\t/* Green or Amber */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED2_COLOR_LAST \\\n+\t\tHWRM_PORT_LED_CFG_INPUT_LED2_COLOR_GREENAMBER\n+\tuint8_t\tunused_2;\n \t/*\n-\t * ID of CoS Queue 5.\n-\t * FF - Invalid id\n-\t *\n-\t * # This ID can be used on any subsequent call to an hwrm command\n-\t * that takes a queue id.\n-\t * # IDs must always be queried by this command before any use\n-\t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n-\t * # A value of 0xff indicates that the queue is not available.\n-\t * # Available queues may not be in sequential order.\n+\t * If the LED #2 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED on between cycles.\n \t */\n-\tuint8_t\tqueue_id5;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tqueue_id5_service_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \\\n-\t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n-\t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \\\n-\t\tUINT32_C(0x3)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN\n+\tuint16_t\tled2_blink_on;\n \t/*\n-\t * ID of CoS Queue 6.\n-\t * FF - Invalid id\n-\t *\n-\t * # This ID can be used on any subsequent call to an hwrm command\n-\t * that takes a queue id.\n-\t * # IDs must always be queried by this command before any use\n-\t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n-\t * # A value of 0xff indicates that the queue is not available.\n-\t * # Available queues may not be in sequential order.\n+\t * If the LED #2 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED off between cycles.\n \t */\n-\tuint8_t\tqueue_id6;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tqueue_id6_service_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \\\n-\t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n-\t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \\\n-\t\tUINT32_C(0x3)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN\n+\tuint16_t\tled2_blink_off;\n \t/*\n-\t * ID of CoS Queue 7.\n-\t * FF - Invalid id\n-\t *\n-\t * # This ID can be used on any subsequent call to an hwrm command\n-\t * that takes a queue id.\n-\t * # IDs must always be queried by this command before any use\n-\t * by the driver or software.\n-\t * # Any driver or software should not make any assumptions about\n-\t * queue IDs.\n-\t * # A value of 0xff indicates that the queue is not available.\n-\t * # Available queues may not be in sequential order.\n+\t * An identifier for the group of LEDs that LED #2 belongs\n+\t * to.\n+\t * If set to 0, then the LED #2 shall not be grouped and\n+\t * shall be treated as an individual resource.\n+\t * For all other non-zero values of this field, LED #2 shall\n+\t * be grouped together with the LEDs with the same group ID\n+\t * value.\n \t */\n-\tuint8_t\tqueue_id7;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tqueue_id7_service_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \\\n-\t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \\\n-\t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n-\t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \\\n-\t\tUINT32_C(0x3)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN\n+\tuint8_t\tled2_group_id;\n+\t/* Reserved field. */\n+\tuint8_t\trsvd2;\n+\t/* An identifier for the LED #3. */\n+\tuint8_t\tled3_id;\n+\t/* The requested state of the LED #3. */\n+\tuint8_t\tled3_state;\n+\t/* Default state of the LED */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_DEFAULT UINT32_C(0x0)\n+\t/* Off */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_OFF UINT32_C(0x1)\n+\t/* On */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_ON UINT32_C(0x2)\n+\t/* Blink */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINK UINT32_C(0x3)\n+\t/* Blink Alternately */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT UINT32_C(0x4)\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_STATE_LAST \\\n+\t\tHWRM_PORT_LED_CFG_INPUT_LED3_STATE_BLINKALT\n+\t/* The requested color of LED #3. */\n+\tuint8_t\tled3_color;\n+\t/* Default */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)\n+\t/* Amber */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_AMBER UINT32_C(0x1)\n+\t/* Green */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREEN UINT32_C(0x2)\n+\t/* Green or Amber */\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)\n+\t#define HWRM_PORT_LED_CFG_INPUT_LED3_COLOR_LAST \\\n+\t\tHWRM_PORT_LED_CFG_INPUT_LED3_COLOR_GREENAMBER\n+\tuint8_t\tunused_3;\n+\t/*\n+\t * If the LED #3 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED on between cycles.\n+\t */\n+\tuint16_t\tled3_blink_on;\n+\t/*\n+\t * If the LED #3 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED off between cycles.\n+\t */\n+\tuint16_t\tled3_blink_off;\n+\t/*\n+\t * An identifier for the group of LEDs that LED #3 belongs\n+\t * to.\n+\t * If set to 0, then the LED #3 shall not be grouped and\n+\t * shall be treated as an individual resource.\n+\t * For all other non-zero values of this field, LED #3 shall\n+\t * be grouped together with the LEDs with the same group ID\n+\t * value.\n+\t */\n+\tuint8_t\tled3_group_id;\n+\t/* Reserved field. */\n+\tuint8_t\trsvd3;\n+} __attribute__((packed));\n+\n+/* hwrm_port_led_cfg_output (size:128b/16B) */\n+struct hwrm_port_led_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -14290,13 +14260,13 @@ struct hwrm_queue_qportcfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************\n- * hwrm_queue_qcfg *\n- *******************/\n+/**********************\n+ * hwrm_port_led_qcfg *\n+ **********************/\n \n \n-/* hwrm_queue_qcfg_input (size:192b/24B) */\n-struct hwrm_queue_qcfg_input {\n+/* hwrm_port_led_qcfg_input (size:192b/24B) */\n+struct hwrm_port_led_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -14324,25 +14294,13 @@ struct hwrm_queue_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n-\t */\n-\t#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX\n-\t/* Queue ID of the queue. */\n-\tuint32_t\tqueue_id;\n+\t/* Port ID of port whose LED configuration is being queried. */\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_queue_qcfg_output (size:128b/16B) */\n-struct hwrm_queue_qcfg_output {\n+/* hwrm_port_led_qcfg_output (size:448b/56B) */\n+struct hwrm_port_led_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -14352,134 +14310,251 @@ struct hwrm_queue_qcfg_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * This value is a the estimate packet length used in the\n-\t * TX arbiter.\n-\t */\n-\tuint32_t\tqueue_len;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tservice_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)\n-\t/* Lossless */\n-\t#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)\n-\t#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN\n-\t/* Information about queue configuration. */\n-\tuint8_t\tqueue_cfg_info;\n-\t/*\n-\t * If this flag is set to '1', then the queue is\n-\t * configured asymmetrically on TX and RX sides.\n-\t * If this flag is set to '0', then this queue is\n-\t * configured symmetrically on TX and RX sides.\n+\t * The number of LEDs that are configured on this port.\n+\t * Up to 4 LEDs can be returned in the response.\n \t */\n-\t#define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \\\n-\t\tUINT32_C(0x1)\n+\tuint8_t\tnum_leds;\n+\t/* An identifier for the LED #0. */\n+\tuint8_t\tled0_id;\n+\t/* The type of LED #0. */\n+\tuint8_t\tled0_type;\n+\t/* Speed LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)\n+\t/* Activity LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)\n+\t/* Invalid */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED0_TYPE_INVALID\n+\t/* The current state of the LED #0. */\n+\tuint8_t\tled0_state;\n+\t/* Default state of the LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT UINT32_C(0x0)\n+\t/* Off */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_OFF UINT32_C(0x1)\n+\t/* On */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_ON UINT32_C(0x2)\n+\t/* Blink */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINK UINT32_C(0x3)\n+\t/* Blink Alternately */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT UINT32_C(0x4)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT\n+\t/* The color of LED #0. */\n+\tuint8_t\tled0_color;\n+\t/* Default */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_DEFAULT UINT32_C(0x0)\n+\t/* Amber */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_AMBER UINT32_C(0x1)\n+\t/* Green */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREEN UINT32_C(0x2)\n+\t/* Green or Amber */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER UINT32_C(0x3)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED0_COLOR_GREENAMBER\n \tuint8_t\tunused_0;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * If the LED #0 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED on between cycles.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/******************\n- * hwrm_queue_cfg *\n- ******************/\n-\n-\n-/* hwrm_queue_cfg_input (size:320b/40B) */\n-struct hwrm_queue_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint16_t\tled0_blink_on;\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * If the LED #0 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED off between cycles.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint16_t\tled0_blink_off;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * An identifier for the group of LEDs that LED #0 belongs\n+\t * to.\n+\t * If set to 0, then the LED #0 is not grouped.\n+\t * For all other non-zero values of this field, LED #0 is\n+\t * grouped together with the LEDs with the same group ID\n+\t * value.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint8_t\tled0_group_id;\n+\t/* An identifier for the LED #1. */\n+\tuint8_t\tled1_id;\n+\t/* The type of LED #1. */\n+\tuint8_t\tled1_type;\n+\t/* Speed LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)\n+\t/* Activity LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)\n+\t/* Invalid */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED1_TYPE_INVALID\n+\t/* The current state of the LED #1. */\n+\tuint8_t\tled1_state;\n+\t/* Default state of the LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_DEFAULT UINT32_C(0x0)\n+\t/* Off */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_OFF UINT32_C(0x1)\n+\t/* On */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_ON UINT32_C(0x2)\n+\t/* Blink */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINK UINT32_C(0x3)\n+\t/* Blink Alternately */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT UINT32_C(0x4)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED1_STATE_BLINKALT\n+\t/* The color of LED #1. */\n+\tuint8_t\tled1_color;\n+\t/* Default */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_DEFAULT UINT32_C(0x0)\n+\t/* Amber */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_AMBER UINT32_C(0x1)\n+\t/* Green */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREEN UINT32_C(0x2)\n+\t/* Green or Amber */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER UINT32_C(0x3)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED1_COLOR_GREENAMBER\n+\tuint8_t\tunused_1;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * If the LED #1 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED on between cycles.\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint16_t\tled1_blink_on;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * If the LED #1 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED off between cycles.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n+\tuint16_t\tled1_blink_off;\n \t/*\n-\t * Enumeration denoting the RX, TX, or both directions applicable to the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n+\t * An identifier for the group of LEDs that LED #1 belongs\n+\t * to.\n+\t * If set to 0, then the LED #1 is not grouped.\n+\t * For all other non-zero values of this field, LED #1 is\n+\t * grouped together with the LEDs with the same group ID\n+\t * value.\n \t */\n-\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)\n-\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0\n-\t/* tx path */\n-\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t/* Bi-directional (Symmetrically applicable to TX and RX paths) */\n-\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)\n-\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR\n-\tuint32_t\tenables;\n+\tuint8_t\tled1_group_id;\n+\t/* An identifier for the LED #2. */\n+\tuint8_t\tled2_id;\n+\t/* The type of LED #2. */\n+\tuint8_t\tled2_type;\n+\t/* Speed LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)\n+\t/* Activity LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)\n+\t/* Invalid */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED2_TYPE_INVALID\n+\t/* The current state of the LED #2. */\n+\tuint8_t\tled2_state;\n+\t/* Default state of the LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_DEFAULT UINT32_C(0x0)\n+\t/* Off */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_OFF UINT32_C(0x1)\n+\t/* On */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_ON UINT32_C(0x2)\n+\t/* Blink */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINK UINT32_C(0x3)\n+\t/* Blink Alternately */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT UINT32_C(0x4)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED2_STATE_BLINKALT\n+\t/* The color of LED #2. */\n+\tuint8_t\tled2_color;\n+\t/* Default */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_DEFAULT UINT32_C(0x0)\n+\t/* Amber */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_AMBER UINT32_C(0x1)\n+\t/* Green */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREEN UINT32_C(0x2)\n+\t/* Green or Amber */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER UINT32_C(0x3)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED2_COLOR_GREENAMBER\n+\tuint8_t\tunused_2;\n \t/*\n-\t * This bit must be '1' for the dflt_len field to be\n-\t * configured.\n+\t * If the LED #2 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED on between cycles.\n \t */\n-\t#define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)\n+\tuint16_t\tled2_blink_on;\n \t/*\n-\t * This bit must be '1' for the service_profile field to be\n-\t * configured.\n+\t * If the LED #2 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED off between cycles.\n \t */\n-\t#define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)\n-\t/* Queue ID of queue that is to be configured by this function. */\n-\tuint32_t\tqueue_id;\n+\tuint16_t\tled2_blink_off;\n \t/*\n-\t * This value is a the estimate packet length used in the\n-\t * TX arbiter.\n-\t * Set to 0xFF... (All Fs) to not adjust this value.\n+\t * An identifier for the group of LEDs that LED #2 belongs\n+\t * to.\n+\t * If set to 0, then the LED #2 is not grouped.\n+\t * For all other non-zero values of this field, LED #2 is\n+\t * grouped together with the LEDs with the same group ID\n+\t * value.\n \t */\n-\tuint32_t\tdflt_len;\n-\t/* This value is applicable to CoS queues only. */\n-\tuint8_t\tservice_profile;\n-\t/* Lossy (best-effort) */\n-\t#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)\n-\t/* Lossless */\n-\t#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)\n-\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n-\t#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)\n-\t#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \\\n-\t\tHWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN\n-\tuint8_t\tunused_0[7];\n-} __attribute__((packed));\n-\n-/* hwrm_queue_cfg_output (size:128b/16B) */\n-struct hwrm_queue_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint8_t\tled2_group_id;\n+\t/* An identifier for the LED #3. */\n+\tuint8_t\tled3_id;\n+\t/* The type of LED #3. */\n+\tuint8_t\tled3_type;\n+\t/* Speed LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)\n+\t/* Activity LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)\n+\t/* Invalid */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED3_TYPE_INVALID\n+\t/* The current state of the LED #3. */\n+\tuint8_t\tled3_state;\n+\t/* Default state of the LED */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_DEFAULT UINT32_C(0x0)\n+\t/* Off */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_OFF UINT32_C(0x1)\n+\t/* On */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_ON UINT32_C(0x2)\n+\t/* Blink */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINK UINT32_C(0x3)\n+\t/* Blink Alternately */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT UINT32_C(0x4)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED3_STATE_BLINKALT\n+\t/* The color of LED #3. */\n+\tuint8_t\tled3_color;\n+\t/* Default */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_DEFAULT UINT32_C(0x0)\n+\t/* Amber */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_AMBER UINT32_C(0x1)\n+\t/* Green */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREEN UINT32_C(0x2)\n+\t/* Green or Amber */\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER UINT32_C(0x3)\n+\t#define HWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_LAST \\\n+\t\tHWRM_PORT_LED_QCFG_OUTPUT_LED3_COLOR_GREENAMBER\n+\tuint8_t\tunused_3;\n+\t/*\n+\t * If the LED #3 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED on between cycles.\n+\t */\n+\tuint16_t\tled3_blink_on;\n+\t/*\n+\t * If the LED #3 state is \"blink\" or \"blinkalt\", then\n+\t * this field represents the requested time in milliseconds\n+\t * to keep LED off between cycles.\n+\t */\n+\tuint16_t\tled3_blink_off;\n+\t/*\n+\t * An identifier for the group of LEDs that LED #3 belongs\n+\t * to.\n+\t * If set to 0, then the LED #3 is not grouped.\n+\t * For all other non-zero values of this field, LED #3 is\n+\t * grouped together with the LEDs with the same group ID\n+\t * value.\n+\t */\n+\tuint8_t\tled3_group_id;\n+\tuint8_t\tunused_4[6];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -14490,13 +14565,13 @@ struct hwrm_queue_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*****************************\n- * hwrm_queue_pfcenable_qcfg *\n- *****************************/\n+/***********************\n+ * hwrm_port_led_qcaps *\n+ ***********************/\n \n \n-/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */\n-struct hwrm_queue_pfcenable_qcfg_input {\n+/* hwrm_port_led_qcaps_input (size:192b/24B) */\n+struct hwrm_port_led_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -14524,17 +14599,13 @@ struct hwrm_queue_pfcenable_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Port ID of port for which the table is being configured.\n-\t * The HWRM needs to check whether this function is allowed\n-\t * to configure pri2cos mapping on this port.\n-\t */\n+\t/* Port ID of port whose LED configuration is being queried. */\n \tuint16_t\tport_id;\n \tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */\n-struct hwrm_queue_pfcenable_qcfg_output {\n+/* hwrm_port_led_qcaps_output (size:384b/48B) */\n+struct hwrm_port_led_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -14543,121 +14614,298 @@ struct hwrm_queue_pfcenable_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint32_t\tflags;\n-\t/* If set to 1, then PFC is enabled on PRI 0. */\n-\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \\\n-\t\tUINT32_C(0x1)\n-\t/* If set to 1, then PFC is enabled on PRI 1. */\n-\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \\\n-\t\tUINT32_C(0x2)\n-\t/* If set to 1, then PFC is enabled on PRI 2. */\n-\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \\\n-\t\tUINT32_C(0x4)\n-\t/* If set to 1, then PFC is enabled on PRI 3. */\n-\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \\\n-\t\tUINT32_C(0x8)\n-\t/* If set to 1, then PFC is enabled on PRI 4. */\n-\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \\\n-\t\tUINT32_C(0x10)\n-\t/* If set to 1, then PFC is enabled on PRI 5. */\n-\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \\\n-\t\tUINT32_C(0x20)\n-\t/* If set to 1, then PFC is enabled on PRI 6. */\n-\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \\\n-\t\tUINT32_C(0x40)\n-\t/* If set to 1, then PFC is enabled on PRI 7. */\n-\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \\\n-\t\tUINT32_C(0x80)\n-\tuint8_t\tunused_0[3];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * The number of LEDs that are configured on this port.\n+\t * Up to 4 LEDs can be returned in the response.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/****************************\n- * hwrm_queue_pfcenable_cfg *\n- ****************************/\n-\n-\n-/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */\n-struct hwrm_queue_pfcenable_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint8_t\tnum_leds;\n+\t/* Reserved for future use. */\n+\tuint8_t\tunused[3];\n+\t/* An identifier for the LED #0. */\n+\tuint8_t\tled0_id;\n+\t/* The type of LED #0. */\n+\tuint8_t\tled0_type;\n+\t/* Speed LED */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_SPEED UINT32_C(0x0)\n+\t/* Activity LED */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_ACTIVITY UINT32_C(0x1)\n+\t/* Invalid */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID UINT32_C(0xff)\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_LAST \\\n+\t\tHWRM_PORT_LED_QCAPS_OUTPUT_LED0_TYPE_INVALID\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * An identifier for the group of LEDs that LED #0 belongs\n+\t * to.\n+\t * If set to 0, then the LED #0 cannot be grouped.\n+\t * For all other non-zero values of this field, LED #0 is\n+\t * grouped together with the LEDs with the same group ID\n+\t * value.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint8_t\tled0_group_id;\n+\tuint8_t\tunused_0;\n+\t/* The states supported by LED #0. */\n+\tuint16_t\tled0_state_caps;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * If set to 1, this LED is enabled.\n+\t * If set to 0, this LED is disabled.\n \t */\n-\tuint16_t\tseq_id;\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ENABLED \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * If set to 1, off state is supported on this LED.\n+\t * If set to 0, off state is not supported on this LED.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_OFF_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * If set to 1, on state is supported on this LED.\n+\t * If set to 0, on state is not supported on this LED.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/* If set to 1, then PFC is requested to be enabled on PRI 0. */\n-\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \\\n-\t\tUINT32_C(0x1)\n-\t/* If set to 1, then PFC is requested to be enabled on PRI 1. */\n-\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \\\n-\t\tUINT32_C(0x2)\n-\t/* If set to 1, then PFC is requested to be enabled on PRI 2. */\n-\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \\\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_ON_SUPPORTED \\\n \t\tUINT32_C(0x4)\n-\t/* If set to 1, then PFC is requested to be enabled on PRI 3. */\n-\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \\\n+\t/*\n+\t * If set to 1, blink state is supported on this LED.\n+\t * If set to 0, blink state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_SUPPORTED \\\n \t\tUINT32_C(0x8)\n-\t/* If set to 1, then PFC is requested to be enabled on PRI 4. */\n-\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \\\n+\t/*\n+\t * If set to 1, blink_alt state is supported on this LED.\n+\t * If set to 0, blink_alt state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED \\\n \t\tUINT32_C(0x10)\n-\t/* If set to 1, then PFC is requested to be enabled on PRI 5. */\n-\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \\\n-\t\tUINT32_C(0x20)\n-\t/* If set to 1, then PFC is requested to be enabled on PRI 6. */\n-\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \\\n-\t\tUINT32_C(0x40)\n-\t/* If set to 1, then PFC is requested to be enabled on PRI 7. */\n-\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \\\n-\t\tUINT32_C(0x80)\n+\t/* The colors supported by LED #0. */\n+\tuint16_t\tled0_color_caps;\n+\t/* reserved. */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_RSVD \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * Port ID of port for which the table is being configured.\n-\t * The HWRM needs to check whether this function is allowed\n-\t * to configure pri2cos mapping on this port.\n+\t * If set to 1, Amber color is supported on this LED.\n+\t * If set to 0, Amber color is not supported on this LED.\n \t */\n-\tuint16_t\tport_id;\n-\tuint8_t\tunused_0[2];\n-} __attribute__((packed));\n-\n-/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */\n-struct hwrm_queue_pfcenable_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_AMBER_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, Green color is supported on this LED.\n+\t * If set to 0, Green color is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED0_COLOR_CAPS_GREEN_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/* An identifier for the LED #1. */\n+\tuint8_t\tled1_id;\n+\t/* The type of LED #1. */\n+\tuint8_t\tled1_type;\n+\t/* Speed LED */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_SPEED UINT32_C(0x0)\n+\t/* Activity LED */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_ACTIVITY UINT32_C(0x1)\n+\t/* Invalid */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID UINT32_C(0xff)\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_LAST \\\n+\t\tHWRM_PORT_LED_QCAPS_OUTPUT_LED1_TYPE_INVALID\n+\t/*\n+\t * An identifier for the group of LEDs that LED #1 belongs\n+\t * to.\n+\t * If set to 0, then the LED #0 cannot be grouped.\n+\t * For all other non-zero values of this field, LED #0 is\n+\t * grouped together with the LEDs with the same group ID\n+\t * value.\n+\t */\n+\tuint8_t\tled1_group_id;\n+\tuint8_t\tunused_1;\n+\t/* The states supported by LED #1. */\n+\tuint16_t\tled1_state_caps;\n+\t/*\n+\t * If set to 1, this LED is enabled.\n+\t * If set to 0, this LED is disabled.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ENABLED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, off state is supported on this LED.\n+\t * If set to 0, off state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_OFF_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, on state is supported on this LED.\n+\t * If set to 0, on state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_ON_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, blink state is supported on this LED.\n+\t * If set to 0, blink state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, blink_alt state is supported on this LED.\n+\t * If set to 0, blink_alt state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED \\\n+\t\tUINT32_C(0x10)\n+\t/* The colors supported by LED #1. */\n+\tuint16_t\tled1_color_caps;\n+\t/* reserved. */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_RSVD \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, Amber color is supported on this LED.\n+\t * If set to 0, Amber color is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_AMBER_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, Green color is supported on this LED.\n+\t * If set to 0, Green color is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED1_COLOR_CAPS_GREEN_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/* An identifier for the LED #2. */\n+\tuint8_t\tled2_id;\n+\t/* The type of LED #2. */\n+\tuint8_t\tled2_type;\n+\t/* Speed LED */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_SPEED UINT32_C(0x0)\n+\t/* Activity LED */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_ACTIVITY UINT32_C(0x1)\n+\t/* Invalid */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID UINT32_C(0xff)\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_LAST \\\n+\t\tHWRM_PORT_LED_QCAPS_OUTPUT_LED2_TYPE_INVALID\n+\t/*\n+\t * An identifier for the group of LEDs that LED #0 belongs\n+\t * to.\n+\t * If set to 0, then the LED #0 cannot be grouped.\n+\t * For all other non-zero values of this field, LED #0 is\n+\t * grouped together with the LEDs with the same group ID\n+\t * value.\n+\t */\n+\tuint8_t\tled2_group_id;\n+\tuint8_t\tunused_2;\n+\t/* The states supported by LED #2. */\n+\tuint16_t\tled2_state_caps;\n+\t/*\n+\t * If set to 1, this LED is enabled.\n+\t * If set to 0, this LED is disabled.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ENABLED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, off state is supported on this LED.\n+\t * If set to 0, off state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_OFF_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, on state is supported on this LED.\n+\t * If set to 0, on state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_ON_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, blink state is supported on this LED.\n+\t * If set to 0, blink state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, blink_alt state is supported on this LED.\n+\t * If set to 0, blink_alt state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED \\\n+\t\tUINT32_C(0x10)\n+\t/* The colors supported by LED #2. */\n+\tuint16_t\tled2_color_caps;\n+\t/* reserved. */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_RSVD \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, Amber color is supported on this LED.\n+\t * If set to 0, Amber color is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_AMBER_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, Green color is supported on this LED.\n+\t * If set to 0, Green color is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED2_COLOR_CAPS_GREEN_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/* An identifier for the LED #3. */\n+\tuint8_t\tled3_id;\n+\t/* The type of LED #3. */\n+\tuint8_t\tled3_type;\n+\t/* Speed LED */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_SPEED UINT32_C(0x0)\n+\t/* Activity LED */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_ACTIVITY UINT32_C(0x1)\n+\t/* Invalid */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID UINT32_C(0xff)\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_LAST \\\n+\t\tHWRM_PORT_LED_QCAPS_OUTPUT_LED3_TYPE_INVALID\n+\t/*\n+\t * An identifier for the group of LEDs that LED #3 belongs\n+\t * to.\n+\t * If set to 0, then the LED #0 cannot be grouped.\n+\t * For all other non-zero values of this field, LED #0 is\n+\t * grouped together with the LEDs with the same group ID\n+\t * value.\n+\t */\n+\tuint8_t\tled3_group_id;\n+\tuint8_t\tunused_3;\n+\t/* The states supported by LED #3. */\n+\tuint16_t\tled3_state_caps;\n+\t/*\n+\t * If set to 1, this LED is enabled.\n+\t * If set to 0, this LED is disabled.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ENABLED \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, off state is supported on this LED.\n+\t * If set to 0, off state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_OFF_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, on state is supported on this LED.\n+\t * If set to 0, on state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_ON_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If set to 1, blink state is supported on this LED.\n+\t * If set to 0, blink state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_SUPPORTED \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * If set to 1, blink_alt state is supported on this LED.\n+\t * If set to 0, blink_alt state is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED \\\n+\t\tUINT32_C(0x10)\n+\t/* The colors supported by LED #3. */\n+\tuint16_t\tled3_color_caps;\n+\t/* reserved. */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_RSVD \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If set to 1, Amber color is supported on this LED.\n+\t * If set to 0, Amber color is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_AMBER_SUPPORTED \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If set to 1, Green color is supported on this LED.\n+\t * If set to 0, Green color is not supported on this LED.\n+\t */\n+\t#define HWRM_PORT_LED_QCAPS_OUTPUT_LED3_COLOR_CAPS_GREEN_SUPPORTED \\\n+\t\tUINT32_C(0x4)\n+\tuint8_t\tunused_4[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -14668,13 +14916,13 @@ struct hwrm_queue_pfcenable_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***************************\n- * hwrm_queue_pri2cos_qcfg *\n- ***************************/\n+/***********************\n+ * hwrm_queue_qportcfg *\n+ ***********************/\n \n \n-/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */\n-struct hwrm_queue_pri2cos_qcfg_input {\n+/* hwrm_queue_qportcfg_input (size:192b/24B) */\n+struct hwrm_queue_qportcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -14708,31 +14956,34 @@ struct hwrm_queue_pri2cos_qcfg_input {\n \t * This enumeration is used for resources that are similar for both\n \t * TX and RX paths of the chip.\n \t */\n-\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)\n+\t#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH UINT32_C(0x1)\n \t/* tx path */\n-\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n+\t#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n \t/* rx path */\n-\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX\n+\t#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n+\t#define HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX\n \t/*\n-\t * When this bit is set to '0', the query is\n-\t * for VLAN PRI field in tunnel headers.\n-\t * When this bit is set to '1', the query is\n-\t * for VLAN PRI field in inner packet headers.\n+\t * Port ID of port for which the queue configuration is being\n+\t * queried. This field is only required when sent by IPC.\n \t */\n-\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)\n+\tuint16_t\tport_id;\n \t/*\n-\t * Port ID of port for which the table is being configured.\n-\t * The HWRM needs to check whether this function is allowed\n-\t * to configure pri2cos mapping on this port.\n+\t * Drivers will set this capability when it can use\n+\t * queue_idx_service_profile to map the queues to application.\n \t */\n-\tuint8_t\tport_id;\n-\tuint8_t\tunused_0[3];\n+\tuint8_t\tdrv_qmap_cap;\n+\t/* disabled */\n+\t#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_DISABLED UINT32_C(0x0)\n+\t/* enabled */\n+\t#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED UINT32_C(0x1)\n+\t#define HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED\n+\tuint8_t\tunused_0;\n } __attribute__((packed));\n \n-/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */\n-struct hwrm_queue_pri2cos_qcfg_output {\n+/* hwrm_queue_qportcfg_output (size:256b/32B) */\n+struct hwrm_queue_qportcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -14742,239 +14993,562 @@ struct hwrm_queue_pri2cos_qcfg_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * CoS Queue assigned to priority 0. This value can only\n-\t * be changed before traffic has started.\n-\t * A value of 0xff indicates that no CoS queue is assigned to the\n-\t * specified priority.\n-\t */\n-\tuint8_t\tpri0_cos_queue_id;\n-\t/*\n-\t * CoS Queue assigned to priority 1. This value can only\n-\t * be changed before traffic has started.\n-\t * A value of 0xff indicates that no CoS queue is assigned to the\n-\t * specified priority.\n-\t */\n-\tuint8_t\tpri1_cos_queue_id;\n-\t/*\n-\t * CoS Queue assigned to priority 2 This value can only\n-\t * be changed before traffic has started.\n-\t * A value of 0xff indicates that no CoS queue is assigned to the\n-\t * specified priority.\n-\t */\n-\tuint8_t\tpri2_cos_queue_id;\n-\t/*\n-\t * CoS Queue assigned to priority 3. This value can only\n-\t * be changed before traffic has started.\n-\t * A value of 0xff indicates that no CoS queue is assigned to the\n-\t * specified priority.\n-\t */\n-\tuint8_t\tpri3_cos_queue_id;\n-\t/*\n-\t * CoS Queue assigned to priority 4. This value can only\n-\t * be changed before traffic has started.\n-\t * A value of 0xff indicates that no CoS queue is assigned to the\n-\t * specified priority.\n-\t */\n-\tuint8_t\tpri4_cos_queue_id;\n-\t/*\n-\t * CoS Queue assigned to priority 5. This value can only\n-\t * be changed before traffic has started.\n-\t * A value of 0xff indicates that no CoS queue is assigned to the\n-\t * specified priority.\n+\t * The maximum number of queues that can be configured on this\n+\t * port.\n+\t * Valid values range from 1 through 8.\n \t */\n-\tuint8_t\tpri5_cos_queue_id;\n+\tuint8_t\tmax_configurable_queues;\n \t/*\n-\t * CoS Queue assigned to priority 6. This value can only\n-\t * be changed before traffic has started.\n-\t * A value of 0xff indicates that no CoS queue is assigned to the\n-\t * specified priority.\n+\t * The maximum number of lossless queues that can be configured\n+\t * on this port.\n+\t * Valid values range from 0 through 8.\n \t */\n-\tuint8_t\tpri6_cos_queue_id;\n+\tuint8_t\tmax_configurable_lossless_queues;\n \t/*\n-\t * CoS Queue assigned to priority 7. This value can only\n-\t * be changed before traffic has started.\n-\t * A value of 0xff indicates that no CoS queue is assigned to the\n-\t * specified priority.\n+\t * Bitmask indicating which queues can be configured by the\n+\t * hwrm_queue_cfg command.\n+\t *\n+\t * Each bit represents a specific queue where bit 0 represents\n+\t * queue 0 and bit 7 represents queue 7.\n+\t * # A value of 0 indicates that the queue is not configurable\n+\t * by the hwrm_queue_cfg command.\n+\t * # A value of 1 indicates that the queue is configurable.\n+\t * # A hwrm_queue_cfg command shall return error when trying to\n+\t * configure a queue not configurable.\n \t */\n-\tuint8_t\tpri7_cos_queue_id;\n+\tuint8_t\tqueue_cfg_allowed;\n \t/* Information about queue configuration. */\n \tuint8_t\tqueue_cfg_info;\n \t/*\n-\t * If this flag is set to '1', then the PRI to CoS\n-\t * configuration is asymmetric on TX and RX sides.\n-\t * If this flag is set to '0', then PRI to CoS configuration\n-\t * is symmetric on TX and RX sides.\n+\t * If this flag is set to '1', then the queues are\n+\t * configured asymmetrically on TX and RX sides.\n+\t * If this flag is set to '0', then the queues are\n+\t * configured symmetrically on TX and RX sides. For\n+\t * symmetric configuration, the queue configuration\n+\t * including queue ids and service profiles on the\n+\t * TX side is the same as the corresponding queue\n+\t * configuration on the RX side.\n \t */\n-\t#define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \\\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \\\n \t\tUINT32_C(0x1)\n-\tuint8_t\tunused_0[6];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**************************\n- * hwrm_queue_pri2cos_cfg *\n- **************************/\n-\n-\n-/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */\n-struct hwrm_queue_pri2cos_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Bitmask indicating which queues can be configured by the\n+\t * hwrm_queue_pfcenable_cfg command.\n+\t *\n+\t * Each bit represents a specific priority where bit 0 represents\n+\t * priority 0 and bit 7 represents priority 7.\n+\t * # A value of 0 indicates that the priority is not configurable by\n+\t * the hwrm_queue_pfcenable_cfg command.\n+\t * # A value of 1 indicates that the priority is configurable.\n+\t * # A hwrm_queue_pfcenable_cfg command shall return error when\n+\t * trying to configure a priority that is not configurable.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n+\tuint8_t\tqueue_pfcenable_cfg_allowed;\n \t/*\n-\t * Enumeration denoting the RX, TX, or both directions applicable to the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n+\t * Bitmask indicating which queues can be configured by the\n+\t * hwrm_queue_pri2cos_cfg command.\n+\t *\n+\t * Each bit represents a specific queue where bit 0 represents\n+\t * queue 0 and bit 7 represents queue 7.\n+\t * # A value of 0 indicates that the queue is not configurable\n+\t * by the hwrm_queue_pri2cos_cfg command.\n+\t * # A value of 1 indicates that the queue is configurable.\n+\t * # A hwrm_queue_pri2cos_cfg command shall return error when\n+\t * trying to configure a queue that is not configurable.\n \t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0\n-\t/* tx path */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t/* Bi-directional (Symmetrically applicable to TX and RX paths) */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR\n+\tuint8_t\tqueue_pri2cos_cfg_allowed;\n \t/*\n-\t * When this bit is set to '0', the mapping is requested\n-\t * for VLAN PRI field in tunnel headers.\n-\t * When this bit is set to '1', the mapping is requested\n-\t * for VLAN PRI field in inner packet headers.\n+\t * Bitmask indicating which queues can be configured by the\n+\t * hwrm_queue_pri2cos_cfg command.\n+\t *\n+\t * Each bit represents a specific queue where bit 0 represents\n+\t * queue 0 and bit 7 represents queue 7.\n+\t * # A value of 0 indicates that the queue is not configurable\n+\t * by the hwrm_queue_pri2cos_cfg command.\n+\t * # A value of 1 indicates that the queue is configurable.\n+\t * # A hwrm_queue_pri2cos_cfg command shall return error when\n+\t * trying to configure a queue not configurable.\n \t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)\n-\tuint32_t\tenables;\n+\tuint8_t\tqueue_cos2bw_cfg_allowed;\n \t/*\n-\t * This bit must be '1' for the pri0_cos_queue_id field to be\n-\t * configured.\n+\t * ID of CoS Queue 0.\n+\t * FF - Invalid id\n+\t *\n+\t * # This ID can be used on any subsequent call to an hwrm command\n+\t * that takes a queue id.\n+\t * # IDs must always be queried by this command before any use\n+\t * by the driver or software.\n+\t * # Any driver or software should not make any assumptions about\n+\t * queue IDs.\n+\t * # A value of 0xff indicates that the queue is not available.\n+\t * # Available queues may not be in sequential order.\n \t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \\\n+\tuint8_t\tqueue_id0;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tqueue_id0_service_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \\\n+\t\tUINT32_C(0x0)\n+\t/* Lossless (legacy) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the pri1_cos_queue_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \\\n+\t/* Lossless RoCE */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossy RoCE CNP */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n \t\tUINT32_C(0x2)\n+\t/* Lossless NIC */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \\\n+\t\tUINT32_C(0x3)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN\n \t/*\n-\t * This bit must be '1' for the pri2_cos_queue_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * This bit must be '1' for the pri3_cos_queue_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * This bit must be '1' for the pri4_cos_queue_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * This bit must be '1' for the pri5_cos_queue_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * This bit must be '1' for the pri6_cos_queue_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * This bit must be '1' for the pri7_cos_queue_id field to be\n-\t * configured.\n+\t * ID of CoS Queue 1.\n+\t * FF - Invalid id\n+\t *\n+\t * # This ID can be used on any subsequent call to an hwrm command\n+\t * that takes a queue id.\n+\t * # IDs must always be queried by this command before any use\n+\t * by the driver or software.\n+\t * # Any driver or software should not make any assumptions about\n+\t * queue IDs.\n+\t * # A value of 0xff indicates that the queue is not available.\n+\t * # Available queues may not be in sequential order.\n \t */\n-\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \\\n-\t\tUINT32_C(0x80)\n+\tuint8_t\tqueue_id1;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tqueue_id1_service_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \\\n+\t\tUINT32_C(0x0)\n+\t/* Lossless (legacy) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossless RoCE */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossy RoCE CNP */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n+\t\tUINT32_C(0x2)\n+\t/* Lossless NIC */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \\\n+\t\tUINT32_C(0x3)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN\n \t/*\n-\t * Port ID of port for which the table is being configured.\n-\t * The HWRM needs to check whether this function is allowed\n-\t * to configure pri2cos mapping on this port.\n+\t * ID of CoS Queue 2.\n+\t * FF - Invalid id\n+\t *\n+\t * # This ID can be used on any subsequent call to an hwrm command\n+\t * that takes a queue id.\n+\t * # IDs must always be queried by this command before any use\n+\t * by the driver or software.\n+\t * # Any driver or software should not make any assumptions about\n+\t * queue IDs.\n+\t * # A value of 0xff indicates that the queue is not available.\n+\t * # Available queues may not be in sequential order.\n \t */\n-\tuint8_t\tport_id;\n+\tuint8_t\tqueue_id2;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tqueue_id2_service_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \\\n+\t\tUINT32_C(0x0)\n+\t/* Lossless (legacy) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossless RoCE */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossy RoCE CNP */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n+\t\tUINT32_C(0x2)\n+\t/* Lossless NIC */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \\\n+\t\tUINT32_C(0x3)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN\n \t/*\n-\t * CoS Queue assigned to priority 0. This value can only\n-\t * be changed before traffic has started.\n+\t * ID of CoS Queue 3.\n+\t * FF - Invalid id\n+\t *\n+\t * # This ID can be used on any subsequent call to an hwrm command\n+\t * that takes a queue id.\n+\t * # IDs must always be queried by this command before any use\n+\t * by the driver or software.\n+\t * # Any driver or software should not make any assumptions about\n+\t * queue IDs.\n+\t * # A value of 0xff indicates that the queue is not available.\n+\t * # Available queues may not be in sequential order.\n \t */\n-\tuint8_t\tpri0_cos_queue_id;\n+\tuint8_t\tqueue_id3;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tqueue_id3_service_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \\\n+\t\tUINT32_C(0x0)\n+\t/* Lossless (legacy) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossless RoCE */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossy RoCE CNP */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n+\t\tUINT32_C(0x2)\n+\t/* Lossless NIC */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \\\n+\t\tUINT32_C(0x3)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN\n \t/*\n-\t * CoS Queue assigned to priority 1. This value can only\n-\t * be changed before traffic has started.\n+\t * ID of CoS Queue 4.\n+\t * FF - Invalid id\n+\t *\n+\t * # This ID can be used on any subsequent call to an hwrm command\n+\t * that takes a queue id.\n+\t * # IDs must always be queried by this command before any use\n+\t * by the driver or software.\n+\t * # Any driver or software should not make any assumptions about\n+\t * queue IDs.\n+\t * # A value of 0xff indicates that the queue is not available.\n+\t * # Available queues may not be in sequential order.\n \t */\n-\tuint8_t\tpri1_cos_queue_id;\n+\tuint8_t\tqueue_id4;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tqueue_id4_service_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \\\n+\t\tUINT32_C(0x0)\n+\t/* Lossless (legacy) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossless RoCE */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossy RoCE CNP */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n+\t\tUINT32_C(0x2)\n+\t/* Lossless NIC */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \\\n+\t\tUINT32_C(0x3)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN\n \t/*\n-\t * CoS Queue assigned to priority 2 This value can only\n-\t * be changed before traffic has started.\n+\t * ID of CoS Queue 5.\n+\t * FF - Invalid id\n+\t *\n+\t * # This ID can be used on any subsequent call to an hwrm command\n+\t * that takes a queue id.\n+\t * # IDs must always be queried by this command before any use\n+\t * by the driver or software.\n+\t * # Any driver or software should not make any assumptions about\n+\t * queue IDs.\n+\t * # A value of 0xff indicates that the queue is not available.\n+\t * # Available queues may not be in sequential order.\n \t */\n-\tuint8_t\tpri2_cos_queue_id;\n+\tuint8_t\tqueue_id5;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tqueue_id5_service_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \\\n+\t\tUINT32_C(0x0)\n+\t/* Lossless (legacy) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossless RoCE */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossy RoCE CNP */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n+\t\tUINT32_C(0x2)\n+\t/* Lossless NIC */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \\\n+\t\tUINT32_C(0x3)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN\n \t/*\n-\t * CoS Queue assigned to priority 3. This value can only\n-\t * be changed before traffic has started.\n+\t * ID of CoS Queue 6.\n+\t * FF - Invalid id\n+\t *\n+\t * # This ID can be used on any subsequent call to an hwrm command\n+\t * that takes a queue id.\n+\t * # IDs must always be queried by this command before any use\n+\t * by the driver or software.\n+\t * # Any driver or software should not make any assumptions about\n+\t * queue IDs.\n+\t * # A value of 0xff indicates that the queue is not available.\n+\t * # Available queues may not be in sequential order.\n \t */\n-\tuint8_t\tpri3_cos_queue_id;\n+\tuint8_t\tqueue_id6;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tqueue_id6_service_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \\\n+\t\tUINT32_C(0x0)\n+\t/* Lossless (legacy) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossless RoCE */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossy RoCE CNP */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n+\t\tUINT32_C(0x2)\n+\t/* Lossless NIC */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \\\n+\t\tUINT32_C(0x3)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN\n \t/*\n-\t * CoS Queue assigned to priority 4. This value can only\n-\t * be changed before traffic has started.\n+\t * ID of CoS Queue 7.\n+\t * FF - Invalid id\n+\t *\n+\t * # This ID can be used on any subsequent call to an hwrm command\n+\t * that takes a queue id.\n+\t * # IDs must always be queried by this command before any use\n+\t * by the driver or software.\n+\t * # Any driver or software should not make any assumptions about\n+\t * queue IDs.\n+\t * # A value of 0xff indicates that the queue is not available.\n+\t * # Available queues may not be in sequential order.\n \t */\n-\tuint8_t\tpri4_cos_queue_id;\n+\tuint8_t\tqueue_id7;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tqueue_id7_service_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \\\n+\t\tUINT32_C(0x0)\n+\t/* Lossless (legacy) */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossless RoCE */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Lossy RoCE CNP */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n+\t\tUINT32_C(0x2)\n+\t/* Lossless NIC */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \\\n+\t\tUINT32_C(0x3)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN\n \t/*\n-\t * CoS Queue assigned to priority 5. This value can only\n-\t * be changed before traffic has started.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\tpri5_cos_queue_id;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/*******************\n+ * hwrm_queue_qcfg *\n+ *******************/\n+\n+\n+/* hwrm_queue_qcfg_input (size:192b/24B) */\n+struct hwrm_queue_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * CoS Queue assigned to priority 6. This value can only\n-\t * be changed before traffic has started.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint8_t\tpri6_cos_queue_id;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * CoS Queue assigned to priority 7. This value can only\n-\t * be changed before traffic has started.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint8_t\tpri7_cos_queue_id;\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/*\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n+\t#define HWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_QUEUE_QCFG_INPUT_FLAGS_PATH_RX\n+\t/* Queue ID of the queue. */\n+\tuint32_t\tqueue_id;\n+} __attribute__((packed));\n+\n+/* hwrm_queue_qcfg_output (size:128b/16B) */\n+struct hwrm_queue_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * This value is a the estimate packet length used in the\n+\t * TX arbiter.\n+\t */\n+\tuint32_t\tqueue_len;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tservice_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)\n+\t/* Lossless */\n+\t#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)\n+\t#define HWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_QCFG_OUTPUT_SERVICE_PROFILE_UNKNOWN\n+\t/* Information about queue configuration. */\n+\tuint8_t\tqueue_cfg_info;\n+\t/*\n+\t * If this flag is set to '1', then the queue is\n+\t * configured asymmetrically on TX and RX sides.\n+\t * If this flag is set to '0', then this queue is\n+\t * configured symmetrically on TX and RX sides.\n+\t */\n+\t#define HWRM_QUEUE_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0;\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/******************\n+ * hwrm_queue_cfg *\n+ ******************/\n+\n+\n+/* hwrm_queue_cfg_input (size:320b/40B) */\n+struct hwrm_queue_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/*\n+\t * Enumeration denoting the RX, TX, or both directions applicable to the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)\n+\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_SFT 0\n+\t/* tx path */\n+\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n+\t/* Bi-directional (Symmetrically applicable to TX and RX paths) */\n+\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)\n+\t#define HWRM_QUEUE_CFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_QUEUE_CFG_INPUT_FLAGS_PATH_BIDIR\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the dflt_len field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_CFG_INPUT_ENABLES_DFLT_LEN UINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the service_profile field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_CFG_INPUT_ENABLES_SERVICE_PROFILE UINT32_C(0x2)\n+\t/* Queue ID of queue that is to be configured by this function. */\n+\tuint32_t\tqueue_id;\n+\t/*\n+\t * This value is a the estimate packet length used in the\n+\t * TX arbiter.\n+\t * Set to 0xFF... (All Fs) to not adjust this value.\n+\t */\n+\tuint32_t\tdflt_len;\n+\t/* This value is applicable to CoS queues only. */\n+\tuint8_t\tservice_profile;\n+\t/* Lossy (best-effort) */\n+\t#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSY UINT32_C(0x0)\n+\t/* Lossless */\n+\t#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LOSSLESS UINT32_C(0x1)\n+\t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n+\t#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN UINT32_C(0xff)\n+\t#define HWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_LAST \\\n+\t\tHWRM_QUEUE_CFG_INPUT_SERVICE_PROFILE_UNKNOWN\n \tuint8_t\tunused_0[7];\n } __attribute__((packed));\n \n-/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */\n-struct hwrm_queue_pri2cos_cfg_output {\n+/* hwrm_queue_cfg_output (size:128b/16B) */\n+struct hwrm_queue_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -14994,13 +15568,13 @@ struct hwrm_queue_pri2cos_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**************************\n- * hwrm_queue_cos2bw_qcfg *\n- **************************/\n+/*****************************\n+ * hwrm_queue_pfcenable_qcfg *\n+ *****************************/\n \n \n-/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */\n-struct hwrm_queue_cos2bw_qcfg_input {\n+/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */\n+struct hwrm_queue_pfcenable_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -15031,14 +15605,14 @@ struct hwrm_queue_cos2bw_qcfg_input {\n \t/*\n \t * Port ID of port for which the table is being configured.\n \t * The HWRM needs to check whether this function is allowed\n-\t * to configure TC BW assignment on this port.\n+\t * to configure pri2cos mapping on this port.\n \t */\n \tuint16_t\tport_id;\n \tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */\n-struct hwrm_queue_cos2bw_qcfg_output {\n+/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */\n+struct hwrm_queue_pfcenable_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -15047,2649 +15621,112 @@ struct hwrm_queue_cos2bw_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* ID of CoS Queue 0. */\n-\tuint8_t\tqueue_id0;\n-\tuint8_t\tunused_0;\n-\tuint16_t\tunused_1;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id0_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id0_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id0_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id0_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id0_bw_weight;\n-\t/* ID of CoS Queue 1. */\n-\tuint8_t\tqueue_id1;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id1_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id1_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id1_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id1_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id1_bw_weight;\n-\t/* ID of CoS Queue 2. */\n-\tuint8_t\tqueue_id2;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id2_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id2_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id2_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id2_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id2_bw_weight;\n-\t/* ID of CoS Queue 3. */\n-\tuint8_t\tqueue_id3;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id3_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id3_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id3_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id3_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id3_bw_weight;\n-\t/* ID of CoS Queue 4. */\n-\tuint8_t\tqueue_id4;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id4_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id4_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id4_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id4_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id4_bw_weight;\n-\t/* ID of CoS Queue 5. */\n-\tuint8_t\tqueue_id5;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id5_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id5_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id5_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id5_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id5_bw_weight;\n-\t/* ID of CoS Queue 6. */\n-\tuint8_t\tqueue_id6;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id6_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id6_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id6_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id6_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id6_bw_weight;\n-\t/* ID of CoS Queue 7. */\n-\tuint8_t\tqueue_id7;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id7_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id7_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id7_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id7_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id7_bw_weight;\n-\tuint8_t\tunused_2[4];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/*************************\n- * hwrm_queue_cos2bw_cfg *\n- *************************/\n-\n-\n-/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */\n-struct hwrm_queue_cos2bw_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\tuint32_t\tenables;\n-\t/*\n-\t * If this bit is set to 1, then all queue_id0 related\n-\t * parameters in this command are valid.\n-\t */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * If this bit is set to 1, then all queue_id1 related\n-\t * parameters in this command are valid.\n-\t */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * If this bit is set to 1, then all queue_id2 related\n-\t * parameters in this command are valid.\n-\t */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * If this bit is set to 1, then all queue_id3 related\n-\t * parameters in this command are valid.\n-\t */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * If this bit is set to 1, then all queue_id4 related\n-\t * parameters in this command are valid.\n-\t */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * If this bit is set to 1, then all queue_id5 related\n-\t * parameters in this command are valid.\n-\t */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * If this bit is set to 1, then all queue_id6 related\n-\t * parameters in this command are valid.\n-\t */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * If this bit is set to 1, then all queue_id7 related\n-\t * parameters in this command are valid.\n-\t */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \\\n-\t\tUINT32_C(0x80)\n-\t/*\n-\t * Port ID of port for which the table is being configured.\n-\t * The HWRM needs to check whether this function is allowed\n-\t * to configure TC BW assignment on this port.\n-\t */\n-\tuint16_t\tport_id;\n-\t/* ID of CoS Queue 0. */\n-\tuint8_t\tqueue_id0;\n-\tuint8_t\tunused_0;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id0_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id0_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id0_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id0_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id0_bw_weight;\n-\t/* ID of CoS Queue 1. */\n-\tuint8_t\tqueue_id1;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id1_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id1_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id1_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id1_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id1_bw_weight;\n-\t/* ID of CoS Queue 2. */\n-\tuint8_t\tqueue_id2;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id2_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id2_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id2_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id2_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id2_bw_weight;\n-\t/* ID of CoS Queue 3. */\n-\tuint8_t\tqueue_id3;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id3_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id3_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id3_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id3_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id3_bw_weight;\n-\t/* ID of CoS Queue 4. */\n-\tuint8_t\tqueue_id4;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id4_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id4_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id4_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id4_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id4_bw_weight;\n-\t/* ID of CoS Queue 5. */\n-\tuint8_t\tqueue_id5;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id5_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id5_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id5_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id5_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id5_bw_weight;\n-\t/* ID of CoS Queue 6. */\n-\tuint8_t\tqueue_id6;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id6_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id6_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id6_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id6_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id6_bw_weight;\n-\t/* ID of CoS Queue 7. */\n-\tuint8_t\tqueue_id7;\n-\t/*\n-\t * Minimum BW allocated to CoS Queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id7_min_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID\n-\t/*\n-\t * Maximum BW allocated to CoS queue.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this COS inside the device.\n-\t */\n-\tuint32_t\tqueue_id7_max_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID\n-\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n-\tuint8_t\tqueue_id7_tsa_assign;\n-\t/* Strict Priority */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \\\n-\t\tUINT32_C(0x0)\n-\t/* Enhanced Transmission Selection */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \\\n-\t\tUINT32_C(0x1)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \\\n-\t\tUINT32_C(0x2)\n-\t/* reserved. */\n-\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \\\n-\t\tUINT32_C(0xff)\n-\t/*\n-\t * Priority level for strict priority. Valid only when the\n-\t * tsa_assign is 0 - Strict Priority (SP)\n-\t * 0..7 - Valid values.\n-\t * 8..255 - Reserved.\n-\t */\n-\tuint8_t\tqueue_id7_pri_lvl;\n-\t/*\n-\t * Weight used to allocate remaining BW for this COS after\n-\t * servicing guaranteed bandwidths for all COS.\n-\t */\n-\tuint8_t\tqueue_id7_bw_weight;\n-\tuint8_t\tunused_1[5];\n-} __attribute__((packed));\n-\n-/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */\n-struct hwrm_queue_cos2bw_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/*************************\n- * hwrm_queue_dscp_qcaps *\n- *************************/\n-\n-\n-/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */\n-struct hwrm_queue_dscp_qcaps_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/*\n-\t * Port ID of port for which the table is being configured.\n-\t * The HWRM needs to check whether this function is allowed\n-\t * to configure pri2cos mapping on this port.\n-\t */\n-\tuint8_t\tport_id;\n-\tuint8_t\tunused_0[7];\n-} __attribute__((packed));\n-\n-/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */\n-struct hwrm_queue_dscp_qcaps_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* The number of bits provided by the hardware for the DSCP value. */\n-\tuint8_t\tnum_dscp_bits;\n-\tuint8_t\tunused_0;\n-\t/* Max number of DSCP-MASK-PRI entries supported. */\n-\tuint16_t\tmax_entries;\n-\tuint8_t\tunused_1[3];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/****************************\n- * hwrm_queue_dscp2pri_qcfg *\n- ****************************/\n-\n-\n-/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */\n-struct hwrm_queue_dscp2pri_qcfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/*\n-\t * This is the host address where the 24-bits DSCP-MASK-PRI\n-\t * tuple(s) will be copied to.\n-\t */\n-\tuint64_t\tdest_data_addr;\n-\t/*\n-\t * Port ID of port for which the table is being configured.\n-\t * The HWRM needs to check whether this function is allowed\n-\t * to configure pri2cos mapping on this port.\n-\t */\n-\tuint8_t\tport_id;\n-\tuint8_t\tunused_0;\n-\t/* Size of the buffer pointed to by dest_data_addr. */\n-\tuint16_t\tdest_data_buffer_size;\n-\tuint8_t\tunused_1[4];\n-} __attribute__((packed));\n-\n-/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */\n-struct hwrm_queue_dscp2pri_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/*\n-\t * A count of the number of DSCP-MASK-PRI tuple(s) pointed to\n-\t * by the dest_data_addr.\n-\t */\n-\tuint16_t\tentry_cnt;\n-\t/*\n-\t * This is the default PRI which un-initialized DSCP values are\n-\t * mapped to.\n-\t */\n-\tuint8_t\tdefault_pri;\n-\tuint8_t\tunused_0[4];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/***************************\n- * hwrm_queue_dscp2pri_cfg *\n- ***************************/\n-\n-\n-/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */\n-struct hwrm_queue_dscp2pri_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/*\n-\t * This is the host address where the 24-bits DSCP-MASK-PRI tuple\n-\t * will be copied from.\n-\t */\n-\tuint64_t\tsrc_data_addr;\n-\tuint32_t\tflags;\n-\t/* use_hw_default_pri is 1 b */\n-\t#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_FLAGS_USE_HW_DEFAULT_PRI \\\n-\t\tUINT32_C(0x1)\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the default_pri field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_QUEUE_DSCP2PRI_CFG_INPUT_ENABLES_DEFAULT_PRI \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * Port ID of port for which the table is being configured.\n-\t * The HWRM needs to check whether this function is allowed\n-\t * to configure pri2cos mapping on this port.\n-\t */\n-\tuint8_t\tport_id;\n-\t/*\n-\t * This is the default PRI which un-initialized DSCP values will be\n-\t * mapped to.\n-\t */\n-\tuint8_t\tdefault_pri;\n-\t/*\n-\t * A count of the number of DSCP-MASK-PRI tuple(s) in the data pointed\n-\t * to by src_data_addr.\n-\t */\n-\tuint16_t\tentry_cnt;\n-\tuint8_t\tunused_0[4];\n-} __attribute__((packed));\n-\n-/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */\n-struct hwrm_queue_dscp2pri_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/*******************\n- * hwrm_vnic_alloc *\n- *******************/\n-\n-\n-/* hwrm_vnic_alloc_input (size:192b/24B) */\n-struct hwrm_vnic_alloc_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/*\n-\t * When this bit is '1', this VNIC is requested to\n-\t * be the default VNIC for this function.\n-\t */\n-\t#define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)\n-\tuint8_t\tunused_0[4];\n-} __attribute__((packed));\n-\n-/* hwrm_vnic_alloc_output (size:128b/16B) */\n-struct hwrm_vnic_alloc_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* Logical vnic ID */\n-\tuint32_t\tvnic_id;\n-\tuint8_t\tunused_0[3];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/******************\n- * hwrm_vnic_free *\n- ******************/\n-\n-\n-/* hwrm_vnic_free_input (size:192b/24B) */\n-struct hwrm_vnic_free_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/* Logical vnic ID */\n-\tuint32_t\tvnic_id;\n-\tuint8_t\tunused_0[4];\n-} __attribute__((packed));\n-\n-/* hwrm_vnic_free_output (size:128b/16B) */\n-struct hwrm_vnic_free_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/*****************\n- * hwrm_vnic_cfg *\n- *****************/\n-\n-\n-/* hwrm_vnic_cfg_input (size:320b/40B) */\n-struct hwrm_vnic_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n \tuint32_t\tflags;\n-\t/*\n-\t * When this bit is '1', the VNIC is requested to\n-\t * be the default VNIC for the function.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * When this bit is '1', the VNIC is being configured to\n-\t * strip VLAN in the RX path.\n-\t * If set to '0', then VLAN stripping is disabled on\n-\t * this VNIC.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * When this bit is '1', the VNIC is being configured to\n-\t * buffer receive packets in the hardware until the host\n-\t * posts new receive buffers.\n-\t * If set to '0', then bd_stall is being configured to be\n-\t * disabled on this VNIC.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * When this bit is '1', the VNIC is being configured to\n-\t * receive both RoCE and non-RoCE traffic.\n-\t * If set to '0', then this VNIC is not configured to be\n-\t * operating in dual VNIC mode.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * When this flag is set to '1', the VNIC is requested to\n-\t * be configured to receive only RoCE traffic.\n-\t * If this flag is set to '0', then this flag shall be\n-\t * ignored by the HWRM.\n-\t * If roce_dual_vnic_mode flag is set to '1'\n-\t * or roce_mirroring_capable_vnic_mode flag to 1,\n-\t * then the HWRM client shall not set this flag to '1'.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * When a VNIC uses one destination ring group for certain\n-\t * application (e.g. Receive Flow Steering) where\n-\t * exact match is used to direct packets to a VNIC with one\n-\t * destination ring group only, there is no need to configure\n-\t * RSS indirection table for that VNIC as only one destination\n-\t * ring group is used.\n-\t *\n-\t * This flag is used to enable a mode where\n-\t * RSS is enabled in the VNIC using a RSS context\n-\t * for computing RSS hash but the RSS indirection table is\n-\t * not configured using hwrm_vnic_rss_cfg.\n-\t *\n-\t * If this mode is enabled, then the driver should not program\n-\t * RSS indirection table for the RSS context that is used for\n-\t * computing RSS hash only.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * When this bit is '1', the VNIC is being configured to\n-\t * receive both RoCE and non-RoCE traffic, but forward only the\n-\t * RoCE traffic further. Also, RoCE traffic can be mirrored to\n-\t * L2 driver.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \\\n-\t\tUINT32_C(0x40)\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the dflt_ring_grp field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \\\n+\t/* If set to 1, then PFC is enabled on PRI 0. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI0_PFC_ENABLED \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the rss_rule field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \\\n+\t/* If set to 1, then PFC is enabled on PRI 1. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI1_PFC_ENABLED \\\n \t\tUINT32_C(0x2)\n-\t/*\n-\t * This bit must be '1' for the cos_rule field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * This bit must be '1' for the lb_rule field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \\\n+\t/* If set to 1, then PFC is enabled on PRI 2. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI2_PFC_ENABLED \\\n+\t\tUINT32_C(0x4)\n+\t/* If set to 1, then PFC is enabled on PRI 3. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI3_PFC_ENABLED \\\n \t\tUINT32_C(0x8)\n-\t/*\n-\t * This bit must be '1' for the mru field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \\\n+\t/* If set to 1, then PFC is enabled on PRI 4. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI4_PFC_ENABLED \\\n \t\tUINT32_C(0x10)\n-\t/*\n-\t * This bit must be '1' for the default_rx_ring_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \\\n+\t/* If set to 1, then PFC is enabled on PRI 5. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI5_PFC_ENABLED \\\n \t\tUINT32_C(0x20)\n-\t/*\n-\t * This bit must be '1' for the default_cmpl_ring_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \\\n+\t/* If set to 1, then PFC is enabled on PRI 6. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI6_PFC_ENABLED \\\n \t\tUINT32_C(0x40)\n-\t/* Logical vnic ID */\n-\tuint16_t\tvnic_id;\n-\t/*\n-\t * Default Completion ring for the VNIC. This ring will\n-\t * be chosen if packet does not match any RSS rules and if\n-\t * there is no COS rule.\n-\t */\n-\tuint16_t\tdflt_ring_grp;\n+\t/* If set to 1, then PFC is enabled on PRI 7. */\n+\t#define HWRM_QUEUE_PFCENABLE_QCFG_OUTPUT_FLAGS_PRI7_PFC_ENABLED \\\n+\t\tUINT32_C(0x80)\n+\tuint8_t\tunused_0[3];\n \t/*\n-\t * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if\n-\t * there is no RSS rule.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint16_t\trss_rule;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/****************************\n+ * hwrm_queue_pfcenable_cfg *\n+ ****************************/\n+\n+\n+/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */\n+struct hwrm_queue_pfcenable_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * RSS ID for COS rule/table structure. 0xFF... (All Fs) if\n-\t * there is no COS rule.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint16_t\tcos_rule;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * RSS ID for load balancing rule/table structure.\n-\t * 0xFF... (All Fs) if there is no LB rule.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint16_t\tlb_rule;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * The maximum receive unit of the vnic.\n-\t * Each vnic is associated with a function.\n-\t * The vnic mru value overwrites the mru setting of the\n-\t * associated function.\n-\t * The HWRM shall make sure that vnic mru does not exceed\n-\t * the mru of the port the function is associated with.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint16_t\tmru;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * Default Rx ring for the VNIC. This ring will\n-\t * be chosen if packet does not match any RSS rules.\n-\t * The aggregation ring associated with the Rx ring is\n-\t * implied based on the Rx ring specified when the\n-\t * aggregation ring was allocated.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint16_t\tdefault_rx_ring_id;\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 0. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI0_PFC_ENABLED \\\n+\t\tUINT32_C(0x1)\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 1. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI1_PFC_ENABLED \\\n+\t\tUINT32_C(0x2)\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 2. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI2_PFC_ENABLED \\\n+\t\tUINT32_C(0x4)\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 3. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI3_PFC_ENABLED \\\n+\t\tUINT32_C(0x8)\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 4. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI4_PFC_ENABLED \\\n+\t\tUINT32_C(0x10)\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 5. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI5_PFC_ENABLED \\\n+\t\tUINT32_C(0x20)\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 6. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI6_PFC_ENABLED \\\n+\t\tUINT32_C(0x40)\n+\t/* If set to 1, then PFC is requested to be enabled on PRI 7. */\n+\t#define HWRM_QUEUE_PFCENABLE_CFG_INPUT_FLAGS_PRI7_PFC_ENABLED \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * Default completion ring for the VNIC. This ring will\n-\t * be chosen if packet does not match any RSS rules.\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure pri2cos mapping on this port.\n \t */\n-\tuint16_t\tdefault_cmpl_ring_id;\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[2];\n } __attribute__((packed));\n \n-/* hwrm_vnic_cfg_output (size:128b/16B) */\n-struct hwrm_vnic_cfg_output {\n+/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */\n+struct hwrm_queue_pfcenable_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -17709,13 +15746,13 @@ struct hwrm_vnic_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/******************\n- * hwrm_vnic_qcfg *\n- ******************/\n+/***************************\n+ * hwrm_queue_pri2cos_qcfg *\n+ ***************************/\n \n \n-/* hwrm_vnic_qcfg_input (size:256b/32B) */\n-struct hwrm_vnic_qcfg_input {\n+/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */\n+struct hwrm_queue_pri2cos_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -17743,21 +15780,37 @@ struct hwrm_vnic_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n+\tuint32_t\tflags;\n \t/*\n-\t * This bit must be '1' for the vf_id_valid field to be\n-\t * configured.\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n \t */\n-\t#define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)\n-\t/* Logical vnic ID */\n-\tuint32_t\tvnic_id;\n-\t/* ID of Virtual Function whose VNIC resource is being queried. */\n-\tuint16_t\tvf_id;\n-\tuint8_t\tunused_0[6];\n+\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n+\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_PATH_RX\n+\t/*\n+\t * When this bit is set to '0', the query is\n+\t * for VLAN PRI field in tunnel headers.\n+\t * When this bit is set to '1', the query is\n+\t * for VLAN PRI field in inner packet headers.\n+\t */\n+\t#define HWRM_QUEUE_PRI2COS_QCFG_INPUT_FLAGS_IVLAN UINT32_C(0x2)\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure pri2cos mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0[3];\n } __attribute__((packed));\n \n-/* hwrm_vnic_qcfg_output (size:256b/32B) */\n-struct hwrm_vnic_qcfg_output {\n+/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */\n+struct hwrm_queue_pri2cos_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -17766,94 +15819,73 @@ struct hwrm_vnic_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Default Completion ring for the VNIC. */\n-\tuint16_t\tdflt_ring_grp;\n-\t/*\n-\t * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if\n-\t * there is no RSS rule.\n-\t */\n-\tuint16_t\trss_rule;\n \t/*\n-\t * RSS ID for COS rule/table structure. 0xFF... (All Fs) if\n-\t * there is no COS rule.\n+\t * CoS Queue assigned to priority 0. This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no CoS queue is assigned to the\n+\t * specified priority.\n \t */\n-\tuint16_t\tcos_rule;\n+\tuint8_t\tpri0_cos_queue_id;\n \t/*\n-\t * RSS ID for load balancing rule/table structure.\n-\t * 0xFF... (All Fs) if there is no LB rule.\n+\t * CoS Queue assigned to priority 1. This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no CoS queue is assigned to the\n+\t * specified priority.\n \t */\n-\tuint16_t\tlb_rule;\n-\t/* The maximum receive unit of the vnic. */\n-\tuint16_t\tmru;\n-\tuint8_t\tunused_0[2];\n-\tuint32_t\tflags;\n+\tuint8_t\tpri1_cos_queue_id;\n \t/*\n-\t * When this bit is '1', the VNIC is the default VNIC for\n-\t * the function.\n+\t * CoS Queue assigned to priority 2 This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no CoS queue is assigned to the\n+\t * specified priority.\n \t */\n-\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \\\n-\t\tUINT32_C(0x1)\n+\tuint8_t\tpri2_cos_queue_id;\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * strip VLAN in the RX path.\n-\t * If set to '0', then VLAN stripping is disabled on\n-\t * this VNIC.\n+\t * CoS Queue assigned to priority 3. This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no CoS queue is assigned to the\n+\t * specified priority.\n \t */\n-\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \\\n-\t\tUINT32_C(0x2)\n+\tuint8_t\tpri3_cos_queue_id;\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * buffer receive packets in the hardware until the host\n-\t * posts new receive buffers.\n-\t * If set to '0', then bd_stall is disabled on\n-\t * this VNIC.\n+\t * CoS Queue assigned to priority 4. This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no CoS queue is assigned to the\n+\t * specified priority.\n \t */\n-\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \\\n-\t\tUINT32_C(0x4)\n+\tuint8_t\tpri4_cos_queue_id;\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * receive both RoCE and non-RoCE traffic.\n-\t * If set to '0', then this VNIC is not configured to\n-\t * operate in dual VNIC mode.\n+\t * CoS Queue assigned to priority 5. This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no CoS queue is assigned to the\n+\t * specified priority.\n \t */\n-\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * When this flag is set to '1', the VNIC is configured to\n-\t * receive only RoCE traffic.\n-\t * When this flag is set to '0', the VNIC is not configured\n-\t * to receive only RoCE traffic.\n-\t * If roce_dual_vnic_mode flag and this flag both are set\n-\t * to '1', then it is an invalid configuration of the\n-\t * VNIC. The HWRM should not allow that type of\n-\t * mis-configuration by HWRM clients.\n+\tuint8_t\tpri5_cos_queue_id;\n+\t/*\n+\t * CoS Queue assigned to priority 6. This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no CoS queue is assigned to the\n+\t * specified priority.\n \t */\n-\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \\\n-\t\tUINT32_C(0x10)\n+\tuint8_t\tpri6_cos_queue_id;\n \t/*\n-\t * When a VNIC uses one destination ring group for certain\n-\t * application (e.g. Receive Flow Steering) where\n-\t * exact match is used to direct packets to a VNIC with one\n-\t * destination ring group only, there is no need to configure\n-\t * RSS indirection table for that VNIC as only one destination\n-\t * ring group is used.\n-\t *\n-\t * When this bit is set to '1', then the VNIC is enabled in a\n-\t * mode where RSS is enabled in the VNIC using a RSS context\n-\t * for computing RSS hash but the RSS indirection table is\n-\t * not configured.\n+\t * CoS Queue assigned to priority 7. This value can only\n+\t * be changed before traffic has started.\n+\t * A value of 0xff indicates that no CoS queue is assigned to the\n+\t * specified priority.\n \t */\n-\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \\\n-\t\tUINT32_C(0x20)\n+\tuint8_t\tpri7_cos_queue_id;\n+\t/* Information about queue configuration. */\n+\tuint8_t\tqueue_cfg_info;\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * receive both RoCE and non-RoCE traffic, but forward only\n-\t * RoCE traffic further. Also RoCE traffic can be mirrored to\n-\t * L2 driver.\n+\t * If this flag is set to '1', then the PRI to CoS\n+\t * configuration is asymmetric on TX and RX sides.\n+\t * If this flag is set to '0', then PRI to CoS configuration\n+\t * is symmetric on TX and RX sides.\n \t */\n-\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \\\n-\t\tUINT32_C(0x40)\n-\tuint8_t\tunused_1[7];\n+\t#define HWRM_QUEUE_PRI2COS_QCFG_OUTPUT_QUEUE_CFG_INFO_ASYM_CFG \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[6];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -17864,13 +15896,13 @@ struct hwrm_vnic_qcfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************\n- * hwrm_vnic_qcaps *\n- *******************/\n+/**************************\n+ * hwrm_queue_pri2cos_cfg *\n+ **************************/\n \n \n-/* hwrm_vnic_qcaps_input (size:192b/24B) */\n-struct hwrm_vnic_qcaps_input {\n+/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */\n+struct hwrm_queue_pri2cos_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -17898,88 +15930,138 @@ struct hwrm_vnic_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n-\tuint8_t\tunused_0[4];\n-} __attribute__((packed));\n-\n-/* hwrm_vnic_qcaps_output (size:192b/24B) */\n-struct hwrm_vnic_qcaps_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* The maximum receive unit that is settable on a vnic. */\n-\tuint16_t\tmru;\n-\tuint8_t\tunused_0[2];\n \tuint32_t\tflags;\n-\t/* Unused. */\n-\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \\\n+\t/*\n+\t * Enumeration denoting the RX, TX, or both directions applicable to the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_MASK UINT32_C(0x3)\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_SFT 0\n+\t/* tx path */\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n+\t/* Bi-directional (Symmetrically applicable to TX and RX paths) */\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR UINT32_C(0x2)\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_PATH_BIDIR\n+\t/*\n+\t * When this bit is set to '0', the mapping is requested\n+\t * for VLAN PRI field in tunnel headers.\n+\t * When this bit is set to '1', the mapping is requested\n+\t * for VLAN PRI field in inner packet headers.\n+\t */\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_FLAGS_IVLAN UINT32_C(0x4)\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the pri0_cos_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI0_COS_QUEUE_ID \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * When this bit is '1', the capability of stripping VLAN in\n-\t * the RX path is supported on VNIC(s).\n-\t * If set to '0', then VLAN stripping capability is\n-\t * not supported on VNIC(s).\n+\t * This bit must be '1' for the pri1_cos_queue_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \\\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI1_COS_QUEUE_ID \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * When this bit is '1', the capability to buffer receive\n-\t * packets in the hardware until the host posts new receive buffers\n-\t * is supported on VNIC(s).\n-\t * If set to '0', then bd_stall capability is not supported\n-\t * on VNIC(s).\n+\t * This bit must be '1' for the pri2_cos_queue_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \\\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI2_COS_QUEUE_ID \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * When this bit is '1', the capability to\n-\t * receive both RoCE and non-RoCE traffic on VNIC(s) is\n-\t * supported.\n-\t * If set to '0', then the capability to receive\n-\t * both RoCE and non-RoCE traffic on VNIC(s) is\n-\t * not supported.\n+\t * This bit must be '1' for the pri3_cos_queue_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \\\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI3_COS_QUEUE_ID \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * When this bit is set to '1', the capability to configure\n-\t * a VNIC to receive only RoCE traffic is supported.\n-\t * When this flag is set to '0', the VNIC capability to\n-\t * configure to receive only RoCE traffic is not supported.\n+\t * This bit must be '1' for the pri4_cos_queue_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \\\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI4_COS_QUEUE_ID \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * When this bit is set to '1', then the capability to enable\n-\t * a VNIC in a mode where RSS context without configuring\n-\t * RSS indirection table is supported (for RSS hash computation).\n-\t * When this bit is set to '0', then a VNIC can not be configured\n-\t * with a mode to enable RSS context without configuring RSS\n-\t * indirection table.\n+\t * This bit must be '1' for the pri5_cos_queue_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \\\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI5_COS_QUEUE_ID \\\n \t\tUINT32_C(0x20)\n \t/*\n-\t * When this bit is '1', the capability to\n-\t * mirror the the RoCE traffic is supported.\n-\t * If set to '0', then the capability to mirror the\n-\t * RoCE traffic is not supported.\n+\t * This bit must be '1' for the pri6_cos_queue_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \\\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI6_COS_QUEUE_ID \\\n \t\tUINT32_C(0x40)\n \t/*\n-\t * When this bit is '1', the outermost RSS hashing capability\n-\t * is supported. If set to '0', then the outermost RSS hashing\n-\t * capability is not supported.\n+\t * This bit must be '1' for the pri7_cos_queue_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \\\n+\t#define HWRM_QUEUE_PRI2COS_CFG_INPUT_ENABLES_PRI7_COS_QUEUE_ID \\\n \t\tUINT32_C(0x80)\n-\tuint8_t\tunused_1[7];\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure pri2cos mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\t/*\n+\t * CoS Queue assigned to priority 0. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\tpri0_cos_queue_id;\n+\t/*\n+\t * CoS Queue assigned to priority 1. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\tpri1_cos_queue_id;\n+\t/*\n+\t * CoS Queue assigned to priority 2 This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\tpri2_cos_queue_id;\n+\t/*\n+\t * CoS Queue assigned to priority 3. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\tpri3_cos_queue_id;\n+\t/*\n+\t * CoS Queue assigned to priority 4. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\tpri4_cos_queue_id;\n+\t/*\n+\t * CoS Queue assigned to priority 5. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\tpri5_cos_queue_id;\n+\t/*\n+\t * CoS Queue assigned to priority 6. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\tpri6_cos_queue_id;\n+\t/*\n+\t * CoS Queue assigned to priority 7. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\tpri7_cos_queue_id;\n+\tuint8_t\tunused_0[7];\n+} __attribute__((packed));\n+\n+/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */\n+struct hwrm_queue_pri2cos_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -17990,13 +16072,13 @@ struct hwrm_vnic_qcaps_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*********************\n- * hwrm_vnic_tpa_cfg *\n- *********************/\n+/**************************\n+ * hwrm_queue_cos2bw_qcfg *\n+ **************************/\n \n \n-/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */\n-struct hwrm_vnic_tpa_cfg_input {\n+/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */\n+struct hwrm_queue_cos2bw_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -18018,331 +16100,1010 @@ struct hwrm_vnic_tpa_cfg_input {\n \t */\n \tuint16_t\ttarget_id;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure TC BW assignment on this port.\n+\t */\n+\tuint16_t\tport_id;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */\n+struct hwrm_queue_cos2bw_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* ID of CoS Queue 0. */\n+\tuint8_t\tqueue_id0;\n+\tuint8_t\tunused_0;\n+\tuint16_t\tunused_1;\n+\t/*\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n+\tuint32_t\tqueue_id0_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * When this bit is '1', the VNIC shall be configured to\n-\t * perform transparent packet aggregation (TPA) of\n-\t * non-tunneled TCP packets.\n+\t * Maximum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \\\n+\tuint32_t\tqueue_id0_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id0_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_ETS \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * When this bit is '1', the VNIC shall be configured to\n-\t * perform transparent packet aggregation (TPA) of\n-\t * tunneled TCP packets.\n-\t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \\\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \\\n \t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * When this bit is '1', the VNIC shall be configured to\n-\t * perform transparent packet aggregation (TPA) according\n-\t * to Windows Receive Segment Coalescing (RSC) rules.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \\\n-\t\tUINT32_C(0x4)\n+\tuint8_t\tqueue_id0_pri_lvl;\n \t/*\n-\t * When this bit is '1', the VNIC shall be configured to\n-\t * perform transparent packet aggregation (TPA) according\n-\t * to Linux Generic Receive Offload (GRO) rules.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \\\n-\t\tUINT32_C(0x8)\n+\tuint8_t\tqueue_id0_bw_weight;\n+\t/* ID of CoS Queue 1. */\n+\tuint8_t\tqueue_id1;\n \t/*\n-\t * When this bit is '1', the VNIC shall be configured to\n-\t * perform transparent packet aggregation (TPA) for TCP\n-\t * packets with IP ECN set to non-zero.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \\\n-\t\tUINT32_C(0x10)\n+\tuint32_t\tqueue_id1_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * When this bit is '1', the VNIC shall be configured to\n-\t * perform transparent packet aggregation (TPA) for\n-\t * GRE tunneled TCP packets only if all packets have the\n-\t * same GRE sequence.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \\\n-\t\tUINT32_C(0x20)\n+\tuint32_t\tqueue_id1_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id1_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * When this bit is '1' and the GRO mode is enabled,\n-\t * the VNIC shall be configured to\n-\t * perform transparent packet aggregation (TPA) for\n-\t * TCP/IPv4 packets with consecutively increasing IPIDs.\n-\t * In other words, the last packet that is being\n-\t * aggregated to an already existing aggregation context\n-\t * shall have IPID 1 more than the IPID of the last packet\n-\t * that was aggregated in that aggregation context.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \\\n-\t\tUINT32_C(0x40)\n+\tuint8_t\tqueue_id1_pri_lvl;\n \t/*\n-\t * When this bit is '1' and the GRO mode is enabled,\n-\t * the VNIC shall be configured to\n-\t * perform transparent packet aggregation (TPA) for\n-\t * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)\n-\t * value.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \\\n-\t\tUINT32_C(0x80)\n-\tuint32_t\tenables;\n+\tuint8_t\tqueue_id1_bw_weight;\n+\t/* ID of CoS Queue 2. */\n+\tuint8_t\tqueue_id2;\n \t/*\n-\t * This bit must be '1' for the max_agg_segs field to be\n-\t * configured.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)\n+\tuint32_t\tqueue_id2_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * This bit must be '1' for the max_aggs field to be\n-\t * configured.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)\n+\tuint32_t\tqueue_id2_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id2_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * This bit must be '1' for the max_agg_timer field to be\n-\t * configured.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)\n+\tuint8_t\tqueue_id2_pri_lvl;\n \t/*\n-\t * This bit must be '1' for the min_agg_len field to be\n-\t * configured.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)\n-\t/* Logical vnic ID */\n-\tuint16_t\tvnic_id;\n+\tuint8_t\tqueue_id2_bw_weight;\n+\t/* ID of CoS Queue 3. */\n+\tuint8_t\tqueue_id3;\n \t/*\n-\t * This is the maximum number of TCP segments that can\n-\t * be aggregated (unit is Log2). Max value is 31.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint16_t\tmax_agg_segs;\n-\t/* 1 segment */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)\n-\t/* 2 segments */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)\n-\t/* 4 segments */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)\n-\t/* 8 segments */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)\n-\t/* Any segment size larger than this is not valid */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \\\n-\t\tHWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX\n+\tuint32_t\tqueue_id3_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * This is the maximum number of aggregations this VNIC is\n-\t * allowed (unit is Log2). Max value is 7\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint16_t\tmax_aggs;\n-\t/* 1 aggregation */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)\n-\t/* 2 aggregations */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)\n-\t/* 4 aggregations */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)\n-\t/* 8 aggregations */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)\n-\t/* 16 aggregations */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)\n-\t/* Any aggregation size larger than this is not valid */\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)\n-\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \\\n-\t\tHWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX\n-\tuint8_t\tunused_0[2];\n+\tuint32_t\tqueue_id3_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id3_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * This is the maximum amount of time allowed for\n-\t * an aggregation context to complete after it was initiated.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\tuint32_t\tmax_agg_timer;\n+\tuint8_t\tqueue_id3_pri_lvl;\n \t/*\n-\t * This is the minimum amount of payload length required to\n-\t * start an aggregation context.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\tuint32_t\tmin_agg_len;\n-} __attribute__((packed));\n-\n-/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */\n-struct hwrm_vnic_tpa_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint8_t\tqueue_id3_bw_weight;\n+\t/* ID of CoS Queue 4. */\n+\tuint8_t\tqueue_id4;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**********************\n- * hwrm_vnic_tpa_qcfg *\n- **********************/\n-\n-\n-/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */\n-struct hwrm_vnic_tpa_qcfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint32_t\tqueue_id4_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint32_t\tqueue_id4_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id4_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint8_t\tqueue_id4_pri_lvl;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint8_t\tqueue_id4_bw_weight;\n+\t/* ID of CoS Queue 5. */\n+\tuint8_t\tqueue_id5;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Logical vnic ID */\n-\tuint16_t\tvnic_id;\n-\tuint8_t\tunused_0[6];\n-} __attribute__((packed));\n-\n-/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */\n-struct hwrm_vnic_tpa_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint32_t\tflags;\n+\tuint32_t\tqueue_id5_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * perform transparent packet aggregation (TPA) of\n-\t * non-tunneled TCP packets.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_TPA \\\n+\tuint32_t\tqueue_id5_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id5_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_ETS \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * perform transparent packet aggregation (TPA) of\n-\t * tunneled TCP packets.\n-\t */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_ENCAP_TPA \\\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \\\n \t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * perform transparent packet aggregation (TPA) according\n-\t * to Windows Receive Segment Coalescing (RSC) rules.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_RSC_WND_UPDATE \\\n-\t\tUINT32_C(0x4)\n+\tuint8_t\tqueue_id5_pri_lvl;\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * perform transparent packet aggregation (TPA) according\n-\t * to Linux Generic Receive Offload (GRO) rules.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO \\\n-\t\tUINT32_C(0x8)\n+\tuint8_t\tqueue_id5_bw_weight;\n+\t/* ID of CoS Queue 6. */\n+\tuint8_t\tqueue_id6;\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * perform transparent packet aggregation (TPA) for TCP\n-\t * packets with IP ECN set to non-zero.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_ECN \\\n-\t\tUINT32_C(0x10)\n+\tuint32_t\tqueue_id6_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * perform transparent packet aggregation (TPA) for\n-\t * GRE tunneled TCP packets only if all packets have the\n-\t * same GRE sequence.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \\\n-\t\tUINT32_C(0x20)\n+\tuint32_t\tqueue_id6_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id6_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * When this bit is '1' and the GRO mode is enabled,\n-\t * the VNIC is configured to\n-\t * perform transparent packet aggregation (TPA) for\n-\t * TCP/IPv4 packets with consecutively increasing IPIDs.\n-\t * In other words, the last packet that is being\n-\t * aggregated to an already existing aggregation context\n-\t * shall have IPID 1 more than the IPID of the last packet\n-\t * that was aggregated in that aggregation context.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_IPID_CHECK \\\n-\t\tUINT32_C(0x40)\n+\tuint8_t\tqueue_id6_pri_lvl;\n \t/*\n-\t * When this bit is '1' and the GRO mode is enabled,\n-\t * the VNIC is configured to\n-\t * perform transparent packet aggregation (TPA) for\n-\t * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)\n-\t * value.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_FLAGS_GRO_TTL_CHECK \\\n-\t\tUINT32_C(0x80)\n+\tuint8_t\tqueue_id6_bw_weight;\n+\t/* ID of CoS Queue 7. */\n+\tuint8_t\tqueue_id7;\n \t/*\n-\t * This is the maximum number of TCP segments that can\n-\t * be aggregated (unit is Log2). Max value is 31.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint16_t\tmax_agg_segs;\n-\t/* 1 segment */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)\n-\t/* 2 segments */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)\n-\t/* 4 segments */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)\n-\t/* 8 segments */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)\n-\t/* Any segment size larger than this is not valid */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_LAST \\\n-\t\tHWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGG_SEGS_MAX\n+\tuint32_t\tqueue_id7_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * This is the maximum number of aggregations this VNIC is\n-\t * allowed (unit is Log2). Max value is 7\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint16_t\tmax_aggs;\n-\t/* 1 aggregation */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_1 UINT32_C(0x0)\n-\t/* 2 aggregations */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_2 UINT32_C(0x1)\n-\t/* 4 aggregations */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_4 UINT32_C(0x2)\n-\t/* 8 aggregations */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_8 UINT32_C(0x3)\n-\t/* 16 aggregations */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_16 UINT32_C(0x4)\n-\t/* Any aggregation size larger than this is not valid */\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX UINT32_C(0x7)\n-\t#define HWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_LAST \\\n-\t\tHWRM_VNIC_TPA_QCFG_OUTPUT_MAX_AGGS_MAX\n+\tuint32_t\tqueue_id7_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id7_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_QCFG_OUTPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * This is the maximum amount of time allowed for\n-\t * an aggregation context to complete after it was initiated.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\tuint32_t\tmax_agg_timer;\n+\tuint8_t\tqueue_id7_pri_lvl;\n \t/*\n-\t * This is the minimum amount of payload length required to\n-\t * start an aggregation context.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\tuint32_t\tmin_agg_len;\n-\tuint8_t\tunused_0[7];\n+\tuint8_t\tqueue_id7_bw_weight;\n+\tuint8_t\tunused_2[4];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -18353,13 +17114,13 @@ struct hwrm_vnic_tpa_qcfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*********************\n- * hwrm_vnic_rss_cfg *\n- *********************/\n+/*************************\n+ * hwrm_queue_cos2bw_cfg *\n+ *************************/\n \n \n-/* hwrm_vnic_rss_cfg_input (size:384b/48B) */\n-struct hwrm_vnic_rss_cfg_input {\n+/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */\n+struct hwrm_queue_cos2bw_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -18387,408 +17148,1044 @@ struct hwrm_vnic_rss_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\thash_type;\n+\tuint32_t\tflags;\n+\tuint32_t\tenables;\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source and destination IPv4 addresses of IPv4\n-\t * packets.\n+\t * If this bit is set to 1, then all queue_id0 related\n+\t * parameters in this command are valid.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID0_VALID \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source/destination IPv4 addresses and\n-\t * source/destination ports of TCP/IPv4 packets.\n+\t * If this bit is set to 1, then all queue_id1 related\n+\t * parameters in this command are valid.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID1_VALID \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source/destination IPv4 addresses and\n-\t * source/destination ports of UDP/IPv4 packets.\n+\t * If this bit is set to 1, then all queue_id2 related\n+\t * parameters in this command are valid.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID2_VALID \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source and destination IPv4 addresses of IPv6\n-\t * packets.\n+\t * If this bit is set to 1, then all queue_id3 related\n+\t * parameters in this command are valid.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID3_VALID \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source/destination IPv6 addresses and\n-\t * source/destination ports of TCP/IPv6 packets.\n+\t * If this bit is set to 1, then all queue_id4 related\n+\t * parameters in this command are valid.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID4_VALID \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source/destination IPv6 addresses and\n-\t * source/destination ports of UDP/IPv6 packets.\n+\t * If this bit is set to 1, then all queue_id5 related\n+\t * parameters in this command are valid.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)\n-\t/* VNIC ID of VNIC associated with RSS table being configured. */\n-\tuint16_t\tvnic_id;\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID5_VALID \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * Specifies which VNIC ring table pair to configure.\n-\t * Valid values range from 0 to 7.\n+\t * If this bit is set to 1, then all queue_id6 related\n+\t * parameters in this command are valid.\n \t */\n-\tuint8_t\tring_table_pair_index;\n-\t/* Flags to specify different RSS hash modes. */\n-\tuint8_t\thash_mode_flags;\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID6_VALID \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * When this bit is '1', it indicates using current RSS\n-\t * hash mode setting configured in the device.\n+\t * If this bit is set to 1, then all queue_id7 related\n+\t * parameters in this command are valid.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_ENABLES_COS_QUEUE_ID7_VALID \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * When this bit is '1', it indicates requesting support of\n-\t * RSS hashing over innermost 4 tuples {l3.src, l3.dest,\n-\t * l4.src, l4.dest} for tunnel packets. For none-tunnel\n-\t * packets, the RSS hash is computed over the normal\n-\t * src/dest l3 and src/dest l4 headers.\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure TC BW assignment on this port.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \\\n-\t\tUINT32_C(0x2)\n+\tuint16_t\tport_id;\n+\t/* ID of CoS Queue 0. */\n+\tuint8_t\tqueue_id0;\n+\tuint8_t\tunused_0;\n+\t/*\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n+\t */\n+\tuint32_t\tqueue_id0_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * When this bit is '1', it indicates requesting support of\n-\t * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for\n-\t * tunnel packets. For none-tunnel packets, the RSS hash is\n-\t * computed over the normal src/dest l3 headers.\n+\t * Maximum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \\\n-\t\tUINT32_C(0x4)\n+\tuint32_t\tqueue_id0_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id0_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * When this bit is '1', it indicates requesting support of\n-\t * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,\n-\t * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel\n-\t * packets, the RSS hash is computed over the normal\n-\t * src/dest l3 and src/dest l4 headers.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \\\n-\t\tUINT32_C(0x8)\n+\tuint8_t\tqueue_id0_pri_lvl;\n \t/*\n-\t * When this bit is '1', it indicates requesting support of\n-\t * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for\n-\t * tunnel packets. For none-tunnel packets, the RSS hash is\n-\t * computed over the normal src/dest l3 headers.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \\\n-\t\tUINT32_C(0x10)\n-\t/* This is the address for rss ring group table */\n-\tuint64_t\tring_grp_tbl_addr;\n-\t/* This is the address for rss hash key table */\n-\tuint64_t\thash_key_tbl_addr;\n-\t/* Index to the rss indirection table. */\n-\tuint16_t\trss_ctx_idx;\n-\tuint8_t\tunused_1[6];\n-} __attribute__((packed));\n-\n-/* hwrm_vnic_rss_cfg_output (size:128b/16B) */\n-struct hwrm_vnic_rss_cfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint8_t\tqueue_id0_bw_weight;\n+\t/* ID of CoS Queue 1. */\n+\tuint8_t\tqueue_id1;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**********************\n- * hwrm_vnic_rss_qcfg *\n- **********************/\n-\n-\n-/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */\n-struct hwrm_vnic_rss_qcfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint32_t\tqueue_id1_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint32_t\tqueue_id1_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id1_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint8_t\tqueue_id1_pri_lvl;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\tuint8_t\tqueue_id1_bw_weight;\n+\t/* ID of CoS Queue 2. */\n+\tuint8_t\tqueue_id2;\n+\t/*\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Index to the rss indirection table. */\n-\tuint16_t\trss_ctx_idx;\n-\tuint8_t\tunused_0[6];\n-} __attribute__((packed));\n-\n-/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */\n-struct hwrm_vnic_rss_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint32_t\thash_type;\n+\tuint32_t\tqueue_id2_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source and destination IPv4 addresses of IPv4\n-\t * packets.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)\n+\tuint32_t\tqueue_id2_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id2_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source/destination IPv4 addresses and\n-\t * source/destination ports of TCP/IPv4 packets.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)\n+\tuint8_t\tqueue_id2_pri_lvl;\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source/destination IPv4 addresses and\n-\t * source/destination ports of UDP/IPv4 packets.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)\n+\tuint8_t\tqueue_id2_bw_weight;\n+\t/* ID of CoS Queue 3. */\n+\tuint8_t\tqueue_id3;\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source and destination IPv4 addresses of IPv6\n-\t * packets.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)\n+\tuint32_t\tqueue_id3_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source/destination IPv6 addresses and\n-\t * source/destination ports of TCP/IPv6 packets.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)\n+\tuint32_t\tqueue_id3_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id3_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * When this bit is '1', the RSS hash shall be computed\n-\t * over source/destination IPv6 addresses and\n-\t * source/destination ports of UDP/IPv6 packets.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)\n-\tuint8_t\tunused_0[4];\n-\t/* This is the value of rss hash key */\n-\tuint32_t\thash_key[10];\n-\t/* Flags to specify different RSS hash modes. */\n-\tuint8_t\thash_mode_flags;\n+\tuint8_t\tqueue_id3_pri_lvl;\n \t/*\n-\t * When this bit is '1', it indicates using current RSS\n-\t * hash mode setting configured in the device.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \\\n-\t\tUINT32_C(0x1)\n+\tuint8_t\tqueue_id3_bw_weight;\n+\t/* ID of CoS Queue 4. */\n+\tuint8_t\tqueue_id4;\n \t/*\n-\t * When this bit is '1', it indicates requesting support of\n-\t * RSS hashing over innermost 4 tuples {l3.src, l3.dest,\n-\t * l4.src, l4.dest} for tunnel packets. For none-tunnel\n-\t * packets, the RSS hash is computed over the normal\n-\t * src/dest l3 and src/dest l4 headers.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \\\n-\t\tUINT32_C(0x2)\n+\tuint32_t\tqueue_id4_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * When this bit is '1', it indicates requesting support of\n-\t * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for\n-\t * tunnel packets. For none-tunnel packets, the RSS hash is\n-\t * computed over the normal src/dest l3 headers.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \\\n-\t\tUINT32_C(0x4)\n+\tuint32_t\tqueue_id4_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id4_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * When this bit is '1', it indicates requesting support of\n-\t * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,\n-\t * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel\n-\t * packets, the RSS hash is computed over the normal\n-\t * src/dest l3 and src/dest l4 headers.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \\\n-\t\tUINT32_C(0x8)\n+\tuint8_t\tqueue_id4_pri_lvl;\n \t/*\n-\t * When this bit is '1', it indicates requesting support of\n-\t * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for\n-\t * tunnel packets. For none-tunnel packets, the RSS hash is\n-\t * computed over the normal src/dest l3 headers.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \\\n-\t\tUINT32_C(0x10)\n-\tuint8_t\tunused_1[6];\n+\tuint8_t\tqueue_id4_bw_weight;\n+\t/* ID of CoS Queue 5. */\n+\tuint8_t\tqueue_id5;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**************************\n- * hwrm_vnic_plcmodes_cfg *\n- **************************/\n-\n-\n-/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */\n-struct hwrm_vnic_plcmodes_cfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint32_t\tqueue_id5_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint32_t\tqueue_id5_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id5_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_ETS \\\n+\t\tUINT32_C(0x1)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST \\\n+\t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint8_t\tqueue_id5_pri_lvl;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint8_t\tqueue_id5_bw_weight;\n+\t/* ID of CoS Queue 6. */\n+\tuint8_t\tqueue_id6;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n+\tuint32_t\tqueue_id6_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * When this bit is '1', the VNIC shall be configured to\n-\t * use regular placement algorithm.\n-\t * By default, the regular placement algorithm shall be\n-\t * enabled on the VNIC.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \\\n+\tuint32_t\tqueue_id6_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id6_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_ETS \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * When this bit is '1', the VNIC shall be configured\n-\t * use the jumbo placement algorithm.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \\\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST \\\n \t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * When this bit is '1', the VNIC shall be configured\n-\t * to enable Header-Data split for IPv4 packets according\n-\t * to the following rules:\n-\t * # If the packet is identified as TCP/IPv4, then the\n-\t * packet is split at the beginning of the TCP payload.\n-\t * # If the packet is identified as UDP/IPv4, then the\n-\t * packet is split at the beginning of UDP payload.\n-\t * # If the packet is identified as non-TCP and non-UDP\n-\t * IPv4 packet, then the packet is split at the beginning\n-\t * of the upper layer protocol header carried in the IPv4\n-\t * packet.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * When this bit is '1', the VNIC shall be configured\n-\t * to enable Header-Data split for IPv6 packets according\n-\t * to the following rules:\n-\t * # If the packet is identified as TCP/IPv6, then the\n-\t * packet is split at the beginning of the TCP payload.\n-\t * # If the packet is identified as UDP/IPv6, then the\n-\t * packet is split at the beginning of UDP payload.\n-\t * # If the packet is identified as non-TCP and non-UDP\n-\t * IPv6 packet, then the packet is split at the beginning\n-\t * of the upper layer protocol header carried in the IPv6\n-\t * packet.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \\\n-\t\tUINT32_C(0x8)\n+\tuint8_t\tqueue_id6_pri_lvl;\n \t/*\n-\t * When this bit is '1', the VNIC shall be configured\n-\t * to enable Header-Data split for FCoE packets at the\n-\t * beginning of FC payload.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \\\n-\t\tUINT32_C(0x10)\n+\tuint8_t\tqueue_id6_bw_weight;\n+\t/* ID of CoS Queue 7. */\n+\tuint8_t\tqueue_id7;\n \t/*\n-\t * When this bit is '1', the VNIC shall be configured\n-\t * to enable Header-Data split for RoCE packets at the\n-\t * beginning of RoCE payload (after BTH/GRH headers).\n+\t * Minimum BW allocated to CoS Queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \\\n-\t\tUINT32_C(0x20)\n-\tuint32_t\tenables;\n+\tuint32_t\tqueue_id7_min_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * This bit must be '1' for the jumbo_thresh_valid field to be\n-\t * configured.\n+\t * Maximum BW allocated to CoS queue.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this COS inside the device.\n \t */\n-\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \\\n+\tuint32_t\tqueue_id7_max_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_SFT \\\n+\t\t0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT \\\n+\t\t29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID\n+\t/* Transmission Selection Algorithm (TSA) for CoS Queue. */\n+\tuint8_t\tqueue_id7_tsa_assign;\n+\t/* Strict Priority */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_SP \\\n+\t\tUINT32_C(0x0)\n+\t/* Enhanced Transmission Selection */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_ETS \\\n \t\tUINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the hds_offset_valid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \\\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST \\\n \t\tUINT32_C(0x2)\n+\t/* reserved. */\n+\t#define HWRM_QUEUE_COS2BW_CFG_INPUT_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST \\\n+\t\tUINT32_C(0xff)\n \t/*\n-\t * This bit must be '1' for the hds_threshold_valid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \\\n-\t\tUINT32_C(0x4)\n-\t/* Logical vnic ID */\n-\tuint32_t\tvnic_id;\n-\t/*\n-\t * When jumbo placement algorithm is enabled, this value\n-\t * is used to determine the threshold for jumbo placement.\n-\t * Packets with length larger than this value will be\n-\t * placed according to the jumbo placement algorithm.\n-\t */\n-\tuint16_t\tjumbo_thresh;\n-\t/*\n-\t * This value is used to determine the offset into\n-\t * packet buffer where the split data (payload) will be\n-\t * placed according to one of of HDS placement algorithm.\n-\t *\n-\t * The lengths of packet buffers provided for split data\n-\t * shall be larger than this value.\n+\t * Priority level for strict priority. Valid only when the\n+\t * tsa_assign is 0 - Strict Priority (SP)\n+\t * 0..7 - Valid values.\n+\t * 8..255 - Reserved.\n \t */\n-\tuint16_t\thds_offset;\n+\tuint8_t\tqueue_id7_pri_lvl;\n \t/*\n-\t * When one of the HDS placement algorithm is enabled, this\n-\t * value is used to determine the threshold for HDS\n-\t * placement.\n-\t * Packets with length larger than this value will be\n-\t * placed according to the HDS placement algorithm.\n-\t * This value shall be in multiple of 4 bytes.\n+\t * Weight used to allocate remaining BW for this COS after\n+\t * servicing guaranteed bandwidths for all COS.\n \t */\n-\tuint16_t\thds_threshold;\n-\tuint8_t\tunused_0[6];\n+\tuint8_t\tqueue_id7_bw_weight;\n+\tuint8_t\tunused_1[5];\n } __attribute__((packed));\n \n-/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */\n-struct hwrm_vnic_plcmodes_cfg_output {\n+/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */\n+struct hwrm_queue_cos2bw_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -18808,13 +18205,13 @@ struct hwrm_vnic_plcmodes_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***************************\n- * hwrm_vnic_plcmodes_qcfg *\n- ***************************/\n+/*******************\n+ * hwrm_vnic_alloc *\n+ *******************/\n \n \n-/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */\n-struct hwrm_vnic_plcmodes_qcfg_input {\n+/* hwrm_vnic_alloc_input (size:192b/24B) */\n+struct hwrm_vnic_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -18842,138 +18239,17 @@ struct hwrm_vnic_plcmodes_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Logical vnic ID */\n-\tuint32_t\tvnic_id;\n-\tuint8_t\tunused_0[4];\n-} __attribute__((packed));\n-\n-/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */\n-struct hwrm_vnic_plcmodes_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n \tuint32_t\tflags;\n \t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * use regular placement algorithm.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * When this bit is '1', the VNIC is configured to\n-\t * use the jumbo placement algorithm.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * When this bit is '1', the VNIC is configured\n-\t * to enable Header-Data split for IPv4 packets.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * When this bit is '1', the VNIC is configured\n-\t * to enable Header-Data split for IPv6 packets.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * When this bit is '1', the VNIC is configured\n-\t * to enable Header-Data split for FCoE packets.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * When this bit is '1', the VNIC is configured\n-\t * to enable Header-Data split for RoCE packets.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * When this bit is '1', the VNIC is configured\n-\t * to be the default VNIC of the requesting function.\n-\t */\n-\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * When jumbo placement algorithm is enabled, this value\n-\t * is used to determine the threshold for jumbo placement.\n-\t * Packets with length larger than this value will be\n-\t * placed according to the jumbo placement algorithm.\n-\t */\n-\tuint16_t\tjumbo_thresh;\n-\t/*\n-\t * This value is used to determine the offset into\n-\t * packet buffer where the split data (payload) will be\n-\t * placed according to one of of HDS placement algorithm.\n-\t *\n-\t * The lengths of packet buffers provided for split data\n-\t * shall be larger than this value.\n-\t */\n-\tuint16_t\thds_offset;\n-\t/*\n-\t * When one of the HDS placement algorithm is enabled, this\n-\t * value is used to determine the threshold for HDS\n-\t * placement.\n-\t * Packets with length larger than this value will be\n-\t * placed according to the HDS placement algorithm.\n-\t * This value shall be in multiple of 4 bytes.\n-\t */\n-\tuint16_t\thds_threshold;\n-\tuint8_t\tunused_0[5];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**********************************\n- * hwrm_vnic_rss_cos_lb_ctx_alloc *\n- **********************************/\n-\n-\n-/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */\n-struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * When this bit is '1', this VNIC is requested to\n+\t * be the default VNIC for this function.\n \t */\n-\tuint64_t\tresp_addr;\n+\t#define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT UINT32_C(0x1)\n+\tuint8_t\tunused_0[4];\n } __attribute__((packed));\n \n-/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */\n-struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {\n+/* hwrm_vnic_alloc_output (size:128b/16B) */\n+struct hwrm_vnic_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -18982,9 +18258,9 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* rss_cos_lb_ctx_id is 16 b */\n-\tuint16_t\trss_cos_lb_ctx_id;\n-\tuint8_t\tunused_0[5];\n+\t/* Logical vnic ID */\n+\tuint32_t\tvnic_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -18995,13 +18271,13 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*********************************\n- * hwrm_vnic_rss_cos_lb_ctx_free *\n- *********************************/\n+/******************\n+ * hwrm_vnic_free *\n+ ******************/\n \n \n-/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */\n-struct hwrm_vnic_rss_cos_lb_ctx_free_input {\n+/* hwrm_vnic_free_input (size:192b/24B) */\n+struct hwrm_vnic_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -19029,13 +18305,13 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* rss_cos_lb_ctx_id is 16 b */\n-\tuint16_t\trss_cos_lb_ctx_id;\n-\tuint8_t\tunused_0[6];\n+\t/* Logical vnic ID */\n+\tuint32_t\tvnic_id;\n+\tuint8_t\tunused_0[4];\n } __attribute__((packed));\n \n-/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */\n-struct hwrm_vnic_rss_cos_lb_ctx_free_output {\n+/* hwrm_vnic_free_output (size:128b/16B) */\n+struct hwrm_vnic_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -19055,13 +18331,13 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************\n- * hwrm_ring_alloc *\n- *******************/\n+/*****************\n+ * hwrm_vnic_cfg *\n+ *****************/\n \n \n-/* hwrm_ring_alloc_input (size:640b/80B) */\n-struct hwrm_ring_alloc_input {\n+/* hwrm_vnic_cfg_input (size:320b/40B) */\n+struct hwrm_vnic_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -19089,268 +18365,168 @@ struct hwrm_ring_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the ring_arb_cfg field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * This bit must be '1' for the stat_ctx_id_valid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * This bit must be '1' for the max_bw_valid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * This bit must be '1' for the rx_ring_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * This bit must be '1' for the nq_ring_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \\\n-\t\tUINT32_C(0x80)\n+\tuint32_t\tflags;\n \t/*\n-\t * This bit must be '1' for the rx_buf_size field to be\n-\t * configured.\n+\t * When this bit is '1', the VNIC is requested to\n+\t * be the default VNIC for the function.\n \t */\n-\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \\\n-\t\tUINT32_C(0x100)\n-\t/* Ring Type. */\n-\tuint8_t\tring_type;\n-\t/* L2 Completion Ring (CR) */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n-\t/* TX Ring (TR) */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)\n-\t/* RX Ring (RR) */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)\n-\t/* RoCE Notification Completion Ring (ROCE_CR) */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n-\t/* RX Aggregation Ring */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)\n-\t/* Notification Queue */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)\n-\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \\\n-\t\tHWRM_RING_ALLOC_INPUT_RING_TYPE_NQ\n-\tuint8_t\tunused_0[3];\n+\t#define HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * This value is a pointer to the page table for the\n-\t * Ring.\n+\t * When this bit is '1', the VNIC is being configured to\n+\t * strip VLAN in the RX path.\n+\t * If set to '0', then VLAN stripping is disabled on\n+\t * this VNIC.\n \t */\n-\tuint64_t\tpage_tbl_addr;\n-\t/* First Byte Offset of the first entry in the first page. */\n-\tuint32_t\tfbo;\n+\t#define HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * Actual page size in 2^page_size. The supported range is increments\n-\t * in powers of 2 from 16 bytes to 1GB.\n-\t * - 4 = 16 B\n-\t * Page size is 16 B.\n-\t * - 12 = 4 KB\n-\t * Page size is 4 KB.\n-\t * - 13 = 8 KB\n-\t * Page size is 8 KB.\n-\t * - 16 = 64 KB\n-\t * Page size is 64 KB.\n-\t * - 21 = 2 MB\n-\t * Page size is 2 MB.\n-\t * - 22 = 4 MB\n-\t * Page size is 4 MB.\n-\t * - 30 = 1 GB\n-\t * Page size is 1 GB.\n+\t * When this bit is '1', the VNIC is being configured to\n+\t * buffer receive packets in the hardware until the host\n+\t * posts new receive buffers.\n+\t * If set to '0', then bd_stall is being configured to be\n+\t * disabled on this VNIC.\n \t */\n-\tuint8_t\tpage_size;\n+\t#define HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * This value indicates the depth of page table.\n-\t * For this version of the specification, value other than 0 or\n-\t * 1 shall be considered as an invalid value.\n-\t * When the page_tbl_depth = 0, then it is treated as a\n-\t * special case with the following.\n-\t * 1. FBO and page size fields are not valid.\n-\t * 2. page_tbl_addr is the physical address of the first\n-\t * element of the ring.\n+\t * When this bit is '1', the VNIC is being configured to\n+\t * receive both RoCE and non-RoCE traffic.\n+\t * If set to '0', then this VNIC is not configured to be\n+\t * operating in dual VNIC mode.\n \t */\n-\tuint8_t\tpage_tbl_depth;\n-\tuint8_t\tunused_1[2];\n+\t#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_DUAL_VNIC_MODE \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * Number of 16B units in the ring. Minimum size for\n-\t * a ring is 16 16B entries.\n+\t * When this flag is set to '1', the VNIC is requested to\n+\t * be configured to receive only RoCE traffic.\n+\t * If this flag is set to '0', then this flag shall be\n+\t * ignored by the HWRM.\n+\t * If roce_dual_vnic_mode flag is set to '1'\n+\t * or roce_mirroring_capable_vnic_mode flag to 1,\n+\t * then the HWRM client shall not set this flag to '1'.\n \t */\n-\tuint32_t\tlength;\n+\t#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_ONLY_VNIC_MODE \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * Logical ring number for the ring to be allocated.\n-\t * This value determines the position in the doorbell\n-\t * area where the update to the ring will be made.\n+\t * When a VNIC uses one destination ring group for certain\n+\t * application (e.g. Receive Flow Steering) where\n+\t * exact match is used to direct packets to a VNIC with one\n+\t * destination ring group only, there is no need to configure\n+\t * RSS indirection table for that VNIC as only one destination\n+\t * ring group is used.\n \t *\n-\t * For completion rings, this value is also the MSI-X\n-\t * vector number for the function the completion ring is\n-\t * associated with.\n+\t * This flag is used to enable a mode where\n+\t * RSS is enabled in the VNIC using a RSS context\n+\t * for computing RSS hash but the RSS indirection table is\n+\t * not configured using hwrm_vnic_rss_cfg.\n+\t *\n+\t * If this mode is enabled, then the driver should not program\n+\t * RSS indirection table for the RSS context that is used for\n+\t * computing RSS hash only.\n \t */\n-\tuint16_t\tlogical_id;\n+\t#define HWRM_VNIC_CFG_INPUT_FLAGS_RSS_DFLT_CR_MODE \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * This field is used only when ring_type is a TX ring.\n-\t * This value indicates what completion ring the TX ring\n-\t * is associated with.\n+\t * When this bit is '1', the VNIC is being configured to\n+\t * receive both RoCE and non-RoCE traffic, but forward only the\n+\t * RoCE traffic further. Also, RoCE traffic can be mirrored to\n+\t * L2 driver.\n \t */\n-\tuint16_t\tcmpl_ring_id;\n+\t#define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \\\n+\t\tUINT32_C(0x40)\n+\tuint32_t\tenables;\n \t/*\n-\t * This field is used only when ring_type is a TX ring.\n-\t * This value indicates what CoS queue the TX ring\n-\t * is associated with.\n+\t * This bit must be '1' for the dflt_ring_grp field to be\n+\t * configured.\n \t */\n-\tuint16_t\tqueue_id;\n+\t#define HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * When allocating a Rx ring or Rx aggregation ring, this field\n-\t * specifies the size of the buffer descriptors posted to the ring.\n+\t * This bit must be '1' for the rss_rule field to be\n+\t * configured.\n \t */\n-\tuint16_t\trx_buf_size;\n+\t#define HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * When allocating an Rx aggregation ring, this field\n-\t * specifies the associated Rx ring ID.\n+\t * This bit must be '1' for the cos_rule field to be\n+\t * configured.\n \t */\n-\tuint16_t\trx_ring_id;\n+\t#define HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * When allocating a completion ring, this field\n-\t * specifies the associated NQ ring ID.\n+\t * This bit must be '1' for the lb_rule field to be\n+\t * configured.\n \t */\n-\tuint16_t\tnq_ring_id;\n+\t#define HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * This field is used only when ring_type is a TX ring.\n-\t * This field is used to configure arbitration related\n-\t * parameters for a TX ring.\n+\t * This bit must be '1' for the mru field to be\n+\t * configured.\n \t */\n-\tuint16_t\tring_arb_cfg;\n-\t/* Arbitration policy used for the ring. */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \\\n-\t\tUINT32_C(0xf)\n-\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0\n+\t#define HWRM_VNIC_CFG_INPUT_ENABLES_MRU \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * Use strict priority for the TX ring.\n-\t * Priority value is specified in arb_policy_param\n+\t * This bit must be '1' for the default_rx_ring_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * Use weighted fair queue arbitration for the TX ring.\n-\t * Weight is specified in arb_policy_param\n+\t * This bit must be '1' for the default_cmpl_ring_id field to be\n+\t * configured.\n \t */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \\\n-\t\tUINT32_C(0x2)\n-\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \\\n-\t\tHWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ\n-\t/* Reserved field. */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \\\n-\t\tUINT32_C(0xf0)\n-\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4\n+\t#define HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID \\\n+\t\tUINT32_C(0x40)\n+\t/* Logical vnic ID */\n+\tuint16_t\tvnic_id;\n \t/*\n-\t * Arbitration policy specific parameter.\n-\t * # For strict priority arbitration policy, this field\n-\t * represents a priority value. If set to 0, then the priority\n-\t * is not specified and the HWRM is allowed to select\n-\t * any priority for this TX ring.\n-\t * # For weighted fair queue arbitration policy, this field\n-\t * represents a weight value. If set to 0, then the weight\n-\t * is not specified and the HWRM is allowed to select\n-\t * any weight for this TX ring.\n+\t * Default Completion ring for the VNIC. This ring will\n+\t * be chosen if packet does not match any RSS rules and if\n+\t * there is no COS rule.\n \t */\n-\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \\\n-\t\tUINT32_C(0xff00)\n-\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8\n-\tuint16_t\tunused_3;\n+\tuint16_t\tdflt_ring_grp;\n \t/*\n-\t * This field is reserved for the future use.\n-\t * It shall be set to 0.\n+\t * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if\n+\t * there is no RSS rule.\n \t */\n-\tuint32_t\treserved3;\n+\tuint16_t\trss_rule;\n \t/*\n-\t * This field is used only when ring_type is a TX ring.\n-\t * This input indicates what statistics context this ring\n-\t * should be associated with.\n+\t * RSS ID for COS rule/table structure. 0xFF... (All Fs) if\n+\t * there is no COS rule.\n \t */\n-\tuint32_t\tstat_ctx_id;\n+\tuint16_t\tcos_rule;\n \t/*\n-\t * This field is reserved for the future use.\n-\t * It shall be set to 0.\n+\t * RSS ID for load balancing rule/table structure.\n+\t * 0xFF... (All Fs) if there is no LB rule.\n \t */\n-\tuint32_t\treserved4;\n+\tuint16_t\tlb_rule;\n \t/*\n-\t * This field is used only when ring_type is a TX ring\n-\t * to specify maximum BW allocated to the TX ring.\n-\t * The HWRM will translate this value into byte counter and\n-\t * time interval used for this ring inside the device.\n+\t * The maximum receive unit of the vnic.\n+\t * Each vnic is associated with a function.\n+\t * The vnic mru value overwrites the mru setting of the\n+\t * associated function.\n+\t * The HWRM shall make sure that vnic mru does not exceed\n+\t * the mru of the port the function is associated with.\n \t */\n-\tuint32_t\tmax_bw;\n-\t/* The bandwidth value. */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \\\n-\t\tHWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID\n+\tuint16_t\tmru;\n \t/*\n-\t * This field is used only when ring_type is a Completion ring.\n-\t * This value indicates what interrupt mode should be used\n-\t * on this completion ring.\n-\t * Note: In the legacy interrupt mode, no more than 16\n-\t * completion rings are allowed.\n+\t * Default Rx ring for the VNIC. This ring will\n+\t * be chosen if packet does not match any RSS rules.\n+\t * The aggregation ring associated with the Rx ring is\n+\t * implied based on the Rx ring specified when the\n+\t * aggregation ring was allocated.\n \t */\n-\tuint8_t\tint_mode;\n-\t/* Legacy INTA */\n-\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)\n-\t/* Reserved */\n-\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)\n-\t/* MSI-X */\n-\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)\n-\t/* No Interrupt - Polled mode */\n-\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)\n-\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \\\n-\t\tHWRM_RING_ALLOC_INPUT_INT_MODE_POLL\n-\tuint8_t\tunused_4[3];\n+\tuint16_t\tdefault_rx_ring_id;\n+\t/*\n+\t * Default completion ring for the VNIC. This ring will\n+\t * be chosen if packet does not match any RSS rules.\n+\t */\n+\tuint16_t\tdefault_cmpl_ring_id;\n } __attribute__((packed));\n \n-/* hwrm_ring_alloc_output (size:128b/16B) */\n-struct hwrm_ring_alloc_output {\n+/* hwrm_vnic_cfg_output (size:128b/16B) */\n+struct hwrm_vnic_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -19359,14 +18535,7 @@ struct hwrm_ring_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Physical number of ring allocated.\n-\t * This value shall be unique for a ring type.\n-\t */\n-\tuint16_t\tring_id;\n-\t/* Logical number of ring allocated. */\n-\tuint16_t\tlogical_ring_id;\n-\tuint8_t\tunused_0[3];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -19378,12 +18547,12 @@ struct hwrm_ring_alloc_output {\n } __attribute__((packed));\n \n /******************\n- * hwrm_ring_free *\n+ * hwrm_vnic_qcfg *\n ******************/\n \n \n-/* hwrm_ring_free_input (size:192b/24B) */\n-struct hwrm_ring_free_input {\n+/* hwrm_vnic_qcfg_input (size:256b/32B) */\n+struct hwrm_vnic_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -19411,30 +18580,21 @@ struct hwrm_ring_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Ring Type. */\n-\tuint8_t\tring_type;\n-\t/* L2 Completion Ring (CR) */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n-\t/* TX Ring (TR) */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)\n-\t/* RX Ring (RR) */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)\n-\t/* RoCE Notification Completion Ring (ROCE_CR) */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n-\t/* RX Aggregation Ring */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)\n-\t/* Notification Queue */\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)\n-\t#define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \\\n-\t\tHWRM_RING_FREE_INPUT_RING_TYPE_NQ\n-\tuint8_t\tunused_0;\n-\t/* Physical number of ring allocated. */\n-\tuint16_t\tring_id;\n-\tuint8_t\tunused_1[4];\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the vf_id_valid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)\n+\t/* Logical vnic ID */\n+\tuint32_t\tvnic_id;\n+\t/* ID of Virtual Function whose VNIC resource is being queried. */\n+\tuint16_t\tvf_id;\n+\tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_ring_free_output (size:128b/16B) */\n-struct hwrm_ring_free_output {\n+/* hwrm_vnic_qcfg_output (size:256b/32B) */\n+struct hwrm_vnic_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -19443,7 +18603,94 @@ struct hwrm_ring_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* Default Completion ring for the VNIC. */\n+\tuint16_t\tdflt_ring_grp;\n+\t/*\n+\t * RSS ID for RSS rule/table structure. 0xFF... (All Fs) if\n+\t * there is no RSS rule.\n+\t */\n+\tuint16_t\trss_rule;\n+\t/*\n+\t * RSS ID for COS rule/table structure. 0xFF... (All Fs) if\n+\t * there is no COS rule.\n+\t */\n+\tuint16_t\tcos_rule;\n+\t/*\n+\t * RSS ID for load balancing rule/table structure.\n+\t * 0xFF... (All Fs) if there is no LB rule.\n+\t */\n+\tuint16_t\tlb_rule;\n+\t/* The maximum receive unit of the vnic. */\n+\tuint16_t\tmru;\n+\tuint8_t\tunused_0[2];\n+\tuint32_t\tflags;\n+\t/*\n+\t * When this bit is '1', the VNIC is the default VNIC for\n+\t * the function.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * strip VLAN in the RX path.\n+\t * If set to '0', then VLAN stripping is disabled on\n+\t * this VNIC.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * buffer receive packets in the hardware until the host\n+\t * posts new receive buffers.\n+\t * If set to '0', then bd_stall is disabled on\n+\t * this VNIC.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * receive both RoCE and non-RoCE traffic.\n+\t * If set to '0', then this VNIC is not configured to\n+\t * operate in dual VNIC mode.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this flag is set to '1', the VNIC is configured to\n+\t * receive only RoCE traffic.\n+\t * When this flag is set to '0', the VNIC is not configured\n+\t * to receive only RoCE traffic.\n+\t * If roce_dual_vnic_mode flag and this flag both are set\n+\t * to '1', then it is an invalid configuration of the\n+\t * VNIC. The HWRM should not allow that type of\n+\t * mis-configuration by HWRM clients.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * When a VNIC uses one destination ring group for certain\n+\t * application (e.g. Receive Flow Steering) where\n+\t * exact match is used to direct packets to a VNIC with one\n+\t * destination ring group only, there is no need to configure\n+\t * RSS indirection table for that VNIC as only one destination\n+\t * ring group is used.\n+\t *\n+\t * When this bit is set to '1', then the VNIC is enabled in a\n+\t * mode where RSS is enabled in the VNIC using a RSS context\n+\t * for computing RSS hash but the RSS indirection table is\n+\t * not configured.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * When this bit is '1', the VNIC is configured to\n+\t * receive both RoCE and non-RoCE traffic, but forward only\n+\t * RoCE traffic further. Also RoCE traffic can be mirrored to\n+\t * L2 driver.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \\\n+\t\tUINT32_C(0x40)\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -19454,13 +18701,13 @@ struct hwrm_ring_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**************************************\n- * hwrm_ring_cmpl_ring_qaggint_params *\n- **************************************/\n+/*******************\n+ * hwrm_vnic_qcaps *\n+ *******************/\n \n \n-/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */\n-struct hwrm_ring_cmpl_ring_qaggint_params_input {\n+/* hwrm_vnic_qcaps_input (size:192b/24B) */\n+struct hwrm_vnic_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -19488,13 +18735,12 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Physical number of completion ring. */\n-\tuint16_t\tring_id;\n-\tuint8_t\tunused_0[6];\n+\tuint32_t\tenables;\n+\tuint8_t\tunused_0[4];\n } __attribute__((packed));\n \n-/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */\n-struct hwrm_ring_cmpl_ring_qaggint_params_output {\n+/* hwrm_vnic_qcaps_output (size:192b/24B) */\n+struct hwrm_vnic_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -19503,53 +18749,74 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint16_t\tflags;\n-\t/*\n-\t * When this bit is set to '1', interrupt max\n-\t * timer is reset whenever a completion is received.\n-\t */\n-\t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \\\n+\t/* The maximum receive unit that is settable on a vnic. */\n+\tuint16_t\tmru;\n+\tuint8_t\tunused_0[2];\n+\tuint32_t\tflags;\n+\t/* Unused. */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_UNUSED \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * When this bit is set to '1', ring idle mode\n-\t * aggregation will be enabled.\n+\t * When this bit is '1', the capability of stripping VLAN in\n+\t * the RX path is supported on VNIC(s).\n+\t * If set to '0', then VLAN stripping capability is\n+\t * not supported on VNIC(s).\n \t */\n-\t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \\\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VLAN_STRIP_CAP \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * Number of completions to aggregate before DMA\n-\t * during the normal mode.\n+\t * When this bit is '1', the capability to buffer receive\n+\t * packets in the hardware until the host posts new receive buffers\n+\t * is supported on VNIC(s).\n+\t * If set to '0', then bd_stall capability is not supported\n+\t * on VNIC(s).\n \t */\n-\tuint16_t\tnum_cmpl_dma_aggr;\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_BD_STALL_CAP \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * Number of completions to aggregate before DMA\n-\t * during the interrupt mode.\n+\t * When this bit is '1', the capability to\n+\t * receive both RoCE and non-RoCE traffic on VNIC(s) is\n+\t * supported.\n+\t * If set to '0', then the capability to receive\n+\t * both RoCE and non-RoCE traffic on VNIC(s) is\n+\t * not supported.\n \t */\n-\tuint16_t\tnum_cmpl_dma_aggr_during_int;\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_DUAL_VNIC_CAP \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * Timer in unit of 80-nsec used to aggregate completions before\n-\t * DMA during the normal mode (not in interrupt mode).\n+\t * When this bit is set to '1', the capability to configure\n+\t * a VNIC to receive only RoCE traffic is supported.\n+\t * When this flag is set to '0', the VNIC capability to\n+\t * configure to receive only RoCE traffic is not supported.\n \t */\n-\tuint16_t\tcmpl_aggr_dma_tmr;\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_ONLY_VNIC_CAP \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * Timer in unit of 80-nsec used to aggregate completions before\n-\t * DMA during the interrupt mode.\n+\t * When this bit is set to '1', then the capability to enable\n+\t * a VNIC in a mode where RSS context without configuring\n+\t * RSS indirection table is supported (for RSS hash computation).\n+\t * When this bit is set to '0', then a VNIC can not be configured\n+\t * with a mode to enable RSS context without configuring RSS\n+\t * indirection table.\n \t */\n-\tuint16_t\tcmpl_aggr_dma_tmr_during_int;\n-\t/* Minimum time (in unit of 80-nsec) between two interrupts. */\n-\tuint16_t\tint_lat_tmr_min;\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_DFLT_CR_CAP \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * Maximum wait time (in unit of 80-nsec) spent aggregating\n-\t * completions before signaling the interrupt after the\n-\t * interrupt is enabled.\n+\t * When this bit is '1', the capability to\n+\t * mirror the the RoCE traffic is supported.\n+\t * If set to '0', then the capability to mirror the\n+\t * RoCE traffic is not supported.\n \t */\n-\tuint16_t\tint_lat_tmr_max;\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * Minimum number of completions aggregated before signaling\n-\t * an interrupt.\n+\t * When this bit is '1', the outermost RSS hashing capability\n+\t * is supported. If set to '0', then the outermost RSS hashing\n+\t * capability is not supported.\n \t */\n-\tuint16_t\tnum_cmpl_aggr_int;\n-\tuint8_t\tunused_0[7];\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \\\n+\t\tUINT32_C(0x80)\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -19560,13 +18827,13 @@ struct hwrm_ring_cmpl_ring_qaggint_params_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*****************************************\n- * hwrm_ring_cmpl_ring_cfg_aggint_params *\n- *****************************************/\n+/*********************\n+ * hwrm_vnic_tpa_cfg *\n+ *********************/\n \n \n-/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */\n-struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {\n+/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */\n+struct hwrm_vnic_tpa_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -19594,109 +18861,145 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Physical number of completion ring. */\n-\tuint16_t\tring_id;\n-\tuint16_t\tflags;\n+\tuint32_t\tflags;\n \t/*\n-\t * When this bit is set to '1', interrupt latency max\n-\t * timer is reset whenever a completion is received.\n+\t * When this bit is '1', the VNIC shall be configured to\n+\t * perform transparent packet aggregation (TPA) of\n+\t * non-tunneled TCP packets.\n \t */\n-\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \\\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * When this bit is set to '1', ring idle mode\n-\t * aggregation will be enabled.\n+\t * When this bit is '1', the VNIC shall be configured to\n+\t * perform transparent packet aggregation (TPA) of\n+\t * tunneled TCP packets.\n \t */\n-\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \\\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * Set this flag to 1 when configuring parameters on a\n-\t * notification queue. Set this flag to 0 when configuring\n-\t * parameters on a completion queue.\n+\t * When this bit is '1', the VNIC shall be configured to\n+\t * perform transparent packet aggregation (TPA) according\n+\t * to Windows Receive Segment Coalescing (RSC) rules.\n \t */\n-\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \\\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * Number of completions to aggregate before DMA\n-\t * during the normal mode.\n+\t * When this bit is '1', the VNIC shall be configured to\n+\t * perform transparent packet aggregation (TPA) according\n+\t * to Linux Generic Receive Offload (GRO) rules.\n \t */\n-\tuint16_t\tnum_cmpl_dma_aggr;\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * Number of completions to aggregate before DMA\n-\t * during the interrupt mode.\n+\t * When this bit is '1', the VNIC shall be configured to\n+\t * perform transparent packet aggregation (TPA) for TCP\n+\t * packets with IP ECN set to non-zero.\n \t */\n-\tuint16_t\tnum_cmpl_dma_aggr_during_int;\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * Timer in unit of 80-nsec used to aggregate completions before\n-\t * DMA during the normal mode (not in interrupt mode).\n+\t * When this bit is '1', the VNIC shall be configured to\n+\t * perform transparent packet aggregation (TPA) for\n+\t * GRE tunneled TCP packets only if all packets have the\n+\t * same GRE sequence.\n \t */\n-\tuint16_t\tcmpl_aggr_dma_tmr;\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * Timer in unit of 80-nsec used to aggregate completions before\n-\t * DMA during the interrupt mode.\n+\t * When this bit is '1' and the GRO mode is enabled,\n+\t * the VNIC shall be configured to\n+\t * perform transparent packet aggregation (TPA) for\n+\t * TCP/IPv4 packets with consecutively increasing IPIDs.\n+\t * In other words, the last packet that is being\n+\t * aggregated to an already existing aggregation context\n+\t * shall have IPID 1 more than the IPID of the last packet\n+\t * that was aggregated in that aggregation context.\n \t */\n-\tuint16_t\tcmpl_aggr_dma_tmr_during_int;\n-\t/* Minimum time (in unit of 80-nsec) between two interrupts. */\n-\tuint16_t\tint_lat_tmr_min;\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_IPID_CHECK \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * Maximum wait time (in unit of 80-nsec) spent aggregating\n-\t * cmpls before signaling the interrupt after the\n-\t * interrupt is enabled.\n+\t * When this bit is '1' and the GRO mode is enabled,\n+\t * the VNIC shall be configured to\n+\t * perform transparent packet aggregation (TPA) for\n+\t * TCP packets with the same TTL (IPv4) or Hop limit (IPv6)\n+\t * value.\n \t */\n-\tuint16_t\tint_lat_tmr_max;\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \\\n+\t\tUINT32_C(0x80)\n+\tuint32_t\tenables;\n \t/*\n-\t * Minimum number of completions aggregated before signaling\n-\t * an interrupt.\n+\t * This bit must be '1' for the max_agg_segs field to be\n+\t * configured.\n \t */\n-\tuint16_t\tnum_cmpl_aggr_int;\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS UINT32_C(0x1)\n \t/*\n-\t * Bitfield that indicates which parameters are to be applied. Only\n-\t * required when configuring devices with notification queues, and\n-\t * used in that case to set certain parameters on completion queues\n-\t * and others on notification queues.\n+\t * This bit must be '1' for the max_aggs field to be\n+\t * configured.\n \t */\n-\tuint16_t\tenables;\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS UINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the num_cmpl_dma_aggr field to be\n+\t * This bit must be '1' for the max_agg_timer field to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \\\n-\t\tUINT32_C(0x1)\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be\n+\t * This bit must be '1' for the min_agg_len field to be\n \t * configured.\n \t */\n-\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \\\n-\t\tUINT32_C(0x2)\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)\n+\t/* Logical vnic ID */\n+\tuint16_t\tvnic_id;\n \t/*\n-\t * This bit must be '1' for the cmpl_aggr_dma_tmr field to be\n-\t * configured.\n+\t * This is the maximum number of TCP segments that can\n+\t * be aggregated (unit is Log2). Max value is 31.\n \t */\n-\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \\\n-\t\tUINT32_C(0x4)\n+\tuint16_t\tmax_agg_segs;\n+\t/* 1 segment */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_1 UINT32_C(0x0)\n+\t/* 2 segments */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_2 UINT32_C(0x1)\n+\t/* 4 segments */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_4 UINT32_C(0x2)\n+\t/* 8 segments */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_8 UINT32_C(0x3)\n+\t/* Any segment size larger than this is not valid */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX UINT32_C(0x1f)\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_LAST \\\n+\t\tHWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX\n \t/*\n-\t * This bit must be '1' for the int_lat_tmr_min field to be\n-\t * configured.\n+\t * This is the maximum number of aggregations this VNIC is\n+\t * allowed (unit is Log2). Max value is 7\n \t */\n-\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \\\n-\t\tUINT32_C(0x8)\n+\tuint16_t\tmax_aggs;\n+\t/* 1 aggregation */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_1 UINT32_C(0x0)\n+\t/* 2 aggregations */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_2 UINT32_C(0x1)\n+\t/* 4 aggregations */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_4 UINT32_C(0x2)\n+\t/* 8 aggregations */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_8 UINT32_C(0x3)\n+\t/* 16 aggregations */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_16 UINT32_C(0x4)\n+\t/* Any aggregation size larger than this is not valid */\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX UINT32_C(0x7)\n+\t#define HWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_LAST \\\n+\t\tHWRM_VNIC_TPA_CFG_INPUT_MAX_AGGS_MAX\n+\tuint8_t\tunused_0[2];\n \t/*\n-\t * This bit must be '1' for the int_lat_tmr_max field to be\n-\t * configured.\n+\t * This is the maximum amount of time allowed for\n+\t * an aggregation context to complete after it was initiated.\n \t */\n-\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \\\n-\t\tUINT32_C(0x10)\n+\tuint32_t\tmax_agg_timer;\n \t/*\n-\t * This bit must be '1' for the num_cmpl_aggr_int field to be\n-\t * configured.\n+\t * This is the minimum amount of payload length required to\n+\t * start an aggregation context.\n \t */\n-\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \\\n-\t\tUINT32_C(0x20)\n-\tuint8_t\tunused_0[4];\n+\tuint32_t\tmin_agg_len;\n } __attribute__((packed));\n \n-/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */\n-struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {\n+/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */\n+struct hwrm_vnic_tpa_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -19716,13 +19019,13 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************\n- * hwrm_ring_reset *\n- *******************/\n+/*********************\n+ * hwrm_vnic_rss_cfg *\n+ *********************/\n \n \n-/* hwrm_ring_reset_input (size:192b/24B) */\n-struct hwrm_ring_reset_input {\n+/* hwrm_vnic_rss_cfg_input (size:384b/48B) */\n+struct hwrm_vnic_rss_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -19750,26 +19053,103 @@ struct hwrm_ring_reset_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Ring Type. */\n-\tuint8_t\tring_type;\n-\t/* L2 Completion Ring (CR) */\n-\t#define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n-\t/* TX Ring (TR) */\n-\t#define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)\n-\t/* RX Ring (RR) */\n-\t#define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)\n-\t/* RoCE Notification Completion Ring (ROCE_CR) */\n-\t#define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n-\t#define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \\\n-\t\tHWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL\n-\tuint8_t\tunused_0;\n-\t/* Physical number of the ring. */\n-\tuint16_t\tring_id;\n-\tuint8_t\tunused_1[4];\n+\tuint32_t\thash_type;\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source and destination IPv4 addresses of IPv4\n+\t * packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4 UINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv4 addresses and\n+\t * source/destination ports of TCP/IPv4 packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv4 addresses and\n+\t * source/destination ports of UDP/IPv4 packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source and destination IPv4 addresses of IPv6\n+\t * packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6 UINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv6 addresses and\n+\t * source/destination ports of TCP/IPv6 packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv6 addresses and\n+\t * source/destination ports of UDP/IPv6 packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)\n+\t/* VNIC ID of VNIC associated with RSS table being configured. */\n+\tuint16_t\tvnic_id;\n+\t/*\n+\t * Specifies which VNIC ring table pair to configure.\n+\t * Valid values range from 0 to 7.\n+\t */\n+\tuint8_t\tring_table_pair_index;\n+\t/* Flags to specify different RSS hash modes. */\n+\tuint8_t\thash_mode_flags;\n+\t/*\n+\t * When this bit is '1', it indicates using current RSS\n+\t * hash mode setting configured in the device.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over innermost 4 tuples {l3.src, l3.dest,\n+\t * l4.src, l4.dest} for tunnel packets. For none-tunnel\n+\t * packets, the RSS hash is computed over the normal\n+\t * src/dest l3 and src/dest l4 headers.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for\n+\t * tunnel packets. For none-tunnel packets, the RSS hash is\n+\t * computed over the normal src/dest l3 headers.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,\n+\t * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel\n+\t * packets, the RSS hash is computed over the normal\n+\t * src/dest l3 and src/dest l4 headers.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for\n+\t * tunnel packets. For none-tunnel packets, the RSS hash is\n+\t * computed over the normal src/dest l3 headers.\n+\t */\n+\t#define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \\\n+\t\tUINT32_C(0x10)\n+\t/* This is the address for rss ring group table */\n+\tuint64_t\tring_grp_tbl_addr;\n+\t/* This is the address for rss hash key table */\n+\tuint64_t\thash_key_tbl_addr;\n+\t/* Index to the rss indirection table. */\n+\tuint16_t\trss_ctx_idx;\n+\tuint8_t\tunused_1[6];\n } __attribute__((packed));\n \n-/* hwrm_ring_reset_output (size:128b/16B) */\n-struct hwrm_ring_reset_output {\n+/* hwrm_vnic_rss_cfg_output (size:128b/16B) */\n+struct hwrm_vnic_rss_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -19789,13 +19169,13 @@ struct hwrm_ring_reset_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_ring_grp_alloc *\n- ***********************/\n+/**********************\n+ * hwrm_vnic_rss_qcfg *\n+ **********************/\n \n \n-/* hwrm_ring_grp_alloc_input (size:192b/24B) */\n-struct hwrm_ring_grp_alloc_input {\n+/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */\n+struct hwrm_vnic_rss_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -19823,31 +19203,13 @@ struct hwrm_ring_grp_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * This value identifies the CR associated with the ring\n-\t * group.\n-\t */\n-\tuint16_t\tcr;\n-\t/*\n-\t * This value identifies the main RR associated with the ring\n-\t * group.\n-\t */\n-\tuint16_t\trr;\n-\t/*\n-\t * This value identifies the aggregation RR associated with\n-\t * the ring group. If this value is 0xFF... (All Fs), then no\n-\t * Aggregation ring will be set.\n-\t */\n-\tuint16_t\tar;\n-\t/*\n-\t * This value identifies the statistics context associated\n-\t * with the ring group.\n-\t */\n-\tuint16_t\tsc;\n+\t/* Index to the rss indirection table. */\n+\tuint16_t\trss_ctx_idx;\n+\tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_ring_grp_alloc_output (size:128b/16B) */\n-struct hwrm_ring_grp_alloc_output {\n+/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */\n+struct hwrm_vnic_rss_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -19856,73 +19218,89 @@ struct hwrm_ring_grp_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\tuint32_t\thash_type;\n \t/*\n-\t * This is the ring group ID value. Use this value to program\n-\t * the default ring group for the VNIC or as table entries\n-\t * in an RSS/COS context.\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source and destination IPv4 addresses of IPv4\n+\t * packets.\n \t */\n-\tuint32_t\tring_group_id;\n-\tuint8_t\tunused_0[3];\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1)\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv4 addresses and\n+\t * source/destination ports of TCP/IPv4 packets.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**********************\n- * hwrm_ring_grp_free *\n- **********************/\n-\n-\n-/* hwrm_ring_grp_free_input (size:192b/24B) */\n-struct hwrm_ring_grp_free_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2)\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv4 addresses and\n+\t * source/destination ports of UDP/IPv4 packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source and destination IPv4 addresses of IPv6\n+\t * packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv6 addresses and\n+\t * source/destination ports of TCP/IPv6 packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv6 addresses and\n+\t * source/destination ports of UDP/IPv6 packets.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20)\n+\tuint8_t\tunused_0[4];\n+\t/* This is the value of rss hash key */\n+\tuint32_t\thash_key[10];\n+\t/* Flags to specify different RSS hash modes. */\n+\tuint8_t\thash_mode_flags;\n+\t/*\n+\t * When this bit is '1', it indicates using current RSS\n+\t * hash mode setting configured in the device.\n+\t */\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over innermost 4 tuples {l3.src, l3.dest,\n+\t * l4.src, l4.dest} for tunnel packets. For none-tunnel\n+\t * packets, the RSS hash is computed over the normal\n+\t * src/dest l3 and src/dest l4 headers.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for\n+\t * tunnel packets. For none-tunnel packets, the RSS hash is\n+\t * computed over the normal src/dest l3 headers.\n \t */\n-\tuint16_t\tseq_id;\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,\n+\t * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel\n+\t * packets, the RSS hash is computed over the normal\n+\t * src/dest l3 and src/dest l4 headers.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for\n+\t * tunnel packets. For none-tunnel packets, the RSS hash is\n+\t * computed over the normal src/dest l3 headers.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* This is the ring group ID value. */\n-\tuint32_t\tring_group_id;\n-\tuint8_t\tunused_0[4];\n-} __attribute__((packed));\n-\n-/* hwrm_ring_grp_free_output (size:128b/16B) */\n-struct hwrm_ring_grp_free_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t#define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \\\n+\t\tUINT32_C(0x10)\n+\tuint8_t\tunused_1[6];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -19933,13 +19311,13 @@ struct hwrm_ring_grp_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/****************************\n- * hwrm_cfa_l2_filter_alloc *\n- ****************************/\n+/**************************\n+ * hwrm_vnic_plcmodes_cfg *\n+ **************************/\n \n \n-/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */\n-struct hwrm_cfa_l2_filter_alloc_input {\n+/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */\n+struct hwrm_vnic_plcmodes_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -19969,344 +19347,251 @@ struct hwrm_cfa_l2_filter_alloc_input {\n \tuint64_t\tresp_addr;\n \tuint32_t\tflags;\n \t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \\\n-\t\tUINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \\\n-\t\tUINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \\\n-\t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX\n-\t/* Setting of this flag indicates the applicability to the loopback path. */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * If this flag is set, all t_l2_* fields are invalid\n-\t * and they should not be specified.\n-\t * If this flag is set, then l2_* fields refer to\n-\t * fields of outermost L2 header.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \\\n-\t\tUINT32_C(0x8)\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the l2_addr field to be\n-\t * configured.\n+\t * When this bit is '1', the VNIC shall be configured to\n+\t * use regular placement algorithm.\n+\t * By default, the regular placement algorithm shall be\n+\t * enabled on the VNIC.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \\\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_REGULAR_PLACEMENT \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the l2_addr_mask field to be\n-\t * configured.\n+\t * When this bit is '1', the VNIC shall be configured\n+\t * use the jumbo placement algorithm.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \\\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the l2_ovlan field to be\n-\t * configured.\n+\t * When this bit is '1', the VNIC shall be configured\n+\t * to enable Header-Data split for IPv4 packets according\n+\t * to the following rules:\n+\t * # If the packet is identified as TCP/IPv4, then the\n+\t * packet is split at the beginning of the TCP payload.\n+\t * # If the packet is identified as UDP/IPv4, then the\n+\t * packet is split at the beginning of UDP payload.\n+\t * # If the packet is identified as non-TCP and non-UDP\n+\t * IPv4 packet, then the packet is split at the beginning\n+\t * of the upper layer protocol header carried in the IPv4\n+\t * packet.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \\\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV4 \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the l2_ovlan_mask field to be\n-\t * configured.\n+\t * When this bit is '1', the VNIC shall be configured\n+\t * to enable Header-Data split for IPv6 packets according\n+\t * to the following rules:\n+\t * # If the packet is identified as TCP/IPv6, then the\n+\t * packet is split at the beginning of the TCP payload.\n+\t * # If the packet is identified as UDP/IPv6, then the\n+\t * packet is split at the beginning of UDP payload.\n+\t * # If the packet is identified as non-TCP and non-UDP\n+\t * IPv6 packet, then the packet is split at the beginning\n+\t * of the upper layer protocol header carried in the IPv6\n+\t * packet.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \\\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_IPV6 \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * This bit must be '1' for the l2_ivlan field to be\n-\t * configured.\n+\t * When this bit is '1', the VNIC shall be configured\n+\t * to enable Header-Data split for FCoE packets at the\n+\t * beginning of FC payload.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \\\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_FCOE \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * This bit must be '1' for the l2_ivlan_mask field to be\n-\t * configured.\n+\t * When this bit is '1', the VNIC shall be configured\n+\t * to enable Header-Data split for RoCE packets at the\n+\t * beginning of RoCE payload (after BTH/GRH headers).\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \\\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_HDS_ROCE \\\n \t\tUINT32_C(0x20)\n+\tuint32_t\tenables;\n \t/*\n-\t * This bit must be '1' for the t_l2_addr field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * This bit must be '1' for the t_l2_addr_mask field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \\\n-\t\tUINT32_C(0x80)\n-\t/*\n-\t * This bit must be '1' for the t_l2_ovlan field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \\\n-\t\tUINT32_C(0x100)\n-\t/*\n-\t * This bit must be '1' for the t_l2_ovlan_mask field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \\\n-\t\tUINT32_C(0x200)\n-\t/*\n-\t * This bit must be '1' for the t_l2_ivlan field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \\\n-\t\tUINT32_C(0x400)\n-\t/*\n-\t * This bit must be '1' for the t_l2_ivlan_mask field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \\\n-\t\tUINT32_C(0x800)\n-\t/*\n-\t * This bit must be '1' for the src_type field to be\n+\t * This bit must be '1' for the jumbo_thresh_valid field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \\\n-\t\tUINT32_C(0x1000)\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the src_id field to be\n+\t * This bit must be '1' for the hds_offset_valid field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \\\n-\t\tUINT32_C(0x2000)\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the tunnel_type field to be\n+\t * This bit must be '1' for the hds_threshold_valid field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n-\t\tUINT32_C(0x4000)\n+\t#define HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID \\\n+\t\tUINT32_C(0x4)\n+\t/* Logical vnic ID */\n+\tuint32_t\tvnic_id;\n \t/*\n-\t * This bit must be '1' for the dst_id field to be\n-\t * configured.\n+\t * When jumbo placement algorithm is enabled, this value\n+\t * is used to determine the threshold for jumbo placement.\n+\t * Packets with length larger than this value will be\n+\t * placed according to the jumbo placement algorithm.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n-\t\tUINT32_C(0x8000)\n+\tuint16_t\tjumbo_thresh;\n \t/*\n-\t * This bit must be '1' for the mirror_vnic_id field to be\n-\t * configured.\n+\t * This value is used to determine the offset into\n+\t * packet buffer where the split data (payload) will be\n+\t * placed according to one of of HDS placement algorithm.\n+\t *\n+\t * The lengths of packet buffers provided for split data\n+\t * shall be larger than this value.\n \t */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n-\t\tUINT32_C(0x10000)\n+\tuint16_t\thds_offset;\n \t/*\n-\t * This value sets the match value for the L2 MAC address.\n-\t * Destination MAC address for RX path.\n-\t * Source MAC address for TX path.\n+\t * When one of the HDS placement algorithm is enabled, this\n+\t * value is used to determine the threshold for HDS\n+\t * placement.\n+\t * Packets with length larger than this value will be\n+\t * placed according to the HDS placement algorithm.\n+\t * This value shall be in multiple of 4 bytes.\n \t */\n-\tuint8_t\tl2_addr[6];\n-\tuint8_t\tunused_0[2];\n+\tuint16_t\thds_threshold;\n+\tuint8_t\tunused_0[6];\n+} __attribute__((packed));\n+\n+/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */\n+struct hwrm_vnic_plcmodes_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * This value sets the mask value for the L2 address.\n-\t * A value of 0 will mask the corresponding bit from\n-\t * compare.\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\tl2_addr_mask[6];\n-\t/* This value sets VLAN ID value for outer VLAN. */\n-\tuint16_t\tl2_ovlan;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***************************\n+ * hwrm_vnic_plcmodes_qcfg *\n+ ***************************/\n+\n+\n+/* hwrm_vnic_plcmodes_qcfg_input (size:192b/24B) */\n+struct hwrm_vnic_plcmodes_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * This value sets the mask value for the ovlan id.\n-\t * A value of 0 will mask the corresponding bit from\n-\t * compare.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint16_t\tl2_ovlan_mask;\n-\t/* This value sets VLAN ID value for inner VLAN. */\n-\tuint16_t\tl2_ivlan;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * This value sets the mask value for the ivlan id.\n-\t * A value of 0 will mask the corresponding bit from\n-\t * compare.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint16_t\tl2_ivlan_mask;\n-\tuint8_t\tunused_1[2];\n+\tuint16_t\tseq_id;\n \t/*\n-\t * This value sets the match value for the tunnel\n-\t * L2 MAC address.\n-\t * Destination MAC address for RX path.\n-\t * Source MAC address for TX path.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint8_t\tt_l2_addr[6];\n-\tuint8_t\tunused_2[2];\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * This value sets the mask value for the tunnel L2\n-\t * address.\n-\t * A value of 0 will mask the corresponding bit from\n-\t * compare.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint8_t\tt_l2_addr_mask[6];\n-\t/* This value sets VLAN ID value for tunnel outer VLAN. */\n-\tuint16_t\tt_l2_ovlan;\n+\tuint64_t\tresp_addr;\n+\t/* Logical vnic ID */\n+\tuint32_t\tvnic_id;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_vnic_plcmodes_qcfg_output (size:192b/24B) */\n+struct hwrm_vnic_plcmodes_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n \t/*\n-\t * This value sets the mask value for the tunnel ovlan id.\n-\t * A value of 0 will mask the corresponding bit from\n-\t * compare.\n+\t * When this bit is '1', the VNIC is configured to\n+\t * use regular placement algorithm.\n \t */\n-\tuint16_t\tt_l2_ovlan_mask;\n-\t/* This value sets VLAN ID value for tunnel inner VLAN. */\n-\tuint16_t\tt_l2_ivlan;\n+\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_REGULAR_PLACEMENT \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * This value sets the mask value for the tunnel ivlan id.\n-\t * A value of 0 will mask the corresponding bit from\n-\t * compare.\n+\t * When this bit is '1', the VNIC is configured to\n+\t * use the jumbo placement algorithm.\n \t */\n-\tuint16_t\tt_l2_ivlan_mask;\n-\t/* This value identifies the type of source of the packet. */\n-\tuint8_t\tsrc_type;\n-\t/* Network port */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)\n-\t/* Physical function */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)\n-\t/* Virtual function */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)\n-\t/* Virtual NIC of a function */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)\n-\t/* Embedded processor for CFA management */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)\n-\t/* Embedded processor for OOB management */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)\n-\t/* Embedded processor for RoCE */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)\n-\t/* Embedded processor for network proxy functions */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \\\n-\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG\n-\tuint8_t\tunused_3;\n+\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_JUMBO_PLACEMENT \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * This value is the id of the source.\n-\t * For a network port, it represents port_id.\n-\t * For a physical function, it represents fid.\n-\t * For a virtual function, it represents vf_id.\n-\t * For a vnic, it represents vnic_id.\n-\t * For embedded processors, this id is not valid.\n-\t *\n-\t * Notes:\n-\t * 1. The function ID is implied if it src_id is\n-\t * not provided for a src_type that is either\n+\t * When this bit is '1', the VNIC is configured\n+\t * to enable Header-Data split for IPv4 packets.\n \t */\n-\tuint32_t\tsrc_id;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n-\t\tUINT32_C(0x0)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n-\t\tUINT32_C(0x2)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n-\t\tUINT32_C(0x3)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV4 \\\n \t\tUINT32_C(0x4)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n-\t\tUINT32_C(0x6)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n-\t\tUINT32_C(0x7)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t/*\n+\t * When this bit is '1', the VNIC is configured\n+\t * to enable Header-Data split for IPv6 packets.\n+\t */\n+\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_IPV6 \\\n \t\tUINT32_C(0x8)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n-\tuint8_t\tunused_4;\n \t/*\n-\t * If set, this value shall represent the\n-\t * Logical VNIC ID of the destination VNIC for the RX\n-\t * path and network port id of the destination port for\n-\t * the TX path.\n+\t * When this bit is '1', the VNIC is configured\n+\t * to enable Header-Data split for FCoE packets.\n \t */\n-\tuint16_t\tdst_id;\n+\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_FCOE \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * Logical VNIC ID of the VNIC where traffic is\n-\t * mirrored.\n+\t * When this bit is '1', the VNIC is configured\n+\t * to enable Header-Data split for RoCE packets.\n \t */\n-\tuint16_t\tmirror_vnic_id;\n+\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_HDS_ROCE \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * This hint is provided to help in placing\n-\t * the filter in the filter table.\n+\t * When this bit is '1', the VNIC is configured\n+\t * to be the default VNIC of the requesting function.\n \t */\n-\tuint8_t\tpri_hint;\n-\t/* No preference */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \\\n-\t\tUINT32_C(0x0)\n-\t/* Above the given filter */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \\\n-\t\tUINT32_C(0x1)\n-\t/* Below the given filter */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \\\n-\t\tUINT32_C(0x2)\n-\t/* As high as possible */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \\\n-\t\tUINT32_C(0x3)\n-\t/* As low as possible */\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \\\n-\t\tUINT32_C(0x4)\n-\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \\\n-\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN\n-\tuint8_t\tunused_5;\n-\tuint32_t\tunused_6;\n+\t#define HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * This is the ID of the filter that goes along with\n-\t * the pri_hint.\n-\t *\n-\t * This field is valid only for the following values.\n-\t * 1 - Above the given filter\n-\t * 2 - Below the given filter\n+\t * When jumbo placement algorithm is enabled, this value\n+\t * is used to determine the threshold for jumbo placement.\n+\t * Packets with length larger than this value will be\n+\t * placed according to the jumbo placement algorithm.\n \t */\n-\tuint64_t\tl2_filter_id_hint;\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */\n-struct hwrm_cfa_l2_filter_alloc_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n+\tuint16_t\tjumbo_thresh;\n \t/*\n-\t * This value identifies a set of CFA data structures used for an L2\n-\t * context.\n+\t * This value is used to determine the offset into\n+\t * packet buffer where the split data (payload) will be\n+\t * placed according to one of of HDS placement algorithm.\n+\t *\n+\t * The lengths of packet buffers provided for split data\n+\t * shall be larger than this value.\n \t */\n-\tuint64_t\tl2_filter_id;\n+\tuint16_t\thds_offset;\n \t/*\n-\t * This is the ID of the flow associated with this\n-\t * filter.\n-\t * This value shall be used to match and associate the\n-\t * flow identifier returned in completion records.\n-\t * A value of 0xFFFFFFFF shall indicate no flow id.\n+\t * When one of the HDS placement algorithm is enabled, this\n+\t * value is used to determine the threshold for HDS\n+\t * placement.\n+\t * Packets with length larger than this value will be\n+\t * placed according to the HDS placement algorithm.\n+\t * This value shall be in multiple of 4 bytes.\n \t */\n-\tuint32_t\tflow_id;\n-\tuint8_t\tunused_0[3];\n+\tuint16_t\thds_threshold;\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -20317,13 +19602,13 @@ struct hwrm_cfa_l2_filter_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***************************\n- * hwrm_cfa_l2_filter_free *\n- ***************************/\n+/**********************************\n+ * hwrm_vnic_rss_cos_lb_ctx_alloc *\n+ **********************************/\n \n \n-/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */\n-struct hwrm_cfa_l2_filter_free_input {\n+/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */\n+struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -20351,15 +19636,10 @@ struct hwrm_cfa_l2_filter_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * This value identifies a set of CFA data structures used for an L2\n-\t * context.\n-\t */\n-\tuint64_t\tl2_filter_id;\n } __attribute__((packed));\n \n-/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */\n-struct hwrm_cfa_l2_filter_free_output {\n+/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */\n+struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -20368,7 +19648,9 @@ struct hwrm_cfa_l2_filter_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* rss_cos_lb_ctx_id is 16 b */\n+\tuint16_t\trss_cos_lb_ctx_id;\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -20379,13 +19661,13 @@ struct hwrm_cfa_l2_filter_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**************************\n- * hwrm_cfa_l2_filter_cfg *\n- **************************/\n+/*********************************\n+ * hwrm_vnic_rss_cos_lb_ctx_free *\n+ *********************************/\n \n \n-/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */\n-struct hwrm_cfa_l2_filter_cfg_input {\n+/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */\n+struct hwrm_vnic_rss_cos_lb_ctx_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -20413,58 +19695,13 @@ struct hwrm_cfa_l2_filter_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX\n-\t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP UINT32_C(0x2)\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the dst_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the new_mirror_vnic_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * This value identifies a set of CFA data structures used for an L2\n-\t * context.\n-\t */\n-\tuint64_t\tl2_filter_id;\n-\t/*\n-\t * If set, this value shall represent the\n-\t * Logical VNIC ID of the destination VNIC for the RX\n-\t * path and network port id of the destination port for\n-\t * the TX path.\n-\t */\n-\tuint32_t\tdst_id;\n-\t/*\n-\t * New Logical VNIC ID of the VNIC where traffic is\n-\t * mirrored.\n-\t */\n-\tuint32_t\tnew_mirror_vnic_id;\n+\t/* rss_cos_lb_ctx_id is 16 b */\n+\tuint16_t\trss_cos_lb_ctx_id;\n+\tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */\n-struct hwrm_cfa_l2_filter_cfg_output {\n+/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */\n+struct hwrm_vnic_rss_cos_lb_ctx_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -20484,13 +19721,13 @@ struct hwrm_cfa_l2_filter_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***************************\n- * hwrm_cfa_l2_set_rx_mask *\n- ***************************/\n+/*******************\n+ * hwrm_ring_alloc *\n+ *******************/\n \n \n-/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */\n-struct hwrm_cfa_l2_set_rx_mask_input {\n+/* hwrm_ring_alloc_input (size:704b/88B) */\n+struct hwrm_ring_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -20518,134 +19755,286 @@ struct hwrm_cfa_l2_set_rx_mask_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* VNIC ID */\n-\tuint32_t\tvnic_id;\n-\tuint32_t\tmask;\n+\tuint32_t\tenables;\n \t/*\n-\t * When this bit is '1', the function is requested to accept\n-\t * multi-cast packets specified by the multicast addr table.\n+\t * This bit must be '1' for the ring_arb_cfg field to be\n+\t * configured.\n \t */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \\\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RING_ARB_CFG \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * When this bit is '1', the function is requested to accept\n-\t * all multi-cast packets.\n+\t * This bit must be '1' for the stat_ctx_id_valid field to be\n+\t * configured.\n \t */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \\\n-\t\tUINT32_C(0x4)\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * When this bit is '1', the function is requested to accept\n-\t * broadcast packets.\n+\t * This bit must be '1' for the max_bw_valid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_MAX_BW_VALID \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the rx_ring_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the nq_ring_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This bit must be '1' for the rx_buf_size field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID \\\n+\t\tUINT32_C(0x100)\n+\t/* Ring Type. */\n+\tuint8_t\tring_type;\n+\t/* L2 Completion Ring (CR) */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n+\t/* TX Ring (TR) */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_TX UINT32_C(0x1)\n+\t/* RX Ring (RR) */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX UINT32_C(0x2)\n+\t/* RoCE Notification Completion Ring (ROCE_CR) */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n+\t/* RX Aggregation Ring */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)\n+\t/* Notification Queue */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ UINT32_C(0x5)\n+\t#define HWRM_RING_ALLOC_INPUT_RING_TYPE_LAST \\\n+\t\tHWRM_RING_ALLOC_INPUT_RING_TYPE_NQ\n+\tuint8_t\tunused_0;\n+\t/* Ring allocation flags. */\n+\tuint16_t\tflags;\n+\t/*\n+\t * For Rx rings, the incoming packet data can be placed at either\n+\t * a 0B or 2B offset from the start of the Rx packet buffer. When\n+\t * '1', the received packet will be padded with 2B of zeros at the\n+\t * front of the packet. Note that this flag is only used for\n+\t * Rx rings and is ignored for all other rings included Rx\n+\t * Aggregation rings.\n+\t */\n+\t#define HWRM_RING_ALLOC_INPUT_FLAGS_RX_SOP_PAD UINT32_C(0x1)\n+\t/*\n+\t * This value is a pointer to the page table for the\n+\t * Ring.\n+\t */\n+\tuint64_t\tpage_tbl_addr;\n+\t/* First Byte Offset of the first entry in the first page. */\n+\tuint32_t\tfbo;\n+\t/*\n+\t * Actual page size in 2^page_size. The supported range is increments\n+\t * in powers of 2 from 16 bytes to 1GB.\n+\t * - 4 = 16 B\n+\t * Page size is 16 B.\n+\t * - 12 = 4 KB\n+\t * Page size is 4 KB.\n+\t * - 13 = 8 KB\n+\t * Page size is 8 KB.\n+\t * - 16 = 64 KB\n+\t * Page size is 64 KB.\n+\t * - 21 = 2 MB\n+\t * Page size is 2 MB.\n+\t * - 22 = 4 MB\n+\t * Page size is 4 MB.\n+\t * - 30 = 1 GB\n+\t * Page size is 1 GB.\n+\t */\n+\tuint8_t\tpage_size;\n+\t/*\n+\t * This value indicates the depth of page table.\n+\t * For this version of the specification, value other than 0 or\n+\t * 1 shall be considered as an invalid value.\n+\t * When the page_tbl_depth = 0, then it is treated as a\n+\t * special case with the following.\n+\t * 1. FBO and page size fields are not valid.\n+\t * 2. page_tbl_addr is the physical address of the first\n+\t * element of the ring.\n+\t */\n+\tuint8_t\tpage_tbl_depth;\n+\tuint8_t\tunused_1[2];\n+\t/*\n+\t * Number of 16B units in the ring. Minimum size for\n+\t * a ring is 16 16B entries.\n+\t */\n+\tuint32_t\tlength;\n+\t/*\n+\t * Logical ring number for the ring to be allocated.\n+\t * This value determines the position in the doorbell\n+\t * area where the update to the ring will be made.\n+\t *\n+\t * For completion rings, this value is also the MSI-X\n+\t * vector number for the function the completion ring is\n+\t * associated with.\n+\t */\n+\tuint16_t\tlogical_id;\n+\t/*\n+\t * This field is used only when ring_type is a TX ring.\n+\t * This value indicates what completion ring the TX ring\n+\t * is associated with.\n+\t */\n+\tuint16_t\tcmpl_ring_id;\n+\t/*\n+\t * This field is used only when ring_type is a TX ring.\n+\t * This value indicates what CoS queue the TX ring\n+\t * is associated with.\n+\t */\n+\tuint16_t\tqueue_id;\n+\t/*\n+\t * When allocating a Rx ring or Rx aggregation ring, this field\n+\t * specifies the size of the buffer descriptors posted to the ring.\n+\t */\n+\tuint16_t\trx_buf_size;\n+\t/*\n+\t * When allocating an Rx aggregation ring, this field\n+\t * specifies the associated Rx ring ID.\n+\t */\n+\tuint16_t\trx_ring_id;\n+\t/*\n+\t * When allocating a completion ring, this field\n+\t * specifies the associated NQ ring ID.\n+\t */\n+\tuint16_t\tnq_ring_id;\n+\t/*\n+\t * This field is used only when ring_type is a TX ring.\n+\t * This field is used to configure arbitration related\n+\t * parameters for a TX ring.\n+\t */\n+\tuint16_t\tring_arb_cfg;\n+\t/* Arbitration policy used for the ring. */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SFT 0\n+\t/*\n+\t * Use strict priority for the TX ring.\n+\t * Priority value is specified in arb_policy_param\n \t */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \\\n-\t\tUINT32_C(0x8)\n+\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_SP \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * When this bit is '1', the function is requested to be\n-\t * put in the promiscuous mode.\n-\t *\n-\t * The HWRM should accept any function to set up\n-\t * promiscuous mode.\n-\t *\n-\t * The HWRM shall follow the semantics below for the\n-\t * promiscuous mode support.\n-\t * # When partitioning is not enabled on a port\n-\t * (i.e. single PF on the port), then the PF shall\n-\t * be allowed to be in the promiscuous mode. When the\n-\t * PF is in the promiscuous mode, then it shall\n-\t * receive all host bound traffic on that port.\n-\t * # When partitioning is enabled on a port\n-\t * (i.e. multiple PFs per port) and a PF on that\n-\t * port is in the promiscuous mode, then the PF\n-\t * receives all traffic within that partition as\n-\t * identified by a unique identifier for the\n-\t * PF (e.g. S-Tag). If a unique outer VLAN\n-\t * for the PF is specified, then the setting of\n-\t * promiscuous mode on that PF shall result in the\n-\t * PF receiving all host bound traffic with matching\n-\t * outer VLAN.\n-\t * # A VF shall can be set in the promiscuous mode.\n-\t * In the promiscuous mode, the VF does not receive any\n-\t * traffic unless a unique outer VLAN for the\n-\t * VF is specified. If a unique outer VLAN\n-\t * for the VF is specified, then the setting of\n-\t * promiscuous mode on that VF shall result in the\n-\t * VF receiving all host bound traffic with the\n-\t * matching outer VLAN.\n-\t * # The HWRM shall allow the setting of promiscuous\n-\t * mode on a function independently from the\n-\t * promiscuous mode settings on other functions.\n+\t * Use weighted fair queue arbitration for the TX ring.\n+\t * Weight is specified in arb_policy_param\n \t */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \\\n-\t\tUINT32_C(0x10)\n+\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_LAST \\\n+\t\tHWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_WFQ\n+\t/* Reserved field. */\n+\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_RSVD_SFT 4\n \t/*\n-\t * If this flag is set, the corresponding RX\n-\t * filters shall be set up to cover multicast/broadcast\n-\t * filters for the outermost Layer 2 destination MAC\n-\t * address field.\n+\t * Arbitration policy specific parameter.\n+\t * # For strict priority arbitration policy, this field\n+\t * represents a priority value. If set to 0, then the priority\n+\t * is not specified and the HWRM is allowed to select\n+\t * any priority for this TX ring.\n+\t * # For weighted fair queue arbitration policy, this field\n+\t * represents a weight value. If set to 0, then the weight\n+\t * is not specified and the HWRM is allowed to select\n+\t * any weight for this TX ring.\n \t */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \\\n-\t\tUINT32_C(0x20)\n+\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_MASK \\\n+\t\tUINT32_C(0xff00)\n+\t#define HWRM_RING_ALLOC_INPUT_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8\n+\tuint16_t\tunused_3;\n \t/*\n-\t * If this flag is set, the corresponding RX\n-\t * filters shall be set up to cover multicast/broadcast\n-\t * filters for the VLAN-tagged packets that match the\n-\t * TPID and VID fields of VLAN tags in the VLAN tag\n-\t * table specified in this command.\n+\t * This field is reserved for the future use.\n+\t * It shall be set to 0.\n \t */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \\\n-\t\tUINT32_C(0x40)\n+\tuint32_t\treserved3;\n \t/*\n-\t * If this flag is set, the corresponding RX\n-\t * filters shall be set up to cover multicast/broadcast\n-\t * filters for non-VLAN tagged packets and VLAN-tagged\n-\t * packets that match the TPID and VID fields of VLAN\n-\t * tags in the VLAN tag table specified in this command.\n+\t * This field is used only when ring_type is a TX ring.\n+\t * This input indicates what statistics context this ring\n+\t * should be associated with.\n \t */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \\\n-\t\tUINT32_C(0x80)\n+\tuint32_t\tstat_ctx_id;\n \t/*\n-\t * If this flag is set, the corresponding RX\n-\t * filters shall be set up to cover multicast/broadcast\n-\t * filters for non-VLAN tagged packets and VLAN-tagged\n-\t * packets matching any VLAN tag.\n-\t *\n-\t * If this flag is set, then the HWRM shall ignore\n-\t * VLAN tags specified in vlan_tag_tbl.\n-\t *\n-\t * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan\n-\t * flags is set, then the HWRM shall ignore\n-\t * VLAN tags specified in vlan_tag_tbl.\n-\t *\n-\t * The HWRM client shall set at most one flag out of\n-\t * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.\n+\t * This field is reserved for the future use.\n+\t * It shall be set to 0.\n \t */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \\\n-\t\tUINT32_C(0x100)\n-\t/* This is the address for mcast address tbl. */\n-\tuint64_t\tmc_tbl_addr;\n+\tuint32_t\treserved4;\n \t/*\n-\t * This value indicates how many entries in mc_tbl are valid.\n-\t * Each entry is 6 bytes.\n+\t * This field is used only when ring_type is a TX ring\n+\t * to specify maximum BW allocated to the TX ring.\n+\t * The HWRM will translate this value into byte counter and\n+\t * time interval used for this ring inside the device.\n \t */\n-\tuint32_t\tnum_mc_entries;\n-\tuint8_t\tunused_0[4];\n+\tuint32_t\tmax_bw;\n+\t/* The bandwidth value. */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_MASK \\\n+\t\tUINT32_C(0xfffffff)\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_SFT 0\n+\t/* The granularity of the value (bits or bytes). */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE \\\n+\t\tUINT32_C(0x10000000)\n+\t/* Value is in bits. */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BITS \\\n+\t\t(UINT32_C(0x0) << 28)\n+\t/* Value is in bytes. */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_LAST \\\n+\t\tHWRM_RING_ALLOC_INPUT_MAX_BW_SCALE_BYTES\n+\t/* bw_value_unit is 3 b */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MASK \\\n+\t\tUINT32_C(0xe0000000)\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_SFT 29\n+\t/* Value is in Mb or MB (base 10). */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_MEGA \\\n+\t\t(UINT32_C(0x0) << 29)\n+\t/* Value is in Kb or KB (base 10). */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_KILO \\\n+\t\t(UINT32_C(0x2) << 29)\n+\t/* Value is in bits or bytes. */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_BASE \\\n+\t\t(UINT32_C(0x4) << 29)\n+\t/* Value is in Gb or GB (base 10). */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_GIGA \\\n+\t\t(UINT32_C(0x6) << 29)\n+\t/* Value is in 1/100th of a percentage of total bandwidth. */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 \\\n+\t\t(UINT32_C(0x1) << 29)\n+\t/* Invalid unit */\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID \\\n+\t\t(UINT32_C(0x7) << 29)\n+\t#define HWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_LAST \\\n+\t\tHWRM_RING_ALLOC_INPUT_MAX_BW_BW_VALUE_UNIT_INVALID\n \t/*\n-\t * This is the address for VLAN tag table.\n-\t * Each VLAN entry in the table is 4 bytes of a VLAN tag\n-\t * including TPID, PCP, DEI, and VID fields in network byte\n-\t * order.\n+\t * This field is used only when ring_type is a Completion ring.\n+\t * This value indicates what interrupt mode should be used\n+\t * on this completion ring.\n+\t * Note: In the legacy interrupt mode, no more than 16\n+\t * completion rings are allowed.\n \t */\n-\tuint64_t\tvlan_tag_tbl_addr;\n+\tuint8_t\tint_mode;\n+\t/* Legacy INTA */\n+\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0)\n+\t/* Reserved */\n+\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1)\n+\t/* MSI-X */\n+\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX UINT32_C(0x2)\n+\t/* No Interrupt - Polled mode */\n+\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_POLL UINT32_C(0x3)\n+\t#define HWRM_RING_ALLOC_INPUT_INT_MODE_LAST \\\n+\t\tHWRM_RING_ALLOC_INPUT_INT_MODE_POLL\n+\tuint8_t\tunused_4[3];\n \t/*\n-\t * This value indicates how many entries in vlan_tag_tbl are\n-\t * valid. Each entry is 4 bytes.\n+\t * The cq_handle is specified when allocating a completion ring. For\n+\t * devices that support NQs, this cq_handle will be included in the\n+\t * NQE to specify which CQ should be read to retrieve the completion\n+\t * record.\n \t */\n-\tuint32_t\tnum_vlan_tags;\n-\tuint8_t\tunused_1[4];\n+\tuint64_t\tcq_handle;\n } __attribute__((packed));\n \n-/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */\n-struct hwrm_cfa_l2_set_rx_mask_output {\n+/* hwrm_ring_alloc_output (size:128b/16B) */\n+struct hwrm_ring_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -20654,7 +20043,14 @@ struct hwrm_cfa_l2_set_rx_mask_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/*\n+\t * Physical number of ring allocated.\n+\t * This value shall be unique for a ring type.\n+\t */\n+\tuint16_t\tring_id;\n+\t/* Logical number of ring allocated. */\n+\tuint16_t\tlogical_ring_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -20665,31 +20061,13 @@ struct hwrm_cfa_l2_set_rx_mask_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */\n-struct hwrm_cfa_l2_set_rx_mask_cmd_err {\n-\t/*\n-\t * command specific error codes that goes to\n-\t * the cmd_err field in Common HWRM Error Response.\n-\t */\n-\tuint8_t\tcode;\n-\t/* Unknown error */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \\\n-\t\tUINT32_C(0x0)\n-\t/* Unable to complete operation due to conflict with Ntuple Filter */\n-\t#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \\\n-\t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR\n-\tuint8_t\tunused_0[7];\n-} __attribute__((packed));\n-\n-/*******************************\n- * hwrm_cfa_vlan_antispoof_cfg *\n- *******************************/\n+/******************\n+ * hwrm_ring_free *\n+ ******************/\n \n \n-/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */\n-struct hwrm_cfa_vlan_antispoof_cfg_input {\n+/* hwrm_ring_free_input (size:192b/24B) */\n+struct hwrm_ring_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -20717,27 +20095,30 @@ struct hwrm_cfa_vlan_antispoof_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Function ID of the function that is being configured.\n-\t * Only valid for a VF FID configured by the PF.\n-\t */\n-\tuint16_t\tfid;\n-\tuint8_t\tunused_0[2];\n-\t/* Number of VLAN entries in the vlan_tag_mask_tbl. */\n-\tuint32_t\tnum_vlan_entries;\n-\t/*\n-\t * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN\n-\t * antispoof table. Each table entry contains the 16-bit TPID\n-\t * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,\n-\t * all in network order to match hwrm_cfa_l2_set_rx_mask.\n-\t * For an individual VLAN entry, the mask value should be 0xfff\n-\t * for the 12-bit VLAN ID.\n-\t */\n-\tuint64_t\tvlan_tag_mask_tbl_addr;\n+\t/* Ring Type. */\n+\tuint8_t\tring_type;\n+\t/* L2 Completion Ring (CR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n+\t/* TX Ring (TR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_TX UINT32_C(0x1)\n+\t/* RX Ring (RR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_RX UINT32_C(0x2)\n+\t/* RoCE Notification Completion Ring (ROCE_CR) */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n+\t/* RX Aggregation Ring */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG UINT32_C(0x4)\n+\t/* Notification Queue */\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_NQ UINT32_C(0x5)\n+\t#define HWRM_RING_FREE_INPUT_RING_TYPE_LAST \\\n+\t\tHWRM_RING_FREE_INPUT_RING_TYPE_NQ\n+\tuint8_t\tunused_0;\n+\t/* Physical number of ring allocated. */\n+\tuint16_t\tring_id;\n+\tuint8_t\tunused_1[4];\n } __attribute__((packed));\n \n-/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */\n-struct hwrm_cfa_vlan_antispoof_cfg_output {\n+/* hwrm_ring_free_output (size:128b/16B) */\n+struct hwrm_ring_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -20757,13 +20138,13 @@ struct hwrm_cfa_vlan_antispoof_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/********************************\n- * hwrm_cfa_vlan_antispoof_qcfg *\n- ********************************/\n+/*******************\n+ * hwrm_ring_reset *\n+ *******************/\n \n \n-/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */\n-struct hwrm_cfa_vlan_antispoof_qcfg_input {\n+/* hwrm_ring_reset_input (size:192b/24B) */\n+struct hwrm_ring_reset_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -20791,30 +20172,26 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Function ID of the function that is being queried.\n-\t * Only valid for a VF FID queried by the PF.\n-\t */\n-\tuint16_t\tfid;\n-\tuint8_t\tunused_0[2];\n-\t/*\n-\t * Maximum number of VLAN entries the firmware is allowed to DMA\n-\t * to vlan_tag_mask_tbl.\n-\t */\n-\tuint32_t\tmax_vlan_entries;\n-\t/*\n-\t * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN\n-\t * antispoof table to which firmware will DMA to. Each table\n-\t * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),\n-\t * 16-bit VLAN ID, and a 16-bit mask, all in network order to\n-\t * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,\n-\t * the mask value should be 0xfff for the 12-bit VLAN ID.\n-\t */\n-\tuint64_t\tvlan_tag_mask_tbl_addr;\n+\t/* Ring Type. */\n+\tuint8_t\tring_type;\n+\t/* L2 Completion Ring (CR) */\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_L2_CMPL UINT32_C(0x0)\n+\t/* TX Ring (TR) */\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_TX UINT32_C(0x1)\n+\t/* RX Ring (RR) */\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_RX UINT32_C(0x2)\n+\t/* RoCE Notification Completion Ring (ROCE_CR) */\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL UINT32_C(0x3)\n+\t#define HWRM_RING_RESET_INPUT_RING_TYPE_LAST \\\n+\t\tHWRM_RING_RESET_INPUT_RING_TYPE_ROCE_CMPL\n+\tuint8_t\tunused_0;\n+\t/* Physical number of the ring. */\n+\tuint16_t\tring_id;\n+\tuint8_t\tunused_1[4];\n } __attribute__((packed));\n \n-/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */\n-struct hwrm_cfa_vlan_antispoof_qcfg_output {\n+/* hwrm_ring_reset_output (size:128b/16B) */\n+struct hwrm_ring_reset_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -20823,9 +20200,7 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */\n-\tuint32_t\tnum_vlan_entries;\n-\tuint8_t\tunused_0[3];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -20836,13 +20211,13 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/********************************\n- * hwrm_cfa_tunnel_filter_alloc *\n- ********************************/\n+/**************************\n+ * hwrm_ring_aggint_qcaps *\n+ **************************/\n \n \n-/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */\n-struct hwrm_cfa_tunnel_filter_alloc_input {\n+/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */\n+struct hwrm_ring_aggint_qcaps_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -20870,230 +20245,111 @@ struct hwrm_cfa_tunnel_filter_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/* Setting of this flag indicates the applicability to the loopback path. */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n-\t\tUINT32_C(0x1)\n-\tuint32_t\tenables;\n+} __attribute__((packed));\n+\n+/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */\n+struct hwrm_ring_aggint_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tcmpl_params;\n \t/*\n-\t * This bit must be '1' for the l2_filter_id field to be\n-\t * configured.\n+\t * When this bit is set to '1', int_lat_tmr_min can be configured\n+\t * on completion rings.\n \t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \\\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MIN \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the l2_addr field to be\n-\t * configured.\n+\t * When this bit is set to '1', int_lat_tmr_max can be configured\n+\t * on completion rings.\n \t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \\\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_INT_LAT_TMR_MAX \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the l2_ivlan field to be\n-\t * configured.\n+\t * When this bit is set to '1', timer_reset can be enabled\n+\t * on completion rings.\n \t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \\\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_TIMER_RESET \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the l3_addr field to be\n-\t * configured.\n+\t * When this bit is set to '1', ring_idle can be enabled\n+\t * on completion rings.\n \t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \\\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_RING_IDLE \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * This bit must be '1' for the l3_addr_type field to be\n-\t * configured.\n+\t * When this bit is set to '1', num_cmpl_dma_aggr can be configured\n+\t * on completion rings.\n \t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \\\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * This bit must be '1' for the t_l3_addr_type field to be\n-\t * configured.\n+\t * When this bit is set to '1', num_cmpl_dma_aggr_during_int can be configured\n+\t * on completion rings.\n \t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \\\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT \\\n \t\tUINT32_C(0x20)\n \t/*\n-\t * This bit must be '1' for the t_l3_addr field to be\n-\t * configured.\n+\t * When this bit is set to '1', cmpl_aggr_dma_tmr can be configured\n+\t * on completion rings.\n \t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \\\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR \\\n \t\tUINT32_C(0x40)\n-\t/*\n-\t * This bit must be '1' for the tunnel_type field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n-\t\tUINT32_C(0x80)\n-\t/*\n-\t * This bit must be '1' for the vni field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \\\n-\t\tUINT32_C(0x100)\n-\t/*\n-\t * This bit must be '1' for the dst_vnic_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \\\n-\t\tUINT32_C(0x200)\n-\t/*\n-\t * This bit must be '1' for the mirror_vnic_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n-\t\tUINT32_C(0x400)\n-\t/*\n-\t * This value identifies a set of CFA data structures used for an L2\n-\t * context.\n-\t */\n-\tuint64_t\tl2_filter_id;\n-\t/*\n-\t * This value sets the match value for the inner L2\n-\t * MAC address.\n-\t * Destination MAC address for RX path.\n-\t * Source MAC address for TX path.\n-\t */\n-\tuint8_t\tl2_addr[6];\n-\t/*\n-\t * This value sets VLAN ID value for inner VLAN.\n-\t * Only 12-bits of VLAN ID are used in setting the filter.\n-\t */\n-\tuint16_t\tl2_ivlan;\n-\t/*\n-\t * The value of inner destination IP address to be used in filtering.\n-\t * For IPv4, first four bytes represent the IP address.\n-\t */\n-\tuint32_t\tl3_addr[4];\n-\t/*\n-\t * The value of tunnel destination IP address to be used in filtering.\n-\t * For IPv4, first four bytes represent the IP address.\n-\t */\n-\tuint32_t\tt_l3_addr[4];\n-\t/*\n-\t * This value indicates the type of inner IP address.\n-\t * 4 - IPv4\n-\t * 6 - IPv6\n-\t * All others are invalid.\n-\t */\n-\tuint8_t\tl3_addr_type;\n-\t/*\n-\t * This value indicates the type of tunnel IP address.\n-\t * 4 - IPv4\n-\t * 6 - IPv6\n-\t * All others are invalid.\n-\t */\n-\tuint8_t\tt_l3_addr_type;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n-\t\tUINT32_C(0x0)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n-\t\tUINT32_C(0x2)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n-\t\tUINT32_C(0x3)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n-\t\tUINT32_C(0x4)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n-\t\tUINT32_C(0x6)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n-\t\tUINT32_C(0x7)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n-\t\tUINT32_C(0x8)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n-\t/*\n-\t * tunnel_flags allows the user to indicate the tunnel tag detection\n-\t * for the tunnel type specified in tunnel_type.\n-\t */\n-\tuint8_t\ttunnel_flags;\n-\t/*\n-\t * If the tunnel_type is geneve, then this bit indicates if we\n-\t * need to match the geneve OAM packet.\n-\t * If the tunnel_type is nvgre or gre, then this bit indicates if\n-\t * we need to detect checksum present bit in geneve header.\n-\t * If the tunnel_type is mpls, then this bit indicates if we need\n-\t * to match mpls packet with explicit IPV4/IPV6 null header.\n-\t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * If the tunnel_type is geneve, then this bit indicates if we\n-\t * need to detect the critical option bit set in the oam packet.\n-\t * If the tunnel_type is nvgre or gre, then this bit indicates\n-\t * if we need to match nvgre packets with key present bit set in\n-\t * gre header.\n-\t * If the tunnel_type is mpls, then this bit indicates if we\n-\t * need to match mpls packet with S bit from inner/second label.\n-\t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * If the tunnel_type is geneve, then this bit indicates if we\n-\t * need to match geneve packet with extended header bit set in\n-\t * geneve header.\n-\t * If the tunnel_type is nvgre or gre, then this bit indicates\n-\t * if we need to match nvgre packets with sequence number\n-\t * present bit set in gre header.\n-\t * If the tunnel_type is mpls, then this bit indicates if we\n-\t * need to match mpls packet with S bit from out/first label.\n-\t */\n-\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * Virtual Network Identifier (VNI). Only valid with\n-\t * tunnel_types VXLAN, NVGRE, and Geneve.\n-\t * Only lower 24-bits of VNI field are used\n-\t * in setting up the filter.\n+\t/*\n+\t * When this bit is set to '1', cmpl_aggr_dma_tmr_during_int can be configured\n+\t * on completion rings.\n \t */\n-\tuint32_t\tvni;\n-\t/* Logical VNIC ID of the destination VNIC. */\n-\tuint32_t\tdst_vnic_id;\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * Logical VNIC ID of the VNIC where traffic is\n-\t * mirrored.\n+\t * When this bit is set to '1', num_cmpl_aggr_int can be configured\n+\t * on completion rings.\n \t */\n-\tuint32_t\tmirror_vnic_id;\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */\n-struct hwrm_cfa_tunnel_filter_alloc_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint64_t\ttunnel_filter_id;\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_CMPL_PARAMS_NUM_CMPL_AGGR_INT \\\n+\t\tUINT32_C(0x100)\n+\tuint32_t\tnq_params;\n \t/*\n-\t * This is the ID of the flow associated with this\n-\t * filter.\n-\t * This value shall be used to match and associate the\n-\t * flow identifier returned in completion records.\n-\t * A value of 0xFFFFFFFF shall indicate no flow id.\n+\t * When this bit is set to '1', int_lat_tmr_min can be configured\n+\t * on notification queues.\n \t */\n-\tuint32_t\tflow_id;\n-\tuint8_t\tunused_0[3];\n+\t#define HWRM_RING_AGGINT_QCAPS_OUTPUT_NQ_PARAMS_INT_LAT_TMR_MIN \\\n+\t\tUINT32_C(0x1)\n+\t/* Minimum value for num_cmpl_dma_aggr */\n+\tuint16_t\tnum_cmpl_dma_aggr_min;\n+\t/* Maximum value for num_cmpl_dma_aggr */\n+\tuint16_t\tnum_cmpl_dma_aggr_max;\n+\t/* Minimum value for num_cmpl_dma_aggr_during_int */\n+\tuint16_t\tnum_cmpl_dma_aggr_during_int_min;\n+\t/* Maximum value for num_cmpl_dma_aggr_during_int */\n+\tuint16_t\tnum_cmpl_dma_aggr_during_int_max;\n+\t/* Minimum value for cmpl_aggr_dma_tmr */\n+\tuint16_t\tcmpl_aggr_dma_tmr_min;\n+\t/* Maximum value for cmpl_aggr_dma_tmr */\n+\tuint16_t\tcmpl_aggr_dma_tmr_max;\n+\t/* Minimum value for cmpl_aggr_dma_tmr_during_int */\n+\tuint16_t\tcmpl_aggr_dma_tmr_during_int_min;\n+\t/* Maximum value for cmpl_aggr_dma_tmr_during_int */\n+\tuint16_t\tcmpl_aggr_dma_tmr_during_int_max;\n+\t/* Minimum value for int_lat_tmr_min */\n+\tuint16_t\tint_lat_tmr_min_min;\n+\t/* Maximum value for int_lat_tmr_min */\n+\tuint16_t\tint_lat_tmr_min_max;\n+\t/* Minimum value for int_lat_tmr_max */\n+\tuint16_t\tint_lat_tmr_max_min;\n+\t/* Maximum value for int_lat_tmr_max */\n+\tuint16_t\tint_lat_tmr_max_max;\n+\t/* Minimum value for num_cmpl_aggr_int */\n+\tuint16_t\tnum_cmpl_aggr_int_min;\n+\t/* Maximum value for num_cmpl_aggr_int */\n+\tuint16_t\tnum_cmpl_aggr_int_max;\n+\t/* The units for timer parameters, in nanoseconds. */\n+\tuint16_t\ttimer_units;\n+\tuint8_t\tunused_0[1];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -21104,13 +20360,13 @@ struct hwrm_cfa_tunnel_filter_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************************\n- * hwrm_cfa_tunnel_filter_free *\n- *******************************/\n+/**************************************\n+ * hwrm_ring_cmpl_ring_qaggint_params *\n+ **************************************/\n \n \n-/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */\n-struct hwrm_cfa_tunnel_filter_free_input {\n+/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */\n+struct hwrm_ring_cmpl_ring_qaggint_params_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -21138,12 +20394,13 @@ struct hwrm_cfa_tunnel_filter_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint64_t\ttunnel_filter_id;\n+\t/* Physical number of completion ring. */\n+\tuint16_t\tring_id;\n+\tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */\n-struct hwrm_cfa_tunnel_filter_free_output {\n+/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */\n+struct hwrm_ring_cmpl_ring_qaggint_params_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -21152,6 +20409,52 @@ struct hwrm_cfa_tunnel_filter_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\tuint16_t\tflags;\n+\t/*\n+\t * When this bit is set to '1', interrupt max\n+\t * timer is reset whenever a completion is received.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_TIMER_RESET \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is set to '1', ring idle mode\n+\t * aggregation will be enabled.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS_OUTPUT_FLAGS_RING_IDLE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Number of completions to aggregate before DMA\n+\t * during the normal mode.\n+\t */\n+\tuint16_t\tnum_cmpl_dma_aggr;\n+\t/*\n+\t * Number of completions to aggregate before DMA\n+\t * during the interrupt mode.\n+\t */\n+\tuint16_t\tnum_cmpl_dma_aggr_during_int;\n+\t/*\n+\t * Timer in unit of 80-nsec used to aggregate completions before\n+\t * DMA during the normal mode (not in interrupt mode).\n+\t */\n+\tuint16_t\tcmpl_aggr_dma_tmr;\n+\t/*\n+\t * Timer in unit of 80-nsec used to aggregate completions before\n+\t * DMA during the interrupt mode.\n+\t */\n+\tuint16_t\tcmpl_aggr_dma_tmr_during_int;\n+\t/* Minimum time (in unit of 80-nsec) between two interrupts. */\n+\tuint16_t\tint_lat_tmr_min;\n+\t/*\n+\t * Maximum wait time (in unit of 80-nsec) spent aggregating\n+\t * completions before signaling the interrupt after the\n+\t * interrupt is enabled.\n+\t */\n+\tuint16_t\tint_lat_tmr_max;\n+\t/*\n+\t * Minimum number of completions aggregated before signaling\n+\t * an interrupt.\n+\t */\n+\tuint16_t\tnum_cmpl_aggr_int;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -21163,13 +20466,13 @@ struct hwrm_cfa_tunnel_filter_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***************************************\n- * hwrm_cfa_redirect_tunnel_type_alloc *\n- ***************************************/\n+/*****************************************\n+ * hwrm_ring_cmpl_ring_cfg_aggint_params *\n+ *****************************************/\n \n \n-/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */\n-struct hwrm_cfa_redirect_tunnel_type_alloc_input {\n+/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */\n+struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -21197,58 +20500,109 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* The destination function id, to whom the traffic is redirected. */\n-\tuint16_t\tdest_fid;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n-\t\tUINT32_C(0x0)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t/* Physical number of completion ring. */\n+\tuint16_t\tring_id;\n+\tuint16_t\tflags;\n+\t/*\n+\t * When this bit is set to '1', interrupt latency max\n+\t * timer is reset whenever a completion is received.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET \\\n \t\tUINT32_C(0x1)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t/*\n+\t * When this bit is set to '1', ring idle mode\n+\t * aggregation will be enabled.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE \\\n \t\tUINT32_C(0x2)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n-\t\tUINT32_C(0x3)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t/*\n+\t * Set this flag to 1 when configuring parameters on a\n+\t * notification queue. Set this flag to 0 when configuring\n+\t * parameters on a completion queue.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_IS_NQ \\\n \t\tUINT32_C(0x4)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n-\t\tUINT32_C(0x6)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n-\t\tUINT32_C(0x7)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n-\t\tUINT32_C(0x8)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n-\t\tUINT32_C(0xa)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n-\t/* Tunnel alloc flags. */\n-\tuint8_t\tflags;\n-\t/* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \\\n+\t/*\n+\t * Number of completions to aggregate before DMA\n+\t * during the normal mode.\n+\t */\n+\tuint16_t\tnum_cmpl_dma_aggr;\n+\t/*\n+\t * Number of completions to aggregate before DMA\n+\t * during the interrupt mode.\n+\t */\n+\tuint16_t\tnum_cmpl_dma_aggr_during_int;\n+\t/*\n+\t * Timer in unit of 80-nsec used to aggregate completions before\n+\t * DMA during the normal mode (not in interrupt mode).\n+\t */\n+\tuint16_t\tcmpl_aggr_dma_tmr;\n+\t/*\n+\t * Timer in unit of 80-nsec used to aggregate completions before\n+\t * DMA during the interrupt mode.\n+\t */\n+\tuint16_t\tcmpl_aggr_dma_tmr_during_int;\n+\t/* Minimum time (in unit of 80-nsec) between two interrupts. */\n+\tuint16_t\tint_lat_tmr_min;\n+\t/*\n+\t * Maximum wait time (in unit of 80-nsec) spent aggregating\n+\t * cmpls before signaling the interrupt after the\n+\t * interrupt is enabled.\n+\t */\n+\tuint16_t\tint_lat_tmr_max;\n+\t/*\n+\t * Minimum number of completions aggregated before signaling\n+\t * an interrupt.\n+\t */\n+\tuint16_t\tnum_cmpl_aggr_int;\n+\t/*\n+\t * Bitfield that indicates which parameters are to be applied. Only\n+\t * required when configuring devices with notification queues, and\n+\t * used in that case to set certain parameters on completion queues\n+\t * and others on notification queues.\n+\t */\n+\tuint16_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the num_cmpl_dma_aggr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR \\\n \t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the num_cmpl_dma_aggr_during_int field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the cmpl_aggr_dma_tmr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the int_lat_tmr_min field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MIN \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the int_lat_tmr_max field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_INT_LAT_TMR_MAX \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the num_cmpl_aggr_int field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_AGGR_INT \\\n+\t\tUINT32_C(0x20)\n \tuint8_t\tunused_0[4];\n } __attribute__((packed));\n \n-/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_redirect_tunnel_type_alloc_output {\n+/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */\n+struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -21268,13 +20622,13 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**************************************\n- * hwrm_cfa_redirect_tunnel_type_free *\n- **************************************/\n-\n+/***********************\n+ * hwrm_ring_grp_alloc *\n+ ***********************/\n \n-/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */\n-struct hwrm_cfa_redirect_tunnel_type_free_input {\n+\n+/* hwrm_ring_grp_alloc_input (size:192b/24B) */\n+struct hwrm_ring_grp_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -21302,53 +20656,31 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* The destination function id, to whom the traffic is redirected. */\n-\tuint16_t\tdest_fid;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n-\t\tUINT32_C(0x0)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \\\n-\t\tUINT32_C(0x2)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \\\n-\t\tUINT32_C(0x3)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \\\n-\t\tUINT32_C(0x4)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \\\n-\t\tUINT32_C(0x6)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \\\n-\t\tUINT32_C(0x7)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \\\n-\t\tUINT32_C(0x8)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n-\t\tUINT32_C(0xa)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL\n-\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This value identifies the CR associated with the ring\n+\t * group.\n+\t */\n+\tuint16_t\tcr;\n+\t/*\n+\t * This value identifies the main RR associated with the ring\n+\t * group.\n+\t */\n+\tuint16_t\trr;\n+\t/*\n+\t * This value identifies the aggregation RR associated with\n+\t * the ring group. If this value is 0xFF... (All Fs), then no\n+\t * Aggregation ring will be set.\n+\t */\n+\tuint16_t\tar;\n+\t/*\n+\t * This value identifies the statistics context associated\n+\t * with the ring group.\n+\t */\n+\tuint16_t\tsc;\n } __attribute__((packed));\n \n-/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */\n-struct hwrm_cfa_redirect_tunnel_type_free_output {\n+/* hwrm_ring_grp_alloc_output (size:128b/16B) */\n+struct hwrm_ring_grp_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -21357,7 +20689,13 @@ struct hwrm_cfa_redirect_tunnel_type_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This is the ring group ID value. Use this value to program\n+\t * the default ring group for the VNIC or as table entries\n+\t * in an RSS/COS context.\n+\t */\n+\tuint32_t\tring_group_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -21368,13 +20706,13 @@ struct hwrm_cfa_redirect_tunnel_type_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**************************************\n- * hwrm_cfa_redirect_tunnel_type_info *\n- **************************************/\n+/**********************\n+ * hwrm_ring_grp_free *\n+ **********************/\n \n \n-/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */\n-struct hwrm_cfa_redirect_tunnel_type_info_input {\n+/* hwrm_ring_grp_free_input (size:192b/24B) */\n+struct hwrm_ring_grp_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -21402,181 +20740,39 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* The source function id. */\n-\tuint16_t\tsrc_fid;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n-\t\tUINT32_C(0x0)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \\\n-\t\tUINT32_C(0x2)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \\\n-\t\tUINT32_C(0x3)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \\\n-\t\tUINT32_C(0x4)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \\\n-\t\tUINT32_C(0x6)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \\\n-\t\tUINT32_C(0x7)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \\\n-\t\tUINT32_C(0x8)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n-\t\tUINT32_C(0xa)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL\n-\tuint8_t\tunused_0[5];\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */\n-struct hwrm_cfa_redirect_tunnel_type_info_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* The destination function id, to whom the traffic is redirected. */\n-\tuint16_t\tdest_fid;\n-\tuint8_t\tunused_0[5];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */\n-struct hwrm_vxlan_ipv4_hdr {\n-\t/* IPv4 version and header length. */\n-\tuint8_t\tver_hlen;\n-\t/* IPv4 header length */\n-\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)\n-\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0\n-\t/* Version */\n-\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)\n-\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4\n-\t/* IPv4 type of service. */\n-\tuint8_t\ttos;\n-\t/* IPv4 identification. */\n-\tuint16_t\tip_id;\n-\t/* IPv4 flags and offset. */\n-\tuint16_t\tflags_frag_offset;\n-\t/* IPv4 TTL. */\n-\tuint8_t\tttl;\n-\t/* IPv4 protocol. */\n-\tuint8_t\tprotocol;\n-\t/* IPv4 source address. */\n-\tuint32_t\tsrc_ip_addr;\n-\t/* IPv4 destination address. */\n-\tuint32_t\tdest_ip_addr;\n-} __attribute__((packed));\n-\n-/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */\n-struct hwrm_vxlan_ipv6_hdr {\n-\t/* IPv6 version, traffic class and flow label. */\n-\tuint32_t\tver_tc_flow_label;\n-\t/* IPv6 version shift */\n-\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \\\n-\t\tUINT32_C(0x1c)\n-\t/* IPv6 version mask */\n-\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \\\n-\t\tUINT32_C(0xf0000000)\n-\t/* IPv6 TC shift */\n-\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \\\n-\t\tUINT32_C(0x14)\n-\t/* IPv6 TC mask */\n-\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \\\n-\t\tUINT32_C(0xff00000)\n-\t/* IPv6 flow label shift */\n-\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \\\n-\t\tUINT32_C(0x0)\n-\t/* IPv6 flow label mask */\n-\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \\\n-\t\tUINT32_C(0xfffff)\n-\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \\\n-\t\tHWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK\n-\t/* IPv6 payload length. */\n-\tuint16_t\tpayload_len;\n-\t/* IPv6 next header. */\n-\tuint8_t\tnext_hdr;\n-\t/* IPv6 TTL. */\n-\tuint8_t\tttl;\n-\t/* IPv6 source address. */\n-\tuint32_t\tsrc_ip_addr[4];\n-\t/* IPv6 destination address. */\n-\tuint32_t\tdest_ip_addr[4];\n+\t/* This is the ring group ID value. */\n+\tuint32_t\tring_group_id;\n+\tuint8_t\tunused_0[4];\n } __attribute__((packed));\n-\n-/* hwrm_cfa_encap_data_vxlan (size:576b/72B) */\n-struct hwrm_cfa_encap_data_vxlan {\n-\t/* Source MAC address. */\n-\tuint8_t\tsrc_mac_addr[6];\n-\t/* reserved. */\n-\tuint16_t\tunused_0;\n-\t/* Destination MAC address. */\n-\tuint8_t\tdst_mac_addr[6];\n-\t/* Number of VLAN tags. */\n-\tuint8_t\tnum_vlan_tags;\n-\t/* reserved. */\n-\tuint8_t\tunused_1;\n-\t/* Outer VLAN TPID. */\n-\tuint16_t\tovlan_tpid;\n-\t/* Outer VLAN TCI. */\n-\tuint16_t\tovlan_tci;\n-\t/* Inner VLAN TPID. */\n-\tuint16_t\tivlan_tpid;\n-\t/* Inner VLAN TCI. */\n-\tuint16_t\tivlan_tci;\n-\t/* L3 header fields. */\n-\tuint32_t\tl3[10];\n-\t/* IP version mask. */\n-\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)\n-\t/* IP version 4. */\n-\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)\n-\t/* IP version 6. */\n-\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)\n-\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \\\n-\t\tHWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6\n-\t/* UDP source port. */\n-\tuint16_t\tsrc_port;\n-\t/* UDP destination port. */\n-\tuint16_t\tdst_port;\n-\t/* VXLAN Network Identifier. */\n-\tuint32_t\tvni;\n+\n+/* hwrm_ring_grp_free_output (size:128b/16B) */\n+struct hwrm_ring_grp_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************************\n- * hwrm_cfa_encap_record_alloc *\n- *******************************/\n+/****************************\n+ * hwrm_cfa_l2_filter_alloc *\n+ ****************************/\n \n \n-/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */\n-struct hwrm_cfa_encap_record_alloc_input {\n+/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */\n+struct hwrm_cfa_l2_filter_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -21603,46 +20799,343 @@ struct hwrm_cfa_encap_record_alloc_input {\n \t * physical address (HPA) or a guest physical address (GPA) and must\n \t * point to a physically contiguous block of memory.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/* Setting of this flag indicates the applicability to the loopback path. */\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \\\n-\t\tUINT32_C(0x1)\n-\t/* Encapsulation Type. */\n-\tuint8_t\tencap_type;\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/*\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH \\\n+\t\tUINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX\n+\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Setting of this flag indicates drop action. If this flag is not set,\n+\t * then it should be considered accept action.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If this flag is set, all t_l2_* fields are invalid\n+\t * and they should not be specified.\n+\t * If this flag is set, then l2_* fields refer to\n+\t * fields of outermost L2 header.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * Enumeration denoting NO_ROCE_L2 to support old drivers.\n+\t * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_MASK \\\n+\t\tUINT32_C(0x30)\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_SFT 4\n+\t/* To support old drivers */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* Only L2 traffic */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2 \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* Roce & L2 traffic */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \\\n+\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the l2_addr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the l2_addr_mask field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the l2_ovlan field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the l2_ovlan_mask field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the l2_ivlan field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the l2_ivlan_mask field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the t_l2_addr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the t_l2_addr_mask field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_ADDR_MASK \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This bit must be '1' for the t_l2_ovlan field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This bit must be '1' for the t_l2_ovlan_mask field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_OVLAN_MASK \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This bit must be '1' for the t_l2_ivlan field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * This bit must be '1' for the t_l2_ivlan_mask field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_L2_IVLAN_MASK \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * This bit must be '1' for the src_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * This bit must be '1' for the src_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * This bit must be '1' for the tunnel_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * This bit must be '1' for the dst_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n+\t\tUINT32_C(0x8000)\n+\t/*\n+\t * This bit must be '1' for the mirror_vnic_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n+\t\tUINT32_C(0x10000)\n+\t/*\n+\t * This value sets the match value for the L2 MAC address.\n+\t * Destination MAC address for RX path.\n+\t * Source MAC address for TX path.\n+\t */\n+\tuint8_t\tl2_addr[6];\n+\tuint8_t\tunused_0[2];\n+\t/*\n+\t * This value sets the mask value for the L2 address.\n+\t * A value of 0 will mask the corresponding bit from\n+\t * compare.\n+\t */\n+\tuint8_t\tl2_addr_mask[6];\n+\t/* This value sets VLAN ID value for outer VLAN. */\n+\tuint16_t\tl2_ovlan;\n+\t/*\n+\t * This value sets the mask value for the ovlan id.\n+\t * A value of 0 will mask the corresponding bit from\n+\t * compare.\n+\t */\n+\tuint16_t\tl2_ovlan_mask;\n+\t/* This value sets VLAN ID value for inner VLAN. */\n+\tuint16_t\tl2_ivlan;\n+\t/*\n+\t * This value sets the mask value for the ivlan id.\n+\t * A value of 0 will mask the corresponding bit from\n+\t * compare.\n+\t */\n+\tuint16_t\tl2_ivlan_mask;\n+\tuint8_t\tunused_1[2];\n+\t/*\n+\t * This value sets the match value for the tunnel\n+\t * L2 MAC address.\n+\t * Destination MAC address for RX path.\n+\t * Source MAC address for TX path.\n+\t */\n+\tuint8_t\tt_l2_addr[6];\n+\tuint8_t\tunused_2[2];\n+\t/*\n+\t * This value sets the mask value for the tunnel L2\n+\t * address.\n+\t * A value of 0 will mask the corresponding bit from\n+\t * compare.\n+\t */\n+\tuint8_t\tt_l2_addr_mask[6];\n+\t/* This value sets VLAN ID value for tunnel outer VLAN. */\n+\tuint16_t\tt_l2_ovlan;\n+\t/*\n+\t * This value sets the mask value for the tunnel ovlan id.\n+\t * A value of 0 will mask the corresponding bit from\n+\t * compare.\n+\t */\n+\tuint16_t\tt_l2_ovlan_mask;\n+\t/* This value sets VLAN ID value for tunnel inner VLAN. */\n+\tuint16_t\tt_l2_ivlan;\n+\t/*\n+\t * This value sets the mask value for the tunnel ivlan id.\n+\t * A value of 0 will mask the corresponding bit from\n+\t * compare.\n+\t */\n+\tuint16_t\tt_l2_ivlan_mask;\n+\t/* This value identifies the type of source of the packet. */\n+\tuint8_t\tsrc_type;\n+\t/* Network port */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_NPORT UINT32_C(0x0)\n+\t/* Physical function */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_PF UINT32_C(0x1)\n+\t/* Virtual function */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VF UINT32_C(0x2)\n+\t/* Virtual NIC of a function */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_VNIC UINT32_C(0x3)\n+\t/* Embedded processor for CFA management */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_KONG UINT32_C(0x4)\n+\t/* Embedded processor for OOB management */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_APE UINT32_C(0x5)\n+\t/* Embedded processor for RoCE */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_BONO UINT32_C(0x6)\n+\t/* Embedded processor for network proxy functions */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG UINT32_C(0x7)\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_LAST \\\n+\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_SRC_TYPE_TANG\n+\tuint8_t\tunused_3;\n+\t/*\n+\t * This value is the id of the source.\n+\t * For a network port, it represents port_id.\n+\t * For a physical function, it represents fid.\n+\t * For a virtual function, it represents vf_id.\n+\t * For a vnic, it represents vnic_id.\n+\t * For embedded processors, this id is not valid.\n+\t *\n+\t * Notes:\n+\t * 1. The function ID is implied if it src_id is\n+\t * not provided for a src_type that is either\n+\t */\n+\tuint32_t\tsrc_id;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n \t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \\\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n \t\tUINT32_C(0x1)\n \t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \\\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n \t\tUINT32_C(0x2)\n-\t/* Generic Routing Encapsulation (GRE) after inside Ethernet payload */\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \\\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n \t\tUINT32_C(0x3)\n \t/* IP in IP */\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \\\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n \t\tUINT32_C(0x4)\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \\\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n \t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \\\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n-\t/* VLAN */\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \\\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n \t\tUINT32_C(0x7)\n \t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \\\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n \t\tUINT32_C(0x8)\n-\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \\\n-\t\tHWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE\n-\tuint8_t\tunused_0[3];\n-\t/* This value is encap data used for the given encap type. */\n-\tuint32_t\tencap_data[20];\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\tuint8_t\tunused_4;\n+\t/*\n+\t * If set, this value shall represent the\n+\t * Logical VNIC ID of the destination VNIC for the RX\n+\t * path and network port id of the destination port for\n+\t * the TX path.\n+\t */\n+\tuint16_t\tdst_id;\n+\t/*\n+\t * Logical VNIC ID of the VNIC where traffic is\n+\t * mirrored.\n+\t */\n+\tuint16_t\tmirror_vnic_id;\n+\t/*\n+\t * This hint is provided to help in placing\n+\t * the filter in the filter table.\n+\t */\n+\tuint8_t\tpri_hint;\n+\t/* No preference */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \\\n+\t\tUINT32_C(0x0)\n+\t/* Above the given filter */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE_FILTER \\\n+\t\tUINT32_C(0x1)\n+\t/* Below the given filter */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_BELOW_FILTER \\\n+\t\tUINT32_C(0x2)\n+\t/* As high as possible */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MAX \\\n+\t\tUINT32_C(0x3)\n+\t/* As low as possible */\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN \\\n+\t\tUINT32_C(0x4)\n+\t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_LAST \\\n+\t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_PRI_HINT_MIN\n+\tuint8_t\tunused_5;\n+\tuint32_t\tunused_6;\n+\t/*\n+\t * This is the ID of the filter that goes along with\n+\t * the pri_hint.\n+\t *\n+\t * This field is valid only for the following values.\n+\t * 1 - Above the given filter\n+\t * 2 - Below the given filter\n+\t */\n+\tuint64_t\tl2_filter_id_hint;\n } __attribute__((packed));\n \n-/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_encap_record_alloc_output {\n+/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */\n+struct hwrm_cfa_l2_filter_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -21651,8 +21144,19 @@ struct hwrm_cfa_encap_record_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint32_t\tencap_record_id;\n+\t/*\n+\t * This value identifies a set of CFA data structures used for an L2\n+\t * context.\n+\t */\n+\tuint64_t\tl2_filter_id;\n+\t/*\n+\t * This is the ID of the flow associated with this\n+\t * filter.\n+\t * This value shall be used to match and associate the\n+\t * flow identifier returned in completion records.\n+\t * A value of 0xFFFFFFFF shall indicate no flow id.\n+\t */\n+\tuint32_t\tflow_id;\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -21664,13 +21168,13 @@ struct hwrm_cfa_encap_record_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/******************************\n- * hwrm_cfa_encap_record_free *\n- ******************************/\n+/***************************\n+ * hwrm_cfa_l2_filter_free *\n+ ***************************/\n \n \n-/* hwrm_cfa_encap_record_free_input (size:192b/24B) */\n-struct hwrm_cfa_encap_record_free_input {\n+/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */\n+struct hwrm_cfa_l2_filter_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -21698,13 +21202,15 @@ struct hwrm_cfa_encap_record_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint32_t\tencap_record_id;\n-\tuint8_t\tunused_0[4];\n+\t/*\n+\t * This value identifies a set of CFA data structures used for an L2\n+\t * context.\n+\t */\n+\tuint64_t\tl2_filter_id;\n } __attribute__((packed));\n \n-/* hwrm_cfa_encap_record_free_output (size:128b/16B) */\n-struct hwrm_cfa_encap_record_free_output {\n+/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */\n+struct hwrm_cfa_l2_filter_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -21724,13 +21230,13 @@ struct hwrm_cfa_encap_record_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/********************************\n- * hwrm_cfa_ntuple_filter_alloc *\n- ********************************/\n+/**************************\n+ * hwrm_cfa_l2_filter_cfg *\n+ **************************/\n \n \n-/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */\n-struct hwrm_cfa_ntuple_filter_alloc_input {\n+/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */\n+struct hwrm_cfa_l2_filter_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -21759,315 +21265,260 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t */\n \tuint64_t\tresp_addr;\n \tuint32_t\tflags;\n-\t/* Setting of this flag indicates the applicability to the loopback path. */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * Setting of this flag indicates that a meter is expected to be attached\n-\t * to this flow. This hint can be used when choosing the action record\n-\t * format required for the flow.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \\\n-\t\tUINT32_C(0x4)\n-\tuint32_t\tenables;\n \t/*\n-\t * This bit must be '1' for the l2_filter_id field to be\n-\t * configured.\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n \t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \\\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH \\\n \t\tUINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX\n \t/*\n-\t * This bit must be '1' for the ethertype field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * This bit must be '1' for the tunnel_type field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n-\t\tUINT32_C(0x4)\n-\t/*\n-\t * This bit must be '1' for the src_macaddr field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \\\n-\t\tUINT32_C(0x8)\n-\t/*\n-\t * This bit must be '1' for the ipaddr_type field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \\\n-\t\tUINT32_C(0x10)\n-\t/*\n-\t * This bit must be '1' for the src_ipaddr field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \\\n-\t\tUINT32_C(0x20)\n-\t/*\n-\t * This bit must be '1' for the src_ipaddr_mask field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \\\n-\t\tUINT32_C(0x40)\n-\t/*\n-\t * This bit must be '1' for the dst_ipaddr field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \\\n-\t\tUINT32_C(0x80)\n-\t/*\n-\t * This bit must be '1' for the dst_ipaddr_mask field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \\\n-\t\tUINT32_C(0x100)\n-\t/*\n-\t * This bit must be '1' for the ip_protocol field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \\\n-\t\tUINT32_C(0x200)\n-\t/*\n-\t * This bit must be '1' for the src_port field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \\\n-\t\tUINT32_C(0x400)\n-\t/*\n-\t * This bit must be '1' for the src_port_mask field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \\\n-\t\tUINT32_C(0x800)\n-\t/*\n-\t * This bit must be '1' for the dst_port field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \\\n-\t\tUINT32_C(0x1000)\n-\t/*\n-\t * This bit must be '1' for the dst_port_mask field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \\\n-\t\tUINT32_C(0x2000)\n-\t/*\n-\t * This bit must be '1' for the pri_hint field to be\n-\t * configured.\n+\t * Setting of this flag indicates drop action. If this flag is not set,\n+\t * then it should be considered accept action.\n \t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \\\n-\t\tUINT32_C(0x4000)\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the ntuple_filter_id field to be\n-\t * configured.\n+\t * Enumeration denoting NO_ROCE_L2 to support old drivers.\n+\t * New driver L2 for only L2 traffic, ROCE for roce and l2 traffic\n \t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \\\n-\t\tUINT32_C(0x8000)\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_MASK \\\n+\t\tUINT32_C(0xc)\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_SFT 2\n+\t/* To support old drivers */\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_NO_ROCE_L2 \\\n+\t\t(UINT32_C(0x0) << 2)\n+\t/* Only L2 traffic */\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_L2 \\\n+\t\t(UINT32_C(0x1) << 2)\n+\t/* Roce & L2 traffic */\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE \\\n+\t\t(UINT32_C(0x2) << 2)\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_LAST \\\n+\t\tHWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_TRAFFIC_ROCE\n+\tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the dst_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n-\t\tUINT32_C(0x10000)\n-\t/*\n-\t * This bit must be '1' for the mirror_vnic_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n-\t\tUINT32_C(0x20000)\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_DST_ID \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the dst_macaddr field to be\n+\t * This bit must be '1' for the new_mirror_vnic_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n-\t\tUINT32_C(0x40000)\n+\t#define HWRM_CFA_L2_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \\\n+\t\tUINT32_C(0x2)\n \t/*\n \t * This value identifies a set of CFA data structures used for an L2\n \t * context.\n \t */\n \tuint64_t\tl2_filter_id;\n \t/*\n-\t * This value indicates the source MAC address in\n-\t * the Ethernet header.\n+\t * If set, this value shall represent the\n+\t * Logical VNIC ID of the destination VNIC for the RX\n+\t * path and network port id of the destination port for\n+\t * the TX path.\n \t */\n-\tuint8_t\tsrc_macaddr[6];\n-\t/* This value indicates the ethertype in the Ethernet header. */\n-\tuint16_t\tethertype;\n+\tuint32_t\tdst_id;\n \t/*\n-\t * This value indicates the type of IP address.\n-\t * 4 - IPv4\n-\t * 6 - IPv6\n-\t * All others are invalid.\n+\t * New Logical VNIC ID of the VNIC where traffic is\n+\t * mirrored.\n \t */\n-\tuint8_t\tip_addr_type;\n-\t/* invalid */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \\\n-\t\tUINT32_C(0x0)\n-\t/* IPv4 */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \\\n-\t\tUINT32_C(0x4)\n-\t/* IPv6 */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \\\n-\t\tUINT32_C(0x6)\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \\\n-\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6\n+\tuint32_t\tnew_mirror_vnic_id;\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */\n+struct hwrm_cfa_l2_filter_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * The value of protocol filed in IP header.\n-\t * Applies to UDP and TCP traffic.\n-\t * 6 - TCP\n-\t * 17 - UDP\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint8_t\tip_protocol;\n-\t/* invalid */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \\\n-\t\tUINT32_C(0x0)\n-\t/* TCP */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \\\n-\t\tUINT32_C(0x6)\n-\t/* UDP */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \\\n-\t\tUINT32_C(0x11)\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \\\n-\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***************************\n+ * hwrm_cfa_l2_set_rx_mask *\n+ ***************************/\n+\n+\n+/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */\n+struct hwrm_cfa_l2_set_rx_mask_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * If set, this value shall represent the\n-\t * Logical VNIC ID of the destination VNIC for the RX\n-\t * path and network port id of the destination port for\n-\t * the TX path.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint16_t\tdst_id;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * Logical VNIC ID of the VNIC where traffic is\n-\t * mirrored.\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint16_t\tmirror_vnic_id;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * This value indicates the tunnel type for this filter.\n-\t * If this field is not specified, then the filter shall\n-\t * apply to both non-tunneled and tunneled packets.\n-\t * If this field conflicts with the tunnel_type specified\n-\t * in the l2_filter_id, then the HWRM shall return an\n-\t * error for this command.\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint8_t\ttunnel_type;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n-\t\tUINT32_C(0x0)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n-\t\tUINT32_C(0x2)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n-\t\tUINT32_C(0x3)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n-\t\tUINT32_C(0x4)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n-\t\tUINT32_C(0x6)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n-\t\tUINT32_C(0x7)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n-\t\tUINT32_C(0x8)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * This hint is provided to help in placing\n-\t * the filter in the filter table.\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint8_t\tpri_hint;\n-\t/* No preference */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \\\n-\t\tUINT32_C(0x0)\n-\t/* Above the given filter */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \\\n-\t\tUINT32_C(0x1)\n-\t/* Below the given filter */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \\\n+\tuint64_t\tresp_addr;\n+\t/* VNIC ID */\n+\tuint32_t\tvnic_id;\n+\tuint32_t\tmask;\n+\t/*\n+\t * When this bit is '1', the function is requested to accept\n+\t * multi-cast packets specified by the multicast addr table.\n+\t */\n+\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST \\\n \t\tUINT32_C(0x2)\n-\t/* As high as possible */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \\\n-\t\tUINT32_C(0x3)\n-\t/* As low as possible */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \\\n+\t/*\n+\t * When this bit is '1', the function is requested to accept\n+\t * all multi-cast packets.\n+\t */\n+\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST \\\n \t\tUINT32_C(0x4)\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \\\n-\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST\n \t/*\n-\t * The value of source IP address to be used in filtering.\n-\t * For IPv4, first four bytes represent the IP address.\n+\t * When this bit is '1', the function is requested to accept\n+\t * broadcast packets.\n \t */\n-\tuint32_t\tsrc_ipaddr[4];\n+\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST \\\n+\t\tUINT32_C(0x8)\n \t/*\n-\t * The value of source IP address mask to be used in\n-\t * filtering.\n-\t * For IPv4, first four bytes represent the IP address mask.\n+\t * When this bit is '1', the function is requested to be\n+\t * put in the promiscuous mode.\n+\t *\n+\t * The HWRM should accept any function to set up\n+\t * promiscuous mode.\n+\t *\n+\t * The HWRM shall follow the semantics below for the\n+\t * promiscuous mode support.\n+\t * # When partitioning is not enabled on a port\n+\t * (i.e. single PF on the port), then the PF shall\n+\t * be allowed to be in the promiscuous mode. When the\n+\t * PF is in the promiscuous mode, then it shall\n+\t * receive all host bound traffic on that port.\n+\t * # When partitioning is enabled on a port\n+\t * (i.e. multiple PFs per port) and a PF on that\n+\t * port is in the promiscuous mode, then the PF\n+\t * receives all traffic within that partition as\n+\t * identified by a unique identifier for the\n+\t * PF (e.g. S-Tag). If a unique outer VLAN\n+\t * for the PF is specified, then the setting of\n+\t * promiscuous mode on that PF shall result in the\n+\t * PF receiving all host bound traffic with matching\n+\t * outer VLAN.\n+\t * # A VF shall can be set in the promiscuous mode.\n+\t * In the promiscuous mode, the VF does not receive any\n+\t * traffic unless a unique outer VLAN for the\n+\t * VF is specified. If a unique outer VLAN\n+\t * for the VF is specified, then the setting of\n+\t * promiscuous mode on that VF shall result in the\n+\t * VF receiving all host bound traffic with the\n+\t * matching outer VLAN.\n+\t * # The HWRM shall allow the setting of promiscuous\n+\t * mode on a function independently from the\n+\t * promiscuous mode settings on other functions.\n \t */\n-\tuint32_t\tsrc_ipaddr_mask[4];\n+\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS \\\n+\t\tUINT32_C(0x10)\n \t/*\n-\t * The value of destination IP address to be used in filtering.\n-\t * For IPv4, first four bytes represent the IP address.\n+\t * If this flag is set, the corresponding RX\n+\t * filters shall be set up to cover multicast/broadcast\n+\t * filters for the outermost Layer 2 destination MAC\n+\t * address field.\n \t */\n-\tuint32_t\tdst_ipaddr[4];\n+\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_OUTERMOST \\\n+\t\tUINT32_C(0x20)\n \t/*\n-\t * The value of destination IP address mask to be used in\n-\t * filtering.\n-\t * For IPv4, first four bytes represent the IP address mask.\n+\t * If this flag is set, the corresponding RX\n+\t * filters shall be set up to cover multicast/broadcast\n+\t * filters for the VLAN-tagged packets that match the\n+\t * TPID and VID fields of VLAN tags in the VLAN tag\n+\t * table specified in this command.\n \t */\n-\tuint32_t\tdst_ipaddr_mask[4];\n+\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * The value of source port to be used in filtering.\n-\t * Applies to UDP and TCP traffic.\n+\t * If this flag is set, the corresponding RX\n+\t * filters shall be set up to cover multicast/broadcast\n+\t * filters for non-VLAN tagged packets and VLAN-tagged\n+\t * packets that match the TPID and VID fields of VLAN\n+\t * tags in the VLAN tag table specified in this command.\n \t */\n-\tuint16_t\tsrc_port;\n+\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * The value of source port mask to be used in filtering.\n-\t * Applies to UDP and TCP traffic.\n+\t * If this flag is set, the corresponding RX\n+\t * filters shall be set up to cover multicast/broadcast\n+\t * filters for non-VLAN tagged packets and VLAN-tagged\n+\t * packets matching any VLAN tag.\n+\t *\n+\t * If this flag is set, then the HWRM shall ignore\n+\t * VLAN tags specified in vlan_tag_tbl.\n+\t *\n+\t * If none of vlanonly, vlan_nonvlan, and anyvlan_nonvlan\n+\t * flags is set, then the HWRM shall ignore\n+\t * VLAN tags specified in vlan_tag_tbl.\n+\t *\n+\t * The HWRM client shall set at most one flag out of\n+\t * vlanonly, vlan_nonvlan, and anyvlan_nonvlan.\n \t */\n-\tuint16_t\tsrc_port_mask;\n+\t#define HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ANYVLAN_NONVLAN \\\n+\t\tUINT32_C(0x100)\n+\t/* This is the address for mcast address tbl. */\n+\tuint64_t\tmc_tbl_addr;\n \t/*\n-\t * The value of destination port to be used in filtering.\n-\t * Applies to UDP and TCP traffic.\n+\t * This value indicates how many entries in mc_tbl are valid.\n+\t * Each entry is 6 bytes.\n \t */\n-\tuint16_t\tdst_port;\n+\tuint32_t\tnum_mc_entries;\n+\tuint8_t\tunused_0[4];\n \t/*\n-\t * The value of destination port mask to be used in\n-\t * filtering.\n-\t * Applies to UDP and TCP traffic.\n+\t * This is the address for VLAN tag table.\n+\t * Each VLAN entry in the table is 4 bytes of a VLAN tag\n+\t * including TPID, PCP, DEI, and VID fields in network byte\n+\t * order.\n \t */\n-\tuint16_t\tdst_port_mask;\n+\tuint64_t\tvlan_tag_tbl_addr;\n \t/*\n-\t * This is the ID of the filter that goes along with\n-\t * the pri_hint.\n+\t * This value indicates how many entries in vlan_tag_tbl are\n+\t * valid. Each entry is 4 bytes.\n \t */\n-\tuint64_t\tntuple_filter_id_hint;\n+\tuint32_t\tnum_vlan_tags;\n+\tuint8_t\tunused_1[4];\n } __attribute__((packed));\n \n-/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */\n-struct hwrm_cfa_ntuple_filter_alloc_output {\n+/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */\n+struct hwrm_cfa_l2_set_rx_mask_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -22076,17 +21527,7 @@ struct hwrm_cfa_ntuple_filter_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint64_t\tntuple_filter_id;\n-\t/*\n-\t * This is the ID of the flow associated with this\n-\t * filter.\n-\t * This value shall be used to match and associate the\n-\t * flow identifier returned in completion records.\n-\t * A value of 0xFFFFFFFF shall indicate no flow id.\n-\t */\n-\tuint32_t\tflow_id;\n-\tuint8_t\tunused_0[3];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -22097,31 +21538,31 @@ struct hwrm_cfa_ntuple_filter_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */\n-struct hwrm_cfa_ntuple_filter_alloc_cmd_err {\n+/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */\n+struct hwrm_cfa_l2_set_rx_mask_cmd_err {\n \t/*\n \t * command specific error codes that goes to\n \t * the cmd_err field in Common HWRM Error Response.\n \t */\n \tuint8_t\tcode;\n \t/* Unknown error */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \\\n+\t#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN \\\n \t\tUINT32_C(0x0)\n-\t/* Unable to complete operation due to conflict with Rx Mask VLAN */\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \\\n+\t/* Unable to complete operation due to conflict with Ntuple Filter */\n+\t#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR \\\n \t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR\n+\t#define HWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR\n \tuint8_t\tunused_0[7];\n } __attribute__((packed));\n \n /*******************************\n- * hwrm_cfa_ntuple_filter_free *\n+ * hwrm_cfa_vlan_antispoof_cfg *\n *******************************/\n \n \n-/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */\n-struct hwrm_cfa_ntuple_filter_free_input {\n+/* hwrm_cfa_vlan_antispoof_cfg_input (size:256b/32B) */\n+struct hwrm_cfa_vlan_antispoof_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -22149,12 +21590,27 @@ struct hwrm_cfa_ntuple_filter_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint64_t\tntuple_filter_id;\n+\t/*\n+\t * Function ID of the function that is being configured.\n+\t * Only valid for a VF FID configured by the PF.\n+\t */\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[2];\n+\t/* Number of VLAN entries in the vlan_tag_mask_tbl. */\n+\tuint32_t\tnum_vlan_entries;\n+\t/*\n+\t * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN\n+\t * antispoof table. Each table entry contains the 16-bit TPID\n+\t * (0x8100 or 0x88a8 only), 16-bit VLAN ID, and a 16-bit mask,\n+\t * all in network order to match hwrm_cfa_l2_set_rx_mask.\n+\t * For an individual VLAN entry, the mask value should be 0xfff\n+\t * for the 12-bit VLAN ID.\n+\t */\n+\tuint64_t\tvlan_tag_mask_tbl_addr;\n } __attribute__((packed));\n \n-/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */\n-struct hwrm_cfa_ntuple_filter_free_output {\n+/* hwrm_cfa_vlan_antispoof_cfg_output (size:128b/16B) */\n+struct hwrm_cfa_vlan_antispoof_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -22174,13 +21630,13 @@ struct hwrm_cfa_ntuple_filter_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/******************************\n- * hwrm_cfa_ntuple_filter_cfg *\n- ******************************/\n+/********************************\n+ * hwrm_cfa_vlan_antispoof_qcfg *\n+ ********************************/\n \n \n-/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */\n-struct hwrm_cfa_ntuple_filter_cfg_input {\n+/* hwrm_cfa_vlan_antispoof_qcfg_input (size:256b/32B) */\n+struct hwrm_cfa_vlan_antispoof_qcfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -22208,59 +21664,30 @@ struct hwrm_cfa_ntuple_filter_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the new_dst_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the new_mirror_vnic_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * This bit must be '1' for the new_meter_instance_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \\\n-\t\tUINT32_C(0x4)\n-\tuint8_t\tunused_0[4];\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint64_t\tntuple_filter_id;\n-\t/*\n-\t * If set, this value shall represent the new\n-\t * Logical VNIC ID of the destination VNIC for the RX\n-\t * path and new network port id of the destination port for\n-\t * the TX path.\n-\t */\n-\tuint32_t\tnew_dst_id;\n \t/*\n-\t * New Logical VNIC ID of the VNIC where traffic is\n-\t * mirrored.\n+\t * Function ID of the function that is being queried.\n+\t * Only valid for a VF FID queried by the PF.\n \t */\n-\tuint32_t\tnew_mirror_vnic_id;\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[2];\n \t/*\n-\t * New meter to attach to the flow. Specifying the\n-\t * invalid instance ID is used to remove any existing\n-\t * meter from the flow.\n+\t * Maximum number of VLAN entries the firmware is allowed to DMA\n+\t * to vlan_tag_mask_tbl.\n \t */\n-\tuint16_t\tnew_meter_instance_id;\n+\tuint32_t\tmax_vlan_entries;\n \t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * instance is not configured.\n+\t * The vlan_tag_mask_tbl_addr is the DMA address of the VLAN\n+\t * antispoof table to which firmware will DMA to. Each table\n+\t * entry will contain the 16-bit TPID (0x8100 or 0x88a8 only),\n+\t * 16-bit VLAN ID, and a 16-bit mask, all in network order to\n+\t * match hwrm_cfa_l2_set_rx_mask. For an individual VLAN entry,\n+\t * the mask value should be 0xfff for the 12-bit VLAN ID.\n \t */\n-\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \\\n-\t\tHWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID\n-\tuint8_t\tunused_1[6];\n+\tuint64_t\tvlan_tag_mask_tbl_addr;\n } __attribute__((packed));\n \n-/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */\n-struct hwrm_cfa_ntuple_filter_cfg_output {\n+/* hwrm_cfa_vlan_antispoof_qcfg_output (size:128b/16B) */\n+struct hwrm_cfa_vlan_antispoof_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -22269,7 +21696,9 @@ struct hwrm_cfa_ntuple_filter_cfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* Number of valid entries DMAd by firmware to vlan_tag_mask_tbl. */\n+\tuint32_t\tnum_vlan_entries;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -22280,13 +21709,13 @@ struct hwrm_cfa_ntuple_filter_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**************************\n- * hwrm_cfa_em_flow_alloc *\n- **************************/\n+/********************************\n+ * hwrm_cfa_tunnel_filter_alloc *\n+ ********************************/\n \n \n-/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */\n-struct hwrm_cfa_em_flow_alloc_input {\n+/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */\n+struct hwrm_cfa_tunnel_filter_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -22309,312 +21738,216 @@ struct hwrm_cfa_em_flow_alloc_input {\n \tuint16_t\ttarget_id;\n \t/*\n \t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX\n-\t/*\n-\t * Setting of this flag indicates enabling of a byte counter for a given\n-\t * flow.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)\n-\t/*\n-\t * Setting of this flag indicates enabling of a packet counter for a given\n-\t * flow.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)\n-\t/* Setting of this flag indicates de-capsulation action for the given flow. */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)\n-\t/* Setting of this flag indicates encapsulation action for the given flow. */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)\n-\t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)\n-\t/*\n-\t * Setting of this flag indicates that a meter is expected to be attached\n-\t * to this flow. This hint can be used when choosing the action record\n-\t * format required for the flow.\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n+\t\tUINT32_C(0x1)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the l2_filter_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the tunnel_type field to be\n+\t * This bit must be '1' for the l2_addr field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the tunnel_id field to be\n+\t * This bit must be '1' for the l2_ivlan field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the src_macaddr field to be\n+\t * This bit must be '1' for the l3_addr field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * This bit must be '1' for the dst_macaddr field to be\n+\t * This bit must be '1' for the l3_addr_type field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_L3_ADDR_TYPE \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * This bit must be '1' for the ovlan_vid field to be\n+\t * This bit must be '1' for the t_l3_addr_type field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR_TYPE \\\n \t\tUINT32_C(0x20)\n \t/*\n-\t * This bit must be '1' for the ivlan_vid field to be\n+\t * This bit must be '1' for the t_l3_addr field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_T_L3_ADDR \\\n \t\tUINT32_C(0x40)\n \t/*\n-\t * This bit must be '1' for the ethertype field to be\n+\t * This bit must be '1' for the tunnel_type field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n \t\tUINT32_C(0x80)\n \t/*\n-\t * This bit must be '1' for the src_ipaddr field to be\n+\t * This bit must be '1' for the vni field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_VNI \\\n \t\tUINT32_C(0x100)\n \t/*\n-\t * This bit must be '1' for the dst_ipaddr field to be\n+\t * This bit must be '1' for the dst_vnic_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_DST_VNIC_ID \\\n \t\tUINT32_C(0x200)\n \t/*\n-\t * This bit must be '1' for the ipaddr_type field to be\n+\t * This bit must be '1' for the mirror_vnic_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n \t\tUINT32_C(0x400)\n \t/*\n-\t * This bit must be '1' for the ip_protocol field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \\\n-\t\tUINT32_C(0x800)\n-\t/*\n-\t * This bit must be '1' for the src_port field to be\n-\t * configured.\n+\t * This value identifies a set of CFA data structures used for an L2\n+\t * context.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \\\n-\t\tUINT32_C(0x1000)\n+\tuint64_t\tl2_filter_id;\n \t/*\n-\t * This bit must be '1' for the dst_port field to be\n-\t * configured.\n+\t * This value sets the match value for the inner L2\n+\t * MAC address.\n+\t * Destination MAC address for RX path.\n+\t * Source MAC address for TX path.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \\\n-\t\tUINT32_C(0x2000)\n+\tuint8_t\tl2_addr[6];\n \t/*\n-\t * This bit must be '1' for the dst_id field to be\n-\t * configured.\n+\t * This value sets VLAN ID value for inner VLAN.\n+\t * Only 12-bits of VLAN ID are used in setting the filter.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \\\n-\t\tUINT32_C(0x4000)\n+\tuint16_t\tl2_ivlan;\n \t/*\n-\t * This bit must be '1' for the mirror_vnic_id field to be\n-\t * configured.\n+\t * The value of inner destination IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n-\t\tUINT32_C(0x8000)\n+\tuint32_t\tl3_addr[4];\n \t/*\n-\t * This bit must be '1' for the encap_record_id field to be\n-\t * configured.\n+\t * The value of tunnel destination IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \\\n-\t\tUINT32_C(0x10000)\n+\tuint32_t\tt_l3_addr[4];\n \t/*\n-\t * This bit must be '1' for the meter_instance_id field to be\n-\t * configured.\n+\t * This value indicates the type of inner IP address.\n+\t * 4 - IPv4\n+\t * 6 - IPv6\n+\t * All others are invalid.\n \t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \\\n-\t\tUINT32_C(0x20000)\n+\tuint8_t\tl3_addr_type;\n \t/*\n-\t * This value identifies a set of CFA data structures used for an L2\n-\t * context.\n+\t * This value indicates the type of tunnel IP address.\n+\t * 4 - IPv4\n+\t * 6 - IPv6\n+\t * All others are invalid.\n \t */\n-\tuint64_t\tl2_filter_id;\n+\tuint8_t\tt_l3_addr_type;\n \t/* Tunnel Type. */\n \tuint8_t\ttunnel_type;\n \t/* Non-tunnel */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n \t\tUINT32_C(0x0)\n \t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n \t\tUINT32_C(0x1)\n \t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n \t\tUINT32_C(0x2)\n \t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n \t\tUINT32_C(0x3)\n \t/* IP in IP */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n \t\tUINT32_C(0x4)\n \t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n \t\tUINT32_C(0x5)\n \t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n \t\tUINT32_C(0x6)\n \t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n \t\tUINT32_C(0x7)\n \t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n \t\tUINT32_C(0x8)\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n \t/* Any tunneled traffic */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n \t\tUINT32_C(0xff)\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n-\tuint8_t\tunused_0[3];\n-\t/*\n-\t * Tunnel identifier.\n-\t * Virtual Network Identifier (VNI). Only valid with\n-\t * tunnel_types VXLAN, NVGRE, and Geneve.\n-\t * Only lower 24-bits of VNI field are used\n-\t * in setting up the filter.\n-\t */\n-\tuint32_t\ttunnel_id;\n-\t/*\n-\t * This value indicates the source MAC address in\n-\t * the Ethernet header.\n-\t */\n-\tuint8_t\tsrc_macaddr[6];\n-\t/* The meter instance to attach to the flow. */\n-\tuint16_t\tmeter_instance_id;\n-\t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * instance is not configured.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \\\n-\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID\n-\t/*\n-\t * This value indicates the destination MAC address in\n-\t * the Ethernet header.\n-\t */\n-\tuint8_t\tdst_macaddr[6];\n-\t/*\n-\t * This value indicates the VLAN ID of the outer VLAN tag\n-\t * in the Ethernet header.\n-\t */\n-\tuint16_t\tovlan_vid;\n-\t/*\n-\t * This value indicates the VLAN ID of the inner VLAN tag\n-\t * in the Ethernet header.\n-\t */\n-\tuint16_t\tivlan_vid;\n-\t/* This value indicates the ethertype in the Ethernet header. */\n-\tuint16_t\tethertype;\n-\t/*\n-\t * This value indicates the type of IP address.\n-\t * 4 - IPv4\n-\t * 6 - IPv6\n-\t * All others are invalid.\n-\t */\n-\tuint8_t\tip_addr_type;\n-\t/* invalid */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)\n-\t/* IPv4 */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)\n-\t/* IPv6 */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \\\n-\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6\n-\t/*\n-\t * The value of protocol filed in IP header.\n-\t * Applies to UDP and TCP traffic.\n-\t * 6 - TCP\n-\t * 17 - UDP\n-\t */\n-\tuint8_t\tip_protocol;\n-\t/* invalid */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)\n-\t/* TCP */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)\n-\t/* UDP */\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)\n-\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \\\n-\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP\n-\tuint8_t\tunused_1[2];\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n \t/*\n-\t * The value of source IP address to be used in filtering.\n-\t * For IPv4, first four bytes represent the IP address.\n+\t * tunnel_flags allows the user to indicate the tunnel tag detection\n+\t * for the tunnel type specified in tunnel_type.\n \t */\n-\tuint32_t\tsrc_ipaddr[4];\n+\tuint8_t\ttunnel_flags;\n \t/*\n-\t * big_endian = True\n-\t * The value of destination IP address to be used in filtering.\n-\t * For IPv4, first four bytes represent the IP address.\n+\t * If the tunnel_type is geneve, then this bit indicates if we\n+\t * need to match the geneve OAM packet.\n+\t * If the tunnel_type is nvgre or gre, then this bit indicates if\n+\t * we need to detect checksum present bit in geneve header.\n+\t * If the tunnel_type is mpls, then this bit indicates if we need\n+\t * to match mpls packet with explicit IPV4/IPV6 null header.\n \t */\n-\tuint32_t\tdst_ipaddr[4];\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR \\\n+\t\tUINT32_C(0x1)\n \t/*\n-\t * The value of source port to be used in filtering.\n-\t * Applies to UDP and TCP traffic.\n+\t * If the tunnel_type is geneve, then this bit indicates if we\n+\t * need to detect the critical option bit set in the oam packet.\n+\t * If the tunnel_type is nvgre or gre, then this bit indicates\n+\t * if we need to match nvgre packets with key present bit set in\n+\t * gre header.\n+\t * If the tunnel_type is mpls, then this bit indicates if we\n+\t * need to match mpls packet with S bit from inner/second label.\n \t */\n-\tuint16_t\tsrc_port;\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * The value of destination port to be used in filtering.\n-\t * Applies to UDP and TCP traffic.\n+\t * If the tunnel_type is geneve, then this bit indicates if we\n+\t * need to match geneve packet with extended header bit set in\n+\t * geneve header.\n+\t * If the tunnel_type is nvgre or gre, then this bit indicates\n+\t * if we need to match nvgre packets with sequence number\n+\t * present bit set in gre header.\n+\t * If the tunnel_type is mpls, then this bit indicates if we\n+\t * need to match mpls packet with S bit from out/first label.\n \t */\n-\tuint16_t\tdst_port;\n+\t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 \\\n+\t\tUINT32_C(0x4)\n \t/*\n-\t * If set, this value shall represent the\n-\t * Logical VNIC ID of the destination VNIC for the RX\n-\t * path and network port id of the destination port for\n-\t * the TX path.\n+\t * Virtual Network Identifier (VNI). Only valid with\n+\t * tunnel_types VXLAN, NVGRE, and Geneve.\n+\t * Only lower 24-bits of VNI field are used\n+\t * in setting up the filter.\n \t */\n-\tuint16_t\tdst_id;\n+\tuint32_t\tvni;\n+\t/* Logical VNIC ID of the destination VNIC. */\n+\tuint32_t\tdst_vnic_id;\n \t/*\n \t * Logical VNIC ID of the VNIC where traffic is\n \t * mirrored.\n \t */\n-\tuint16_t\tmirror_vnic_id;\n-\t/* Logical ID of the encapsulation record. */\n-\tuint32_t\tencap_record_id;\n-\tuint8_t\tunused_2[4];\n+\tuint32_t\tmirror_vnic_id;\n } __attribute__((packed));\n \n-/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */\n-struct hwrm_cfa_em_flow_alloc_output {\n+/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */\n+struct hwrm_cfa_tunnel_filter_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -22624,7 +21957,7 @@ struct hwrm_cfa_em_flow_alloc_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/* This value is an opaque id into CFA data structures. */\n-\tuint64_t\tem_filter_id;\n+\tuint64_t\ttunnel_filter_id;\n \t/*\n \t * This is the ID of the flow associated with this\n \t * filter.\n@@ -22644,72 +21977,13 @@ struct hwrm_cfa_em_flow_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*************************\n- * hwrm_cfa_em_flow_free *\n- *************************/\n-\n-\n-/* hwrm_cfa_em_flow_free_input (size:192b/24B) */\n-struct hwrm_cfa_em_flow_free_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint64_t\tem_filter_id;\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_em_flow_free_output (size:128b/16B) */\n-struct hwrm_cfa_em_flow_free_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/************************\n- * hwrm_cfa_em_flow_cfg *\n- ************************/\n+/*******************************\n+ * hwrm_cfa_tunnel_filter_free *\n+ *******************************/\n \n \n-/* hwrm_cfa_em_flow_cfg_input (size:384b/48B) */\n-struct hwrm_cfa_em_flow_cfg_input {\n+/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */\n+struct hwrm_cfa_tunnel_filter_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -22737,59 +22011,12 @@ struct hwrm_cfa_em_flow_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the new_dst_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_DST_ID \\\n-\t\tUINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the new_mirror_vnic_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * This bit must be '1' for the new_meter_instance_id field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \\\n-\t\tUINT32_C(0x4)\n-\tuint8_t\tunused_0[4];\n \t/* This value is an opaque id into CFA data structures. */\n-\tuint64_t\tem_filter_id;\n-\t/*\n-\t * If set, this value shall represent the new\n-\t * Logical VNIC ID of the destination VNIC for the RX\n-\t * path and network port id of the destination port for\n-\t * the TX path.\n-\t */\n-\tuint32_t\tnew_dst_id;\n-\t/*\n-\t * New Logical VNIC ID of the VNIC where traffic is\n-\t * mirrored.\n-\t */\n-\tuint32_t\tnew_mirror_vnic_id;\n-\t/*\n-\t * New meter to attach to the flow. Specifying the\n-\t * invalid instance ID is used to remove any existing\n-\t * meter from the flow.\n-\t */\n-\tuint16_t\tnew_meter_instance_id;\n-\t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * instance is not configured.\n-\t */\n-\t#define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \\\n-\t\tHWRM_CFA_EM_FLOW_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID\n-\tuint8_t\tunused_1[6];\n+\tuint64_t\ttunnel_filter_id;\n } __attribute__((packed));\n \n-/* hwrm_cfa_em_flow_cfg_output (size:128b/16B) */\n-struct hwrm_cfa_em_flow_cfg_output {\n+/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */\n+struct hwrm_cfa_tunnel_filter_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -22809,13 +22036,13 @@ struct hwrm_cfa_em_flow_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/********************************\n- * hwrm_cfa_meter_profile_alloc *\n- ********************************/\n+/***************************************\n+ * hwrm_cfa_redirect_tunnel_type_alloc *\n+ ***************************************/\n \n \n-/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */\n-struct hwrm_cfa_meter_profile_alloc_input {\n+/* hwrm_cfa_redirect_tunnel_type_alloc_input (size:192b/24B) */\n+struct hwrm_cfa_redirect_tunnel_type_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -22841,222 +22068,60 @@ struct hwrm_cfa_meter_profile_alloc_input {\n \t * command's response data will be written. This can be either a host\n \t * physical address (HPA) or a guest physical address (GPA) and must\n \t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\tuint8_t\tflags;\n-\t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n-\t */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \\\n-\t\tUINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \\\n-\t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX\n-\t/* The meter algorithm type. */\n-\tuint8_t\tmeter_type;\n-\t/* RFC 2697 (srTCM) */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \\\n-\t\tUINT32_C(0x0)\n-\t/* RFC 2698 (trTCM) */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \\\n-\t\tUINT32_C(0x1)\n-\t/* RFC 4115 (trTCM) */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \\\n-\t\tUINT32_C(0x2)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115\n-\t/*\n-\t * This field is reserved for the future use.\n-\t * It shall be set to 0.\n-\t */\n-\tuint16_t\treserved1;\n-\t/*\n-\t * This field is reserved for the future use.\n-\t * It shall be set to 0.\n-\t */\n-\tuint32_t\treserved2;\n-\t/* A meter rate specified in bytes-per-second. */\n-\tuint32_t\tcommit_rate;\n-\t/* The bandwidth value. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID\n-\t/* A meter burst size specified in bytes. */\n-\tuint32_t\tcommit_burst;\n-\t/* The bandwidth value. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID\n-\t/* A meter rate specified in bytes-per-second. */\n-\tuint32_t\texcess_peak_rate;\n-\t/* The bandwidth value. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID\n-\t/* A meter burst size specified in bytes. */\n-\tuint32_t\texcess_peak_burst;\n-\t/* The bandwidth value. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* The destination function id, to whom the traffic is redirected. */\n+\tuint16_t\tdest_fid;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\t/* Tunnel alloc flags. */\n+\tuint8_t\tflags;\n+\t/* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \\\n+\t\tUINT32_C(0x1)\n+\tuint8_t\tunused_0[4];\n } __attribute__((packed));\n \n-/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_meter_profile_alloc_output {\n+/* hwrm_cfa_redirect_tunnel_type_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_redirect_tunnel_type_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -23065,17 +22130,7 @@ struct hwrm_cfa_meter_profile_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This value identifies a meter profile in CFA. */\n-\tuint16_t\tmeter_profile_id;\n-\t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * profile is not configured.\n-\t */\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID\n-\tuint8_t\tunused_0[5];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -23086,13 +22141,13 @@ struct hwrm_cfa_meter_profile_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************************\n- * hwrm_cfa_meter_profile_free *\n- *******************************/\n+/**************************************\n+ * hwrm_cfa_redirect_tunnel_type_free *\n+ **************************************/\n \n \n-/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */\n-struct hwrm_cfa_meter_profile_free_input {\n+/* hwrm_cfa_redirect_tunnel_type_free_input (size:192b/24B) */\n+struct hwrm_cfa_redirect_tunnel_type_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -23120,37 +22175,53 @@ struct hwrm_cfa_meter_profile_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint8_t\tflags;\n-\t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n-\t */\n-\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \\\n+\t/* The destination function id, to whom the traffic is redirected. */\n+\tuint16_t\tdest_fid;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n \t\tUINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \\\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN \\\n \t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX\n-\tuint8_t\tunused_0;\n-\t/* This value identifies a meter profile in CFA. */\n-\tuint16_t\tmeter_profile_id;\n-\t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * profile is not configured.\n-\t */\n-\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID\n-\tuint8_t\tunused_1[4];\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\tuint8_t\tunused_0[5];\n } __attribute__((packed));\n \n-/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */\n-struct hwrm_cfa_meter_profile_free_output {\n+/* hwrm_cfa_redirect_tunnel_type_free_output (size:128b/16B) */\n+struct hwrm_cfa_redirect_tunnel_type_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -23170,13 +22241,13 @@ struct hwrm_cfa_meter_profile_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/******************************\n- * hwrm_cfa_meter_profile_cfg *\n- ******************************/\n+/**************************************\n+ * hwrm_cfa_redirect_tunnel_type_info *\n+ **************************************/\n \n \n-/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */\n-struct hwrm_cfa_meter_profile_cfg_input {\n+/* hwrm_cfa_redirect_tunnel_type_info_input (size:192b/24B) */\n+struct hwrm_cfa_redirect_tunnel_type_info_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -23204,223 +22275,53 @@ struct hwrm_cfa_meter_profile_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint8_t\tflags;\n-\t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n-\t */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX\n-\t/* The meter algorithm type. */\n-\tuint8_t\tmeter_type;\n-\t/* RFC 2697 (srTCM) */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \\\n+\t/* The source function id. */\n+\tuint16_t\tsrc_fid;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n \t\tUINT32_C(0x0)\n-\t/* RFC 2698 (trTCM) */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \\\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN \\\n \t\tUINT32_C(0x1)\n-\t/* RFC 4115 (trTCM) */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \\\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_NVGRE \\\n \t\tUINT32_C(0x2)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115\n-\t/* This value identifies a meter profile in CFA. */\n-\tuint16_t\tmeter_profile_id;\n-\t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * profile is not configured.\n-\t */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID\n-\t/*\n-\t * This field is reserved for the future use.\n-\t * It shall be set to 0.\n-\t */\n-\tuint32_t\treserved;\n-\t/* A meter rate specified in bytes-per-second. */\n-\tuint32_t\tcommit_rate;\n-\t/* The bandwidth value. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID\n-\t/* A meter burst size specified in bytes. */\n-\tuint32_t\tcommit_burst;\n-\t/* The bandwidth value. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID\n-\t/* A meter rate specified in bytes-per-second. */\n-\tuint32_t\texcess_peak_rate;\n-\t/* The bandwidth value. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID\n-\t/* A meter burst size specified in bytes. */\n-\tuint32_t\texcess_peak_burst;\n-\t/* The bandwidth value. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \\\n-\t\tUINT32_C(0xfffffff)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \\\n-\t\t0\n-\t/* The granularity of the value (bits or bytes). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \\\n-\t\tUINT32_C(0x10000000)\n-\t/* Value is in bits. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \\\n-\t\t(UINT32_C(0x0) << 28)\n-\t/* Value is in bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \\\n-\t\t(UINT32_C(0x1) << 28)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES\n-\t/* bw_value_unit is 3 b */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \\\n-\t\tUINT32_C(0xe0000000)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \\\n-\t\t29\n-\t/* Value is in Mb or MB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \\\n-\t\t(UINT32_C(0x0) << 29)\n-\t/* Value is in Kb or KB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \\\n-\t\t(UINT32_C(0x2) << 29)\n-\t/* Value is in bits or bytes. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \\\n-\t\t(UINT32_C(0x4) << 29)\n-\t/* Value is in Gb or GB (base 10). */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \\\n-\t\t(UINT32_C(0x6) << 29)\n-\t/* Value is in 1/100th of a percentage of total bandwidth. */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \\\n-\t\t(UINT32_C(0x1) << 29)\n-\t/* Invalid unit */\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \\\n-\t\t(UINT32_C(0x7) << 29)\n-\t#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \\\n-\t\tHWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\tuint8_t\tunused_0[5];\n } __attribute__((packed));\n \n-/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */\n-struct hwrm_cfa_meter_profile_cfg_output {\n+/* hwrm_cfa_redirect_tunnel_type_info_output (size:128b/16B) */\n+struct hwrm_cfa_redirect_tunnel_type_info_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -23429,7 +22330,9 @@ struct hwrm_cfa_meter_profile_cfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* The destination function id, to whom the traffic is redirected. */\n+\tuint16_t\tdest_fid;\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -23440,13 +22343,120 @@ struct hwrm_cfa_meter_profile_cfg_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*********************************\n- * hwrm_cfa_meter_instance_alloc *\n- *********************************/\n+/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */\n+struct hwrm_vxlan_ipv4_hdr {\n+\t/* IPv4 version and header length. */\n+\tuint8_t\tver_hlen;\n+\t/* IPv4 header length */\n+\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK UINT32_C(0xf)\n+\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0\n+\t/* Version */\n+\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK UINT32_C(0xf0)\n+\t#define HWRM_VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4\n+\t/* IPv4 type of service. */\n+\tuint8_t\ttos;\n+\t/* IPv4 identification. */\n+\tuint16_t\tip_id;\n+\t/* IPv4 flags and offset. */\n+\tuint16_t\tflags_frag_offset;\n+\t/* IPv4 TTL. */\n+\tuint8_t\tttl;\n+\t/* IPv4 protocol. */\n+\tuint8_t\tprotocol;\n+\t/* IPv4 source address. */\n+\tuint32_t\tsrc_ip_addr;\n+\t/* IPv4 destination address. */\n+\tuint32_t\tdest_ip_addr;\n+} __attribute__((packed));\n+\n+/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */\n+struct hwrm_vxlan_ipv6_hdr {\n+\t/* IPv6 version, traffic class and flow label. */\n+\tuint32_t\tver_tc_flow_label;\n+\t/* IPv6 version shift */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT \\\n+\t\tUINT32_C(0x1c)\n+\t/* IPv6 version mask */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK \\\n+\t\tUINT32_C(0xf0000000)\n+\t/* IPv6 TC shift */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT \\\n+\t\tUINT32_C(0x14)\n+\t/* IPv6 TC mask */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK \\\n+\t\tUINT32_C(0xff00000)\n+\t/* IPv6 flow label shift */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT \\\n+\t\tUINT32_C(0x0)\n+\t/* IPv6 flow label mask */\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK \\\n+\t\tUINT32_C(0xfffff)\n+\t#define HWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST \\\n+\t\tHWRM_VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK\n+\t/* IPv6 payload length. */\n+\tuint16_t\tpayload_len;\n+\t/* IPv6 next header. */\n+\tuint8_t\tnext_hdr;\n+\t/* IPv6 TTL. */\n+\tuint8_t\tttl;\n+\t/* IPv6 source address. */\n+\tuint32_t\tsrc_ip_addr[4];\n+\t/* IPv6 destination address. */\n+\tuint32_t\tdest_ip_addr[4];\n+} __attribute__((packed));\n+\n+/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */\n+struct hwrm_cfa_encap_data_vxlan {\n+\t/* Source MAC address. */\n+\tuint8_t\tsrc_mac_addr[6];\n+\t/* reserved. */\n+\tuint16_t\tunused_0;\n+\t/* Destination MAC address. */\n+\tuint8_t\tdst_mac_addr[6];\n+\t/* Number of VLAN tags. */\n+\tuint8_t\tnum_vlan_tags;\n+\t/* reserved. */\n+\tuint8_t\tunused_1;\n+\t/* Outer VLAN TPID. */\n+\tuint16_t\tovlan_tpid;\n+\t/* Outer VLAN TCI. */\n+\tuint16_t\tovlan_tci;\n+\t/* Inner VLAN TPID. */\n+\tuint16_t\tivlan_tpid;\n+\t/* Inner VLAN TCI. */\n+\tuint16_t\tivlan_tci;\n+\t/* L3 header fields. */\n+\tuint32_t\tl3[10];\n+\t/* IP version mask. */\n+\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_MASK UINT32_C(0xf)\n+\t/* IP version 4. */\n+\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 UINT32_C(0x4)\n+\t/* IP version 6. */\n+\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 UINT32_C(0x6)\n+\t#define HWRM_CFA_ENCAP_DATA_VXLAN_L3_LAST \\\n+\t\tHWRM_CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6\n+\t/* UDP source port. */\n+\tuint16_t\tsrc_port;\n+\t/* UDP destination port. */\n+\tuint16_t\tdst_port;\n+\t/* VXLAN Network Identifier. */\n+\tuint32_t\tvni;\n+\t/* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */\n+\tuint8_t\thdr_rsvd0[3];\n+\t/* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */\n+\tuint8_t\thdr_rsvd1;\n+\t/* VXLAN header flags field. */\n+\tuint8_t\thdr_flags;\n+\tuint8_t\tunused[3];\n+} __attribute__((packed));\n+\n+/*******************************\n+ * hwrm_cfa_encap_record_alloc *\n+ *******************************/\n \n \n-/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */\n-struct hwrm_cfa_meter_instance_alloc_input {\n+/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */\n+struct hwrm_cfa_encap_record_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -23474,38 +22484,48 @@ struct hwrm_cfa_meter_instance_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint8_t\tflags;\n-\t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n-\t */\n-\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \\\n+\tuint32_t\tflags;\n+\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \\\n \t\tUINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \\\n-\t\tUINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \\\n+\t/* Encapsulation Type. */\n+\tuint8_t\tencap_type;\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN \\\n \t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX\n-\tuint8_t\tunused_0;\n-\t/* This value identifies a meter profile in CFA. */\n-\tuint16_t\tmeter_profile_id;\n-\t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * profile is not configured.\n-\t */\n-\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \\\n-\t\tHWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID\n-\tuint8_t\tunused_1[4];\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) after inside Ethernet payload */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* VLAN */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VLAN \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \\\n+\t\tHWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4\n+\tuint8_t\tunused_0[3];\n+\t/* This value is encap data used for the given encap type. */\n+\tuint32_t\tencap_data[20];\n } __attribute__((packed));\n \n-/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_meter_instance_alloc_output {\n+/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_encap_record_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -23514,17 +22534,9 @@ struct hwrm_cfa_meter_instance_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This value identifies a meter instance in CFA. */\n-\tuint16_t\tmeter_instance_id;\n-\t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * instance is not configured.\n-\t */\n-\t#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \\\n-\t\tHWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID\n-\tuint8_t\tunused_0[5];\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint32_t\tencap_record_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -23535,13 +22547,13 @@ struct hwrm_cfa_meter_instance_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/********************************\n- * hwrm_cfa_meter_instance_free *\n- ********************************/\n+/******************************\n+ * hwrm_cfa_encap_record_free *\n+ ******************************/\n \n \n-/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */\n-struct hwrm_cfa_meter_instance_free_input {\n+/* hwrm_cfa_encap_record_free_input (size:192b/24B) */\n+struct hwrm_cfa_encap_record_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -23569,37 +22581,13 @@ struct hwrm_cfa_meter_instance_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint8_t\tflags;\n-\t/*\n-\t * Enumeration denoting the RX, TX type of the resource.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n-\t */\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)\n-\t/* tx path */\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \\\n-\t\tUINT32_C(0x0)\n-\t/* rx path */\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \\\n-\t\tUINT32_C(0x1)\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \\\n-\t\tHWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX\n-\tuint8_t\tunused_0;\n-\t/* This value identifies a meter instance in CFA. */\n-\tuint16_t\tmeter_instance_id;\n-\t/*\n-\t * A value of 0xfff is considered invalid and implies the\n-\t * instance is not configured.\n-\t */\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \\\n-\t\tUINT32_C(0xffff)\n-\t#define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \\\n-\t\tHWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID\n-\tuint8_t\tunused_1[4];\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint32_t\tencap_record_id;\n+\tuint8_t\tunused_0[4];\n } __attribute__((packed));\n \n-/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */\n-struct hwrm_cfa_meter_instance_free_output {\n+/* hwrm_cfa_encap_record_free_output (size:128b/16B) */\n+struct hwrm_cfa_encap_record_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -23619,13 +22607,13 @@ struct hwrm_cfa_meter_instance_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*******************************\n- * hwrm_cfa_decap_filter_alloc *\n- *******************************/\n+/********************************\n+ * hwrm_cfa_ntuple_filter_alloc *\n+ ********************************/\n \n \n-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */\n-struct hwrm_cfa_decap_filter_alloc_input {\n+/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */\n+struct hwrm_cfa_ntuple_filter_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -23654,190 +22642,147 @@ struct hwrm_cfa_decap_filter_alloc_input {\n \t */\n \tuint64_t\tresp_addr;\n \tuint32_t\tflags;\n-\t/* ovs_tunnel is 1 b */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \\\n+\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n \t\tUINT32_C(0x1)\n+\t/*\n+\t * Setting of this flag indicates drop action. If this flag is not set,\n+\t * then it should be considered accept action.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Setting of this flag indicates that a meter is expected to be attached\n+\t * to this flow. This hint can be used when choosing the action record\n+\t * format required for the flow.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \\\n+\t\tUINT32_C(0x4)\n \tuint32_t\tenables;\n \t/*\n-\t * This bit must be '1' for the tunnel_type field to be\n+\t * This bit must be '1' for the l2_filter_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the tunnel_id field to be\n+\t * This bit must be '1' for the ethertype field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the src_macaddr field to be\n+\t * This bit must be '1' for the tunnel_type field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the dst_macaddr field to be\n+\t * This bit must be '1' for the src_macaddr field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * This bit must be '1' for the ovlan_vid field to be\n+\t * This bit must be '1' for the ipaddr_type field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * This bit must be '1' for the ivlan_vid field to be\n+\t * This bit must be '1' for the src_ipaddr field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \\\n \t\tUINT32_C(0x20)\n \t/*\n-\t * This bit must be '1' for the t_ovlan_vid field to be\n+\t * This bit must be '1' for the src_ipaddr_mask field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK \\\n \t\tUINT32_C(0x40)\n \t/*\n-\t * This bit must be '1' for the t_ivlan_vid field to be\n+\t * This bit must be '1' for the dst_ipaddr field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \\\n \t\tUINT32_C(0x80)\n \t/*\n-\t * This bit must be '1' for the ethertype field to be\n+\t * This bit must be '1' for the dst_ipaddr_mask field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK \\\n \t\tUINT32_C(0x100)\n \t/*\n-\t * This bit must be '1' for the src_ipaddr field to be\n+\t * This bit must be '1' for the ip_protocol field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \\\n \t\tUINT32_C(0x200)\n \t/*\n-\t * This bit must be '1' for the dst_ipaddr field to be\n+\t * This bit must be '1' for the src_port field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \\\n \t\tUINT32_C(0x400)\n \t/*\n-\t * This bit must be '1' for the ipaddr_type field to be\n+\t * This bit must be '1' for the src_port_mask field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK \\\n \t\tUINT32_C(0x800)\n \t/*\n-\t * This bit must be '1' for the ip_protocol field to be\n+\t * This bit must be '1' for the dst_port field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \\\n \t\tUINT32_C(0x1000)\n \t/*\n-\t * This bit must be '1' for the src_port field to be\n+\t * This bit must be '1' for the dst_port_mask field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK \\\n \t\tUINT32_C(0x2000)\n \t/*\n-\t * This bit must be '1' for the dst_port field to be\n+\t * This bit must be '1' for the pri_hint field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_PRI_HINT \\\n \t\tUINT32_C(0x4000)\n \t/*\n-\t * This bit must be '1' for the dst_id field to be\n+\t * This bit must be '1' for the ntuple_filter_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_NTUPLE_FILTER_ID \\\n \t\tUINT32_C(0x8000)\n \t/*\n-\t * This bit must be '1' for the mirror_vnic_id field to be\n+\t * This bit must be '1' for the dst_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n \t\tUINT32_C(0x10000)\n \t/*\n-\t * Tunnel identifier.\n-\t * Virtual Network Identifier (VNI). Only valid with\n-\t * tunnel_types VXLAN, NVGRE, and Geneve.\n-\t * Only lower 24-bits of VNI field are used\n-\t * in setting up the filter.\n-\t */\n-\tuint32_t\ttunnel_id;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Non-tunnel */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n-\t\tUINT32_C(0x0)\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n-\t\tUINT32_C(0x2)\n-\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n-\t\tUINT32_C(0x3)\n-\t/* IP in IP */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n-\t\tUINT32_C(0x4)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* Multi-Protocol Lable Switching (MPLS) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n-\t\tUINT32_C(0x6)\n-\t/* Stateless Transport Tunnel (STT) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n-\t\tUINT32_C(0x7)\n-\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n-\t\tUINT32_C(0x8)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Any tunneled traffic */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n-\t\tUINT32_C(0xff)\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n-\tuint8_t\tunused_0;\n-\tuint16_t\tunused_1;\n-\t/*\n-\t * This value indicates the source MAC address in\n-\t * the Ethernet header.\n-\t */\n-\tuint8_t\tsrc_macaddr[6];\n-\tuint8_t\tunused_2[2];\n-\t/*\n-\t * This value indicates the destination MAC address in\n-\t * the Ethernet header.\n-\t */\n-\tuint8_t\tdst_macaddr[6];\n-\t/*\n-\t * This value indicates the VLAN ID of the outer VLAN tag\n-\t * in the Ethernet header.\n+\t * This bit must be '1' for the mirror_vnic_id field to be\n+\t * configured.\n \t */\n-\tuint16_t\tovlan_vid;\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n+\t\tUINT32_C(0x20000)\n \t/*\n-\t * This value indicates the VLAN ID of the inner VLAN tag\n-\t * in the Ethernet header.\n+\t * This bit must be '1' for the dst_macaddr field to be\n+\t * configured.\n \t */\n-\tuint16_t\tivlan_vid;\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n+\t\tUINT32_C(0x40000)\n \t/*\n-\t * This value indicates the VLAN ID of the outer VLAN tag\n-\t * in the tunnel Ethernet header.\n+\t * This value identifies a set of CFA data structures used for an L2\n+\t * context.\n \t */\n-\tuint16_t\tt_ovlan_vid;\n+\tuint64_t\tl2_filter_id;\n \t/*\n-\t * This value indicates the VLAN ID of the inner VLAN tag\n-\t * in the tunnel Ethernet header.\n+\t * This value indicates the source MAC address in\n+\t * the Ethernet header.\n \t */\n-\tuint16_t\tt_ivlan_vid;\n+\tuint8_t\tsrc_macaddr[6];\n \t/* This value indicates the ethertype in the Ethernet header. */\n \tuint16_t\tethertype;\n \t/*\n@@ -23848,16 +22793,16 @@ struct hwrm_cfa_decap_filter_alloc_input {\n \t */\n \tuint8_t\tip_addr_type;\n \t/* invalid */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \\\n \t\tUINT32_C(0x0)\n \t/* IPv4 */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \\\n \t\tUINT32_C(0x4)\n \t/* IPv6 */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \\\n \t\tUINT32_C(0x6)\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \\\n-\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \\\n+\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6\n \t/*\n \t * The value of protocol filed in IP header.\n \t * Applies to UDP and TCP traffic.\n@@ -23866,53 +22811,146 @@ struct hwrm_cfa_decap_filter_alloc_input {\n \t */\n \tuint8_t\tip_protocol;\n \t/* invalid */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \\\n \t\tUINT32_C(0x0)\n \t/* TCP */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \\\n \t\tUINT32_C(0x6)\n \t/* UDP */\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \\\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \\\n \t\tUINT32_C(0x11)\n-\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \\\n-\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP\n-\tuint16_t\tunused_3;\n-\tuint32_t\tunused_4;\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \\\n+\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP\n+\t/*\n+\t * If set, this value shall represent the\n+\t * Logical VNIC ID of the destination VNIC for the RX\n+\t * path and network port id of the destination port for\n+\t * the TX path.\n+\t */\n+\tuint16_t\tdst_id;\n+\t/*\n+\t * Logical VNIC ID of the VNIC where traffic is\n+\t * mirrored.\n+\t */\n+\tuint16_t\tmirror_vnic_id;\n+\t/*\n+\t * This value indicates the tunnel type for this filter.\n+\t * If this field is not specified, then the filter shall\n+\t * apply to both non-tunneled and tunneled packets.\n+\t * If this field conflicts with the tunnel_type specified\n+\t * in the l2_filter_id, then the HWRM shall return an\n+\t * error for this command.\n+\t */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\t/*\n+\t * This hint is provided to help in placing\n+\t * the filter in the filter table.\n+\t */\n+\tuint8_t\tpri_hint;\n+\t/* No preference */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_NO_PREFER \\\n+\t\tUINT32_C(0x0)\n+\t/* Above the given filter */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_ABOVE \\\n+\t\tUINT32_C(0x1)\n+\t/* Below the given filter */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_BELOW \\\n+\t\tUINT32_C(0x2)\n+\t/* As high as possible */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_HIGHEST \\\n+\t\tUINT32_C(0x3)\n+\t/* As low as possible */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST \\\n+\t\tUINT32_C(0x4)\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LAST \\\n+\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_PRI_HINT_LOWEST\n \t/*\n \t * The value of source IP address to be used in filtering.\n \t * For IPv4, first four bytes represent the IP address.\n \t */\n-\tuint32_t\tsrc_ipaddr[4];\n+\tuint32_t\tsrc_ipaddr[4];\n+\t/*\n+\t * The value of source IP address mask to be used in\n+\t * filtering.\n+\t * For IPv4, first four bytes represent the IP address mask.\n+\t */\n+\tuint32_t\tsrc_ipaddr_mask[4];\n \t/*\n \t * The value of destination IP address to be used in filtering.\n \t * For IPv4, first four bytes represent the IP address.\n \t */\n \tuint32_t\tdst_ipaddr[4];\n+\t/*\n+\t * The value of destination IP address mask to be used in\n+\t * filtering.\n+\t * For IPv4, first four bytes represent the IP address mask.\n+\t */\n+\tuint32_t\tdst_ipaddr_mask[4];\n \t/*\n \t * The value of source port to be used in filtering.\n \t * Applies to UDP and TCP traffic.\n \t */\n \tuint16_t\tsrc_port;\n+\t/*\n+\t * The value of source port mask to be used in filtering.\n+\t * Applies to UDP and TCP traffic.\n+\t */\n+\tuint16_t\tsrc_port_mask;\n \t/*\n \t * The value of destination port to be used in filtering.\n \t * Applies to UDP and TCP traffic.\n \t */\n \tuint16_t\tdst_port;\n \t/*\n-\t * If set, this value shall represent the\n-\t * Logical VNIC ID of the destination VNIC for the RX\n-\t * path.\n+\t * The value of destination port mask to be used in\n+\t * filtering.\n+\t * Applies to UDP and TCP traffic.\n \t */\n-\tuint16_t\tdst_id;\n+\tuint16_t\tdst_port_mask;\n \t/*\n-\t * If set, this value shall represent the L2 context that matches the L2\n-\t * information of the decap filter.\n+\t * This is the ID of the filter that goes along with\n+\t * the pri_hint.\n \t */\n-\tuint16_t\tl2_ctxt_ref_id;\n+\tuint64_t\tntuple_filter_id_hint;\n } __attribute__((packed));\n \n-/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_decap_filter_alloc_output {\n+/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */\n+struct hwrm_cfa_ntuple_filter_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -23922,7 +22960,15 @@ struct hwrm_cfa_decap_filter_alloc_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/* This value is an opaque id into CFA data structures. */\n-\tuint32_t\tdecap_filter_id;\n+\tuint64_t\tntuple_filter_id;\n+\t/*\n+\t * This is the ID of the flow associated with this\n+\t * filter.\n+\t * This value shall be used to match and associate the\n+\t * flow identifier returned in completion records.\n+\t * A value of 0xFFFFFFFF shall indicate no flow id.\n+\t */\n+\tuint32_t\tflow_id;\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -23934,73 +22980,31 @@ struct hwrm_cfa_decap_filter_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/******************************\n- * hwrm_cfa_decap_filter_free *\n- ******************************/\n-\n-\n-/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */\n-struct hwrm_cfa_decap_filter_free_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n+/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */\n+struct hwrm_cfa_ntuple_filter_alloc_cmd_err {\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * command specific error codes that goes to\n+\t * the cmd_err field in Common HWRM Error Response.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* This value is an opaque id into CFA data structures. */\n-\tuint32_t\tdecap_filter_id;\n-\tuint8_t\tunused_0[4];\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */\n-struct hwrm_cfa_decap_filter_free_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n+\tuint8_t\tcode;\n+\t/* Unknown error */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN \\\n+\t\tUINT32_C(0x0)\n+\t/* Unable to complete operation due to conflict with Rx Mask VLAN */\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST \\\n+\t\tHWRM_CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR\n \tuint8_t\tunused_0[7];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_cfa_flow_alloc *\n- ***********************/\n+/*******************************\n+ * hwrm_cfa_ntuple_filter_free *\n+ *******************************/\n \n \n-/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */\n-struct hwrm_cfa_flow_alloc_input {\n+/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */\n+struct hwrm_cfa_ntuple_filter_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24027,155 +23031,13 @@ struct hwrm_cfa_flow_alloc_input {\n \t * physical address (HPA) or a guest physical address (GPA) and must\n \t * point to a physically contiguous block of memory.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint16_t\tflags;\n-\t/* tunnel is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL UINT32_C(0x1)\n-\t/* num_vlan is 2 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK UINT32_C(0x6)\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1\n-\t/* no tags */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \\\n-\t\t(UINT32_C(0x0) << 1)\n-\t/* 1 tag */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \\\n-\t\t(UINT32_C(0x1) << 1)\n-\t/* 2 tags */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \\\n-\t\t(UINT32_C(0x2) << 1)\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \\\n-\t\tHWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO\n-\t/* Enumeration denoting the Flow Type. */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK UINT32_C(0x38)\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3\n-\t/* L2 flow */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \\\n-\t\t(UINT32_C(0x0) << 3)\n-\t/* IPV4 flow */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \\\n-\t\t(UINT32_C(0x1) << 3)\n-\t/* IPV6 flow */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \\\n-\t\t(UINT32_C(0x2) << 3)\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \\\n-\t\tHWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6\n-\t/*\n-\t * Tx Flow: vf fid.\n-\t * Rx Flow: pf fid.\n-\t */\n-\tuint16_t\tsrc_fid;\n-\t/* Tunnel handle valid when tunnel flag is set. */\n-\tuint32_t\ttunnel_handle;\n-\tuint16_t\taction_flags;\n-\t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n-\t */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \\\n-\t\tUINT32_C(0x1)\n-\t/* recycle is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \\\n-\t\tUINT32_C(0x2)\n-\t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n-\t */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \\\n-\t\tUINT32_C(0x4)\n-\t/* meter is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \\\n-\t\tUINT32_C(0x8)\n-\t/* tunnel is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \\\n-\t\tUINT32_C(0x10)\n-\t/* nat_src is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \\\n-\t\tUINT32_C(0x20)\n-\t/* nat_dest is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \\\n-\t\tUINT32_C(0x40)\n-\t/* nat_ipv4_address is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \\\n-\t\tUINT32_C(0x80)\n-\t/* l2_header_rewrite is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \\\n-\t\tUINT32_C(0x100)\n-\t/* ttl_decrement is 1 b */\n-\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \\\n-\t\tUINT32_C(0x200)\n-\t/*\n-\t * Tx Flow: pf or vf fid.\n-\t * Rx Flow: vf fid.\n-\t */\n-\tuint16_t\tdst_fid;\n-\t/* VLAN tpid, valid when push_vlan flag is set. */\n-\tuint16_t\tl2_rewrite_vlan_tpid;\n-\t/* VLAN tci, valid when push_vlan flag is set. */\n-\tuint16_t\tl2_rewrite_vlan_tci;\n-\t/* Meter id, valid when meter flag is set. */\n-\tuint16_t\tact_meter_id;\n-\t/* Flow with the same l2 context tcam key. */\n-\tuint16_t\tref_flow_handle;\n-\t/* This value sets the match value for the ethertype. */\n-\tuint16_t\tethertype;\n-\t/* valid when num tags is 1 or 2. */\n-\tuint16_t\touter_vlan_tci;\n-\t/* This value sets the match value for the Destination MAC address. */\n-\tuint16_t\tdmac[3];\n-\t/* valid when num tags is 2. */\n-\tuint16_t\tinner_vlan_tci;\n-\t/* This value sets the match value for the Source MAC address. */\n-\tuint16_t\tsmac[3];\n-\t/* The bit length of destination IP address mask. */\n-\tuint8_t\tip_dst_mask_len;\n-\t/* The bit length of source IP address mask. */\n-\tuint8_t\tip_src_mask_len;\n-\t/* The value of destination IPv4/IPv6 address. */\n-\tuint32_t\tip_dst[4];\n-\t/* The source IPv4/IPv6 address. */\n-\tuint32_t\tip_src[4];\n-\t/*\n-\t * The value of source port.\n-\t * Applies to UDP and TCP traffic.\n-\t */\n-\tuint16_t\tl4_src_port;\n-\t/*\n-\t * The value of source port mask.\n-\t * Applies to UDP and TCP traffic.\n-\t */\n-\tuint16_t\tl4_src_port_mask;\n-\t/*\n-\t * The value of destination port.\n-\t * Applies to UDP and TCP traffic.\n-\t */\n-\tuint16_t\tl4_dst_port;\n-\t/*\n-\t * The value of destination port mask.\n-\t * Applies to UDP and TCP traffic.\n-\t */\n-\tuint16_t\tl4_dst_port_mask;\n-\t/*\n-\t * NAT IPv4/6 address based on address type flag.\n-\t * 0 values are ignored.\n-\t */\n-\tuint32_t\tnat_ip_address[4];\n-\t/* L2 header re-write Destination MAC address. */\n-\tuint16_t\tl2_rewrite_dmac[3];\n-\t/*\n-\t * The NAT source/destination port based on direction flag.\n-\t * Applies to UDP and TCP traffic.\n-\t * 0 values are ignored.\n-\t */\n-\tuint16_t\tnat_port;\n-\t/* L2 header re-write Source MAC address. */\n-\tuint16_t\tl2_rewrite_smac[3];\n-\t/* The value of ip protocol. */\n-\tuint8_t\tip_proto;\n-\tuint8_t\tunused_0;\n+\tuint64_t\tresp_addr;\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint64_t\tntuple_filter_id;\n } __attribute__((packed));\n \n-/* hwrm_cfa_flow_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_flow_alloc_output {\n+/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */\n+struct hwrm_cfa_ntuple_filter_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24184,9 +23046,7 @@ struct hwrm_cfa_flow_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Flow record index. */\n-\tuint16_t\tflow_handle;\n-\tuint8_t\tunused_0[5];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -24197,13 +23057,13 @@ struct hwrm_cfa_flow_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**********************\n- * hwrm_cfa_flow_free *\n- **********************/\n+/******************************\n+ * hwrm_cfa_ntuple_filter_cfg *\n+ ******************************/\n \n \n-/* hwrm_cfa_flow_free_input (size:192b/24B) */\n-struct hwrm_cfa_flow_free_input {\n+/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */\n+struct hwrm_cfa_ntuple_filter_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24231,13 +23091,59 @@ struct hwrm_cfa_flow_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Flow record index. */\n-\tuint16_t\tflow_handle;\n-\tuint8_t\tunused_0[6];\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the new_dst_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_DST_ID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the new_mirror_vnic_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_MIRROR_VNIC_ID \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the new_meter_instance_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \\\n+\t\tUINT32_C(0x4)\n+\tuint8_t\tunused_0[4];\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint64_t\tntuple_filter_id;\n+\t/*\n+\t * If set, this value shall represent the new\n+\t * Logical VNIC ID of the destination VNIC for the RX\n+\t * path and new network port id of the destination port for\n+\t * the TX path.\n+\t */\n+\tuint32_t\tnew_dst_id;\n+\t/*\n+\t * New Logical VNIC ID of the VNIC where traffic is\n+\t * mirrored.\n+\t */\n+\tuint32_t\tnew_mirror_vnic_id;\n+\t/*\n+\t * New meter to attach to the flow. Specifying the\n+\t * invalid instance ID is used to remove any existing\n+\t * meter from the flow.\n+\t */\n+\tuint16_t\tnew_meter_instance_id;\n+\t/*\n+\t * A value of 0xfff is considered invalid and implies the\n+\t * instance is not configured.\n+\t */\n+\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_LAST \\\n+\t\tHWRM_CFA_NTUPLE_FILTER_CFG_INPUT_NEW_METER_INSTANCE_ID_INVALID\n+\tuint8_t\tunused_1[6];\n } __attribute__((packed));\n \n-/* hwrm_cfa_flow_free_output (size:256b/32B) */\n-struct hwrm_cfa_flow_free_output {\n+/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */\n+struct hwrm_cfa_ntuple_filter_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24246,10 +23152,6 @@ struct hwrm_cfa_flow_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* packet is 64 b */\n-\tuint64_t\tpacket;\n-\t/* byte is 64 b */\n-\tuint64_t\tbyte;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -24261,13 +23163,13 @@ struct hwrm_cfa_flow_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**********************\n- * hwrm_cfa_flow_info *\n- **********************/\n+/**************************\n+ * hwrm_cfa_em_flow_alloc *\n+ **************************/\n \n \n-/* hwrm_cfa_flow_info_input (size:192b/24B) */\n-struct hwrm_cfa_flow_info_input {\n+/* hwrm_cfa_em_flow_alloc_input (size:896b/112B) */\n+struct hwrm_cfa_em_flow_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24295,288 +23197,307 @@ struct hwrm_cfa_flow_info_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Flow record index. */\n-\tuint16_t\tflow_handle;\n-\t/* Max flow handle */\n-\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \\\n-\t\tUINT32_C(0xfff)\n-\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0\n-\t/* CNP flow handle */\n-\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \\\n+\tuint32_t\tflags;\n+\t/*\n+\t * Enumeration denoting the RX, TX type of the resource.\n+\t * This enumeration is used for resources that are similar for both\n+\t * TX and RX paths of the chip.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)\n+\t/* tx path */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_TX UINT32_C(0x0)\n+\t/* rx path */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX UINT32_C(0x1)\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \\\n+\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX\n+\t/*\n+\t * Setting of this flag indicates enabling of a byte counter for a given\n+\t * flow.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR UINT32_C(0x2)\n+\t/*\n+\t * Setting of this flag indicates enabling of a packet counter for a given\n+\t * flow.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR UINT32_C(0x4)\n+\t/* Setting of this flag indicates de-capsulation action for the given flow. */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP UINT32_C(0x8)\n+\t/* Setting of this flag indicates encapsulation action for the given flow. */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP UINT32_C(0x10)\n+\t/*\n+\t * Setting of this flag indicates drop action. If this flag is not set,\n+\t * then it should be considered accept action.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP UINT32_C(0x20)\n+\t/*\n+\t * Setting of this flag indicates that a meter is expected to be attached\n+\t * to this flow. This hint can be used when choosing the action record\n+\t * format required for the flow.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER UINT32_C(0x40)\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the l2_filter_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the tunnel_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the tunnel_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_TUNNEL_ID \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the src_macaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the dst_macaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the ovlan_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the ivlan_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the ethertype field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This bit must be '1' for the src_ipaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This bit must be '1' for the dst_ipaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This bit must be '1' for the ipaddr_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * This bit must be '1' for the ip_protocol field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * This bit must be '1' for the src_port field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT \\\n \t\tUINT32_C(0x1000)\n-\t/* Direction rx = 1 */\n-\t#define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \\\n+\t/*\n+\t * This bit must be '1' for the dst_port field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * This bit must be '1' for the dst_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * This bit must be '1' for the mirror_vnic_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n \t\tUINT32_C(0x8000)\n-\tuint8_t\tunused_0[6];\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_flow_info_output (size:448b/56B) */\n-struct hwrm_cfa_flow_info_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* flags is 8 b */\n-\tuint8_t\tflags;\n-\t/* profile is 8 b */\n-\tuint8_t\tprofile;\n-\t/* src_fid is 16 b */\n-\tuint16_t\tsrc_fid;\n-\t/* dst_fid is 16 b */\n-\tuint16_t\tdst_fid;\n-\t/* l2_ctxt_id is 16 b */\n-\tuint16_t\tl2_ctxt_id;\n-\t/* em_info is 64 b */\n-\tuint64_t\tem_info;\n-\t/* tcam_info is 64 b */\n-\tuint64_t\ttcam_info;\n-\t/* vfp_tcam_info is 64 b */\n-\tuint64_t\tvfp_tcam_info;\n-\t/* ar_id is 16 b */\n-\tuint16_t\tar_id;\n-\t/* flow_handle is 16 b */\n-\tuint16_t\tflow_handle;\n-\t/* tunnel_handle is 32 b */\n-\tuint32_t\ttunnel_handle;\n-\tuint8_t\tunused_0[7];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This bit must be '1' for the encap_record_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ENCAP_RECORD_ID \\\n+\t\tUINT32_C(0x10000)\n+\t/*\n+\t * This bit must be '1' for the meter_instance_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_METER_INSTANCE_ID \\\n+\t\tUINT32_C(0x20000)\n+\t/*\n+\t * This value identifies a set of CFA data structures used for an L2\n+\t * context.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/***********************\n- * hwrm_cfa_flow_flush *\n- ***********************/\n-\n-\n-/* hwrm_cfa_flow_flush_input (size:192b/24B) */\n-struct hwrm_cfa_flow_flush_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint64_t\tl2_filter_id;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\tuint8_t\tunused_0[3];\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * Tunnel identifier.\n+\t * Virtual Network Identifier (VNI). Only valid with\n+\t * tunnel_types VXLAN, NVGRE, and Geneve.\n+\t * Only lower 24-bits of VNI field are used\n+\t * in setting up the filter.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint32_t\ttunnel_id;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * This value indicates the source MAC address in\n+\t * the Ethernet header.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint8_t\tsrc_macaddr[6];\n+\t/* The meter instance to attach to the flow. */\n+\tuint16_t\tmeter_instance_id;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * A value of 0xfff is considered invalid and implies the\n+\t * instance is not configured.\n \t */\n-\tuint16_t\ttarget_id;\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_LAST \\\n+\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_METER_INSTANCE_ID_INVALID\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * This value indicates the destination MAC address in\n+\t * the Ethernet header.\n \t */\n-\tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\tuint8_t\tunused_0[4];\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_flow_flush_output (size:128b/16B) */\n-struct hwrm_cfa_flow_flush_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint8_t\tdst_macaddr[6];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This value indicates the VLAN ID of the outer VLAN tag\n+\t * in the Ethernet header.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/***********************\n- * hwrm_cfa_flow_stats *\n- ***********************/\n-\n-\n-/* hwrm_cfa_flow_stats_input (size:320b/40B) */\n-struct hwrm_cfa_flow_stats_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint16_t\tovlan_vid;\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * This value indicates the VLAN ID of the inner VLAN tag\n+\t * in the Ethernet header.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint16_t\tivlan_vid;\n+\t/* This value indicates the ethertype in the Ethernet header. */\n+\tuint16_t\tethertype;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * This value indicates the type of IP address.\n+\t * 4 - IPv4\n+\t * 6 - IPv6\n+\t * All others are invalid.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint8_t\tip_addr_type;\n+\t/* invalid */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN UINT32_C(0x0)\n+\t/* IPv4 */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 UINT32_C(0x4)\n+\t/* IPv6 */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 UINT32_C(0x6)\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_LAST \\\n+\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * The value of protocol filed in IP header.\n+\t * Applies to UDP and TCP traffic.\n+\t * 6 - TCP\n+\t * 17 - UDP\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint8_t\tip_protocol;\n+\t/* invalid */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN UINT32_C(0x0)\n+\t/* TCP */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_TCP UINT32_C(0x6)\n+\t/* UDP */\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP UINT32_C(0x11)\n+\t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_LAST \\\n+\t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_PROTOCOL_UDP\n+\tuint8_t\tunused_1[2];\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * The value of source IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Flow handle. */\n-\tuint16_t\tnum_flows;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_0;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_1;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_2;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_3;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_4;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_5;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_6;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_7;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_8;\n-\t/* Flow handle. */\n-\tuint16_t\tflow_handle_9;\n-\tuint8_t\tunused_0[2];\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_flow_stats_output (size:1408b/176B) */\n-struct hwrm_cfa_flow_stats_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* packet_0 is 64 b */\n-\tuint64_t\tpacket_0;\n-\t/* packet_1 is 64 b */\n-\tuint64_t\tpacket_1;\n-\t/* packet_2 is 64 b */\n-\tuint64_t\tpacket_2;\n-\t/* packet_3 is 64 b */\n-\tuint64_t\tpacket_3;\n-\t/* packet_4 is 64 b */\n-\tuint64_t\tpacket_4;\n-\t/* packet_5 is 64 b */\n-\tuint64_t\tpacket_5;\n-\t/* packet_6 is 64 b */\n-\tuint64_t\tpacket_6;\n-\t/* packet_7 is 64 b */\n-\tuint64_t\tpacket_7;\n-\t/* packet_8 is 64 b */\n-\tuint64_t\tpacket_8;\n-\t/* packet_9 is 64 b */\n-\tuint64_t\tpacket_9;\n-\t/* byte_0 is 64 b */\n-\tuint64_t\tbyte_0;\n-\t/* byte_1 is 64 b */\n-\tuint64_t\tbyte_1;\n-\t/* byte_2 is 64 b */\n-\tuint64_t\tbyte_2;\n-\t/* byte_3 is 64 b */\n-\tuint64_t\tbyte_3;\n-\t/* byte_4 is 64 b */\n-\tuint64_t\tbyte_4;\n-\t/* byte_5 is 64 b */\n-\tuint64_t\tbyte_5;\n-\t/* byte_6 is 64 b */\n-\tuint64_t\tbyte_6;\n-\t/* byte_7 is 64 b */\n-\tuint64_t\tbyte_7;\n-\t/* byte_8 is 64 b */\n-\tuint64_t\tbyte_8;\n-\t/* byte_9 is 64 b */\n-\tuint64_t\tbyte_9;\n-\tuint8_t\tunused_0[7];\n+\tuint32_t\tsrc_ipaddr[4];\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * big_endian = True\n+\t * The value of destination IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**************************\n- * hwrm_cfa_vf_pair_alloc *\n- **************************/\n-\n-\n-/* hwrm_cfa_vf_pair_alloc_input (size:448b/56B) */\n-struct hwrm_cfa_vf_pair_alloc_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint32_t\tdst_ipaddr[4];\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * The value of source port to be used in filtering.\n+\t * Applies to UDP and TCP traffic.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint16_t\tsrc_port;\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * The value of destination port to be used in filtering.\n+\t * Applies to UDP and TCP traffic.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint16_t\tdst_port;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * If set, this value shall represent the\n+\t * Logical VNIC ID of the destination VNIC for the RX\n+\t * path and network port id of the destination port for\n+\t * the TX path.\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint16_t\tdst_id;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Logical VNIC ID of the VNIC where traffic is\n+\t * mirrored.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_a_id;\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_b_id;\n-\tuint8_t\tunused_0[4];\n-\t/* VF Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n+\tuint16_t\tmirror_vnic_id;\n+\t/* Logical ID of the encapsulation record. */\n+\tuint32_t\tencap_record_id;\n+\tuint8_t\tunused_2[4];\n } __attribute__((packed));\n \n-/* hwrm_cfa_vf_pair_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_vf_pair_alloc_output {\n+/* hwrm_cfa_em_flow_alloc_output (size:192b/24B) */\n+struct hwrm_cfa_em_flow_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24585,7 +23506,17 @@ struct hwrm_cfa_vf_pair_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint64_t\tem_filter_id;\n+\t/*\n+\t * This is the ID of the flow associated with this\n+\t * filter.\n+\t * This value shall be used to match and associate the\n+\t * flow identifier returned in completion records.\n+\t * A value of 0xFFFFFFFF shall indicate no flow id.\n+\t */\n+\tuint32_t\tflow_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -24597,12 +23528,12 @@ struct hwrm_cfa_vf_pair_alloc_output {\n } __attribute__((packed));\n \n /*************************\n- * hwrm_cfa_vf_pair_free *\n+ * hwrm_cfa_em_flow_free *\n *************************/\n \n \n-/* hwrm_cfa_vf_pair_free_input (size:384b/48B) */\n-struct hwrm_cfa_vf_pair_free_input {\n+/* hwrm_cfa_em_flow_free_input (size:192b/24B) */\n+struct hwrm_cfa_em_flow_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24630,12 +23561,12 @@ struct hwrm_cfa_vf_pair_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* VF Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint64_t\tem_filter_id;\n } __attribute__((packed));\n \n-/* hwrm_cfa_vf_pair_free_output (size:128b/16B) */\n-struct hwrm_cfa_vf_pair_free_output {\n+/* hwrm_cfa_em_flow_free_output (size:128b/16B) */\n+struct hwrm_cfa_em_flow_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24655,13 +23586,13 @@ struct hwrm_cfa_vf_pair_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*************************\n- * hwrm_cfa_vf_pair_info *\n- *************************/\n+/*******************************\n+ * hwrm_cfa_decap_filter_alloc *\n+ *******************************/\n \n \n-/* hwrm_cfa_vf_pair_info_input (size:448b/56B) */\n-struct hwrm_cfa_vf_pair_info_input {\n+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */\n+struct hwrm_cfa_decap_filter_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24690,177 +23621,265 @@ struct hwrm_cfa_vf_pair_info_input {\n \t */\n \tuint64_t\tresp_addr;\n \tuint32_t\tflags;\n-\t/* If this flag is set, lookup by name else lookup by index. */\n-\t#define HWRM_CFA_VF_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)\n-\t/* vf pair table index. */\n-\tuint16_t\tvf_pair_index;\n-\tuint8_t\tunused_0[2];\n-\t/* VF Pair name (32 byte string). */\n-\tchar\tvf_pair_name[32];\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_vf_pair_info_output (size:512b/64B) */\n-struct hwrm_cfa_vf_pair_info_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* vf pair table index. */\n-\tuint16_t\tnext_vf_pair_index;\n-\t/* vf pair member a's vf_fid. */\n-\tuint16_t\tvf_a_fid;\n-\t/* vf pair member a's Linux logical VF number. */\n-\tuint16_t\tvf_a_index;\n-\t/* vf pair member b's vf_fid. */\n-\tuint16_t\tvf_b_fid;\n-\t/* vf pair member a's Linux logical VF number. */\n-\tuint16_t\tvf_b_index;\n-\t/* vf pair state. */\n-\tuint8_t\tpair_state;\n-\t/* Pair has been allocated */\n-\t#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)\n-\t/* Both pair members are active */\n-\t#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)\n-\t#define HWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \\\n-\t\tHWRM_CFA_VF_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE\n-\tuint8_t\tunused_0[5];\n-\t/* VF Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n-\tuint8_t\tunused_1[7];\n+\t/* ovs_tunnel is 1 b */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \\\n+\t\tUINT32_C(0x1)\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the tunnel_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the tunnel_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the src_macaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the dst_macaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the ovlan_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the ivlan_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the t_ovlan_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the t_ivlan_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * This bit must be '1' for the ethertype field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * This bit must be '1' for the src_ipaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * This bit must be '1' for the dst_ipaddr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * This bit must be '1' for the ipaddr_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * This bit must be '1' for the ip_protocol field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * This bit must be '1' for the src_port field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * This bit must be '1' for the dst_port field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * This bit must be '1' for the dst_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \\\n+\t\tUINT32_C(0x8000)\n+\t/*\n+\t * This bit must be '1' for the mirror_vnic_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \\\n+\t\tUINT32_C(0x10000)\n+\t/*\n+\t * Tunnel identifier.\n+\t * Virtual Network Identifier (VNI). Only valid with\n+\t * tunnel_types VXLAN, NVGRE, and Geneve.\n+\t * Only lower 24-bits of VNI field are used\n+\t * in setting up the filter.\n+\t */\n+\tuint32_t\ttunnel_id;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \\\n+\t\tUINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \\\n+\t\tUINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \\\n+\t\tUINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \\\n+\t\tUINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \\\n+\t\tUINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \\\n+\t\tUINT32_C(0xff)\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n+\tuint8_t\tunused_0;\n+\tuint16_t\tunused_1;\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * This value indicates the source MAC address in\n+\t * the Ethernet header.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/***********************\n- * hwrm_cfa_pair_alloc *\n- ***********************/\n-\n-\n-/* hwrm_cfa_pair_alloc_input (size:576b/72B) */\n-struct hwrm_cfa_pair_alloc_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\tuint8_t\tsrc_macaddr[6];\n+\tuint8_t\tunused_2[2];\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * This value indicates the destination MAC address in\n+\t * the Ethernet header.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\tuint8_t\tdst_macaddr[6];\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * This value indicates the VLAN ID of the outer VLAN tag\n+\t * in the Ethernet header.\n \t */\n-\tuint16_t\tseq_id;\n+\tuint16_t\tovlan_vid;\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * This value indicates the VLAN ID of the inner VLAN tag\n+\t * in the Ethernet header.\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint16_t\tivlan_vid;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * This value indicates the VLAN ID of the outer VLAN tag\n+\t * in the tunnel Ethernet header.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair, 5-rep2fn_mod). */\n-\tuint8_t\tpair_mode;\n-\t/* Pair between VF on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0)\n-\t/* Pair between REP on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1)\n-\t/* Pair between REP on local host with REP on specified host. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2)\n-\t/* Pair for the proxy interface. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY UINT32_C(0x3)\n-\t/* Pair for the PF interface. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)\n-\t/* Modify exiting rep2fn pair and move pair to new PF. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5)\n-\t/* Modify exiting rep2fn pairs paired with same PF and move pairs to new PF. */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6)\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \\\n-\t\tHWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL\n-\tuint8_t\tunused_0;\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_a_id;\n-\t/* Logical Host (0xff-local host). */\n-\tuint8_t\thost_b_id;\n-\t/* Logical PF (0xff-PF for command channel). */\n-\tuint8_t\tpf_b_id;\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_b_id;\n-\t/* Loopback port (0xff-internal loopback), valid for mode-3. */\n-\tuint8_t\tport_id;\n-\t/* Priority used for encap of loopback packets valid for mode-3. */\n-\tuint8_t\tpri;\n-\t/* New PF for rep2fn modify, valid for mode 5. */\n-\tuint16_t\tnew_pf_fid;\n-\tuint32_t\tenables;\n+\tuint16_t\tt_ovlan_vid;\n \t/*\n-\t * This bit must be '1' for the q_ab field to be\n-\t * configured.\n+\t * This value indicates the VLAN ID of the inner VLAN tag\n+\t * in the tunnel Ethernet header.\n \t */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_AB_VALID UINT32_C(0x1)\n+\tuint16_t\tt_ivlan_vid;\n+\t/* This value indicates the ethertype in the Ethernet header. */\n+\tuint16_t\tethertype;\n \t/*\n-\t * This bit must be '1' for the q_ba field to be\n-\t * configured.\n+\t * This value indicates the type of IP address.\n+\t * 4 - IPv4\n+\t * 6 - IPv6\n+\t * All others are invalid.\n \t */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_Q_BA_VALID UINT32_C(0x2)\n+\tuint8_t\tip_addr_type;\n+\t/* invalid */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \\\n+\t\tUINT32_C(0x0)\n+\t/* IPv4 */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \\\n+\t\tUINT32_C(0x4)\n+\t/* IPv6 */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \\\n+\t\tUINT32_C(0x6)\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \\\n+\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6\n \t/*\n-\t * This bit must be '1' for the fc_ab field to be\n-\t * configured.\n+\t * The value of protocol filed in IP header.\n+\t * Applies to UDP and TCP traffic.\n+\t * 6 - TCP\n+\t * 17 - UDP\n+\t */\n+\tuint8_t\tip_protocol;\n+\t/* invalid */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \\\n+\t\tUINT32_C(0x0)\n+\t/* TCP */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \\\n+\t\tUINT32_C(0x6)\n+\t/* UDP */\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \\\n+\t\tUINT32_C(0x11)\n+\t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \\\n+\t\tHWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP\n+\tuint16_t\tunused_3;\n+\tuint32_t\tunused_4;\n+\t/*\n+\t * The value of source IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n \t */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_AB_VALID UINT32_C(0x4)\n+\tuint32_t\tsrc_ipaddr[4];\n \t/*\n-\t * This bit must be '1' for the fc_ba field to be\n-\t * configured.\n+\t * The value of destination IP address to be used in filtering.\n+\t * For IPv4, first four bytes represent the IP address.\n \t */\n-\t#define HWRM_CFA_PAIR_ALLOC_INPUT_ENABLES_FC_BA_VALID UINT32_C(0x8)\n-\t/* VF Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n+\tuint32_t\tdst_ipaddr[4];\n \t/*\n-\t * The q_ab value specifies the logical index of the TX/RX CoS\n-\t * queue to be assigned for traffic in the A to B direction of\n-\t * the interface pair. The default value is 0.\n+\t * The value of source port to be used in filtering.\n+\t * Applies to UDP and TCP traffic.\n \t */\n-\tuint8_t\tq_ab;\n+\tuint16_t\tsrc_port;\n \t/*\n-\t * The q_ba value specifies the logical index of the TX/RX CoS\n-\t * queue to be assigned for traffic in the B to A direction of\n-\t * the interface pair. The default value is 1.\n+\t * The value of destination port to be used in filtering.\n+\t * Applies to UDP and TCP traffic.\n \t */\n-\tuint8_t\tq_ba;\n+\tuint16_t\tdst_port;\n \t/*\n-\t * Specifies whether RX ring flow control is disabled (0) or enabled\n-\t * (1) in the A to B direction. The default value is 0, meaning that\n-\t * packets will be dropped when the B-side RX rings are full.\n+\t * If set, this value shall represent the\n+\t * Logical VNIC ID of the destination VNIC for the RX\n+\t * path.\n \t */\n-\tuint8_t\tfc_ab;\n+\tuint16_t\tdst_id;\n \t/*\n-\t * Specifies whether RX ring flow control is disabled (0) or enabled\n-\t * (1) in the B to A direction. The default value is 1, meaning that\n-\t * the RX CoS queue will be flow controlled when the A-side RX rings\n-\t * are full.\n+\t * If set, this value shall represent the L2 context that matches the L2\n+\t * information of the decap filter.\n \t */\n-\tuint8_t\tfc_ba;\n-\tuint8_t\tunused_1[4];\n+\tuint16_t\tl2_ctxt_ref_id;\n } __attribute__((packed));\n \n-/* hwrm_cfa_pair_alloc_output (size:192b/24B) */\n-struct hwrm_cfa_pair_alloc_output {\n+/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */\n+struct hwrm_cfa_decap_filter_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24869,15 +23888,9 @@ struct hwrm_cfa_pair_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Only valid for modes 1 and 2. */\n-\tuint16_t\trx_cfa_code_a;\n-\t/* Only valid for modes 1 and 2. */\n-\tuint16_t\ttx_cfa_action_a;\n-\t/* Only valid for mode 2. */\n-\tuint16_t\trx_cfa_code_b;\n-\t/* Only valid for mode 2. */\n-\tuint16_t\ttx_cfa_action_b;\n-\tuint8_t\tunused_0[7];\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint32_t\tdecap_filter_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -24888,13 +23901,13 @@ struct hwrm_cfa_pair_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**********************\n- * hwrm_cfa_pair_free *\n- **********************/\n+/******************************\n+ * hwrm_cfa_decap_filter_free *\n+ ******************************/\n \n \n-/* hwrm_cfa_pair_free_input (size:384b/48B) */\n-struct hwrm_cfa_pair_free_input {\n+/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */\n+struct hwrm_cfa_decap_filter_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24922,12 +23935,13 @@ struct hwrm_cfa_pair_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* VF Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n+\t/* This value is an opaque id into CFA data structures. */\n+\tuint32_t\tdecap_filter_id;\n+\tuint8_t\tunused_0[4];\n } __attribute__((packed));\n \n-/* hwrm_cfa_pair_free_output (size:128b/16B) */\n-struct hwrm_cfa_pair_free_output {\n+/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */\n+struct hwrm_cfa_decap_filter_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -24947,13 +23961,13 @@ struct hwrm_cfa_pair_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**********************\n- * hwrm_cfa_pair_info *\n- **********************/\n+/***********************\n+ * hwrm_cfa_flow_alloc *\n+ ***********************/\n \n \n-/* hwrm_cfa_pair_info_input (size:448b/56B) */\n-struct hwrm_cfa_pair_info_input {\n+/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */\n+struct hwrm_cfa_flow_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -24981,140 +23995,213 @@ struct hwrm_cfa_pair_info_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\tuint32_t\tflags;\n-\t/* If this flag is set, lookup by name else lookup by index. */\n-\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)\n-\t/* If this flag is set, lookup by PF id and VF id. */\n-\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)\n-\t/* Pair table index. */\n-\tuint16_t\tpair_index;\n-\t/* Pair pf index. */\n-\tuint8_t\tpair_pfid;\n-\t/* Pair vf index. */\n-\tuint8_t\tpair_vfid;\n-\t/* Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n-} __attribute__((packed));\n-\n-/* hwrm_cfa_pair_info_output (size:576b/72B) */\n-struct hwrm_cfa_pair_info_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* Pair table index. */\n-\tuint16_t\tnext_pair_index;\n-\t/* Pair member a's fid. */\n-\tuint16_t\ta_fid;\n-\t/* Logical host number. */\n-\tuint8_t\thost_a_index;\n-\t/* Logical PF number. */\n-\tuint8_t\tpf_a_index;\n-\t/* Pair member a's Linux logical VF number. */\n-\tuint16_t\tvf_a_index;\n-\t/* Rx CFA code. */\n-\tuint16_t\trx_cfa_code_a;\n-\t/* Tx CFA action. */\n-\tuint16_t\ttx_cfa_action_a;\n-\t/* Pair member b's fid. */\n-\tuint16_t\tb_fid;\n-\t/* Logical host number. */\n-\tuint8_t\thost_b_index;\n-\t/* Logical PF number. */\n-\tuint8_t\tpf_b_index;\n-\t/* Pair member a's Linux logical VF number. */\n-\tuint16_t\tvf_b_index;\n-\t/* Rx CFA code. */\n-\tuint16_t\trx_cfa_code_b;\n-\t/* Tx CFA action. */\n-\tuint16_t\ttx_cfa_action_b;\n-\t/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */\n-\tuint8_t\tpair_mode;\n-\t/* Pair between VF on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)\n-\t/* Pair between REP on local host with PF or VF on specified host. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)\n-\t/* Pair between REP on local host with REP on specified host. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)\n-\t/* Pair for the proxy interface. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)\n-\t/* Pair for the PF interface. */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \\\n-\t\tHWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR\n-\t/* Pair state. */\n-\tuint8_t\tpair_state;\n-\t/* Pair has been allocated */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)\n-\t/* Both pair members are active */\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)\n-\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \\\n-\t\tHWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE\n-\t/* Pair name (32 byte string). */\n-\tchar\tpair_name[32];\n-\tuint8_t\tunused_0[7];\n+\tuint16_t\tflags;\n+\t/* tunnel is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \\\n+\t\tUINT32_C(0x1)\n+\t/* num_vlan is 2 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \\\n+\t\tUINT32_C(0x6)\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1\n+\t/* no tags */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \\\n+\t\t(UINT32_C(0x0) << 1)\n+\t/* 1 tag */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \\\n+\t\t(UINT32_C(0x1) << 1)\n+\t/* 2 tags */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \\\n+\t\t(UINT32_C(0x2) << 1)\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \\\n+\t\tHWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO\n+\t/* Enumeration denoting the Flow Type. */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \\\n+\t\tUINT32_C(0x38)\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3\n+\t/* L2 flow */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \\\n+\t\t(UINT32_C(0x0) << 3)\n+\t/* IPV4 flow */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \\\n+\t\t(UINT32_C(0x1) << 3)\n+\t/* IPV6 flow */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \\\n+\t\t(UINT32_C(0x2) << 3)\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \\\n+\t\tHWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6\n \t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * when set to 1, indicates TX flow offload for function specified in src_fid and\n+\t * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both\n+\t * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload\n+\t * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV\n+\t * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID\n+\t * belong to the children VFs of the same PF to indicate VM to VM flow.\n \t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/**********************\n- * hwrm_cfa_vfr_alloc *\n- **********************/\n-\n-\n-/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */\n-struct hwrm_cfa_vfr_alloc_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \\\n+\t\tUINT32_C(0x40)\n \t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t * when set to 1, indicates RX flow offload for function specified in dst_fid and\n+\t * the src_fid should be set to invalid value.\n \t */\n-\tuint16_t\tcmpl_ring;\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \\\n+\t\tUINT32_C(0x80)\n \t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is\n+\t * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.\n+\t * This flag is only valid when the flow direction is RX.\n \t */\n-\tuint16_t\tseq_id;\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \\\n+\t\tUINT32_C(0x100)\n \t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n+\t * Tx Flow: vf fid.\n+\t * Rx Flow: pf fid.\n \t */\n-\tuint16_t\ttarget_id;\n+\tuint16_t\tsrc_fid;\n+\t/* Tunnel handle valid when tunnel flag is set. */\n+\tuint32_t\ttunnel_handle;\n+\tuint16_t\taction_flags;\n \t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n+\t * Setting of this flag indicates drop action. If this flag is not set,\n+\t * then it should be considered accept action.\n \t */\n-\tuint64_t\tresp_addr;\n-\t/* Logical VF number (range: 0 -> MAX_VFS -1). */\n-\tuint16_t\tvf_id;\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \\\n+\t\tUINT32_C(0x1)\n+\t/* recycle is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \\\n+\t\tUINT32_C(0x2)\n \t/*\n-\t * This field is reserved for the future use.\n-\t * It shall be set to 0.\n+\t * Setting of this flag indicates drop action. If this flag is not set,\n+\t * then it should be considered accept action.\n \t */\n-\tuint16_t\treserved;\n-\tuint8_t\tunused_0[4];\n-\t/* VF Representor name (32 byte string). */\n-\tchar\tvfr_name[32];\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \\\n+\t\tUINT32_C(0x4)\n+\t/* meter is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \\\n+\t\tUINT32_C(0x8)\n+\t/* tunnel is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \\\n+\t\tUINT32_C(0x10)\n+\t/* nat_src is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \\\n+\t\tUINT32_C(0x20)\n+\t/* nat_dest is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \\\n+\t\tUINT32_C(0x40)\n+\t/* nat_ipv4_address is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \\\n+\t\tUINT32_C(0x80)\n+\t/* l2_header_rewrite is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \\\n+\t\tUINT32_C(0x100)\n+\t/* ttl_decrement is 1 b */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * If set to 1 and flow direction is TX, it indicates decap of L2 header\n+\t * and encap of tunnel header. If set to 1 and flow direction is RX, it\n+\t * indicates decap of tunnel header and encap L2 header. The type of tunnel\n+\t * is specified in the tunnel_type field.\n+\t */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * Tx Flow: pf or vf fid.\n+\t * Rx Flow: vf fid.\n+\t */\n+\tuint16_t\tdst_fid;\n+\t/* VLAN tpid, valid when push_vlan flag is set. */\n+\tuint16_t\tl2_rewrite_vlan_tpid;\n+\t/* VLAN tci, valid when push_vlan flag is set. */\n+\tuint16_t\tl2_rewrite_vlan_tci;\n+\t/* Meter id, valid when meter flag is set. */\n+\tuint16_t\tact_meter_id;\n+\t/* Flow with the same l2 context tcam key. */\n+\tuint16_t\tref_flow_handle;\n+\t/* This value sets the match value for the ethertype. */\n+\tuint16_t\tethertype;\n+\t/* valid when num tags is 1 or 2. */\n+\tuint16_t\touter_vlan_tci;\n+\t/* This value sets the match value for the Destination MAC address. */\n+\tuint16_t\tdmac[3];\n+\t/* valid when num tags is 2. */\n+\tuint16_t\tinner_vlan_tci;\n+\t/* This value sets the match value for the Source MAC address. */\n+\tuint16_t\tsmac[3];\n+\t/* The bit length of destination IP address mask. */\n+\tuint8_t\tip_dst_mask_len;\n+\t/* The bit length of source IP address mask. */\n+\tuint8_t\tip_src_mask_len;\n+\t/* The value of destination IPv4/IPv6 address. */\n+\tuint32_t\tip_dst[4];\n+\t/* The source IPv4/IPv6 address. */\n+\tuint32_t\tip_src[4];\n+\t/*\n+\t * The value of source port.\n+\t * Applies to UDP and TCP traffic.\n+\t */\n+\tuint16_t\tl4_src_port;\n+\t/*\n+\t * The value of source port mask.\n+\t * Applies to UDP and TCP traffic.\n+\t */\n+\tuint16_t\tl4_src_port_mask;\n+\t/*\n+\t * The value of destination port.\n+\t * Applies to UDP and TCP traffic.\n+\t */\n+\tuint16_t\tl4_dst_port;\n+\t/*\n+\t * The value of destination port mask.\n+\t * Applies to UDP and TCP traffic.\n+\t */\n+\tuint16_t\tl4_dst_port_mask;\n+\t/*\n+\t * NAT IPv4/6 address based on address type flag.\n+\t * 0 values are ignored.\n+\t */\n+\tuint32_t\tnat_ip_address[4];\n+\t/* L2 header re-write Destination MAC address. */\n+\tuint16_t\tl2_rewrite_dmac[3];\n+\t/*\n+\t * The NAT source/destination port based on direction flag.\n+\t * Applies to UDP and TCP traffic.\n+\t * 0 values are ignored.\n+\t */\n+\tuint16_t\tnat_port;\n+\t/* L2 header re-write Source MAC address. */\n+\tuint16_t\tl2_rewrite_smac[3];\n+\t/* The value of ip protocol. */\n+\tuint8_t\tip_proto;\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)\n+\t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n } __attribute__((packed));\n \n-/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */\n-struct hwrm_cfa_vfr_alloc_output {\n+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */\n+struct hwrm_cfa_flow_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -25123,11 +24210,20 @@ struct hwrm_cfa_vfr_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Rx CFA code. */\n-\tuint16_t\trx_cfa_code;\n-\t/* Tx CFA action. */\n-\tuint16_t\ttx_cfa_action;\n-\tuint8_t\tunused_0[3];\n+\t/* Flow record index. */\n+\tuint16_t\tflow_handle;\n+\tuint8_t\tunused_0[2];\n+\t/*\n+\t * This is the ID of the flow associated with this\n+\t * filter.\n+\t * This value shall be used to match and associate the\n+\t * flow identifier returned in completion records.\n+\t * A value of 0xFFFFFFFF shall indicate no flow id.\n+\t */\n+\tuint32_t\tflow_id;\n+\t/* This value identifies a set of CFA data structures used for a flow. */\n+\tuint64_t\text_flow_handle;\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -25138,13 +24234,13 @@ struct hwrm_cfa_vfr_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*********************\n- * hwrm_cfa_vfr_free *\n- *********************/\n+/**********************\n+ * hwrm_cfa_flow_free *\n+ **********************/\n \n \n-/* hwrm_cfa_vfr_free_input (size:384b/48B) */\n-struct hwrm_cfa_vfr_free_input {\n+/* hwrm_cfa_flow_free_input (size:256b/32B) */\n+struct hwrm_cfa_flow_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -25172,12 +24268,15 @@ struct hwrm_cfa_vfr_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* VF Representor name (32 byte string). */\n-\tchar\tvfr_name[32];\n+\t/* Flow record index. */\n+\tuint16_t\tflow_handle;\n+\tuint8_t\tunused_0[6];\n+\t/* This value identifies a set of CFA data structures used for a flow. */\n+\tuint64_t\text_flow_handle;\n } __attribute__((packed));\n \n-/* hwrm_cfa_vfr_free_output (size:128b/16B) */\n-struct hwrm_cfa_vfr_free_output {\n+/* hwrm_cfa_flow_free_output (size:256b/32B) */\n+struct hwrm_cfa_flow_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -25186,6 +24285,10 @@ struct hwrm_cfa_vfr_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n+\t/* packet is 64 b */\n+\tuint64_t\tpacket;\n+\t/* byte is 64 b */\n+\tuint64_t\tbyte;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -25197,13 +24300,13 @@ struct hwrm_cfa_vfr_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/******************************\n- * hwrm_tunnel_dst_port_query *\n- ******************************/\n+/***********************\n+ * hwrm_cfa_flow_flush *\n+ ***********************/\n \n \n-/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */\n-struct hwrm_tunnel_dst_port_query_input {\n+/* hwrm_cfa_flow_flush_input (size:192b/24B) */\n+struct hwrm_cfa_flow_flush_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -25231,27 +24334,12 @@ struct hwrm_tunnel_dst_port_query_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n-\t\tUINT32_C(0xa)\n-\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1\n-\tuint8_t\tunused_0[7];\n+\tuint32_t\tflags;\n+\tuint8_t\tunused_0[4];\n } __attribute__((packed));\n \n-/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */\n-struct hwrm_tunnel_dst_port_query_output {\n+/* hwrm_cfa_flow_flush_output (size:128b/16B) */\n+struct hwrm_cfa_flow_flush_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -25260,25 +24348,7 @@ struct hwrm_tunnel_dst_port_query_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * This field represents the identifier of L4 destination port\n-\t * used for the given tunnel type. This field is valid for\n-\t * specific tunnel types that use layer 4 (e.g. UDP)\n-\t * transports for tunneling.\n-\t */\n-\tuint16_t\ttunnel_dst_port_id;\n-\t/*\n-\t * This field represents the value of L4 destination port\n-\t * identified by tunnel_dst_port_id. This field is valid for\n-\t * specific tunnel types that use layer 4 (e.g. UDP)\n-\t * transports for tunneling.\n-\t * This field is in network byte order.\n-\t *\n-\t * A value of 0 means that the destination port is not\n-\t * configured.\n-\t */\n-\tuint16_t\ttunnel_dst_port_val;\n-\tuint8_t\tunused_0[3];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -25289,13 +24359,13 @@ struct hwrm_tunnel_dst_port_query_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/******************************\n- * hwrm_tunnel_dst_port_alloc *\n- ******************************/\n+/***********************\n+ * hwrm_cfa_flow_stats *\n+ ***********************/\n \n \n-/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */\n-struct hwrm_tunnel_dst_port_alloc_input {\n+/* hwrm_cfa_flow_stats_input (size:640b/80B) */\n+struct hwrm_cfa_flow_stats_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -25323,39 +24393,53 @@ struct hwrm_tunnel_dst_port_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n-\t\tUINT32_C(0xa)\n-\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1\n-\tuint8_t\tunused_0;\n-\t/*\n-\t * This field represents the value of L4 destination port used\n-\t * for the given tunnel type. This field is valid for\n-\t * specific tunnel types that use layer 4 (e.g. UDP)\n-\t * transports for tunneling.\n-\t *\n-\t * This field is in network byte order.\n-\t *\n-\t * A value of 0 shall fail the command.\n-\t */\n-\tuint16_t\ttunnel_dst_port_val;\n-\tuint8_t\tunused_1[4];\n+\t/* Flow handle. */\n+\tuint16_t\tnum_flows;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_0;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_1;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_2;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_3;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_4;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_5;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_6;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_7;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_8;\n+\t/* Flow handle. */\n+\tuint16_t\tflow_handle_9;\n+\tuint8_t\tunused_0[2];\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_0;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_1;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_2;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_3;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_4;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_5;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_6;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_7;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_8;\n+\t/* Flow ID of a flow. */\n+\tuint32_t\tflow_id_9;\n } __attribute__((packed));\n \n-/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */\n-struct hwrm_tunnel_dst_port_alloc_output {\n+/* hwrm_cfa_flow_stats_output (size:1408b/176B) */\n+struct hwrm_cfa_flow_stats_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -25364,12 +24448,47 @@ struct hwrm_tunnel_dst_port_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/*\n-\t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n-\t * types that has l4 destination port parameters.\n-\t */\n-\tuint16_t\ttunnel_dst_port_id;\n-\tuint8_t\tunused_0[5];\n+\t/* packet_0 is 64 b */\n+\tuint64_t\tpacket_0;\n+\t/* packet_1 is 64 b */\n+\tuint64_t\tpacket_1;\n+\t/* packet_2 is 64 b */\n+\tuint64_t\tpacket_2;\n+\t/* packet_3 is 64 b */\n+\tuint64_t\tpacket_3;\n+\t/* packet_4 is 64 b */\n+\tuint64_t\tpacket_4;\n+\t/* packet_5 is 64 b */\n+\tuint64_t\tpacket_5;\n+\t/* packet_6 is 64 b */\n+\tuint64_t\tpacket_6;\n+\t/* packet_7 is 64 b */\n+\tuint64_t\tpacket_7;\n+\t/* packet_8 is 64 b */\n+\tuint64_t\tpacket_8;\n+\t/* packet_9 is 64 b */\n+\tuint64_t\tpacket_9;\n+\t/* byte_0 is 64 b */\n+\tuint64_t\tbyte_0;\n+\t/* byte_1 is 64 b */\n+\tuint64_t\tbyte_1;\n+\t/* byte_2 is 64 b */\n+\tuint64_t\tbyte_2;\n+\t/* byte_3 is 64 b */\n+\tuint64_t\tbyte_3;\n+\t/* byte_4 is 64 b */\n+\tuint64_t\tbyte_4;\n+\t/* byte_5 is 64 b */\n+\tuint64_t\tbyte_5;\n+\t/* byte_6 is 64 b */\n+\tuint64_t\tbyte_6;\n+\t/* byte_7 is 64 b */\n+\tuint64_t\tbyte_7;\n+\t/* byte_8 is 64 b */\n+\tuint64_t\tbyte_8;\n+\t/* byte_9 is 64 b */\n+\tuint64_t\tbyte_9;\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -25380,13 +24499,13 @@ struct hwrm_tunnel_dst_port_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/*****************************\n- * hwrm_tunnel_dst_port_free *\n- *****************************/\n+/**********************\n+ * hwrm_cfa_pair_info *\n+ **********************/\n \n \n-/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */\n-struct hwrm_tunnel_dst_port_free_input {\n+/* hwrm_cfa_pair_info_input (size:448b/56B) */\n+struct hwrm_cfa_pair_info_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -25414,33 +24533,23 @@ struct hwrm_tunnel_dst_port_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Tunnel Type. */\n-\tuint8_t\ttunnel_type;\n-\t/* Virtual eXtensible Local Area Network (VXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \\\n-\t\tUINT32_C(0x1)\n-\t/* Generic Network Virtualization Encapsulation (Geneve) */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \\\n-\t\tUINT32_C(0x5)\n-\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n-\t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n-\t\tUINT32_C(0xa)\n-\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \\\n-\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1\n-\tuint8_t\tunused_0;\n-\t/*\n-\t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n-\t * types that has l4 destination port parameters.\n-\t */\n-\tuint16_t\ttunnel_dst_port_id;\n-\tuint8_t\tunused_1[4];\n+\tuint32_t\tflags;\n+\t/* If this flag is set, lookup by name else lookup by index. */\n+\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)\n+\t/* If this flag is set, lookup by PF id and VF id. */\n+\t#define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)\n+\t/* Pair table index. */\n+\tuint16_t\tpair_index;\n+\t/* Pair pf index. */\n+\tuint8_t\tpair_pfid;\n+\t/* Pair vf index. */\n+\tuint8_t\tpair_vfid;\n+\t/* Pair name (32 byte string). */\n+\tchar\tpair_name[32];\n } __attribute__((packed));\n \n-/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */\n-struct hwrm_tunnel_dst_port_free_output {\n+/* hwrm_cfa_pair_info_output (size:576b/72B) */\n+struct hwrm_cfa_pair_info_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -25449,68 +24558,74 @@ struct hwrm_tunnel_dst_port_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_1[7];\n+\t/* Pair table index. */\n+\tuint16_t\tnext_pair_index;\n+\t/* Pair member a's fid. */\n+\tuint16_t\ta_fid;\n+\t/* Logical host number. */\n+\tuint8_t\thost_a_index;\n+\t/* Logical PF number. */\n+\tuint8_t\tpf_a_index;\n+\t/* Pair member a's Linux logical VF number. */\n+\tuint16_t\tvf_a_index;\n+\t/* Rx CFA code. */\n+\tuint16_t\trx_cfa_code_a;\n+\t/* Tx CFA action. */\n+\tuint16_t\ttx_cfa_action_a;\n+\t/* Pair member b's fid. */\n+\tuint16_t\tb_fid;\n+\t/* Logical host number. */\n+\tuint8_t\thost_b_index;\n+\t/* Logical PF number. */\n+\tuint8_t\tpf_b_index;\n+\t/* Pair member a's Linux logical VF number. */\n+\tuint16_t\tvf_b_index;\n+\t/* Rx CFA code. */\n+\tuint16_t\trx_cfa_code_b;\n+\t/* Tx CFA action. */\n+\tuint16_t\ttx_cfa_action_b;\n+\t/* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */\n+\tuint8_t\tpair_mode;\n+\t/* Pair between VF on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0)\n+\t/* Pair between REP on local host with PF or VF on specified host. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1)\n+\t/* Pair between REP on local host with REP on specified host. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2)\n+\t/* Pair for the proxy interface. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3)\n+\t/* Pair for the PF interface. */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4)\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \\\n+\t\tHWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR\n+\t/* Pair state. */\n+\tuint8_t\tpair_state;\n+\t/* Pair has been allocated */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ALLOCATED UINT32_C(0x1)\n+\t/* Both pair members are active */\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE UINT32_C(0x2)\n+\t#define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_LAST \\\n+\t\tHWRM_CFA_PAIR_INFO_OUTPUT_PAIR_STATE_ACTIVE\n+\t/* Pair name (32 byte string). */\n+\tchar\tpair_name[32];\n+\tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/* ctx_hw_stats (size:1280b/160B) */\n-struct ctx_hw_stats {\n-\t/* Number of received unicast packets */\n-\tuint64_t\trx_ucast_pkts;\n-\t/* Number of received multicast packets */\n-\tuint64_t\trx_mcast_pkts;\n-\t/* Number of received broadcast packets */\n-\tuint64_t\trx_bcast_pkts;\n-\t/* Number of discarded packets on received path */\n-\tuint64_t\trx_discard_pkts;\n-\t/* Number of dropped packets on received path */\n-\tuint64_t\trx_drop_pkts;\n-\t/* Number of received bytes for unicast traffic */\n-\tuint64_t\trx_ucast_bytes;\n-\t/* Number of received bytes for multicast traffic */\n-\tuint64_t\trx_mcast_bytes;\n-\t/* Number of received bytes for broadcast traffic */\n-\tuint64_t\trx_bcast_bytes;\n-\t/* Number of transmitted unicast packets */\n-\tuint64_t\ttx_ucast_pkts;\n-\t/* Number of transmitted multicast packets */\n-\tuint64_t\ttx_mcast_pkts;\n-\t/* Number of transmitted broadcast packets */\n-\tuint64_t\ttx_bcast_pkts;\n-\t/* Number of discarded packets on transmit path */\n-\tuint64_t\ttx_discard_pkts;\n-\t/* Number of dropped packets on transmit path */\n-\tuint64_t\ttx_drop_pkts;\n-\t/* Number of transmitted bytes for unicast traffic */\n-\tuint64_t\ttx_ucast_bytes;\n-\t/* Number of transmitted bytes for multicast traffic */\n-\tuint64_t\ttx_mcast_bytes;\n-\t/* Number of transmitted bytes for broadcast traffic */\n-\tuint64_t\ttx_bcast_bytes;\n-\t/* Number of TPA packets */\n-\tuint64_t\ttpa_pkts;\n-\t/* Number of TPA bytes */\n-\tuint64_t\ttpa_bytes;\n-\t/* Number of TPA events */\n-\tuint64_t\ttpa_events;\n-\t/* Number of TPA aborts */\n-\tuint64_t\ttpa_aborts;\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_stat_ctx_alloc *\n- ***********************/\n+/***************************************\n+ * hwrm_cfa_redirect_query_tunnel_type *\n+ ***************************************/\n \n \n-/* hwrm_stat_ctx_alloc_input (size:256b/32B) */\n-struct hwrm_stat_ctx_alloc_input {\n+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */\n+struct hwrm_cfa_redirect_query_tunnel_type_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -25538,36 +24653,13 @@ struct hwrm_stat_ctx_alloc_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* This is the address for statistic block. */\n-\tuint64_t\tstats_dma_addr;\n-\t/*\n-\t * The statistic block update period in ms.\n-\t * e.g. 250ms, 500ms, 750ms, 1000ms.\n-\t * If update_period_ms is 0, then the stats update\n-\t * shall be never done and the DMA address shall not be used.\n-\t * In this case, the stat block can only be read by\n-\t * hwrm_stat_ctx_query command.\n-\t */\n-\tuint32_t\tupdate_period_ms;\n-\t/*\n-\t * This field is used to specify statistics context specific\n-\t * configuration flags.\n-\t */\n-\tuint8_t\tstat_ctx_flags;\n-\t/*\n-\t * When this bit is set to '1', the statistics context shall be\n-\t * allocated for RoCE traffic only. In this case, traffic other\n-\t * than offloaded RoCE traffic shall not be included in this\n-\t * statistic context.\n-\t * When this bit is set to '0', the statistics context shall be\n-\t * used for the network traffic other than offloaded RoCE traffic.\n-\t */\n-\t#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)\n-\tuint8_t\tunused_0[3];\n+\t/* The source function id. */\n+\tuint16_t\tsrc_fid;\n+\tuint8_t\tunused_0[6];\n } __attribute__((packed));\n \n-/* hwrm_stat_ctx_alloc_output (size:128b/16B) */\n-struct hwrm_stat_ctx_alloc_output {\n+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */\n+struct hwrm_cfa_redirect_query_tunnel_type_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -25576,8 +24668,44 @@ struct hwrm_stat_ctx_alloc_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This is the statistics context ID value. */\n-\tuint32_t\tstat_ctx_id;\n+\t/* Tunnel Mask. */\n+\tuint32_t\ttunnel_mask;\n+\t/* Non-tunnel */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \\\n+\t\tUINT32_C(0x1)\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \\\n+\t\tUINT32_C(0x2)\n+\t/* Network Virtualization Generic Routing Encapsulation (NVGRE) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \\\n+\t\tUINT32_C(0x4)\n+\t/* Generic Routing Encapsulation (GRE) inside Ethernet payload */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \\\n+\t\tUINT32_C(0x8)\n+\t/* IP in IP */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \\\n+\t\tUINT32_C(0x10)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \\\n+\t\tUINT32_C(0x20)\n+\t/* Multi-Protocol Lable Switching (MPLS) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \\\n+\t\tUINT32_C(0x40)\n+\t/* Stateless Transport Tunnel (STT) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \\\n+\t\tUINT32_C(0x80)\n+\t/* Generic Routing Encapsulation (GRE) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \\\n+\t\tUINT32_C(0x100)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \\\n+\t\tUINT32_C(0x200)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \\\n+\t\tUINT32_C(0x400)\n+\t/* Any tunneled traffic */\n+\t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \\\n+\t\tUINT32_C(0x800)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -25589,13 +24717,13 @@ struct hwrm_stat_ctx_alloc_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/**********************\n- * hwrm_stat_ctx_free *\n- **********************/\n+/******************************\n+ * hwrm_tunnel_dst_port_query *\n+ ******************************/\n \n \n-/* hwrm_stat_ctx_free_input (size:192b/24B) */\n-struct hwrm_stat_ctx_free_input {\n+/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */\n+struct hwrm_tunnel_dst_port_query_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -25623,13 +24751,27 @@ struct hwrm_stat_ctx_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* ID of the statistics context that is being queried. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tunused_0[4];\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1\n+\tuint8_t\tunused_0[7];\n } __attribute__((packed));\n \n-/* hwrm_stat_ctx_free_output (size:128b/16B) */\n-struct hwrm_stat_ctx_free_output {\n+/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */\n+struct hwrm_tunnel_dst_port_query_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -25638,8 +24780,24 @@ struct hwrm_stat_ctx_free_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* This is the statistics context ID value. */\n-\tuint32_t\tstat_ctx_id;\n+\t/*\n+\t * This field represents the identifier of L4 destination port\n+\t * used for the given tunnel type. This field is valid for\n+\t * specific tunnel types that use layer 4 (e.g. UDP)\n+\t * transports for tunneling.\n+\t */\n+\tuint16_t\ttunnel_dst_port_id;\n+\t/*\n+\t * This field represents the value of L4 destination port\n+\t * identified by tunnel_dst_port_id. This field is valid for\n+\t * specific tunnel types that use layer 4 (e.g. UDP)\n+\t * transports for tunneling.\n+\t * This field is in network byte order.\n+\t *\n+\t * A value of 0 means that the destination port is not\n+\t * configured.\n+\t */\n+\tuint16_t\ttunnel_dst_port_val;\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -25651,13 +24809,13 @@ struct hwrm_stat_ctx_free_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***********************\n- * hwrm_stat_ctx_query *\n- ***********************/\n+/******************************\n+ * hwrm_tunnel_dst_port_alloc *\n+ ******************************/\n \n \n-/* hwrm_stat_ctx_query_input (size:192b/24B) */\n-struct hwrm_stat_ctx_query_input {\n+/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */\n+struct hwrm_tunnel_dst_port_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -25685,13 +24843,39 @@ struct hwrm_stat_ctx_query_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* ID of the statistics context that is being queried. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tunused_0[4];\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1\n+\tuint8_t\tunused_0;\n+\t/*\n+\t * This field represents the value of L4 destination port used\n+\t * for the given tunnel type. This field is valid for\n+\t * specific tunnel types that use layer 4 (e.g. UDP)\n+\t * transports for tunneling.\n+\t *\n+\t * This field is in network byte order.\n+\t *\n+\t * A value of 0 shall fail the command.\n+\t */\n+\tuint16_t\ttunnel_dst_port_val;\n+\tuint8_t\tunused_1[4];\n } __attribute__((packed));\n \n-/* hwrm_stat_ctx_query_output (size:1408b/176B) */\n-struct hwrm_stat_ctx_query_output {\n+/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */\n+struct hwrm_tunnel_dst_port_alloc_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -25700,47 +24884,12 @@ struct hwrm_stat_ctx_query_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Number of transmitted unicast packets */\n-\tuint64_t\ttx_ucast_pkts;\n-\t/* Number of transmitted multicast packets */\n-\tuint64_t\ttx_mcast_pkts;\n-\t/* Number of transmitted broadcast packets */\n-\tuint64_t\ttx_bcast_pkts;\n-\t/* Number of transmitted packets with error */\n-\tuint64_t\ttx_err_pkts;\n-\t/* Number of dropped packets on transmit path */\n-\tuint64_t\ttx_drop_pkts;\n-\t/* Number of transmitted bytes for unicast traffic */\n-\tuint64_t\ttx_ucast_bytes;\n-\t/* Number of transmitted bytes for multicast traffic */\n-\tuint64_t\ttx_mcast_bytes;\n-\t/* Number of transmitted bytes for broadcast traffic */\n-\tuint64_t\ttx_bcast_bytes;\n-\t/* Number of received unicast packets */\n-\tuint64_t\trx_ucast_pkts;\n-\t/* Number of received multicast packets */\n-\tuint64_t\trx_mcast_pkts;\n-\t/* Number of received broadcast packets */\n-\tuint64_t\trx_bcast_pkts;\n-\t/* Number of received packets with error */\n-\tuint64_t\trx_err_pkts;\n-\t/* Number of dropped packets on received path */\n-\tuint64_t\trx_drop_pkts;\n-\t/* Number of received bytes for unicast traffic */\n-\tuint64_t\trx_ucast_bytes;\n-\t/* Number of received bytes for multicast traffic */\n-\tuint64_t\trx_mcast_bytes;\n-\t/* Number of received bytes for broadcast traffic */\n-\tuint64_t\trx_bcast_bytes;\n-\t/* Number of aggregated unicast packets */\n-\tuint64_t\trx_agg_pkts;\n-\t/* Number of aggregated unicast bytes */\n-\tuint64_t\trx_agg_bytes;\n-\t/* Number of aggregation events */\n-\tuint64_t\trx_agg_events;\n-\t/* Number of aborted aggregations */\n-\tuint64_t\trx_agg_aborts;\n-\tuint8_t\tunused_0[7];\n+\t/*\n+\t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n+\t * types that has l4 destination port parameters.\n+\t */\n+\tuint16_t\ttunnel_dst_port_id;\n+\tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -25751,13 +24900,13 @@ struct hwrm_stat_ctx_query_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/***************************\n- * hwrm_stat_ctx_clr_stats *\n- ***************************/\n+/*****************************\n+ * hwrm_tunnel_dst_port_free *\n+ *****************************/\n \n \n-/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */\n-struct hwrm_stat_ctx_clr_stats_input {\n+/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */\n+struct hwrm_tunnel_dst_port_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -25785,13 +24934,33 @@ struct hwrm_stat_ctx_clr_stats_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* ID of the statistics context that is being queried. */\n-\tuint32_t\tstat_ctx_id;\n-\tuint8_t\tunused_0[4];\n+\t/* Tunnel Type. */\n+\tuint8_t\ttunnel_type;\n+\t/* Virtual eXtensible Local Area Network (VXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN \\\n+\t\tUINT32_C(0x1)\n+\t/* Generic Network Virtualization Encapsulation (Geneve) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE \\\n+\t\tUINT32_C(0x5)\n+\t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n+\t\tUINT32_C(0x9)\n+\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n+\t\tUINT32_C(0xa)\n+\t#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \\\n+\t\tHWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1\n+\tuint8_t\tunused_0;\n+\t/*\n+\t * Identifier of a tunnel L4 destination port value. Only applies to tunnel\n+\t * types that has l4 destination port parameters.\n+\t */\n+\tuint16_t\ttunnel_dst_port_id;\n+\tuint8_t\tunused_1[4];\n } __attribute__((packed));\n-\n-/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */\n-struct hwrm_stat_ctx_clr_stats_output {\n+\n+/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */\n+struct hwrm_tunnel_dst_port_free_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -25800,7 +24969,7 @@ struct hwrm_stat_ctx_clr_stats_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[7];\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -25811,13 +24980,58 @@ struct hwrm_stat_ctx_clr_stats_output {\n \tuint8_t\tvalid;\n } __attribute__((packed));\n \n-/********************\n- * hwrm_pcie_qstats *\n- ********************/\n+/* Periodic statistics context DMA to host. */\n+/* ctx_hw_stats (size:1280b/160B) */\n+struct ctx_hw_stats {\n+\t/* Number of received unicast packets */\n+\tuint64_t\trx_ucast_pkts;\n+\t/* Number of received multicast packets */\n+\tuint64_t\trx_mcast_pkts;\n+\t/* Number of received broadcast packets */\n+\tuint64_t\trx_bcast_pkts;\n+\t/* Number of discarded packets on received path */\n+\tuint64_t\trx_discard_pkts;\n+\t/* Number of dropped packets on received path */\n+\tuint64_t\trx_drop_pkts;\n+\t/* Number of received bytes for unicast traffic */\n+\tuint64_t\trx_ucast_bytes;\n+\t/* Number of received bytes for multicast traffic */\n+\tuint64_t\trx_mcast_bytes;\n+\t/* Number of received bytes for broadcast traffic */\n+\tuint64_t\trx_bcast_bytes;\n+\t/* Number of transmitted unicast packets */\n+\tuint64_t\ttx_ucast_pkts;\n+\t/* Number of transmitted multicast packets */\n+\tuint64_t\ttx_mcast_pkts;\n+\t/* Number of transmitted broadcast packets */\n+\tuint64_t\ttx_bcast_pkts;\n+\t/* Number of discarded packets on transmit path */\n+\tuint64_t\ttx_discard_pkts;\n+\t/* Number of dropped packets on transmit path */\n+\tuint64_t\ttx_drop_pkts;\n+\t/* Number of transmitted bytes for unicast traffic */\n+\tuint64_t\ttx_ucast_bytes;\n+\t/* Number of transmitted bytes for multicast traffic */\n+\tuint64_t\ttx_mcast_bytes;\n+\t/* Number of transmitted bytes for broadcast traffic */\n+\tuint64_t\ttx_bcast_bytes;\n+\t/* Number of TPA packets */\n+\tuint64_t\ttpa_pkts;\n+\t/* Number of TPA bytes */\n+\tuint64_t\ttpa_bytes;\n+\t/* Number of TPA events */\n+\tuint64_t\ttpa_events;\n+\t/* Number of TPA aborts */\n+\tuint64_t\ttpa_aborts;\n+} __attribute__((packed));\n \n+/***********************\n+ * hwrm_stat_ctx_alloc *\n+ ***********************/\n \n-/* hwrm_pcie_qstats_input (size:256b/32B) */\n-struct hwrm_pcie_qstats_input {\n+\n+/* hwrm_stat_ctx_alloc_input (size:256b/32B) */\n+struct hwrm_stat_ctx_alloc_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -25845,412 +25059,348 @@ struct hwrm_pcie_qstats_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n+\t/* This is the address for statistic block. */\n+\tuint64_t\tstats_dma_addr;\n \t/*\n-\t * The size of PCIe statistics block in bytes.\n-\t * Firmware will DMA the PCIe statistics to\n-\t * the host with this field size in the response.\n-\t */\n-\tuint16_t\tpcie_stat_size;\n-\tuint8_t\tunused_0[6];\n-\t/*\n-\t * This is the host address where\n-\t * PCIe statistics will be stored\n-\t */\n-\tuint64_t\tpcie_stat_host_addr;\n-} __attribute__((packed));\n-\n-/* hwrm_pcie_qstats_output (size:128b/16B) */\n-struct hwrm_pcie_qstats_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\t/* The size of PCIe statistics block in bytes. */\n-\tuint16_t\tpcie_stat_size;\n-\tuint8_t\tunused_0[5];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/* Port Tx Statistics Formats */\n-/* tx_port_stats (size:3264b/408B) */\n-struct tx_port_stats {\n-\t/* Total Number of 64 Bytes frames transmitted */\n-\tuint64_t\ttx_64b_frames;\n-\t/* Total Number of 65-127 Bytes frames transmitted */\n-\tuint64_t\ttx_65b_127b_frames;\n-\t/* Total Number of 128-255 Bytes frames transmitted */\n-\tuint64_t\ttx_128b_255b_frames;\n-\t/* Total Number of 256-511 Bytes frames transmitted */\n-\tuint64_t\ttx_256b_511b_frames;\n-\t/* Total Number of 512-1023 Bytes frames transmitted */\n-\tuint64_t\ttx_512b_1023b_frames;\n-\t/* Total Number of 1024-1518 Bytes frames transmitted */\n-\tuint64_t\ttx_1024b_1518_frames;\n-\t/*\n-\t * Total Number of each good VLAN (exludes FCS errors)\n-\t * frame transmitted which is 1519 to 1522 bytes in length\n-\t * inclusive (excluding framing bits but including FCS bytes).\n-\t */\n-\tuint64_t\ttx_good_vlan_frames;\n-\t/* Total Number of 1519-2047 Bytes frames transmitted */\n-\tuint64_t\ttx_1519b_2047_frames;\n-\t/* Total Number of 2048-4095 Bytes frames transmitted */\n-\tuint64_t\ttx_2048b_4095b_frames;\n-\t/* Total Number of 4096-9216 Bytes frames transmitted */\n-\tuint64_t\ttx_4096b_9216b_frames;\n-\t/* Total Number of 9217-16383 Bytes frames transmitted */\n-\tuint64_t\ttx_9217b_16383b_frames;\n-\t/* Total Number of good frames transmitted */\n-\tuint64_t\ttx_good_frames;\n-\t/* Total Number of frames transmitted */\n-\tuint64_t\ttx_total_frames;\n-\t/* Total number of unicast frames transmitted */\n-\tuint64_t\ttx_ucast_frames;\n-\t/* Total number of multicast frames transmitted */\n-\tuint64_t\ttx_mcast_frames;\n-\t/* Total number of broadcast frames transmitted */\n-\tuint64_t\ttx_bcast_frames;\n-\t/* Total number of PAUSE control frames transmitted */\n-\tuint64_t\ttx_pause_frames;\n-\t/*\n-\t * Total number of PFC/per-priority PAUSE\n-\t * control frames transmitted\n-\t */\n-\tuint64_t\ttx_pfc_frames;\n-\t/* Total number of jabber frames transmitted */\n-\tuint64_t\ttx_jabber_frames;\n-\t/* Total number of frames transmitted with FCS error */\n-\tuint64_t\ttx_fcs_err_frames;\n-\t/* Total number of control frames transmitted */\n-\tuint64_t\ttx_control_frames;\n-\t/* Total number of over-sized frames transmitted */\n-\tuint64_t\ttx_oversz_frames;\n-\t/* Total number of frames with single deferral */\n-\tuint64_t\ttx_single_dfrl_frames;\n-\t/* Total number of frames with multiple deferrals */\n-\tuint64_t\ttx_multi_dfrl_frames;\n-\t/* Total number of frames with single collision */\n-\tuint64_t\ttx_single_coll_frames;\n-\t/* Total number of frames with multiple collisions */\n-\tuint64_t\ttx_multi_coll_frames;\n-\t/* Total number of frames with late collisions */\n-\tuint64_t\ttx_late_coll_frames;\n-\t/* Total number of frames with excessive collisions */\n-\tuint64_t\ttx_excessive_coll_frames;\n-\t/* Total number of fragmented frames transmitted */\n-\tuint64_t\ttx_frag_frames;\n-\t/* Total number of transmit errors */\n-\tuint64_t\ttx_err;\n-\t/* Total number of single VLAN tagged frames transmitted */\n-\tuint64_t\ttx_tagged_frames;\n-\t/* Total number of double VLAN tagged frames transmitted */\n-\tuint64_t\ttx_dbl_tagged_frames;\n-\t/* Total number of runt frames transmitted */\n-\tuint64_t\ttx_runt_frames;\n-\t/* Total number of TX FIFO under runs */\n-\tuint64_t\ttx_fifo_underruns;\n-\t/*\n-\t * Total number of PFC frames with PFC enabled bit for\n-\t * Pri 0 transmitted\n-\t */\n-\tuint64_t\ttx_pfc_ena_frames_pri0;\n-\t/*\n-\t * Total number of PFC frames with PFC enabled bit for\n-\t * Pri 1 transmitted\n-\t */\n-\tuint64_t\ttx_pfc_ena_frames_pri1;\n-\t/*\n-\t * Total number of PFC frames with PFC enabled bit for\n-\t * Pri 2 transmitted\n-\t */\n-\tuint64_t\ttx_pfc_ena_frames_pri2;\n-\t/*\n-\t * Total number of PFC frames with PFC enabled bit for\n-\t * Pri 3 transmitted\n-\t */\n-\tuint64_t\ttx_pfc_ena_frames_pri3;\n-\t/*\n-\t * Total number of PFC frames with PFC enabled bit for\n-\t * Pri 4 transmitted\n-\t */\n-\tuint64_t\ttx_pfc_ena_frames_pri4;\n-\t/*\n-\t * Total number of PFC frames with PFC enabled bit for\n-\t * Pri 5 transmitted\n-\t */\n-\tuint64_t\ttx_pfc_ena_frames_pri5;\n-\t/*\n-\t * Total number of PFC frames with PFC enabled bit for\n-\t * Pri 6 transmitted\n-\t */\n-\tuint64_t\ttx_pfc_ena_frames_pri6;\n-\t/*\n-\t * Total number of PFC frames with PFC enabled bit for\n-\t * Pri 7 transmitted\n-\t */\n-\tuint64_t\ttx_pfc_ena_frames_pri7;\n-\t/* Total number of EEE LPI Events on TX */\n-\tuint64_t\ttx_eee_lpi_events;\n-\t/* EEE LPI Duration Counter on TX */\n-\tuint64_t\ttx_eee_lpi_duration;\n-\t/*\n-\t * Total number of Link Level Flow Control (LLFC) messages\n-\t * transmitted\n+\t * The statistic block update period in ms.\n+\t * e.g. 250ms, 500ms, 750ms, 1000ms.\n+\t * If update_period_ms is 0, then the stats update\n+\t * shall be never done and the DMA address shall not be used.\n+\t * In this case, the stat block can only be read by\n+\t * hwrm_stat_ctx_query command.\n \t */\n-\tuint64_t\ttx_llfc_logical_msgs;\n-\t/* Total number of HCFC messages transmitted */\n-\tuint64_t\ttx_hcfc_msgs;\n-\t/* Total number of TX collisions */\n-\tuint64_t\ttx_total_collisions;\n-\t/* Total number of transmitted bytes */\n-\tuint64_t\ttx_bytes;\n-\t/* Total number of end-to-end HOL frames */\n-\tuint64_t\ttx_xthol_frames;\n-\t/* Total Tx Drops per Port reported by STATS block */\n-\tuint64_t\ttx_stat_discard;\n-\t/* Total Tx Error Drops per Port reported by STATS block */\n-\tuint64_t\ttx_stat_error;\n-} __attribute__((packed));\n-\n-/* Port Rx Statistics Formats */\n-/* rx_port_stats (size:4224b/528B) */\n-struct rx_port_stats {\n-\t/* Total Number of 64 Bytes frames received */\n-\tuint64_t\trx_64b_frames;\n-\t/* Total Number of 65-127 Bytes frames received */\n-\tuint64_t\trx_65b_127b_frames;\n-\t/* Total Number of 128-255 Bytes frames received */\n-\tuint64_t\trx_128b_255b_frames;\n-\t/* Total Number of 256-511 Bytes frames received */\n-\tuint64_t\trx_256b_511b_frames;\n-\t/* Total Number of 512-1023 Bytes frames received */\n-\tuint64_t\trx_512b_1023b_frames;\n-\t/* Total Number of 1024-1518 Bytes frames received */\n-\tuint64_t\trx_1024b_1518_frames;\n+\tuint32_t\tupdate_period_ms;\n \t/*\n-\t * Total Number of each good VLAN (exludes FCS errors)\n-\t * frame received which is 1519 to 1522 bytes in length\n-\t * inclusive (excluding framing bits but including FCS bytes).\n+\t * This field is used to specify statistics context specific\n+\t * configuration flags.\n \t */\n-\tuint64_t\trx_good_vlan_frames;\n-\t/* Total Number of 1519-2047 Bytes frames received */\n-\tuint64_t\trx_1519b_2047b_frames;\n-\t/* Total Number of 2048-4095 Bytes frames received */\n-\tuint64_t\trx_2048b_4095b_frames;\n-\t/* Total Number of 4096-9216 Bytes frames received */\n-\tuint64_t\trx_4096b_9216b_frames;\n-\t/* Total Number of 9217-16383 Bytes frames received */\n-\tuint64_t\trx_9217b_16383b_frames;\n-\t/* Total number of frames received */\n-\tuint64_t\trx_total_frames;\n-\t/* Total number of unicast frames received */\n-\tuint64_t\trx_ucast_frames;\n-\t/* Total number of multicast frames received */\n-\tuint64_t\trx_mcast_frames;\n-\t/* Total number of broadcast frames received */\n-\tuint64_t\trx_bcast_frames;\n-\t/* Total number of received frames with FCS error */\n-\tuint64_t\trx_fcs_err_frames;\n-\t/* Total number of control frames received */\n-\tuint64_t\trx_ctrl_frames;\n-\t/* Total number of PAUSE frames received */\n-\tuint64_t\trx_pause_frames;\n-\t/* Total number of PFC frames received */\n-\tuint64_t\trx_pfc_frames;\n+\tuint8_t\tstat_ctx_flags;\n \t/*\n-\t * Total number of frames received with an unsupported\n-\t * opcode\n+\t * When this bit is set to '1', the statistics context shall be\n+\t * allocated for RoCE traffic only. In this case, traffic other\n+\t * than offloaded RoCE traffic shall not be included in this\n+\t * statistic context.\n+\t * When this bit is set to '0', the statistics context shall be\n+\t * used for the network traffic other than offloaded RoCE traffic.\n \t */\n-\tuint64_t\trx_unsupported_opcode_frames;\n+\t#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)\n+\tuint8_t\tunused_0[3];\n+} __attribute__((packed));\n+\n+/* hwrm_stat_ctx_alloc_output (size:128b/16B) */\n+struct hwrm_stat_ctx_alloc_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* This is the statistics context ID value. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n-\t * Total number of frames received with an unsupported\n-\t * DA for pause and PFC\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint64_t\trx_unsupported_da_pausepfc_frames;\n-\t/* Total number of frames received with an unsupported SA */\n-\tuint64_t\trx_wrong_sa_frames;\n-\t/* Total number of received packets with alignment error */\n-\tuint64_t\trx_align_err_frames;\n-\t/* Total number of received frames with out-of-range length */\n-\tuint64_t\trx_oor_len_frames;\n-\t/* Total number of received frames with error termination */\n-\tuint64_t\trx_code_err_frames;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/**********************\n+ * hwrm_stat_ctx_free *\n+ **********************/\n+\n+\n+/* hwrm_stat_ctx_free_input (size:192b/24B) */\n+struct hwrm_stat_ctx_free_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * Total number of received frames with a false carrier is\n-\t * detected during idle, as defined by RX_ER samples active\n-\t * and RXD is 0xE. The event is reported along with the\n-\t * statistics generated on the next received frame. Only\n-\t * one false carrier condition can be detected and logged\n-\t * between frames.\n-\t *\n-\t * Carrier event, valid for 10M/100M speed modes only.\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint64_t\trx_false_carrier_frames;\n-\t/* Total number of over-sized frames received */\n-\tuint64_t\trx_ovrsz_frames;\n-\t/* Total number of jabber packets received */\n-\tuint64_t\trx_jbr_frames;\n-\t/* Total number of received frames with MTU error */\n-\tuint64_t\trx_mtu_err_frames;\n-\t/* Total number of received frames with CRC match */\n-\tuint64_t\trx_match_crc_frames;\n-\t/* Total number of frames received promiscuously */\n-\tuint64_t\trx_promiscuous_frames;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * Total number of received frames with one or two VLAN\n-\t * tags\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint64_t\trx_tagged_frames;\n-\t/* Total number of received frames with two VLAN tags */\n-\tuint64_t\trx_double_tagged_frames;\n-\t/* Total number of truncated frames received */\n-\tuint64_t\trx_trunc_frames;\n-\t/* Total number of good frames (without errors) received */\n-\tuint64_t\trx_good_frames;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * Total number of received PFC frames with transition from\n-\t * XON to XOFF on Pri 0\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint64_t\trx_pfc_xon2xoff_frames_pri0;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * Total number of received PFC frames with transition from\n-\t * XON to XOFF on Pri 1\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint64_t\trx_pfc_xon2xoff_frames_pri1;\n+\tuint64_t\tresp_addr;\n+\t/* ID of the statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_stat_ctx_free_output (size:128b/16B) */\n+struct hwrm_stat_ctx_free_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* This is the statistics context ID value. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[3];\n \t/*\n-\t * Total number of received PFC frames with transition from\n-\t * XON to XOFF on Pri 2\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint64_t\trx_pfc_xon2xoff_frames_pri2;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***********************\n+ * hwrm_stat_ctx_query *\n+ ***********************/\n+\n+\n+/* hwrm_stat_ctx_query_input (size:192b/24B) */\n+struct hwrm_stat_ctx_query_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * Total number of received PFC frames with transition from\n-\t * XON to XOFF on Pri 3\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint64_t\trx_pfc_xon2xoff_frames_pri3;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * Total number of received PFC frames with transition from\n-\t * XON to XOFF on Pri 4\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint64_t\trx_pfc_xon2xoff_frames_pri4;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * Total number of received PFC frames with transition from\n-\t * XON to XOFF on Pri 5\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint64_t\trx_pfc_xon2xoff_frames_pri5;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * Total number of received PFC frames with transition from\n-\t * XON to XOFF on Pri 6\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint64_t\trx_pfc_xon2xoff_frames_pri6;\n+\tuint64_t\tresp_addr;\n+\t/* ID of the statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_stat_ctx_query_output (size:1408b/176B) */\n+struct hwrm_stat_ctx_query_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* Number of transmitted unicast packets */\n+\tuint64_t\ttx_ucast_pkts;\n+\t/* Number of transmitted multicast packets */\n+\tuint64_t\ttx_mcast_pkts;\n+\t/* Number of transmitted broadcast packets */\n+\tuint64_t\ttx_bcast_pkts;\n+\t/* Number of transmitted packets with error */\n+\tuint64_t\ttx_err_pkts;\n+\t/* Number of dropped packets on transmit path */\n+\tuint64_t\ttx_drop_pkts;\n+\t/* Number of transmitted bytes for unicast traffic */\n+\tuint64_t\ttx_ucast_bytes;\n+\t/* Number of transmitted bytes for multicast traffic */\n+\tuint64_t\ttx_mcast_bytes;\n+\t/* Number of transmitted bytes for broadcast traffic */\n+\tuint64_t\ttx_bcast_bytes;\n+\t/* Number of received unicast packets */\n+\tuint64_t\trx_ucast_pkts;\n+\t/* Number of received multicast packets */\n+\tuint64_t\trx_mcast_pkts;\n+\t/* Number of received broadcast packets */\n+\tuint64_t\trx_bcast_pkts;\n+\t/* Number of received packets with error */\n+\tuint64_t\trx_err_pkts;\n+\t/* Number of dropped packets on received path */\n+\tuint64_t\trx_drop_pkts;\n+\t/* Number of received bytes for unicast traffic */\n+\tuint64_t\trx_ucast_bytes;\n+\t/* Number of received bytes for multicast traffic */\n+\tuint64_t\trx_mcast_bytes;\n+\t/* Number of received bytes for broadcast traffic */\n+\tuint64_t\trx_bcast_bytes;\n+\t/* Number of aggregated unicast packets */\n+\tuint64_t\trx_agg_pkts;\n+\t/* Number of aggregated unicast bytes */\n+\tuint64_t\trx_agg_bytes;\n+\t/* Number of aggregation events */\n+\tuint64_t\trx_agg_events;\n+\t/* Number of aborted aggregations */\n+\tuint64_t\trx_agg_aborts;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * Total number of received PFC frames with transition from\n-\t * XON to XOFF on Pri 7\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint64_t\trx_pfc_xon2xoff_frames_pri7;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/***************************\n+ * hwrm_stat_ctx_clr_stats *\n+ ***************************/\n+\n+\n+/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */\n+struct hwrm_stat_ctx_clr_stats_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * Total number of received PFC frames with PFC enabled\n-\t * bit for Pri 0\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint64_t\trx_pfc_ena_frames_pri0;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * Total number of received PFC frames with PFC enabled\n-\t * bit for Pri 1\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint64_t\trx_pfc_ena_frames_pri1;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * Total number of received PFC frames with PFC enabled\n-\t * bit for Pri 2\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint64_t\trx_pfc_ena_frames_pri2;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * Total number of received PFC frames with PFC enabled\n-\t * bit for Pri 3\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint64_t\trx_pfc_ena_frames_pri3;\n+\tuint64_t\tresp_addr;\n+\t/* ID of the statistics context that is being queried. */\n+\tuint32_t\tstat_ctx_id;\n+\tuint8_t\tunused_0[4];\n+} __attribute__((packed));\n+\n+/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */\n+struct hwrm_stat_ctx_clr_stats_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n \t/*\n-\t * Total number of received PFC frames with PFC enabled\n-\t * bit for Pri 4\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n \t */\n-\tuint64_t\trx_pfc_ena_frames_pri4;\n+\tuint8_t\tvalid;\n+} __attribute__((packed));\n+\n+/********************\n+ * hwrm_pcie_qstats *\n+ ********************/\n+\n+\n+/* hwrm_pcie_qstats_input (size:256b/32B) */\n+struct hwrm_pcie_qstats_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n \t/*\n-\t * Total number of received PFC frames with PFC enabled\n-\t * bit for Pri 5\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n \t */\n-\tuint64_t\trx_pfc_ena_frames_pri5;\n+\tuint16_t\tcmpl_ring;\n \t/*\n-\t * Total number of received PFC frames with PFC enabled\n-\t * bit for Pri 6\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n \t */\n-\tuint64_t\trx_pfc_ena_frames_pri6;\n+\tuint16_t\tseq_id;\n \t/*\n-\t * Total number of received PFC frames with PFC enabled\n-\t * bit for Pri 7\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n+\t * * 0xFFFF - HWRM\n \t */\n-\tuint64_t\trx_pfc_ena_frames_pri7;\n-\t/* Total Number of frames received with SCH CRC error */\n-\tuint64_t\trx_sch_crc_err_frames;\n-\t/* Total Number of under-sized frames received */\n-\tuint64_t\trx_undrsz_frames;\n-\t/* Total Number of fragmented frames received */\n-\tuint64_t\trx_frag_frames;\n-\t/* Total number of RX EEE LPI Events */\n-\tuint64_t\trx_eee_lpi_events;\n-\t/* EEE LPI Duration Counter on RX */\n-\tuint64_t\trx_eee_lpi_duration;\n+\tuint16_t\ttarget_id;\n \t/*\n-\t * Total number of physical type Link Level Flow Control\n-\t * (LLFC) messages received\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n \t */\n-\tuint64_t\trx_llfc_physical_msgs;\n+\tuint64_t\tresp_addr;\n \t/*\n-\t * Total number of logical type Link Level Flow Control\n-\t * (LLFC) messages received\n+\t * The size of PCIe statistics block in bytes.\n+\t * Firmware will DMA the PCIe statistics to\n+\t * the host with this field size in the response.\n \t */\n-\tuint64_t\trx_llfc_logical_msgs;\n+\tuint16_t\tpcie_stat_size;\n+\tuint8_t\tunused_0[6];\n \t/*\n-\t * Total number of logical type Link Level Flow Control\n-\t * (LLFC) messages received with CRC error\n+\t * This is the host address where\n+\t * PCIe statistics will be stored\n \t */\n-\tuint64_t\trx_llfc_msgs_with_crc_err;\n-\t/* Total number of HCFC messages received */\n-\tuint64_t\trx_hcfc_msgs;\n-\t/* Total number of HCFC messages received with CRC error */\n-\tuint64_t\trx_hcfc_msgs_with_crc_err;\n-\t/* Total number of received bytes */\n-\tuint64_t\trx_bytes;\n-\t/* Total number of bytes received in runt frames */\n-\tuint64_t\trx_runt_bytes;\n-\t/* Total number of runt frames received */\n-\tuint64_t\trx_runt_frames;\n-\t/* Total Rx Discards per Port reported by STATS block */\n-\tuint64_t\trx_stat_discard;\n-\tuint64_t\trx_stat_err;\n+\tuint64_t\tpcie_stat_host_addr;\n } __attribute__((packed));\n \n-/* Port Rx Statistics extended Formats */\n-/* rx_port_stats_ext (size:320b/40B) */\n-struct rx_port_stats_ext {\n-\t/* Number of times link state changed to down */\n-\tuint64_t\tlink_down_events;\n-\t/* Number of times the idle rings with pause bit are found */\n-\tuint64_t\tcontinuous_pause_events;\n-\t/* Number of times the active rings pause bit resumed back */\n-\tuint64_t\tresume_pause_events;\n-\t/* Number of times, the ROCE cos queue PFC is disabled to avoid pause flood/burst */\n-\tuint64_t\tcontinuous_roce_pause_events;\n-\t/* Number of times, the ROCE cos queue PFC is enabled back */\n-\tuint64_t\tresume_roce_pause_events;\n+/* hwrm_pcie_qstats_output (size:128b/16B) */\n+struct hwrm_pcie_qstats_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* The size of PCIe statistics block in bytes. */\n+\tuint16_t\tpcie_stat_size;\n+\tuint8_t\tunused_0[5];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n } __attribute__((packed));\n \n /* PCIe Statistics Formats */\n@@ -28109,103 +27259,4 @@ struct hwrm_nvm_validate_option_cmd_err {\n \tuint8_t\tunused_0[7];\n } __attribute__((packed));\n \n-/*****************************\n- * hwrm_nvm_factory_defaults *\n- *****************************/\n-\n-\n-/* hwrm_nvm_factory_defaults_input (size:192b/24B) */\n-struct hwrm_nvm_factory_defaults_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFE - Reserved for internal processors\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/* mode is 8 b */\n-\tuint8_t\tmode;\n-\t/* If set to 1, it will trigger restoration of factory default settings */\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_RESTORE UINT32_C(0x0)\n-\t/* If set to 1, it will trigger creation of factory default settings */\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE UINT32_C(0x1)\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_LAST \\\n-\t\tHWRM_NVM_FACTORY_DEFAULTS_INPUT_MODE_CREATE\n-\tuint8_t\tunused_0[7];\n-} __attribute__((packed));\n-\n-/* hwrm_nvm_factory_defaults_output (size:128b/16B) */\n-struct hwrm_nvm_factory_defaults_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint8_t\tresult;\n-\t/* factory defaults created successfully. */\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_OK \\\n-\t\tUINT32_C(0x0)\n-\t/* factory defaults restored successfully. */\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_RESTORE_OK \\\n-\t\tUINT32_C(0x1)\n-\t/* factory defaults already created. */\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY \\\n-\t\tUINT32_C(0x2)\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_LAST \\\n-\t\tHWRM_NVM_FACTORY_DEFAULTS_OUTPUT_RESULT_CREATE_ALREADY\n-\tuint8_t\tunused_0[6];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM. This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __attribute__((packed));\n-\n-/* hwrm_nvm_factory_defaults_cmd_err (size:64b/8B) */\n-struct hwrm_nvm_factory_defaults_cmd_err {\n-\t/*\n-\t * command specific error codes that goes to\n-\t * the cmd_err field in Common HWRM Error Response.\n-\t */\n-\tuint8_t\tcode;\n-\t/* Unknown error */\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_UNKNOWN \\\n-\t\tUINT32_C(0x0)\n-\t/* valid configuration not present to create defaults */\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_VALID_CFG \\\n-\t\tUINT32_C(0x1)\n-\t/* No saved configuration present to restore, restore failed */\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG \\\n-\t\tUINT32_C(0x2)\n-\t#define HWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_LAST \\\n-\t\tHWRM_NVM_FACTORY_DEFAULTS_CMD_ERR_CODE_NO_SAVED_CFG\n-\tuint8_t\tunused_0[7];\n-} __attribute__((packed));\n-\n #endif /* _HSI_STRUCT_DEF_DPDK_H_ */\n", "prefixes": [ "v2", "04/12" ] }