Patch Detail

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{
    "id": 44639,
    "url": "http://patches.dpdk.org/api/patches/44639/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20180913060846.29930-4-g.singh@nxp.com/",
    "project": {
        "id": 1,
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        "name": "DPDK",
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    "msgid": "<20180913060846.29930-4-g.singh@nxp.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20180913060846.29930-4-g.singh@nxp.com",
    "date": "2018-09-13T06:08:39",
    "name": "[03/10] crypto/caam_jr: add HW config for job rings",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "724f87163002773b8707b99208f7afdd1ddc66cf",
    "submitter": {
        "id": 1068,
        "url": "http://patches.dpdk.org/api/people/1068/?format=api",
        "name": "Gagandeep Singh",
        "email": "g.singh@nxp.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20180913060846.29930-4-g.singh@nxp.com/mbox/",
    "series": [
        {
            "id": 1300,
            "url": "http://patches.dpdk.org/api/series/1300/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=1300",
            "date": "2018-09-13T06:08:36",
            "name": "Introducing the NXP CAAM job ring driver",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/1300/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/44639/comments/",
    "check": "fail",
    "checks": "http://patches.dpdk.org/api/patches/44639/checks/",
    "tags": {},
    "related": [],
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        "From": "Gagandeep Singh <g.singh@nxp.com>",
        "To": "dev@dpdk.org,\n\takhil.goyal@nxp.com",
        "Cc": "Hemant Agrawal <hemant.agrawal@nxp.com>,\n\tGagandeep Singh <g.singh@nxp.com>",
        "Date": "Thu, 13 Sep 2018 11:38:39 +0530",
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        "Subject": "[dpdk-dev] [PATCH 03/10] crypto/caam_jr: add HW config for job rings",
        "X-BeenThere": "dev@dpdk.org",
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    },
    "content": "From: Hemant Agrawal <hemant.agrawal@nxp.com>\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\nSigned-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>\n---\n drivers/crypto/caam_jr/Makefile              |   6 +\n drivers/crypto/caam_jr/caam_jr.c             | 329 +++++++++++-\n drivers/crypto/caam_jr/caam_jr_config.h      | 207 ++++++++\n drivers/crypto/caam_jr/caam_jr_hw.c          | 365 ++++++++++++++\n drivers/crypto/caam_jr/caam_jr_hw_specific.h | 503 +++++++++++++++++++\n drivers/crypto/caam_jr/caam_jr_pvt.h         | 285 +++++++++++\n drivers/crypto/caam_jr/caam_jr_uio.c         | 491 ++++++++++++++++++\n drivers/crypto/caam_jr/meson.build           |   5 +-\n 8 files changed, 2188 insertions(+), 3 deletions(-)\n create mode 100644 drivers/crypto/caam_jr/caam_jr_config.h\n create mode 100644 drivers/crypto/caam_jr/caam_jr_hw.c\n create mode 100644 drivers/crypto/caam_jr/caam_jr_hw_specific.h\n create mode 100644 drivers/crypto/caam_jr/caam_jr_pvt.h\n create mode 100644 drivers/crypto/caam_jr/caam_jr_uio.c",
    "diff": "diff --git a/drivers/crypto/caam_jr/Makefile b/drivers/crypto/caam_jr/Makefile\nindex 46d752af7..8b863b4af 100644\n--- a/drivers/crypto/caam_jr/Makefile\n+++ b/drivers/crypto/caam_jr/Makefile\n@@ -19,7 +19,10 @@ CFLAGS += -O3\n CFLAGS += $(WERROR_FLAGS)\n endif\n \n+CFLAGS += -I$(RTE_SDK)/drivers/bus/dpaa/include\n CFLAGS += -I$(RTE_SDK)/drivers/crypto/caam_jr\n+#sharing the hw flib headers from dpaa2_sec pmd\n+CFLAGS += -I$(RTE_SDK)/drivers/crypto/dpaa2_sec/\n CFLAGS += -I$(RTE_SDK)/lib/librte_eal/common/include\n CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal\n \n@@ -30,11 +33,14 @@ EXPORT_MAP := rte_pmd_caam_jr_version.map\n LIBABIVER := 1\n \n # library source files\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) += caam_jr_hw.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) += caam_jr_uio.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) += caam_jr.c\n # library dependencies\n \n LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n LDLIBS += -lrte_cryptodev\n+LDLIBS += -lrte_bus_dpaa\n LDLIBS += -lrte_bus_vdev\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/caam_jr/caam_jr.c b/drivers/crypto/caam_jr/caam_jr.c\nindex 68779cba5..9d5f5b79b 100644\n--- a/drivers/crypto/caam_jr/caam_jr.c\n+++ b/drivers/crypto/caam_jr/caam_jr.c\n@@ -16,13 +16,146 @@\n #include <rte_malloc.h>\n #include <rte_security_driver.h>\n #include <rte_hexdump.h>\n+#include <caam_jr_config.h>\n \n+/* RTA header files */\n+#include <hw/desc/common.h>\n+#include <of.h>\n+#include <caam_jr_hw_specific.h>\n+#include <caam_jr_pvt.h>\n #include <caam_jr_log.h>\n \n #define CRYPTODEV_NAME_CAAM_JR_PMD\tcrypto_caam_jr\n static uint8_t cryptodev_driver_id;\n int caam_jr_logtype;\n \n+enum rta_sec_era rta_sec_era;\n+\n+/* Lists the states possible for the SEC user space driver. */\n+enum sec_driver_state_e {\n+\tSEC_DRIVER_STATE_IDLE,\t\t/* Driver not initialized */\n+\tSEC_DRIVER_STATE_STARTED,\t/* Driver initialized and can be used*/\n+\tSEC_DRIVER_STATE_RELEASE,\t/* Driver release is in progress */\n+};\n+\n+/* Job rings used for communication with SEC HW */\n+static struct sec_job_ring_t g_job_rings[MAX_SEC_JOB_RINGS];\n+\n+/* The current state of SEC user space driver */\n+static enum sec_driver_state_e g_driver_state = SEC_DRIVER_STATE_IDLE;\n+\n+/* The number of job rings used by SEC user space driver */\n+static int g_job_rings_no;\n+static int g_job_rings_max;\n+\n+/* @brief Poll the HW for already processed jobs in the JR\n+ * and silently discard the available jobs or notify them to UA\n+ * with indicated error code.\n+ *\n+ * @param [in,out]  job_ring        The job ring to poll.\n+ * @param [in]  do_notify           Can be #TRUE or #FALSE. Indicates if\n+ *\t\t\t\t    descriptors are to be discarded\n+ *                                  or notified to UA with given error_code.\n+ * @param [out] notified_descs    Number of notified descriptors. Can be NULL\n+ *\t\t\t\t\tif do_notify is #FALSE\n+ */\n+static void hw_flush_job_ring(struct sec_job_ring_t *job_ring,\n+\t\t\t      uint32_t do_notify,\n+\t\t\t      uint32_t *notified_descs)\n+{\n+\tint32_t jobs_no_to_discard = 0;\n+\tint32_t discarded_descs_no = 0;\n+\n+\tCAAM_JR_DEBUG(\"Jr[%p] pi[%d] ci[%d].Flushing jr notify desc=[%d]\",\n+\t\tjob_ring, job_ring->pidx, job_ring->cidx, do_notify);\n+\n+\tjobs_no_to_discard = hw_get_no_finished_jobs(job_ring);\n+\n+\t/* Discard all jobs */\n+\tCAAM_JR_DEBUG(\"Jr[%p] pi[%d] ci[%d].Discarding %d descs\",\n+\t\t  job_ring, job_ring->pidx, job_ring->cidx,\n+\t\t  jobs_no_to_discard);\n+\n+\twhile (jobs_no_to_discard > discarded_descs_no) {\n+\t\t/* Get completed descriptor */\n+#if 0\n+\t\t/*TODO if we want to do something with desc*/\n+\t\t/* Since the memory is contigous, then P2V translation is a\n+\t\t * mere addition to the base descriptor physical address\n+\t\t */\n+\t\tcurrent_desc = job_ring->output_ring[job_ring->cidx].desc;\n+#endif\n+\n+\t\tdiscarded_descs_no++;\n+\t\t/* Now increment the consumer index for the current job ring,\n+\t\t * AFTER saving job in temporary location!\n+\t\t * Increment the consumer index for the current job ring\n+\t\t */\n+\t\tjob_ring->cidx = SEC_CIRCULAR_COUNTER(job_ring->cidx,\n+\t\t\t\t\t SEC_JOB_RING_SIZE);\n+\n+\t\thw_remove_entries(job_ring, 1);\n+\t}\n+\n+\tif (do_notify == true) {\n+\t\tASSERT(notified_descs != NULL);\n+\t\t*notified_descs = discarded_descs_no;\n+\t}\n+}\n+\n+\n+/* @brief Flush job rings of any processed descs.\n+ * The processed descs are silently dropped,\n+ * WITHOUT being notified to UA.\n+ */\n+static void close_job_ring(struct sec_job_ring_t *job_ring)\n+{\n+\tif (job_ring->irq_fd) {\n+\t\t/* Producer index is frozen. If consumer index is not equal\n+\t\t * with producer index, then we have descs to flush.\n+\t\t */\n+\t\twhile (job_ring->pidx != job_ring->cidx)\n+\t\t\thw_flush_job_ring(job_ring, false, NULL);\n+\n+\t\t/* free the uio job ring */\n+\t\tfree_job_ring(job_ring->irq_fd);\n+\t\tjob_ring->irq_fd = 0;\n+\t\tcaam_jr_dma_free(job_ring->input_ring);\n+\t\tcaam_jr_dma_free(job_ring->output_ring);\n+\n+\t\tg_job_rings_no--;\n+\n+\t}\n+}\n+\n+/** @brief Release the software and hardware resources tied to a job ring.\n+ * @param [in] job_ring The job ring\n+ *\n+ * @retval  0 for success\n+ * @retval  -1 for error\n+ */\n+static int shutdown_job_ring(struct sec_job_ring_t *job_ring)\n+{\n+\tint ret = 0;\n+\n+\tASSERT(job_ring != NULL);\n+\tret = hw_shutdown_job_ring(job_ring);\n+\tSEC_ASSERT(ret == 0, ret,\n+\t\t\"Failed to shutdown hardware job ring %p\",\n+\t\tjob_ring);\n+\n+\tif (job_ring->coalescing_en)\n+\t\thw_job_ring_disable_coalescing(job_ring);\n+\n+\tif (job_ring->jr_mode != SEC_NOTIFICATION_TYPE_POLL) {\n+\t\tret = caam_jr_disable_irqs(job_ring->irq_fd);\n+\t\tSEC_ASSERT(ret == 0, ret,\n+\t\t\"Failed to disable irqs for job ring %p\",\n+\t\tjob_ring);\n+\t}\n+\n+\treturn ret;\n+}\n \n /*\n  * @brief Release the resources used by the SEC user space driver.\n@@ -42,31 +175,195 @@ int caam_jr_logtype;\n static int\n caam_jr_dev_uninit(struct rte_cryptodev *dev)\n {\n+\tstruct sec_job_ring_t *internals;\n \n \tif (dev == NULL)\n \t\treturn -ENODEV;\n \n+\tinternals = dev->data->dev_private;\n+\trte_free(dev->security_ctx);\n+\n+\n+\t/* If any descriptors in flight , poll and wait\n+\t * until all descriptors are received and silently discarded.\n+\t */\n+\tif (internals) {\n+\t\tshutdown_job_ring(internals);\n+\t\tclose_job_ring(internals);\n+\t\trte_mempool_free(internals->ctx_pool);\n+\t}\n \n \tCAAM_JR_INFO(\"Closing DPAA_SEC device %s\", dev->data->name);\n \n+\t/* last caam jr instance) */\n+\tif (g_job_rings_no == 0)\n+\t\tg_driver_state = SEC_DRIVER_STATE_IDLE;\n \n-\treturn 0;\n+\treturn SEC_SUCCESS;\n }\n \n+/* @brief Initialize the software and hardware resources tied to a job ring.\n+ * @param [in] jr_mode;\t\tModel to be used by SEC Driver to receive\n+ *\t\t\t\tnotifications from SEC.  Can be either\n+ *\t\t\t\tof the three: #SEC_NOTIFICATION_TYPE_NAPI\n+ *\t\t\t\t#SEC_NOTIFICATION_TYPE_IRQ or\n+ *\t\t\t\t#SEC_NOTIFICATION_TYPE_POLL\n+ * @param [in] NAPI_mode\tThe NAPI work mode to configure a job ring at\n+ *\t\t\t\tstartup. Used only when #SEC_NOTIFICATION_TYPE\n+ *\t\t\t\tis set to #SEC_NOTIFICATION_TYPE_NAPI.\n+ * @param [in] irq_coalescing_timer This value determines the maximum\n+ *\t\t\t\t\tamount of time after processing a\n+ *\t\t\t\t\tdescriptor before raising an interrupt.\n+ * @param [in] irq_coalescing_count This value determines how many\n+ *\t\t\t\t\tdescriptors are completed before\n+ *\t\t\t\t\traising an interrupt.\n+ * @param [in] reg_base_addr,\tThe job ring base address register\n+ * @param [in] irq_id\t\tThe job ring interrupt identification number.\n+ * @retval  job_ring_handle for successful job ring configuration\n+ * @retval  NULL on error\n+ *\n+ */\n+static void *\n+init_job_ring(void *reg_base_addr, uint32_t irq_id)\n+{\n+\tstruct sec_job_ring_t *job_ring = NULL;\n+\tint i, ret = 0;\n+\tint jr_mode = SEC_NOTIFICATION_TYPE_POLL;\n+\tint napi_mode = 0;\n+\tint irq_coalescing_timer = 0;\n+\tint irq_coalescing_count = 0;\n+\n+\tfor (i = 0; i < MAX_SEC_JOB_RINGS; i++) {\n+\t\tif (g_job_rings[i].irq_fd == 0) {\n+\t\t\tjob_ring = &g_job_rings[i];\n+\t\t\tg_job_rings_no++;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (job_ring == NULL) {\n+\t\tCAAM_JR_ERR(\"No free job ring\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\tjob_ring->register_base_addr = reg_base_addr;\n+\tjob_ring->jr_mode = jr_mode;\n+\tjob_ring->napi_mode = 0;\n+\tjob_ring->irq_fd = irq_id;\n+\n+\t/* Allocate mem for input and output ring */\n+\n+\t/* Allocate memory for input ring */\n+\tjob_ring->input_ring = caam_jr_dma_mem_alloc(L1_CACHE_BYTES,\n+\t\t\t\tSEC_DMA_MEM_INPUT_RING_SIZE);\n+\tmemset(job_ring->input_ring, 0, SEC_DMA_MEM_INPUT_RING_SIZE);\n+\n+\t/* Allocate memory for output ring */\n+\tjob_ring->output_ring = caam_jr_dma_mem_alloc(L1_CACHE_BYTES,\n+\t\t\t\tSEC_DMA_MEM_OUTPUT_RING_SIZE);\n+\tmemset(job_ring->output_ring, 0, SEC_DMA_MEM_OUTPUT_RING_SIZE);\n+\n+\t/* Reset job ring in SEC hw and configure job ring registers */\n+\tret = hw_reset_job_ring(job_ring);\n+\tif (ret != 0) {\n+\t\tCAAM_JR_ERR(\"Failed to reset hardware job ring\");\n+\t\tgoto cleanup;\n+\t}\n+\n+\tif (jr_mode == SEC_NOTIFICATION_TYPE_NAPI) {\n+\t/* When SEC US driver works in NAPI mode, the UA can select\n+\t * if the driver starts with IRQs on or off.\n+\t */\n+\t\tif (napi_mode == SEC_STARTUP_INTERRUPT_MODE) {\n+\t\t\tCAAM_JR_INFO(\"Enabling DONE IRQ generationon job ring - %p\",\n+\t\t\t\tjob_ring);\n+\t\t\tret = caam_jr_enable_irqs(job_ring->irq_fd);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tCAAM_JR_ERR(\"Failed to enable irqs for job ring\");\n+\t\t\t\tgoto cleanup;\n+\t\t\t}\n+\t\t}\n+\t} else if (jr_mode == SEC_NOTIFICATION_TYPE_IRQ) {\n+\t/* When SEC US driver works in pure interrupt mode,\n+\t * IRQ's are always enabled.\n+\t */\n+\t\tCAAM_JR_INFO(\"Enabling DONE IRQ generation on job ring - %p\",\n+\t\t\t job_ring);\n+\t\tret = caam_jr_enable_irqs(job_ring->irq_fd);\n+\t\tif (ret != 0) {\n+\t\t\tCAAM_JR_ERR(\"Failed to enable irqs for job ring\");\n+\t\t\tgoto cleanup;\n+\t\t}\n+\t}\n+\tif (irq_coalescing_timer || irq_coalescing_count) {\n+\t\thw_job_ring_set_coalescing_param(job_ring,\n+\t\t\t irq_coalescing_timer,\n+\t\t\t irq_coalescing_count);\n+\n+\t\thw_job_ring_enable_coalescing(job_ring);\n+\t\tjob_ring->coalescing_en = 1;\n+\t}\n+\n+\tjob_ring->jr_state = SEC_JOB_RING_STATE_STARTED;\n+\tjob_ring->max_nb_queue_pairs = RTE_CAAM_MAX_NB_SEC_QPS;\n+\tjob_ring->max_nb_sessions = RTE_CAAM_JR_PMD_MAX_NB_SESSIONS;\n+\n+\treturn job_ring;\n+cleanup:\n+\tcaam_jr_dma_free(job_ring->output_ring);\n+\tcaam_jr_dma_free(job_ring->input_ring);\n+\treturn NULL;\n+}\n+\n+\n static int\n caam_jr_dev_init(const char *name,\n \t\t\t struct rte_vdev_device *vdev,\n \t\t\t struct rte_cryptodev_pmd_init_params *init_params)\n {\n \tstruct rte_cryptodev *dev;\n+\tstruct uio_job_ring *job_ring;\n+\tchar str[RTE_CRYPTODEV_NAME_MAX_LEN];\n \n \tPMD_INIT_FUNC_TRACE();\n \n+\t/* Validate driver state */\n+\tif (g_driver_state == SEC_DRIVER_STATE_IDLE) {\n+\t\tg_job_rings_max = sec_configure();\n+\t\tif (!g_job_rings_max) {\n+\t\t\tCAAM_JR_ERR(\"No job ring detected on UIO !!!!\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\t/* Update driver state */\n+\t\tg_driver_state = SEC_DRIVER_STATE_STARTED;\n+\t}\n+\n+\tif (g_job_rings_no >= g_job_rings_max) {\n+\t\tCAAM_JR_ERR(\"No more job rings available max=%d!!!!\",\n+\t\t\t\tg_job_rings_max);\n+\t\treturn -1;\n+\t}\n+\n+\tjob_ring = config_job_ring();\n+\tif (job_ring == NULL) {\n+\t\tCAAM_JR_ERR(\"failed to create job ring\");\n+\t\tgoto init_error;\n+\t}\n+\n+\tsnprintf(str, sizeof(str), \"caam_jr%d\", job_ring->jr_id);\n+\n \tdev = rte_cryptodev_pmd_create(name, &vdev->device, init_params);\n \tif (dev == NULL) {\n \t\tCAAM_JR_ERR(\"failed to create cryptodev vdev\");\n \t\tgoto cleanup;\n \t}\n+\t/*TODO free it during teardown*/\n+\tdev->data->dev_private = init_job_ring(job_ring->register_base_addr,\n+\t\t\t\t\t\tjob_ring->uio_fd);\n+\n+\tif (!dev->data->dev_private) {\n+\t\tCAAM_JR_ERR(\"Ring memory allocation failed\\n\");\n+\t\tgoto cleanup2;\n+\t}\n \n \tdev->driver_id = cryptodev_driver_id;\n \tdev->dev_ops = NULL;\n@@ -84,7 +381,12 @@ caam_jr_dev_init(const char *name,\n \n \treturn 0;\n \n+cleanup2:\n+\tcaam_jr_dev_uninit(dev);\n+\trte_cryptodev_pmd_release_device(dev);\n cleanup:\n+\tfree_job_ring(job_ring->uio_fd);\n+init_error:\n \tCAAM_JR_ERR(\"driver %s: cryptodev_caam_jr_create failed\",\n \t\t\tinit_params->name);\n \n@@ -97,7 +399,7 @@ cryptodev_caam_jr_probe(struct rte_vdev_device *vdev)\n {\n \tstruct rte_cryptodev_pmd_init_params init_params = {\n \t\t\"\",\n-\t\t128,\n+\t\tsizeof(struct sec_job_ring_t),\n \t\trte_socket_id(),\n \t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS\n \t};\n@@ -111,6 +413,29 @@ cryptodev_caam_jr_probe(struct rte_vdev_device *vdev)\n \tinput_args = rte_vdev_device_args(vdev);\n \trte_cryptodev_pmd_parse_input_args(&init_params, input_args);\n \n+\t/* if sec device version is not configured */\n+\tif (!rta_get_sec_era()) {\n+\t\tconst struct device_node *caam_node;\n+\n+\t\tfor_each_compatible_node(caam_node, NULL, \"fsl,sec-v4.0\") {\n+\t\t\tconst uint32_t *prop = of_get_property(caam_node,\n+\t\t\t\t\t\"fsl,sec-era\",\n+\t\t\t\t\tNULL);\n+\t\t\tif (prop) {\n+\t\t\t\trta_set_sec_era(\n+\t\t\t\t\tINTL_SEC_ERA(cpu_to_caam32(*prop)));\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t}\n+#ifdef RTE_LIBRTE_PMD_CAAM_JR_BE\n+\tif (rta_get_sec_era() > RTA_SEC_ERA_8) {\n+\t\tRTE_LOG(ERR, PMD,\n+\t\t\"CAAM is compiled in BE mode for device with sec era > 8???\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+#endif\n+\n \treturn caam_jr_dev_init(name, vdev, &init_params);\n }\n \ndiff --git a/drivers/crypto/caam_jr/caam_jr_config.h b/drivers/crypto/caam_jr/caam_jr_config.h\nnew file mode 100644\nindex 000000000..e7855cee6\n--- /dev/null\n+++ b/drivers/crypto/caam_jr/caam_jr_config.h\n@@ -0,0 +1,207 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2017-2018 NXP\n+ */\n+\n+#ifndef CAAM_JR_CONFIG_H\n+#define CAAM_JR_CONFIG_H\n+\n+#include <rte_byteorder.h>\n+\n+#ifdef RTE_LIBRTE_PMD_CAAM_JR_BE\n+#define CAAM_BYTE_ORDER __BIG_ENDIAN\n+#else\n+#define CAAM_BYTE_ORDER __LITTLE_ENDIAN\n+#endif\n+\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+#define CORE_BYTE_ORDER __BIG_ENDIAN\n+#else\n+#define CORE_BYTE_ORDER __LITTLE_ENDIAN\n+#endif\n+\n+typedef uint64_t\tdma_addr_t;\n+\n+#if CORE_BYTE_ORDER != CAAM_BYTE_ORDER\n+\n+#define cpu_to_caam64 rte_cpu_to_be_64\n+#define cpu_to_caam32 rte_cpu_to_be_32\n+#else\n+#define cpu_to_caam64\n+#define cpu_to_caam32\n+\n+#endif\n+\n+/*\n+ * SEC is configured to start work in polling mode,\n+ * when configured for NAPI notification style.\n+ */\n+#define SEC_STARTUP_POLLING_MODE     0\n+/*\n+ * SEC is configured to start work in interrupt mode,\n+ * when configured for NAPI notification style.\n+ */\n+#define SEC_STARTUP_INTERRUPT_MODE   1\n+\n+/*\n+ * SEC driver will use NAPI model to receive notifications\n+ * for processed packets from SEC engine hardware:\n+ * - IRQ for low traffic\n+ * - polling for high traffic.\n+ */\n+#define SEC_NOTIFICATION_TYPE_NAPI  0\n+/*\n+ * SEC driver will use ONLY interrupts to receive notifications\n+ * for processed packets from SEC engine hardware.\n+ */\n+#define SEC_NOTIFICATION_TYPE_IRQ   1\n+/*\n+ * SEC driver will use ONLY polling to receive notifications\n+ * for processed packets from SEC engine hardware.\n+ */\n+#define SEC_NOTIFICATION_TYPE_POLL  2\n+\n+/*\n+ * SEC USER SPACE DRIVER related configuration.\n+ */\n+\n+/*\n+ * Determines how SEC user space driver will receive notifications\n+ * for processed packets from SEC engine.\n+ * Valid values are: #SEC_NOTIFICATION_TYPE_POLL, #SEC_NOTIFICATION_TYPE_IRQ\n+ * and #SEC_NOTIFICATION_TYPE_NAPI.\n+ */\n+#define SEC_NOTIFICATION_TYPE   SEC_NOTIFICATION_TYPE_POLL\n+\n+/* Maximum number of job rings supported by SEC hardware */\n+#define MAX_SEC_JOB_RINGS         4\n+\n+/* Maximum number of QP per job ring */\n+#define RTE_CAAM_MAX_NB_SEC_QPS    1\n+\n+/*\n+ * Size of cryptographic context that is used directly in communicating\n+ * with SEC device. SEC device works only with physical addresses. This\n+ * is the maximum size for a SEC descriptor ( = 64 words).\n+ */\n+#define SEC_CRYPTO_DESCRIPTOR_SIZE  256\n+\n+/*\n+ * Size of job descriptor submitted to SEC device for each packet to\n+ * be processed.\n+ * Job descriptor contains 3 DMA address pointers:\n+ *\t- to shared descriptor, to input buffer and to output buffer.\n+ * The job descriptor contains other SEC specific commands as well:\n+ *\t- HEADER command, SEQ IN PTR command SEQ OUT PTR command and opaque data\n+ *      each measuring 4 bytes.\n+ * Job descriptor size, depending on physical address representation:\n+ *\t- 32 bit - size is 28 bytes - cacheline-aligned size is 64 bytes\n+ *\t- 36 bit - size is 40 bytes - cacheline-aligned size is 64 bytes\n+ * @note: Job descriptor must be cacheline-aligned to ensure efficient\n+ *\tmemory access.\n+ * @note: If other format is used for job descriptor, then the size must be\n+ *\trevised.\n+ */\n+#define SEC_JOB_DESCRIPTOR_SIZE     64\n+\n+/*\n+ * Size of one entry in the input ring of a job ring.\n+ * Input ring contains pointers to job descriptors.\n+ * The memory used for an input ring and output ring must be physically\n+ * contiguous.\n+ */\n+#define SEC_JOB_INPUT_RING_ENTRY_SIZE  sizeof(dma_addr_t)\n+\n+/*\n+ * Size of one entry in the output ring of a job ring.\n+ * Output ring entry is a pointer to a job descriptor followed by a 4 byte\n+ * status word.\n+ * The memory used for an input ring and output ring must be physically\n+ * contiguous.\n+ * @note If desired to use also the optional SEQ OUT indication in output ring\n+ * entries,\n+ * then 4 more bytes must be added to the size.\n+ */\n+#define SEC_JOB_OUTPUT_RING_ENTRY_SIZE  (SEC_JOB_INPUT_RING_ENTRY_SIZE + 4)\n+\n+/*\n+ * DMA memory required for an input ring of a job ring.\n+ */\n+#define SEC_DMA_MEM_INPUT_RING_SIZE     ((SEC_JOB_INPUT_RING_ENTRY_SIZE) * \\\n+\t\t\t\t\t(SEC_JOB_RING_SIZE))\n+\n+/*\n+ * DMA memory required for an output ring of a job ring.\n+ *  Required extra 4 byte for status word per each entry.\n+ */\n+#define SEC_DMA_MEM_OUTPUT_RING_SIZE    ((SEC_JOB_OUTPUT_RING_ENTRY_SIZE) * \\\n+\t\t\t\t\t(SEC_JOB_RING_SIZE))\n+\n+/* DMA memory required for a job ring, including both input and output rings. */\n+#define SEC_DMA_MEM_JOB_RING_SIZE       ((SEC_DMA_MEM_INPUT_RING_SIZE) + \\\n+\t\t\t\t\t(SEC_DMA_MEM_OUTPUT_RING_SIZE))\n+\n+/*\n+ * When calling sec_init() UA will provide an area of virtual memory\n+ *  of size #SEC_DMA_MEMORY_SIZE to be  used internally by the driver\n+ *  to allocate data (like SEC descriptors) that needs to be passed to\n+ *  SEC device in physical addressing and later on retrieved from SEC device.\n+ *  At initialization the UA provides specialized ptov/vtop functions/macros to\n+ *  translate addresses allocated from this memory area.\n+ */\n+#define SEC_DMA_MEMORY_SIZE          ((SEC_DMA_MEM_JOB_RING_SIZE) * \\\n+\t\t\t\t\t(MAX_SEC_JOB_RINGS))\n+\n+#define L1_CACHE_BYTES 64\n+\n+/* SEC JOB RING related configuration. */\n+\n+/*\n+ * Configure the size of the JOB RING.\n+ * The maximum size of the ring in hardware limited to 1024.\n+ * However the number of packets in flight in a time interval of 1ms can\n+ * be calculated from the traffic rate (Mbps) and packet size.\n+ * Here it was considered a packet size of 64 bytes.\n+ *\n+ * @note Round up to nearest power of 2 for optimized update\n+ * of producer/consumer indexes of each job ring\n+ */\n+#define SEC_JOB_RING_SIZE     512\n+\n+/*\n+ * Interrupt coalescing related configuration.\n+ * NOTE: SEC hardware enabled interrupt\n+ * coalescing is not supported on SEC version 3.1!\n+ * SEC version 4.4 has support for interrupt\n+ * coalescing.\n+ */\n+\n+#if SEC_NOTIFICATION_TYPE != SEC_NOTIFICATION_TYPE_POLL\n+\n+#define SEC_INT_COALESCING_ENABLE   1\n+/*\n+ * Interrupt Coalescing Descriptor Count Threshold.\n+ * While interrupt coalescing is enabled (ICEN=1), this value determines\n+ * how many Descriptors are completed before raising an interrupt.\n+ *\n+ * Valid values for this field are from 0 to 255.\n+ * Note that a value of 1 functionally defeats the advantages of interrupt\n+ * coalescing since the threshold value is reached each time that a\n+ * Job Descriptor is completed. A value of 0 is treated in the same\n+ * manner as a value of 1.\n+ */\n+#define SEC_INTERRUPT_COALESCING_DESCRIPTOR_COUNT_THRESH  10\n+\n+/*\n+ * Interrupt Coalescing Timer Threshold.\n+ * While interrupt coalescing is enabled (ICEN=1), this value determines the\n+ * maximum amount of time after processing a Descriptor before raising an\n+ * interrupt.\n+ * The threshold value is represented in units equal to 64 CAAM interface\n+ * clocks. Valid values for this field are from 1 to 65535.\n+ * A value of 0 results in behavior identical to that when interrupt\n+ * coalescing is disabled.\n+ */\n+#define SEC_INTERRUPT_COALESCING_TIMER_THRESH  100\n+#endif /* SEC_NOTIFICATION_TYPE_POLL */\n+\n+#endif /* CAAM_JR_CONFIG_H */\ndiff --git a/drivers/crypto/caam_jr/caam_jr_hw.c b/drivers/crypto/caam_jr/caam_jr_hw.c\nnew file mode 100644\nindex 000000000..5baac95f8\n--- /dev/null\n+++ b/drivers/crypto/caam_jr/caam_jr_hw.c\n@@ -0,0 +1,365 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2017-2018 NXP\n+ */\n+\n+#include <fcntl.h>\n+#include <unistd.h>\n+#include <inttypes.h>\n+#include <rte_common.h>\n+#include <rte_memory.h>\n+#include <rte_malloc.h>\n+#include <rte_crypto.h>\n+#include <rte_security.h>\n+#include <caam_jr_config.h>\n+\n+/* RTA header files */\n+#include <hw/desc/common.h>\n+#include <hw/desc/algo.h>\n+#include <hw/desc/ipsec.h>\n+\n+#include <caam_jr_hw_specific.h>\n+#include <caam_jr_pvt.h>\n+#include <caam_jr_log.h>\n+\n+/* Used to retry resetting a job ring in SEC hardware. */\n+#define SEC_TIMEOUT 100000\n+\n+/* @brief Process Jump Halt Condition related errors\n+ *\n+ * @param [in]  error_code        The error code in the descriptor status word\n+ */\n+static inline void hw_handle_jmp_halt_cond_err(union hw_error_code\n+\t\t\t\t\t\terror_code) {\n+\tCAAM_JR_DEBUG(\"JMP: %d, Descriptor Index: 0x%x, Condition: 0x%x\",\n+\t\t\terror_code.error_desc.jmp_halt_cond_src.jmp,\n+\t\t\terror_code.error_desc.jmp_halt_cond_src.desc_idx,\n+\t\t\terror_code.error_desc.jmp_halt_cond_src.cond);\n+\t(void)error_code;\n+}\n+\n+/* @brief Process DECO related errors\n+ *\n+ * @param [in]  error_code        The error code in the descriptor status word\n+ */\n+static inline void hw_handle_deco_err(union hw_error_code\n+\t\t\t\terror_code) {\n+\tCAAM_JR_DEBUG(\"JMP: %d, Descriptor Index: 0x%x\",\n+\t\t\terror_code.error_desc.deco_src.jmp,\n+\t\t\terror_code.error_desc.deco_src.desc_idx);\n+\n+\tswitch (error_code.error_desc.deco_src.desc_err) {\n+\tcase SEC_HW_ERR_DECO_HFN_THRESHOLD:\n+\t\tCAAM_JR_DEBUG(\" Warning: Descriptor completed normally,\"\n+\t\t\t\"but 3GPP HFN matches or exceeds the Threshold \");\n+\t\tbreak;\n+\tdefault:\n+\t\tCAAM_JR_DEBUG(\"Error 0x%04x not implemented\",\n+\t\t\t\terror_code.error_desc.deco_src.desc_err);\n+\t\tbreak;\n+\t}\n+}\n+\n+/* @brief Process  Jump Halt User Status related errors\n+ *\n+ * @param [in]  error_code        The error code in the descriptor status word\n+ */\n+static inline void hw_handle_jmp_halt_user_err(union hw_error_code\n+\t\t\t\t\t\terror_code __rte_unused)\n+{\n+\tCAAM_JR_DEBUG(\" Not implemented\");\n+}\n+\n+/* @brief Process CCB related errors\n+ *\n+ * @param [in]  error_code        The error code in the descriptor status word\n+ */\n+static inline void\n+hw_handle_ccb_err(union hw_error_code hw_error_code __rte_unused)\n+{\n+\tCAAM_JR_DEBUG(\" Not implemented\");\n+}\n+\n+/* @brief Process Job Ring related errors\n+ *\n+ * @param [in]  error_code        The error code in the descriptor status word\n+ */\n+static inline\n+void hw_handle_jr_err(union hw_error_code hw_error_code __rte_unused)\n+{\n+\tCAAM_JR_DEBUG(\" Not implemented\");\n+}\n+\n+int hw_reset_job_ring(struct sec_job_ring_t *job_ring)\n+{\n+\tint ret = 0;\n+\n+\tASSERT(job_ring->register_base_addr != NULL);\n+\n+\t/* First reset the job ring in hw */\n+\tret = hw_shutdown_job_ring(job_ring);\n+\tSEC_ASSERT(ret == 0, ret, \"Failed resetting job ring in hardware\");\n+\n+\t/* In order to have the HW JR in a workable state\n+\t * after a reset, I need to re-write the input\n+\t * queue size, input start address, output queue\n+\t * size and output start address\n+\t */\n+\t/* Write the JR input queue size to the HW register */\n+\thw_set_input_ring_size(job_ring, SEC_JOB_RING_SIZE);\n+\n+\t/* Write the JR output queue size to the HW register */\n+\thw_set_output_ring_size(job_ring, SEC_JOB_RING_SIZE);\n+\n+\t/* Write the JR input queue start address */\n+\thw_set_input_ring_start_addr(job_ring,\n+\t\t\tcaam_jr_dma_vtop(job_ring->input_ring));\n+\tCAAM_JR_DEBUG(\" Set input ring base address to : Virtual: 0x%\" PRIx64\n+\t\t      \",Physical: 0x%\" PRIx64 \", Read from HW: 0x%\" PRIx64,\n+\t\t      (uint64_t)(uintptr_t)job_ring->input_ring,\n+\t\t      caam_jr_dma_vtop(job_ring->input_ring),\n+\t\t      hw_get_inp_queue_base(job_ring));\n+\n+\t/* Write the JR output queue start address */\n+\thw_set_output_ring_start_addr(job_ring,\n+\t\t\tcaam_jr_dma_vtop(job_ring->output_ring));\n+\tCAAM_JR_DEBUG(\" Set output ring base address to: Virtual: 0x%\" PRIx64\n+\t\t      \",Physical: 0x%\" PRIx64 \", Read from HW: 0x%\" PRIx64,\n+\t\t      (uint64_t)(uintptr_t)job_ring->output_ring,\n+\t\t      caam_jr_dma_vtop(job_ring->output_ring),\n+\t\t      hw_get_out_queue_base(job_ring));\n+\treturn ret;\n+}\n+\n+int hw_shutdown_job_ring(struct sec_job_ring_t *job_ring)\n+{\n+\tunsigned int timeout = SEC_TIMEOUT;\n+\tuint32_t tmp = 0;\n+\tint usleep_interval = 10;\n+\n+\tif (job_ring->register_base_addr == NULL) {\n+\t\tCAAM_JR_ERR(\"Jr[%p] has reg base addr as NULL.driver not init\",\n+\t\t\tjob_ring);\n+\t\treturn 0;\n+\t}\n+\n+\tCAAM_JR_INFO(\"Resetting Job ring %p\", job_ring);\n+\n+\t/*\n+\t * Mask interrupts since we are going to poll\n+\t * for reset completion status\n+\t * Also, at POR, interrupts are ENABLED on a JR, thus\n+\t * this is the point where I can disable them without\n+\t * changing the code logic too much\n+\t */\n+\tcaam_jr_disable_irqs(job_ring->irq_fd);\n+\n+\t/* initiate flush (required prior to reset) */\n+\tSET_JR_REG(JRCR, job_ring, JR_REG_JRCR_VAL_RESET);\n+\n+\t/* dummy read */\n+\ttmp = GET_JR_REG(JRCR, job_ring);\n+\n+\tdo {\n+\t\ttmp = GET_JR_REG(JRINT, job_ring);\n+\t\tusleep(usleep_interval);\n+\t} while (((tmp & JRINT_ERR_HALT_MASK) ==\n+\t\t\tJRINT_ERR_HALT_INPROGRESS) && --timeout);\n+\n+\tCAAM_JR_INFO(\"JRINT is %x\", tmp);\n+\n+\tif ((tmp & JRINT_ERR_HALT_MASK) != JRINT_ERR_HALT_COMPLETE ||\n+\t\ttimeout == 0) {\n+\t\tCAAM_JR_ERR(\"0x%x, %d\", tmp, timeout);\n+\t\t/* unmask interrupts */\n+\t\tif (job_ring->jr_mode != SEC_NOTIFICATION_TYPE_POLL)\n+\t\t\tcaam_jr_enable_irqs(job_ring->irq_fd);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Initiate reset */\n+\ttimeout = SEC_TIMEOUT;\n+\tSET_JR_REG(JRCR, job_ring, JR_REG_JRCR_VAL_RESET);\n+\n+\tdo {\n+\t\ttmp = GET_JR_REG(JRCR, job_ring);\n+\t\tusleep(usleep_interval);\n+\t} while ((tmp & JR_REG_JRCR_VAL_RESET) && --timeout);\n+\n+\tCAAM_JR_DEBUG(\"JRCR is %x\", tmp);\n+\n+\tif (timeout == 0) {\n+\t\tCAAM_JR_ERR(\"Failed to reset hw job ring %p\", job_ring);\n+\t\t/* unmask interrupts */\n+\t\tif (job_ring->jr_mode != SEC_NOTIFICATION_TYPE_POLL)\n+\t\t\tcaam_jr_enable_irqs(job_ring->irq_fd);\n+\t\treturn -1;\n+\t}\n+\t/* unmask interrupts */\n+\tif (job_ring->jr_mode != SEC_NOTIFICATION_TYPE_POLL)\n+\t\tcaam_jr_enable_irqs(job_ring->irq_fd);\n+\treturn 0;\n+\n+}\n+\n+void hw_handle_job_ring_error(struct sec_job_ring_t *job_ring __rte_unused,\n+\t\t\tuint32_t error_code)\n+{\n+\tunion hw_error_code hw_err_code;\n+\n+\thw_err_code.error = error_code;\n+\n+\tswitch (hw_err_code.error_desc.value.ssrc) {\n+\tcase SEC_HW_ERR_SSRC_NO_SRC:\n+\t\tASSERT(hw_err_code.error_desc.no_status_src.res == 0);\n+\t\tCAAM_JR_ERR(\"No Status Source \");\n+\t\tbreak;\n+\tcase SEC_HW_ERR_SSRC_CCB_ERR:\n+\t\tCAAM_JR_ERR(\"CCB Status Source\");\n+\t\thw_handle_ccb_err(hw_err_code);\n+\t\tbreak;\n+\tcase SEC_HW_ERR_SSRC_JMP_HALT_U:\n+\t\tCAAM_JR_ERR(\"Jump Halt User Status Source\");\n+\t\thw_handle_jmp_halt_user_err(hw_err_code);\n+\t\tbreak;\n+\tcase SEC_HW_ERR_SSRC_DECO:\n+\t\tCAAM_JR_ERR(\"DECO Status Source\");\n+\t\thw_handle_deco_err(hw_err_code);\n+\t\tbreak;\n+\tcase SEC_HW_ERR_SSRC_JR:\n+\t\tCAAM_JR_ERR(\"Job Ring Status Source\");\n+\t\thw_handle_jr_err(hw_err_code);\n+\t\tbreak;\n+\tcase SEC_HW_ERR_SSRC_JMP_HALT_COND:\n+\t\tCAAM_JR_ERR(\"Jump Halt Condition Codes\");\n+\t\thw_handle_jmp_halt_cond_err(hw_err_code);\n+\t\tbreak;\n+\tdefault:\n+\t\tASSERT(0);\n+\t\tCAAM_JR_ERR(\"Unknown SSRC\");\n+\t\tbreak;\n+\t}\n+}\n+\n+void hw_job_ring_error_print(struct sec_job_ring_t *job_ring, int code)\n+{\n+\tswitch (code) {\n+\tcase JRINT_ERR_WRITE_STATUS:\n+\t\tCAAM_JR_ERR(\"Error writing status to Output Ring \");\n+\t\tbreak;\n+\tcase JRINT_ERR_BAD_INPUT_BASE:\n+\t\tCAAM_JR_ERR(\n+\t\t\"Bad Input Ring Base (%p) (not on a 4-byte boundary) \",\n+\t\t(void *)job_ring);\n+\t\tbreak;\n+\tcase JRINT_ERR_BAD_OUTPUT_BASE:\n+\t\tCAAM_JR_ERR(\n+\t\t\"Bad Output Ring Base (%p) (not on a 4-byte boundary) \",\n+\t\t(void *)job_ring);\n+\t\tbreak;\n+\tcase JRINT_ERR_WRITE_2_IRBA:\n+\t\tCAAM_JR_ERR(\n+\t\t\"Invalid write to Input Ring Base Address Register \");\n+\t\tbreak;\n+\tcase JRINT_ERR_WRITE_2_ORBA:\n+\t\tCAAM_JR_ERR(\n+\t\t\"Invalid write to Output Ring Base Address Register \");\n+\t\tbreak;\n+\tcase JRINT_ERR_RES_B4_HALT:\n+\t\tCAAM_JR_ERR(\n+\t\t\"Job Ring [%p] released before Job Ring is halted\",\n+\t\t(void *)job_ring);\n+\t\tbreak;\n+\tcase JRINT_ERR_REM_TOO_MANY:\n+\t\tCAAM_JR_ERR(\"Removed too many jobs from job ring [%p]\",\n+\t\t\t(void *)job_ring);\n+\t\tbreak;\n+\tcase JRINT_ERR_ADD_TOO_MANY:\n+\t\tCAAM_JR_ERR(\"Added too many jobs on job ring [%p]\", job_ring);\n+\t\tbreak;\n+\tdefault:\n+\t\tCAAM_JR_ERR(\" Unknown SEC JR Error :%d\",\n+\t\t\t\tcode);\n+\t\tbreak;\n+\t}\n+}\n+\n+int hw_job_ring_set_coalescing_param(struct sec_job_ring_t *job_ring,\n+\t\t\t\tuint16_t irq_coalescing_timer,\n+\t\t\t\tuint8_t irq_coalescing_count)\n+{\n+\tuint32_t reg_val = 0;\n+\n+\tASSERT(job_ring != NULL);\n+\n+\tif (job_ring->register_base_addr == NULL) {\n+\t\tCAAM_JR_ERR(\"Jr[%p] has reg base addr as NULL.driver not init\",\n+\t\t\tjob_ring);\n+\t\treturn -1;\n+\t}\n+\t/* Set descriptor count coalescing */\n+\treg_val |= (irq_coalescing_count << JR_REG_JRCFG_LO_ICDCT_SHIFT);\n+\n+\t/* Set coalescing timer value */\n+\treg_val |= (irq_coalescing_timer << JR_REG_JRCFG_LO_ICTT_SHIFT);\n+\n+\t/* Update parameters in HW */\n+\tSET_JR_REG_LO(JRCFG, job_ring, reg_val);\n+\n+\tCAAM_JR_DEBUG(\"Set coalescing params on jr %p timer:%d, desc count: %d\",\n+\t\t\tjob_ring, irq_coalescing_timer, irq_coalescing_timer);\n+\n+\treturn 0;\n+}\n+\n+int hw_job_ring_enable_coalescing(struct sec_job_ring_t *job_ring)\n+{\n+\tuint32_t reg_val = 0;\n+\n+\tASSERT(job_ring != NULL);\n+\tif (job_ring->register_base_addr == NULL) {\n+\t\tCAAM_JR_ERR(\"Jr[%p] has reg base addr as NULL.driver not init\",\n+\t\t\tjob_ring);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Get the current value of the register */\n+\treg_val = GET_JR_REG_LO(JRCFG, job_ring);\n+\n+\t/* Enable coalescing */\n+\treg_val |= JR_REG_JRCFG_LO_ICEN_EN;\n+\n+\t/* Write in hw */\n+\tSET_JR_REG_LO(JRCFG, job_ring, reg_val);\n+\n+\tCAAM_JR_DEBUG(\"Enabled coalescing on jr %p \",\n+\t\t\tjob_ring);\n+\n+\treturn 0;\n+}\n+\n+int hw_job_ring_disable_coalescing(struct sec_job_ring_t *job_ring)\n+{\n+\tuint32_t reg_val = 0;\n+\n+\tASSERT(job_ring != NULL);\n+\n+\tif (job_ring->register_base_addr == NULL) {\n+\t\tCAAM_JR_ERR(\"Jr[%p] has reg base addr as NULL.driver not init\",\n+\t\t\tjob_ring);\n+\t\treturn -1;\n+\t}\n+\n+\t/* Get the current value of the register */\n+\treg_val = GET_JR_REG_LO(JRCFG, job_ring);\n+\n+\t/* Disable coalescing */\n+\treg_val &= ~JR_REG_JRCFG_LO_ICEN_EN;\n+\n+\t/* Write in hw */\n+\tSET_JR_REG_LO(JRCFG, job_ring, reg_val);\n+\n+\tCAAM_JR_DEBUG(\"Disabled coalescing on jr %p \", job_ring);\n+\n+\treturn 0;\n+\n+}\ndiff --git a/drivers/crypto/caam_jr/caam_jr_hw_specific.h b/drivers/crypto/caam_jr/caam_jr_hw_specific.h\nnew file mode 100644\nindex 000000000..7c8909d2b\n--- /dev/null\n+++ b/drivers/crypto/caam_jr/caam_jr_hw_specific.h\n@@ -0,0 +1,503 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2017 NXP\n+ */\n+\n+#ifndef CAAM_JR_HW_SPECIFIC_H\n+#define CAAM_JR_HW_SPECIFIC_H\n+\n+#include <caam_jr_config.h>\n+\n+/*\n+ * Offset to the registers of a job ring.\n+ * Is different for each job ring.\n+ */\n+#define CHAN_BASE(jr)   ((size_t)(jr)->register_base_addr)\n+\n+#ifndef unlikely\n+#define unlikely(x)     __builtin_expect(!!(x), 0)\n+#endif\n+\n+#define SEC_JOB_RING_IS_FULL(pi, ci, ring_max_size, ring_threshold) \\\n+\t\t((((pi) + 1 + ((ring_max_size) - (ring_threshold))) & \\\n+\t\t  (ring_max_size - 1))  == ((ci)))\n+\n+#define SEC_CIRCULAR_COUNTER(x, max)   (((x) + 1) & (max - 1))\n+\n+/*\n+ * Assert that cond is true. If !cond is true, display str and the vararg list\n+ * in a printf-like syntax. also, if !cond is true, return altRet.\n+ *\n+ * \\param cond          A boolean expression to be asserted true\n+ * \\param altRet        The value to be returned if cond doesn't hold true\n+ * \\param str           A quoted char string\n+ *\n+ * E.g.:\n+ *      SEC_ASSERT(ret > 0, 0, \"ERROR initializing app: code = %d\\n\", ret);\n+ */\n+#define SEC_ASSERT(cond, altRet, ...) {\\\n+\tif (unlikely(!(cond))) {\\\n+\t\tCAAM_JR_ERR(__VA_ARGS__); \\\n+\t\t\treturn altRet; \\\n+\t} \\\n+}\n+\n+#define SEC_DP_ASSERT(cond, altRet, ...) {\\\n+\tif (unlikely(!(cond))) {\\\n+\t\tCAAM_JR_DP_ERR(__VA_ARGS__); \\\n+\t\t\treturn altRet; \\\n+\t} \\\n+}\n+\n+#define ASSERT(x)\n+\n+/*\n+ * Constants representing various job ring registers\n+ */\n+#if CAAM_BYTE_ORDER == __BIG_ENDIAN\n+#define JR_REG_IRBA_OFFSET\t\t0x0000\n+#define JR_REG_IRBA_OFFSET_LO\t\t0x0004\n+#else\n+#define JR_REG_IRBA_OFFSET\t\t0x0004\n+#define JR_REG_IRBA_OFFSET_LO\t\t0x0000\n+#endif\n+\n+#define JR_REG_IRSR_OFFSET\t\t0x000C\n+#define JR_REG_IRSA_OFFSET\t\t0x0014\n+#define JR_REG_IRJA_OFFSET\t\t0x001C\n+\n+#if CAAM_BYTE_ORDER == __BIG_ENDIAN\n+#define JR_REG_ORBA_OFFSET\t\t0x0020\n+#define JR_REG_ORBA_OFFSET_LO\t\t0x0024\n+#else\n+#define JR_REG_ORBA_OFFSET\t\t0x0024\n+#define JR_REG_ORBA_OFFSET_LO\t\t0x0020\n+#endif\n+\n+#define JR_REG_ORSR_OFFSET\t\t0x002C\n+#define JR_REG_ORJR_OFFSET\t\t0x0034\n+#define JR_REG_ORSFR_OFFSET\t\t0x003C\n+#define JR_REG_JROSR_OFFSET\t\t0x0044\n+#define JR_REG_JRINT_OFFSET\t\t0x004C\n+\n+#define JR_REG_JRCFG_OFFSET\t\t0x0050\n+#define JR_REG_JRCFG_OFFSET_LO\t\t0x0054\n+\n+#define JR_REG_IRRI_OFFSET\t\t0x005C\n+#define JR_REG_ORWI_OFFSET\t\t0x0064\n+#define JR_REG_JRCR_OFFSET\t\t0x006C\n+\n+/*\n+ * Constants for error handling on job ring\n+ */\n+#define JR_REG_JRINT_ERR_TYPE_SHIFT\t8\n+#define JR_REG_JRINT_ERR_ORWI_SHIFT\t16\n+#define JR_REG_JRINIT_JRE_SHIFT\t\t1\n+\n+#define JRINT_JRE\t\t\t(1 << JR_REG_JRINIT_JRE_SHIFT)\n+#define JRINT_ERR_WRITE_STATUS\t\t(1 << JR_REG_JRINT_ERR_TYPE_SHIFT)\n+#define JRINT_ERR_BAD_INPUT_BASE\t(3 << JR_REG_JRINT_ERR_TYPE_SHIFT)\n+#define JRINT_ERR_BAD_OUTPUT_BASE\t(4 << JR_REG_JRINT_ERR_TYPE_SHIFT)\n+#define JRINT_ERR_WRITE_2_IRBA\t\t(5 << JR_REG_JRINT_ERR_TYPE_SHIFT)\n+#define JRINT_ERR_WRITE_2_ORBA\t\t(6 << JR_REG_JRINT_ERR_TYPE_SHIFT)\n+#define JRINT_ERR_RES_B4_HALT\t\t(7 << JR_REG_JRINT_ERR_TYPE_SHIFT)\n+#define JRINT_ERR_REM_TOO_MANY\t\t(8 << JR_REG_JRINT_ERR_TYPE_SHIFT)\n+#define JRINT_ERR_ADD_TOO_MANY\t\t(9 << JR_REG_JRINT_ERR_TYPE_SHIFT)\n+#define JRINT_ERR_HALT_MASK\t\t0x0C\n+#define JRINT_ERR_HALT_INPROGRESS\t0x04\n+#define JRINT_ERR_HALT_COMPLETE\t\t0x08\n+\n+#define JR_REG_JRCR_VAL_RESET\t\t0x00000001\n+\n+#define JR_REG_JRCFG_LO_ICTT_SHIFT\t0x10\n+#define JR_REG_JRCFG_LO_ICDCT_SHIFT\t0x08\n+#define JR_REG_JRCFG_LO_ICEN_EN\t\t0x02\n+\n+/*\n+ * Constants for Descriptor Processing errors\n+ */\n+#define SEC_HW_ERR_SSRC_NO_SRC\t\t0x00\n+#define SEC_HW_ERR_SSRC_CCB_ERR\t\t0x02\n+#define SEC_HW_ERR_SSRC_JMP_HALT_U\t0x03\n+#define SEC_HW_ERR_SSRC_DECO\t\t0x04\n+#define SEC_HW_ERR_SSRC_JR\t\t0x06\n+#define SEC_HW_ERR_SSRC_JMP_HALT_COND   0x07\n+\n+#define SEC_HW_ERR_DECO_HFN_THRESHOLD   0xF1\n+#define SEC_HW_ERR_CCB_ICV_CHECK_FAIL   0x0A\n+\n+/*\n+ * Constants for descriptors\n+ */\n+/* Return higher 32 bits of physical address */\n+#define PHYS_ADDR_HI(phys_addr) \\\n+\t    (uint32_t)(((uint64_t)phys_addr) >> 32)\n+\n+/* Return lower 32 bits of physical address */\n+#define PHYS_ADDR_LO(phys_addr) \\\n+\t    (uint32_t)(((uint64_t)phys_addr) & 0xFFFFFFFF)\n+\n+/*\n+ * Macros for extracting error codes for the job ring\n+ */\n+#define JR_REG_JRINT_ERR_TYPE_EXTRACT(value)      ((value) & 0x00000F00)\n+#define JR_REG_JRINT_ERR_ORWI_EXTRACT(value)     \\\n+\t(((value) & 0x3FFF0000) >> JR_REG_JRINT_ERR_ORWI_SHIFT)\n+#define JR_REG_JRINT_JRE_EXTRACT(value)\t   ((value) & JRINT_JRE)\n+\n+/*\n+ * Macros for managing the job ring\n+ */\n+/* Read pointer to job ring input ring start address */\n+#if defined(RTE_ARCH_ARM64)\n+#define hw_get_inp_queue_base(jr) ((((dma_addr_t)GET_JR_REG(IRBA, (jr))) << 32) | \\\n+\t\t\t\t\t(GET_JR_REG_LO(IRBA, (jr))))\n+\n+/* Read pointer to job ring output ring start address */\n+#define hw_get_out_queue_base(jr)   (((dma_addr_t)(GET_JR_REG(ORBA, (jr))) << 32) | \\\n+\t\t\t\t\t(GET_JR_REG_LO(ORBA, (jr))))\n+#else\n+#define hw_get_inp_queue_base(jr)   ((dma_addr_t)(GET_JR_REG_LO(IRBA, (jr))))\n+\n+#define hw_get_out_queue_base(jr)   ((dma_addr_t)(GET_JR_REG_LO(ORBA, (jr))))\n+#endif\n+\n+/*\n+ * IRJA - Input Ring Jobs Added Register shows\n+ * how many new jobs were added to the Input Ring.\n+ */\n+#define hw_enqueue_desc_on_job_ring(job_ring) SET_JR_REG(IRJA, (job_ring), 1)\n+\n+#define hw_set_input_ring_size(job_ring, size) SET_JR_REG(IRSR, job_ring, (size))\n+\n+#define hw_set_output_ring_size(job_ring, size) SET_JR_REG(ORSR, job_ring, (size))\n+\n+#if defined(RTE_ARCH_ARM64)\n+#define hw_set_input_ring_start_addr(job_ring, start_addr)\t\\\n+{\t\t\t\t\t\t\t\t\\\n+\tSET_JR_REG(IRBA, job_ring, PHYS_ADDR_HI(start_addr));\t\\\n+\tSET_JR_REG_LO(IRBA, job_ring, PHYS_ADDR_LO(start_addr));\\\n+}\n+\n+#define hw_set_output_ring_start_addr(job_ring, start_addr) \\\n+{\t\t\t\t\t\t\t\t\\\n+\tSET_JR_REG(ORBA, job_ring, PHYS_ADDR_HI(start_addr));\t\\\n+\tSET_JR_REG_LO(ORBA, job_ring, PHYS_ADDR_LO(start_addr));\\\n+}\n+\n+#else\n+#define hw_set_input_ring_start_addr(job_ring, start_addr)\t\\\n+{\t\t\t\t\t\t\t\t\\\n+\tSET_JR_REG(IRBA, job_ring, 0);\t\\\n+\tSET_JR_REG_LO(IRBA, job_ring, PHYS_ADDR_LO(start_addr));\\\n+}\n+\n+#define hw_set_output_ring_start_addr(job_ring, start_addr) \\\n+{\t\t\t\t\t\t\t\t\\\n+\tSET_JR_REG(ORBA, job_ring, 0);\t\\\n+\tSET_JR_REG_LO(ORBA, job_ring, PHYS_ADDR_LO(start_addr));\\\n+}\n+#endif\n+\n+/* ORJR - Output Ring Jobs Removed Register shows how many jobs were\n+ * removed from the Output Ring for processing by software. This is done after\n+ * the software has processed the entries.\n+ */\n+#define hw_remove_entries(jr, no_entries) SET_JR_REG(ORJR, (jr), (no_entries))\n+\n+/* IRSA - Input Ring Slots Available register holds the number of entries in\n+ * the Job Ring's input ring. Once a job is enqueued, the value returned is\n+ * decremented by the hardware by the number of jobs enqueued.\n+ */\n+#define hw_get_available_slots(jr)\t\tGET_JR_REG(IRSA, jr)\n+\n+/* ORSFR - Output Ring Slots Full register holds the number of jobs which were\n+ * processed by the SEC and can be retrieved by the software. Once a job has\n+ * been processed by software, the user will call hw_remove_one_entry in order\n+ * to notify the SEC that the entry was processed.\n+ */\n+#define hw_get_no_finished_jobs(jr)\t\tGET_JR_REG(ORSFR, jr)\n+\n+/*\n+ * Macros for manipulating JR registers\n+ */\n+#if CORE_BYTE_ORDER == CAAM_BYTE_ORDER\n+#define sec_read_32(addr)\t(*(volatile unsigned int *)(addr))\n+#define sec_write_32(addr, val)\t(*(volatile unsigned int *)(addr) = (val))\n+\n+#else\n+#define sec_read_32(addr)\trte_bswap32((*(volatile unsigned int *)(addr)))\n+#define sec_write_32(addr, val) \\\n+\t\t\t(*(volatile unsigned int *)(addr) = rte_bswap32(val))\n+#endif\n+\n+#if CAAM_BYTE_ORDER == __LITTLE_ENDIAN\n+#define sec_read_64(addr)\t(((u64)sec_read_32((u32 *)(addr) + 1) << 32) | \\\n+\t\t\t\t(sec_read_32((u32 *)(addr))))\n+\n+#define sec_write_64(addr, val) {\t\t\t\t\\\n+\tsec_write_32((u32 *)(addr) + 1, (u32)((val) >> 32));\t\\\n+\tsec_write_32((u32 *)(addr), (u32)(val));\t\t\\\n+}\n+#else /* CAAM_BYTE_ORDER == __BIG_ENDIAN */\n+#define sec_read_64(addr)\t(((u64)sec_read_32((u32 *)(addr)) << 32) | \\\n+\t\t\t\t(sec_read_32((u32 *)(addr) + 1)))\n+\n+#define sec_write_64(addr, val) {\t\t\t\t\\\n+\tsec_write_32((u32 *)(addr), (u32)((val) >> 32));\t\\\n+\tsec_write_32((u32 *)(addr) + 1, (u32)(val));\t\t\\\n+}\n+#endif\n+\n+#if defined(RTE_ARCH_ARM64)\n+#define sec_read_addr(a)\tsec_read_64((a))\n+#define sec_write_addr(a, v)\tsec_write_64((a), (v))\n+#else\n+#define sec_read_addr(a)\tsec_read_32((a))\n+#define sec_write_addr(a, v)\tsec_write_32((a), (v))\n+#endif\n+\n+#define JR_REG(name, jr)\t(CHAN_BASE(jr) + JR_REG_##name##_OFFSET)\n+#define JR_REG_LO(name, jr)\t(CHAN_BASE(jr) + JR_REG_##name##_OFFSET_LO)\n+\n+#define GET_JR_REG(name, jr)\t(sec_read_32(JR_REG(name, (jr))))\n+#define GET_JR_REG_LO(name, jr)\t(sec_read_32(JR_REG_LO(name, (jr))))\n+\n+#define SET_JR_REG(name, jr, value) \\\n+\t\t\t\t(sec_write_32(JR_REG(name, (jr)), value))\n+#define SET_JR_REG_LO(name, jr, value) \\\n+\t\t\t\t(sec_write_32(JR_REG_LO(name, (jr)), value))\n+\n+/* Lists the possible states for a job ring. */\n+typedef enum sec_job_ring_state_e {\n+\tSEC_JOB_RING_STATE_STARTED,\t/* Job ring is initialized */\n+\tSEC_JOB_RING_STATE_RESET,\t/* Job ring reset is in progress */\n+} sec_job_ring_state_t;\n+\n+/* code or cmd block to caam */\n+struct sec_cdb {\n+\tstruct {\n+\t\tunion {\n+\t\t\tuint32_t word;\n+\t\t\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\t\t\tuint16_t rsvd63_48;\n+\t\t\t\tunsigned int rsvd47_39:9;\n+\t\t\t\tunsigned int idlen:7;\n+#else\n+\t\t\t\tunsigned int idlen:7;\n+\t\t\t\tunsigned int rsvd47_39:9;\n+\t\t\t\tuint16_t rsvd63_48;\n+#endif\n+\t\t\t} field;\n+\t\t} __rte_packed hi;\n+\n+\t\tunion {\n+\t\t\tuint32_t word;\n+\t\t\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\t\t\tunsigned int rsvd31_30:2;\n+\t\t\t\tunsigned int fsgt:1;\n+\t\t\t\tunsigned int lng:1;\n+\t\t\t\tunsigned int offset:2;\n+\t\t\t\tunsigned int abs:1;\n+\t\t\t\tunsigned int add_buf:1;\n+\t\t\t\tuint8_t pool_id;\n+\t\t\t\tuint16_t pool_buffer_size;\n+#else\n+\t\t\t\tuint16_t pool_buffer_size;\n+\t\t\t\tuint8_t pool_id;\n+\t\t\t\tunsigned int add_buf:1;\n+\t\t\t\tunsigned int abs:1;\n+\t\t\t\tunsigned int offset:2;\n+\t\t\t\tunsigned int lng:1;\n+\t\t\t\tunsigned int fsgt:1;\n+\t\t\t\tunsigned int rsvd31_30:2;\n+#endif\n+\t\t\t} field;\n+\t\t} __rte_packed lo;\n+\t} __rte_packed sh_hdr;\n+\n+\tuint32_t sh_desc[SEC_JOB_DESCRIPTOR_SIZE];\n+};\n+\n+struct caam_jr_qp {\n+\tstruct sec_job_ring_t *ring;\n+\tuint64_t rx_pkts;\n+\tuint64_t rx_errs;\n+\tuint64_t rx_poll_err;\n+\tuint64_t tx_pkts;\n+\tuint64_t tx_errs;\n+\tuint64_t tx_ring_full;\n+};\n+\n+struct sec_job_ring_t {\n+\t/* TODO: Add wrapper macro to make it obvious this is the consumer index\n+\t * on the output ring\n+\t */\n+\tuint32_t cidx;\t\t/* Consumer index for job ring (jobs array).\n+\t\t\t\t * @note: cidx and pidx are accessed from\n+\t\t\t\t * different threads. Place the cidx and pidx\n+\t\t\t\t * inside the structure so that they lay on\n+\t\t\t\t * different cachelines, to avoid false sharing\n+\t\t\t\t * between threads when the threads run on\n+\t\t\t\t * different cores!\n+\t\t\t\t */\n+\t/* TODO: Add wrapper macro to make it obvious this is the producer index\n+\t * on the input ring\n+\t */\n+\tuint32_t pidx;\t\t/* Producer index for job ring (jobs array) */\n+\n+\tphys_addr_t *input_ring;/* Ring of output descriptors received from SEC.\n+\t\t\t\t * Size of array is power of 2 to allow fast\n+\t\t\t\t * update of producer/consumer indexes with\n+\t\t\t\t * bitwise operations.\n+\t\t\t\t */\n+\n+\tstruct sec_outring_entry *output_ring;\n+\t\t\t\t/* Ring of output descriptors received from SEC.\n+\t\t\t\t * Size of array is power of 2 to allow fast\n+\t\t\t\t * update of producer/consumer indexes with\n+\t\t\t\t * bitwise operations.\n+\t\t\t\t */\n+\n+\tuint32_t irq_fd;\t/* The file descriptor used for polling from\n+\t\t\t\t * user space for interrupts notifications\n+\t\t\t\t */\n+\tuint32_t jr_mode;\t/* Model used by SEC Driver to receive\n+\t\t\t\t * notifications from SEC.  Can be either\n+\t\t\t\t * of the three: #SEC_NOTIFICATION_TYPE_NAPI\n+\t\t\t\t * #SEC_NOTIFICATION_TYPE_IRQ or\n+\t\t\t\t * #SEC_NOTIFICATION_TYPE_POLL\n+\t\t\t\t */\n+\tuint32_t napi_mode;\t/* Job ring mode if NAPI mode is chosen\n+\t\t\t\t * Used only when jr_mode is set to\n+\t\t\t\t * #SEC_NOTIFICATION_TYPE_NAPI\n+\t\t\t\t */\n+\tvoid *register_base_addr;\t/* Base address for SEC's\n+\t\t\t\t\t * register memory for this job ring.\n+\t\t\t\t\t */\n+\tuint8_t coalescing_en;\t\t/* notifies if coelescing is\n+\t\t\t\t\t * enabled for the job ring\n+\t\t\t\t\t */\n+\tsec_job_ring_state_t jr_state;\t/* The state of this job ring */\n+\n+\tstruct rte_mempool *ctx_pool;   /* per dev mempool for caam_jr_op_ctx */\n+\tunsigned int max_nb_queue_pairs;\n+\tunsigned int max_nb_sessions;\n+\tstruct caam_jr_qp qps[RTE_CAAM_MAX_NB_SEC_QPS]; /* i/o queue for sec */\n+};\n+\n+/* Union describing the possible error codes that\n+ * can be set in the descriptor status word\n+ */\n+union hw_error_code {\n+\tuint32_t error;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint32_t ssrc:4;\n+\t\t\tuint32_t ssed_val:28;\n+\t\t} __rte_packed value;\n+\t\tstruct {\n+\t\t\tuint32_t ssrc:4;\n+\t\t\tuint32_t res:28;\n+\t\t} __rte_packed no_status_src;\n+\t\tstruct {\n+\t\t\tuint32_t ssrc:4;\n+\t\t\tuint32_t jmp:1;\n+\t\t\tuint32_t res:11;\n+\t\t\tuint32_t desc_idx:8;\n+\t\t\tuint32_t cha_id:4;\n+\t\t\tuint32_t err_id:4;\n+\t\t} __rte_packed ccb_status_src;\n+\t\tstruct {\n+\t\t\tuint32_t ssrc:4;\n+\t\t\tuint32_t jmp:1;\n+\t\t\tuint32_t res:11;\n+\t\t\tuint32_t desc_idx:8;\n+\t\t\tuint32_t offset:8;\n+\t\t} __rte_packed jmp_halt_user_src;\n+\t\tstruct {\n+\t\t\tuint32_t ssrc:4;\n+\t\t\tuint32_t jmp:1;\n+\t\t\tuint32_t res:11;\n+\t\t\tuint32_t desc_idx:8;\n+\t\t\tuint32_t desc_err:8;\n+\t\t} __rte_packed deco_src;\n+\t\tstruct {\n+\t\t\tuint32_t ssrc:4;\n+\t\t\tuint32_t res:17;\n+\t\t\tuint32_t naddr:3;\n+\t\t\tuint32_t desc_err:8;\n+\t\t} __rte_packed jr_src;\n+\t\tstruct {\n+\t\t\tuint32_t ssrc:4;\n+\t\t\tuint32_t jmp:1;\n+\t\t\tuint32_t res:11;\n+\t\t\tuint32_t desc_idx:8;\n+\t\t\tuint32_t cond:8;\n+\t\t} __rte_packed jmp_halt_cond_src;\n+\t} __rte_packed error_desc;\n+} __rte_packed;\n+\n+/* @brief Initialize a job ring/channel in SEC device.\n+ * Write configuration register/s to properly initialize a job ring.\n+ *\n+ * @param [in] job_ring     The job ring\n+ *\n+ * @retval 0 for success\n+ * @retval other for error\n+ */\n+int hw_reset_job_ring(struct sec_job_ring_t *job_ring);\n+\n+/* @brief Reset a job ring/channel in SEC device.\n+ * Write configuration register/s to reset a job ring.\n+ *\n+ * @param [in] job_ring     The job ring\n+ *\n+ * @retval 0 for success\n+ * @retval -1 in case job ring reset failed\n+ */\n+int hw_shutdown_job_ring(struct sec_job_ring_t *job_ring);\n+\n+/* @brief Handle a job ring/channel error in SEC device.\n+ * Identify the error type and clear error bits if required.\n+ *\n+ * @param [in]  job_ring\tThe job ring\n+ * @param [in]  sec_error_code  The job ring's error code\n+ */\n+void hw_handle_job_ring_error(struct sec_job_ring_t *job_ring,\n+\t\t\t\tuint32_t sec_error_code);\n+\n+/* @brief Handle a job ring error in the device.\n+ * Identify the error type and printout a explanatory\n+ * messages.\n+ *\n+ * @param [in]  job_ring\tThe job ring\n+ *\n+ */\n+void hw_job_ring_error_print(struct sec_job_ring_t *job_ring, int code);\n+\n+/* @brief Set interrupt coalescing parameters on the Job Ring.\n+ * @param [in]  job_ring\t\tThe job ring\n+ * @param [in]  irq_coalesing_timer     Interrupt coalescing timer threshold.\n+ *\t\t\t\t\tThis value determines the maximum\n+ *\t\t\t\t\tamount of time after processing a\n+ *\t\t\t\t\tdescriptor before raising an interrupt.\n+ * @param [in]  irq_coalescing_count    Interrupt coalescing descriptor count\n+ *\t\t\t\t\tthreshold.\n+ */\n+int hw_job_ring_set_coalescing_param(struct sec_job_ring_t *job_ring,\n+\t\t\t\tuint16_t irq_coalescing_timer,\n+\t\t\t\tuint8_t irq_coalescing_count);\n+\n+/* @brief Enable interrupt coalescing on a job ring\n+ * @param [in]  job_ring\t\tThe job ring\n+ */\n+int hw_job_ring_enable_coalescing(struct sec_job_ring_t *job_ring);\n+\n+/* @brief Disable interrupt coalescing on a job ring\n+ * @param [in]  job_ring\t\tThe job ring\n+ */\n+int hw_job_ring_disable_coalescing(struct sec_job_ring_t *job_ring);\n+\n+#endif /* CAAM_JR_HW_SPECIFIC_H */\ndiff --git a/drivers/crypto/caam_jr/caam_jr_pvt.h b/drivers/crypto/caam_jr/caam_jr_pvt.h\nnew file mode 100644\nindex 000000000..cc0aa65f1\n--- /dev/null\n+++ b/drivers/crypto/caam_jr/caam_jr_pvt.h\n@@ -0,0 +1,285 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2017-2018 NXP\n+ */\n+\n+#ifndef CAAM_JR_PVT_H\n+#define CAAM_JR_PVT_H\n+\n+/* NXP CAAM JR PMD device name */\n+\n+#define CAAM_JR_ALG_UNSUPPORT\t(-1)\n+\n+/* Minimum job descriptor consists of a oneword job descriptor HEADER and\n+ * a pointer to the shared descriptor.\n+ */\n+#define MIN_JOB_DESC_SIZE\t(CAAM_CMD_SZ + CAAM_PTR_SZ)\n+#define CAAM_JOB_DESC_SIZE\t13\n+\n+/* CTX_POOL_NUM_BUFS is set as per the ipsec-secgw application */\n+#define CTX_POOL_NUM_BUFS\t32000\n+#define CTX_POOL_CACHE_SIZE\t512\n+\n+#define DIR_ENC                 1\n+#define DIR_DEC                 0\n+\n+#define JR_MAX_NB_MAX_DIGEST\t32\n+\n+#define RTE_CAAM_JR_PMD_MAX_NB_SESSIONS 2048\n+\n+\n+/* Return codes for SEC user space driver APIs */\n+enum sec_return_code_e {\n+\tSEC_SUCCESS = 0,\t       /* Operation executed successfully.*/\n+\tSEC_INVALID_INPUT_PARAM,       /* API received an invalid input\n+\t\t\t\t\t* parameter\n+\t\t\t\t\t*/\n+\tSEC_OUT_OF_MEMORY,\t       /* Memory allocation failed. */\n+\tSEC_DESCRIPTOR_IN_FLIGHT,      /* API function indicates there are\n+\t\t\t\t\t* descriptors in flight\n+\t\t\t\t\t* for SEC to process.\n+\t\t\t\t\t*/\n+\tSEC_LAST_DESCRIPTOR_IN_FLIGHT, /* API function indicates there is one\n+\t\t\t\t\t* last descriptor in flight\n+\t\t\t\t\t* for SEC to process that.\n+\t\t\t\t\t*/\n+\tSEC_PROCESSING_ERROR,\t       /* Indicates a SEC processing error\n+\t\t\t\t\t* occurred on a Job Ring which requires\n+\t\t\t\t\t* a SEC user space driver shutdown. Can\n+\t\t\t\t\t* be returned from sec_poll_job_ring().\n+\t\t\t\t\t* Then the only other API that can be\n+\t\t\t\t\t* called after this error is\n+\t\t\t\t\t* sec_release().\n+\t\t\t\t\t*/\n+\tSEC_DESC_PROCESSING_ERROR,     /* Indicates a SEC descriptor processing\n+\t\t\t\t\t* error occurred on a Job Ring. Can be\n+\t\t\t\t\t* returned from sec_poll_job_ring().\n+\t\t\t\t\t* The driver was able to reset job ring\n+\t\t\t\t\t* and job ring can be used like in a\n+\t\t\t\t\t* normal case.\n+\t\t\t\t\t*/\n+\tSEC_JR_IS_FULL,\t\t\t/* Job Ring is full. There is no more\n+\t\t\t\t\t * room in the JR for new descriptors.\n+\t\t\t\t\t * This can happen if the descriptor RX\n+\t\t\t\t\t * rate is higher than SEC's capacity.\n+\t\t\t\t\t */\n+\tSEC_DRIVER_RELEASE_IN_PROGRESS, /* SEC driver shutdown is in progress,\n+\t\t\t\t\t * descriptors processing or polling is\n+\t\t\t\t\t * allowed.\n+\t\t\t\t\t */\n+\tSEC_DRIVER_ALREADY_INITIALIZED, /* SEC driver is already initialized.*/\n+\tSEC_DRIVER_NOT_INITIALIZED,\t/* SEC driver is NOT initialized. */\n+\tSEC_JOB_RING_RESET_IN_PROGRESS, /* Job ring is resetting due to a\n+\t\t\t\t\t * per-descriptor SEC processing error\n+\t\t\t\t\t * ::SEC_desc_PROCESSING_ERROR. Reset is\n+\t\t\t\t\t * finished when sec_poll_job_ring()\n+\t\t\t\t\t * return. Then the job ring can be used\n+\t\t\t\t\t * again.\n+\t\t\t\t\t */\n+\tSEC_RESET_ENGINE_FAILED,\t/* Resetting of SEC Engine by SEC Kernel\n+\t\t\t\t\t * Driver Failed\n+\t\t\t\t\t */\n+\tSEC_ENABLE_IRQS_FAILED,\t\t/* Enabling of IRQs in SEC Kernel Driver\n+\t\t\t\t\t * Failed\n+\t\t\t\t\t */\n+\tSEC_DISABLE_IRQS_FAILED,\t/* Disabling of IRQs in SEC Kernel\n+\t\t\t\t\t * Driver Failed\n+\t\t\t\t\t */\n+\t/* END OF VALID VALUES */\n+\n+\tSEC_RETURN_CODE_MAX_VALUE,\t/* Invalid value for return code. It is\n+\t\t\t\t\t * used to mark the end of the return\n+\t\t\t\t\t * code values. @note ALL new return\n+\t\t\t\t\t * code values MUST be added before\n+\t\t\t\t\t * ::SEC_RETURN_CODE_MAX_VALUE!\n+\t\t\t\t\t */\n+};\n+\n+enum caam_jr_op_type {\n+\tCAAM_JR_NONE,  /* No Cipher operations*/\n+\tCAAM_JR_CIPHER,/* CIPHER operations */\n+\tCAAM_JR_AUTH,  /* Authentication Operations */\n+\tCAAM_JR_AEAD,  /* Authenticated Encryption with associated data */\n+\tCAAM_JR_IPSEC, /* IPSEC protocol operations*/\n+\tCAAM_JR_PDCP,  /* PDCP protocol operations*/\n+\tCAAM_JR_PKC,   /* Public Key Cryptographic Operations */\n+\tCAAM_JR_MAX\n+};\n+\n+struct caam_jr_session {\n+\tuint8_t dir;         /* Operation Direction */\n+\tenum rte_crypto_cipher_algorithm cipher_alg; /* Cipher Algorithm*/\n+\tenum rte_crypto_auth_algorithm auth_alg; /* Authentication Algorithm*/\n+\tenum rte_crypto_aead_algorithm aead_alg; /* AEAD Algorithm*/\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint8_t *data;\t/* pointer to key data */\n+\t\t\tsize_t length;\t/* key length in bytes */\n+\t\t} aead_key;\n+\t\tstruct {\n+\t\t\tstruct {\n+\t\t\t\tuint8_t *data;\t/* pointer to key data */\n+\t\t\t\tsize_t length;\t/* key length in bytes */\n+\t\t\t} cipher_key;\n+\t\t\tstruct {\n+\t\t\t\tuint8_t *data;\t/* pointer to key data */\n+\t\t\t\tsize_t length;\t/* key length in bytes */\n+\t\t\t} auth_key;\n+\t\t};\n+\t};\n+\tstruct {\n+\t\tuint16_t length;\n+\t\tuint16_t offset;\n+\t} iv;\t/* Initialisation vector parameters */\n+\tuint16_t auth_only_len; /* Length of data for Auth only */\n+\tuint32_t digest_length;\n+\tstruct ip ip4_hdr;\n+\tstruct caam_jr_qp *qp;\n+\tstruct sec_cdb *cdb;\t/* cmd block associated with qp */\n+\tstruct rte_mempool *ctx_pool; /* session mempool for caam_jr_op_ctx */\n+};\n+\n+/*\n+ * 16-byte hardware scatter/gather table\n+ */\n+\n+#define SEC4_SG_LEN_EXT\t\t0x80000000\t/* Entry points to table */\n+#define SEC4_SG_LEN_FIN\t\t0x40000000\t/* Last ent in table */\n+#define SEC4_SG_BPID_MASK\t0x000000ff\n+#define SEC4_SG_BPID_SHIFT\t16\n+#define SEC4_SG_LEN_MASK\t0x3fffffff\t/* Excludes EXT and FINAL */\n+#define SEC4_SG_OFFSET_MASK\t0x00001fff\n+\n+struct sec4_sg_entry {\n+\tuint64_t ptr;\n+\tuint32_t len;\n+\tuint32_t bpid_offset;\n+};\n+\n+#define MAX_SG_ENTRIES\t\t16\n+#define SG_CACHELINE_0\t\t0\n+#define SG_CACHELINE_1\t\t4\n+#define SG_CACHELINE_2\t\t8\n+#define SG_CACHELINE_3\t\t12\n+\n+/* Structure encompassing a job descriptor which is to be processed\n+ * by SEC. User should also initialise this structure with the callback\n+ * function pointer which will be called by driver after recieving proccessed\n+ * descriptor from SEC. User data is also passed in this data structure which\n+ * will be sent as an argument to the user callback function.\n+ */\n+struct job_descriptor {\n+\tuint32_t desc[CAAM_JOB_DESC_SIZE];\n+};\n+\n+struct caam_jr_op_ctx {\n+\tstruct job_descriptor jobdes;\n+\t/* sg[0] output, sg[1] input, others are possible sub frames */\n+\tstruct sec4_sg_entry sg[MAX_SG_ENTRIES];\n+\tstruct rte_crypto_op *op;\n+\tstruct rte_mempool *ctx_pool; /* mempool pointer for caam_jr_op_ctx */\n+\tint64_t vtop_offset;\n+\tuint8_t digest[JR_MAX_NB_MAX_DIGEST];\n+};\n+\n+/**\n+ * Checksum\n+ *\n+ * @param buffer calculate chksum for buffer\n+ * @param len    buffer length\n+ *\n+ * @return checksum value in host cpu order\n+ */\n+static inline uint16_t\n+calc_chksum(void *buffer, int len)\n+{\n+\tuint16_t *buf = (uint16_t *)buffer;\n+\tuint32_t sum = 0;\n+\tuint16_t result;\n+\n+\tfor (sum = 0; len > 1; len -= 2)\n+\t\tsum += *buf++;\n+\n+\tif (len == 1)\n+\t\tsum += *(unsigned char *)buf;\n+\n+\tsum = (sum >> 16) + (sum & 0xFFFF);\n+\tsum += (sum >> 16);\n+\tresult = ~sum;\n+\n+\treturn  result;\n+}\n+struct uio_job_ring {\n+\tuint32_t jr_id;\n+\tuint32_t uio_fd;\n+\tvoid *register_base_addr;\n+\tint map_size;\n+\tint uio_minor_number;\n+};\n+\n+int sec_cleanup(void);\n+int sec_configure(void);\n+struct uio_job_ring *config_job_ring(void);\n+void free_job_ring(uint32_t uio_fd);\n+\n+/* For Dma memory allocation of specified length and alignment */\n+static inline void *caam_jr_dma_mem_alloc(size_t align, size_t len)\n+{\n+\treturn rte_malloc(\"mem_alloc\", len, align);\n+}\n+\n+/* For freeing dma memory */\n+static inline void caam_jr_dma_free(void *ptr)\n+{\n+\trte_free(ptr);\n+}\n+\n+static inline rte_iova_t\n+caam_jr_mem_vtop(void *vaddr)\n+{\n+\tconst struct rte_memseg *ms;\n+\n+\tms = rte_mem_virt2memseg(vaddr, NULL);\n+\tif (ms)\n+\t\treturn ms->iova + RTE_PTR_DIFF(vaddr, ms->addr);\n+\treturn (size_t)NULL;\n+}\n+\n+static inline void *\n+caam_jr_dma_ptov(rte_iova_t paddr)\n+{\n+\treturn rte_mem_iova2virt(paddr);\n+}\n+\n+/* Virtual to physical address conversion */\n+static inline rte_iova_t caam_jr_dma_vtop(void *ptr)\n+{\n+\t//return rte_malloc_virt2iova(ptr);\n+\treturn caam_jr_mem_vtop(ptr);\n+}\n+\n+/** @brief Request to SEC kernel driver to enable interrupts for\n+ *         descriptor finished processing\n+ *  Use UIO to communicate with SEC kernel driver: write command\n+ *  value that indicates an IRQ enable action into UIO file descriptor\n+ *  of this job ring.\n+ *\n+ * @param [in]  uio_fd     Job Ring UIO File descriptor\n+ * @retval 0 for success\n+ * @retval -1 value for error\n+ */\n+uint32_t caam_jr_enable_irqs(uint32_t uio_fd);\n+\n+/** @brief Request to SEC kernel driver to disable interrupts for descriptor\n+ *  finished processing\n+ *  Use UIO to communicate with SEC kernel driver: write command\n+ *  value that indicates an IRQ disable action into UIO file descriptor\n+ *  of this job ring.\n+ *\n+ * @param [in]  uio_fd    UIO File descripto\n+ * @retval 0 for success\n+ * @retval -1 value for error\n+ *\n+ */\n+uint32_t caam_jr_disable_irqs(uint32_t uio_fd);\n+\n+#endif\ndiff --git a/drivers/crypto/caam_jr/caam_jr_uio.c b/drivers/crypto/caam_jr/caam_jr_uio.c\nnew file mode 100644\nindex 000000000..bc9ace07e\n--- /dev/null\n+++ b/drivers/crypto/caam_jr/caam_jr_uio.c\n@@ -0,0 +1,491 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright 2017-2018 NXP\n+ */\n+\n+#include <stdbool.h>\n+#include <stdint.h>\n+#include <stdio.h>\n+#include <unistd.h>\n+#include <stdlib.h>\n+#include <dirent.h>\n+#include <string.h>\n+#include <sys/mman.h>\n+#include <errno.h>\n+#include <fcntl.h>\n+#include <rte_common.h>\n+#include <rte_malloc.h>\n+#include <rte_crypto.h>\n+#include <rte_security.h>\n+#include <caam_jr_config.h>\n+\n+/* RTA header files */\n+#include <hw/desc/common.h>\n+#include <hw/desc/algo.h>\n+#include <hw/desc/ipsec.h>\n+\n+#include <caam_jr_hw_specific.h>\n+#include <caam_jr_pvt.h>\n+#include <caam_jr_log.h>\n+\n+/* Prefix path to sysfs directory where UIO device attributes are exported.\n+ * Path for UIO device X is /sys/class/uio/uioX\n+ */\n+#define SEC_UIO_DEVICE_SYS_ATTR_PATH    \"/sys/class/uio\"\n+\n+/* Subfolder in sysfs where mapping attributes are exported\n+ * for each UIO device. Path for mapping Y for device X is:\n+ *      /sys/class/uio/uioX/maps/mapY\n+ */\n+#define SEC_UIO_DEVICE_SYS_MAP_ATTR     \"maps/map\"\n+\n+/* Name of UIO device file prefix. Each UIO device will have a device file\n+ * /dev/uioX, where X is the minor device number.\n+ */\n+#define SEC_UIO_DEVICE_FILE_NAME    \"/dev/uio\"\n+\n+/*\n+ * Name of UIO device. Each user space SEC job ring will have a corresponding\n+ * UIO device with the name sec-channelX, where X is the job ring id.\n+ * Maximum length is #SEC_UIO_MAX_DEVICE_NAME_LENGTH.\n+ *\n+ * @note  Must be kept in synch with SEC kernel driver\n+ * define #SEC_UIO_DEVICE_NAME !\n+ */\n+#define SEC_UIO_DEVICE_NAME     \"fsl-jr\"\n+\n+/* Maximum length for the name of an UIO device file.\n+ * Device file name format is: /dev/uioX.\n+ */\n+#define SEC_UIO_MAX_DEVICE_FILE_NAME_LENGTH 30\n+\n+/* Maximum length for the name of an attribute file for an UIO device.\n+ * Attribute files are exported in sysfs and have the name formatted as:\n+ *      /sys/class/uio/uioX/<attribute_file_name>\n+ */\n+#define SEC_UIO_MAX_ATTR_FILE_NAME  100\n+\n+/* Command that is used by SEC user space driver and SEC kernel driver\n+ *  to signal a request from the former to the later to disable job DONE\n+ *  and error IRQs on a certain job ring.\n+ *  The configuration is done at SEC Controller's level.\n+ *  @note   Need to be kept in synch with #SEC_UIO_DISABLE_IRQ_CMD from\n+ *          linux/drivers/crypto/talitos.c !\n+ */\n+#define SEC_UIO_DISABLE_IRQ_CMD     0\n+\n+/* Command that is used by SEC user space driver and SEC kernel driver\n+ *  to signal a request from the former to the later to enable job DONE\n+ *  and error IRQs on a certain job ring.\n+ *  The configuration is done at SEC Controller's level.\n+ *  @note   Need to be kept in synch with #SEC_UIO_ENABLE_IRQ_CMD from\n+ *          linux/drivers/crypto/talitos.c !\n+ */\n+#define SEC_UIO_ENABLE_IRQ_CMD      1\n+\n+/** Command that is used by SEC user space driver and SEC kernel driver\n+ *  to signal a request from the former to the later to do a SEC engine reset.\n+ *  @note   Need to be kept in synch with #SEC_UIO_RESET_SEC_ENGINE_CMD from\n+ *          linux/drivers/crypto/talitos.c !\n+ */\n+#define SEC_UIO_RESET_SEC_ENGINE_CMD    3\n+\n+/* The id for the mapping used to export SEC's registers to\n+ * user space through UIO devices.\n+ */\n+#define SEC_UIO_MAP_ID              0\n+\n+static struct uio_job_ring g_uio_job_ring[MAX_SEC_JOB_RINGS];\n+static int g_uio_jr_num;\n+\n+/** @brief Checks if a file name contains a certain substring.\n+ * If so, it extracts the number following the substring.\n+ * This function assumes a filename format of: [text][number].\n+ * @param [in]  filename    File name\n+ * @param [in]  match       String to match in file name\n+ * @param [out] number      The number extracted from filename\n+ *\n+ * @retval true if file name matches the criteria\n+ * @retval false if file name does not match the criteria\n+ */\n+static bool\n+file_name_match_extract(const char filename[], const char match[], int *number)\n+{\n+\tchar *substr = NULL;\n+\n+\tsubstr = strstr(filename, match);\n+\tif (substr == NULL)\n+\t\treturn false;\n+\n+\t/* substring <match> was found in <filename>\n+\t * read number following <match> substring in <filename>\n+\t */\n+\tsscanf(filename + strlen(match), \"%d\", number);\n+\treturn true;\n+}\n+\n+/** @brief Reads first line from a file.\n+ * Composes file name as: root/subdir/filename\n+ *\n+ * @param [in]  root     Root path\n+ * @param [in]  subdir   Subdirectory name\n+ * @param [in]  filename File name\n+ * @param [out] line     The first line read from file.\n+ *\n+ * @retval 0 for succes\n+ * @retval other value for error\n+ */\n+static int\n+file_read_first_line(const char root[], const char subdir[],\n+\t\t    const char filename[], char *line)\n+{\n+\tchar absolute_file_name[SEC_UIO_MAX_ATTR_FILE_NAME];\n+\tint fd = 0, ret = 0;\n+\n+\t/*compose the file name: root/subdir/filename */\n+\tmemset(absolute_file_name, 0, sizeof(absolute_file_name));\n+\tsnprintf(absolute_file_name, SEC_UIO_MAX_ATTR_FILE_NAME,\n+\t\t \"%s/%s/%s\", root, subdir, filename);\n+\n+\tfd = open(absolute_file_name, O_RDONLY);\n+\tSEC_ASSERT(fd > 0, fd, \"Error opening file %s\",\n+\t\t\tabsolute_file_name);\n+\n+\t/* read UIO device name from first line in file */\n+\tret = read(fd, line, SEC_UIO_MAX_DEVICE_FILE_NAME_LENGTH);\n+\tclose(fd);\n+\n+\t/* NULL-ify string */\n+\tline[SEC_UIO_MAX_DEVICE_FILE_NAME_LENGTH - 1] = '\\0';\n+\n+\tif (ret <= 0) {\n+\t\tCAAM_JR_ERR(\"Error reading from file %s\", absolute_file_name);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/** @brief Uses UIO control to send commands to SEC kernel driver.\n+ * The mechanism is to write a command word into the file descriptor\n+ * that the user-space driver obtained for each user-space SEC job ring.\n+ * Both user-space driver and kernel driver must have the same understanding\n+ * about the command codes.\n+ *\n+ * @param [in]  UIO FD\t\t    The UIO file descriptor\n+ * @param [in]  uio_command         Command word\n+ *\n+ * @retval Result of write operation on the job ring's UIO file descriptor.\n+ *         Should be sizeof(int) for success operations.\n+ *         Other values can be returned and used, if desired to add special\n+ *         meaning to return values, but this has to be programmed in SEC\n+ *         kernel driver as well. No special return values are used.\n+ */\n+static int sec_uio_send_command(uint32_t uio_fd, int32_t uio_command)\n+{\n+\tint ret;\n+\n+\t/* Use UIO file descriptor we have for this job ring.\n+\t * Writing a command code to this file descriptor will make the\n+\t * SEC kernel driver execute the desired command.\n+\t */\n+\tret = write(uio_fd, &uio_command, sizeof(int));\n+\treturn ret;\n+}\n+\n+/** @brief Request to SEC kernel driver to enable interrupts for\n+ *         descriptor finished processing\n+ *  Use UIO to communicate with SEC kernel driver: write command\n+ *  value that indicates an IRQ enable action into UIO file descriptor\n+ *  of this job ring.\n+ *\n+ * @param [in]  uio_fd     Job Ring UIO File descriptor\n+ * @retval 0 for success\n+ * @retval -1 value for error\n+ */\n+uint32_t caam_jr_enable_irqs(uint32_t uio_fd)\n+{\n+\tint ret;\n+\n+\t/* Use UIO file descriptor we have for this job ring.\n+\t * Writing a command code to this file descriptor will make the\n+\t * SEC kernel driver enable DONE and Error IRQs for this job ring,\n+\t * at Controller level.\n+\t */\n+\tret = sec_uio_send_command(uio_fd, SEC_UIO_ENABLE_IRQ_CMD);\n+\tSEC_ASSERT(ret == sizeof(int), -1,\n+\t\t\"Failed to request SEC engine to enable job done and \"\n+\t\t\"error IRQs through UIO control. UIO FD %d. Reset SEC driver!\",\n+\t\tuio_fd);\n+\tCAAM_JR_DEBUG(\"Enabled IRQs on jr with uio_fd %d\", uio_fd);\n+\treturn 0;\n+}\n+\n+\n+/** @brief Request to SEC kernel driver to disable interrupts for descriptor\n+ *  finished processing\n+ *  Use UIO to communicate with SEC kernel driver: write command\n+ *  value that indicates an IRQ disable action into UIO file descriptor\n+ *  of this job ring.\n+ *\n+ * @param [in]  uio_fd    UIO File descripto\n+ * @retval 0 for success\n+ * @retval -1 value for error\n+ *\n+ */\n+uint32_t caam_jr_disable_irqs(uint32_t uio_fd)\n+{\n+\tint ret;\n+\n+\t/* Use UIO file descriptor we have for this job ring.\n+\t * Writing a command code to this file descriptor will make the\n+\t * SEC kernel driver disable IRQs for this job ring,\n+\t * at Controller level.\n+\t */\n+\n+\tret = sec_uio_send_command(uio_fd, SEC_UIO_DISABLE_IRQ_CMD);\n+\tSEC_ASSERT(ret == sizeof(int), -1,\n+\t\t\"Failed to request SEC engine to disable job done and \"\n+\t\t\"IRQs through UIO control. UIO_FD %d Reset SEC driver!\",\n+\t\tuio_fd);\n+\tCAAM_JR_DEBUG(\"Disabled IRQs on jr with uio_fd %d\", uio_fd);\n+\treturn 0;\n+}\n+\n+/** @brief Maps register range assigned for a job ring.\n+ *\n+ * @param [in] uio_device_fd    UIO device file descriptor\n+ * @param [in] uio_device_id    UIO device id\n+ * @param [in] uio_map_id       UIO allows maximum 5 different mapping for\n+\t\t\t\teach device. Maps start with id 0.\n+ * @param [out] map_size        Map size.\n+ * @retval  NULL if failed to map registers\n+ * @retval  Virtual address for mapped register address range\n+ */\n+static void *\n+uio_map_registers(int uio_device_fd, int uio_device_id,\n+\t\tint uio_map_id, int *map_size)\n+{\n+\tvoid *mapped_address = NULL;\n+\tunsigned int uio_map_size = 0;\n+\tchar uio_sys_root[SEC_UIO_MAX_ATTR_FILE_NAME];\n+\tchar uio_sys_map_subdir[SEC_UIO_MAX_ATTR_FILE_NAME];\n+\tchar uio_map_size_str[32];\n+\tint ret = 0;\n+\n+\t/* compose the file name: root/subdir/filename */\n+\tmemset(uio_sys_root, 0, sizeof(uio_sys_root));\n+\tmemset(uio_sys_map_subdir, 0, sizeof(uio_sys_map_subdir));\n+\tmemset(uio_map_size_str, 0, sizeof(uio_map_size_str));\n+\n+\t/* Compose string: /sys/class/uio/uioX */\n+\tsprintf(uio_sys_root, \"%s/%s%d\", SEC_UIO_DEVICE_SYS_ATTR_PATH,\n+\t\t\"uio\", uio_device_id);\n+\t/* Compose string: maps/mapY */\n+\tsprintf(uio_sys_map_subdir, \"%s%d\", SEC_UIO_DEVICE_SYS_MAP_ATTR,\n+\t\tuio_map_id);\n+\n+\t/* Read first (and only) line from file\n+\t * /sys/class/uio/uioX/maps/mapY/size\n+\t */\n+\tret = file_read_first_line(uio_sys_root, uio_sys_map_subdir,\n+\t\t\t\t \"size\", uio_map_size_str);\n+\tSEC_ASSERT(ret == 0, NULL, \"file_read_first_line() failed\");\n+\n+\t/* Read mapping size, expressed in hexa(base 16) */\n+\tuio_map_size = strtol(uio_map_size_str, NULL, 16);\n+\n+\t/* Map the region in user space */\n+\tmapped_address = mmap(0, /*dynamically choose virtual address */\n+\t\tuio_map_size, PROT_READ | PROT_WRITE,\n+\t\tMAP_SHARED, uio_device_fd, 0);\n+\t/* offset = 0 because UIO device has only one mapping\n+\t * for the entire SEC register memory\n+\t */\n+\tif (mapped_address == MAP_FAILED) {\n+\t\tCAAM_JR_ERR(\n+\t\t\t\"Failed to map registers! errno = %d job ring fd  = %d,\"\n+\t\t\t\"uio device id = %d, uio map id = %d\", errno,\n+\t\t\tuio_device_fd, uio_device_id, uio_map_id);\n+\t\treturn NULL;\n+\t}\n+\n+\t/*\n+\t * Save the map size to use it later on for munmap-ing.\n+\t */\n+\t*map_size = uio_map_size;\n+\n+\tCAAM_JR_INFO(\"UIO dev[%d] mapped region [id =%d] size 0x%x at %p\",\n+\t\tuio_device_id, uio_map_id, uio_map_size, mapped_address);\n+\n+\treturn mapped_address;\n+}\n+\n+void free_job_ring(uint32_t uio_fd)\n+{\n+\tstruct uio_job_ring *job_ring = NULL;\n+\tint i;\n+\n+\tif (!job_ring->uio_fd)\n+\t\treturn;\n+\n+\tfor (i = 0; i < MAX_SEC_JOB_RINGS; i++) {\n+\t\tif (g_uio_job_ring[i].uio_fd == uio_fd) {\n+\t\t\tjob_ring = &g_uio_job_ring[i];\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\tif (job_ring == NULL) {\n+\t\tCAAM_JR_ERR(\"JR not available for fd = %x\\n\", uio_fd);\n+\t\treturn;\n+\t}\n+\n+\t/* Open device file */\n+\tCAAM_JR_INFO(\"Closed device file for job ring %d , fd = %d\",\n+\t\t\tjob_ring->jr_id, job_ring->uio_fd);\n+\tclose(job_ring->uio_fd);\n+\tg_uio_jr_num--;\n+\tjob_ring->uio_fd = 0;\n+\n+\tif (job_ring->register_base_addr == NULL)\n+\t\treturn;\n+\n+\t/* Unmap the PCI memory resource of device */\n+\tif (munmap(job_ring->register_base_addr, job_ring->map_size)) {\n+\t\tCAAM_JR_INFO(\"cannot munmap(%p, 0x%lx): %s\",\n+\t\t\tjob_ring->register_base_addr,\n+\t\t\t(unsigned long)job_ring->map_size, strerror(errno));\n+\t} else\n+\t\tCAAM_JR_DEBUG(\"  JR UIO memory unmapped at %p\",\n+\t\t\t\tjob_ring->register_base_addr);\n+\tjob_ring->register_base_addr = NULL;\n+}\n+\n+struct uio_job_ring *config_job_ring(void)\n+{\n+\tchar uio_device_file_name[32];\n+\tstruct uio_job_ring *job_ring = NULL;\n+\tint i;\n+\n+\tfor (i = 0; i < MAX_SEC_JOB_RINGS; i++) {\n+\t\tif (g_uio_job_ring[i].uio_fd == 0) {\n+\t\t\tjob_ring = &g_uio_job_ring[i];\n+\t\t\tg_uio_jr_num++;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tif (job_ring == NULL) {\n+\t\tCAAM_JR_ERR(\"No free job ring\\n\");\n+\t\treturn NULL;\n+\t}\n+\n+\t/* Find UIO device created by SEC kernel driver for this job ring. */\n+\tmemset(uio_device_file_name, 0, sizeof(uio_device_file_name));\n+\n+\tsprintf(uio_device_file_name, \"%s%d\", SEC_UIO_DEVICE_FILE_NAME,\n+\t\tjob_ring->uio_minor_number);\n+\n+\t/* Open device file */\n+\tjob_ring->uio_fd = open(uio_device_file_name, O_RDWR);\n+\tSEC_ASSERT(job_ring->uio_fd > 0, NULL,\n+\t\t\"Failed to open UIO device file for job ring %d\",\n+\t\tjob_ring->jr_id);\n+\n+\tCAAM_JR_INFO(\"Open device(%s) file for job ring=%d , uio_fd = %d\",\n+\t\tuio_device_file_name, job_ring->jr_id, job_ring->uio_fd);\n+\n+\tASSERT(job_ring->register_base_addr == NULL);\n+\tjob_ring->register_base_addr = uio_map_registers(\n+\t\t\tjob_ring->uio_fd, job_ring->uio_minor_number,\n+\t\t\tSEC_UIO_MAP_ID, &job_ring->map_size);\n+\n+\tSEC_ASSERT(job_ring->register_base_addr != NULL, NULL,\n+\t\t\"Failed to map SEC registers\");\n+\treturn job_ring;\n+}\n+\n+int sec_configure(void)\n+{\n+\tchar uio_name[32];\n+\tint config_jr_no = 0, jr_id = -1;\n+\tint uio_minor_number = -1;\n+\tint ret;\n+\tDIR *d = NULL;\n+\tstruct dirent *dir;\n+\n+\td = opendir(SEC_UIO_DEVICE_SYS_ATTR_PATH);\n+\tif (d == NULL) {\n+\t\tprintf(\"\\nError opening directory '%s': %s\\n\",\n+\t\t\tSEC_UIO_DEVICE_SYS_ATTR_PATH, strerror(errno));\n+\t\treturn -1;\n+\t}\n+\n+\t/* Iterate through all subdirs */\n+\twhile ((dir = readdir(d)) != NULL) {\n+\t\tif (!strncmp(dir->d_name, \".\", 1) ||\n+\t\t\t\t!strncmp(dir->d_name, \"..\", 2))\n+\t\t\tcontinue;\n+\n+\t\tif (file_name_match_extract\n+\t\t\t(dir->d_name, \"uio\", &uio_minor_number)) {\n+\t\t/*\n+\t\t * Open file uioX/name and read first line which contains\n+\t\t * the name for the device. Based on the name check if this\n+\t\t * UIO device is UIO device for job ring with id jr_id.\n+\t\t */\n+\t\t\tmemset(uio_name, 0, sizeof(uio_name));\n+\t\t\tret = file_read_first_line(SEC_UIO_DEVICE_SYS_ATTR_PATH,\n+\t\t\t\t\tdir->d_name, \"name\", uio_name);\n+\t\t\tCAAM_JR_INFO(\"sec device uio name: %s\", uio_name);\n+\t\t\tSEC_ASSERT(ret == 0, -1, \"file_read_first_line failed\");\n+\n+\t\t\tif (file_name_match_extract(uio_name,\n+\t\t\t\t\t\tSEC_UIO_DEVICE_NAME,\n+\t\t\t\t\t\t&jr_id)) {\n+\t\t\t\tg_uio_job_ring[config_jr_no].jr_id = jr_id;\n+\t\t\t\tg_uio_job_ring[config_jr_no].uio_minor_number =\n+\t\t\t\t\t\t\tuio_minor_number;\n+\t\t\t\tCAAM_JR_INFO(\"Detected logical JRID:%d\", jr_id);\n+\t\t\t\tconfig_jr_no++;\n+\n+\t\t\t\t/* todo  find the actual ring id\n+\t\t\t\t * OF_FULLNAME=/soc/crypto@1700000/jr@20000\n+\t\t\t\t */\n+\t\t\t}\n+\t\t}\n+\t}\n+\tclosedir(d);\n+\n+\tif (config_jr_no == 0) {\n+\t\tCAAM_JR_ERR(\"! No SEC Job Rings assigned for userspace usage!\");\n+\t\treturn 0;\n+\t}\n+\tCAAM_JR_INFO(\"Total JR detected =%d\", config_jr_no);\n+\treturn config_jr_no;\n+}\n+\n+int sec_cleanup(void)\n+{\n+\tint i;\n+\tstruct uio_job_ring *job_ring;\n+\n+\tfor (i = 0; i < g_uio_jr_num; i++) {\n+\t\tjob_ring = &g_uio_job_ring[i];\n+\t\t/* munmap SEC's register memory */\n+\t\tif (job_ring->register_base_addr) {\n+\t\t\tmunmap(job_ring->register_base_addr,\n+\t\t\t\tjob_ring->map_size);\n+\t\t\tjob_ring->register_base_addr = NULL;\n+\t\t}\n+\t\t/* I need to close the fd after shutdown UIO commands need to be\n+\t\t * sent using the fd\n+\t\t */\n+\t\tif (job_ring->uio_fd != 0) {\n+\t\t\tCAAM_JR_INFO(\n+\t\t\t\"Closed device file for job ring %d , fd = %d\",\n+\t\t\tjob_ring->jr_id, job_ring->uio_fd);\n+\t\t\tclose(job_ring->uio_fd);\n+\t\t}\n+\t}\n+\treturn 0;\n+}\ndiff --git a/drivers/crypto/caam_jr/meson.build b/drivers/crypto/caam_jr/meson.build\nindex 3edd0a212..7b024e886 100644\n--- a/drivers/crypto/caam_jr/meson.build\n+++ b/drivers/crypto/caam_jr/meson.build\n@@ -6,6 +6,9 @@ if host_machine.system() != 'linux'\n endif\n \n deps += ['bus_vdev', 'bus_dpaa', 'security']\n-sources = files('caam_jr.c')\n+sources = files('caam_jr_hw.c', 'caam_jr_uio.c', 'caam_jr.c')\n \n allow_experimental_apis = true\n+\n+includes += include_directories('../dpaa2_sec/')\n+includes += include_directories('../../bus/dpaa/include/')\n",
    "prefixes": [
        "03/10"
    ]
}